2 * twl4030-irq.c - TWL4030/TPS659x0 irq support
4 * Copyright (C) 2005-2006 Texas Instruments, Inc.
6 * Modifications to defer interrupt handling to a kernel thread:
7 * Copyright (C) 2006 MontaVista Software, Inc.
9 * Based on tlv320aic23.c:
10 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
12 * Code cleanup and modifications to IRQ handler.
13 * by syed khasim <x0khasim@ti.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 #include <linux/init.h>
31 #include <linux/interrupt.h>
32 #include <linux/irq.h>
33 #include <linux/kthread.h>
35 #include <linux/i2c/twl4030.h>
39 * TWL4030 IRQ handling has two stages in hardware, and thus in software.
40 * The Primary Interrupt Handler (PIH) stage exposes status bits saying
41 * which Secondary Interrupt Handler (SIH) stage is raising an interrupt.
42 * SIH modules are more traditional IRQ components, which support per-IRQ
43 * enable/disable and trigger controls; they do most of the work.
45 * These chips are designed to support IRQ handling from two different
46 * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status
47 * and mask registers in the PIH and SIH modules.
49 * We set up IRQs starting at a platform-specified base, always starting
50 * with PIH and the SIH for PWR_INT and then usually adding GPIO:
51 * base + 0 .. base + 7 PIH
52 * base + 8 .. base + 15 SIH for PWR_INT
53 * base + 16 .. base + 33 SIH for GPIO
56 /* PIH register offsets */
57 #define REG_PIH_ISR_P1 0x01
58 #define REG_PIH_ISR_P2 0x02
59 #define REG_PIH_SIR 0x03 /* for testing */
62 /* Linux could (eventually) use either IRQ line */
67 u8 module; /* module id */
68 u8 control_offset; /* for SIH_CTRL */
71 u8 bits; /* valid in isr/imr */
72 u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */
75 u8 bytes_edr; /* bytelen of EDR */
77 /* SIR ignored -- set interrupt, for testing only */
82 /* + 2 bytes padding */
85 #define SIH_INITIALIZER(modname, nbits) \
86 .module = TWL4030_MODULE_ ## modname, \
87 .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \
89 .bytes_ixr = DIV_ROUND_UP(nbits, 8), \
90 .edr_offset = TWL4030_ ## modname ## _EDR, \
91 .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \
93 .isr_offset = TWL4030_ ## modname ## _ISR1, \
94 .imr_offset = TWL4030_ ## modname ## _IMR1, \
97 .isr_offset = TWL4030_ ## modname ## _ISR2, \
98 .imr_offset = TWL4030_ ## modname ## _IMR2, \
101 /* register naming policies are inconsistent ... */
102 #define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1
103 #define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD
104 #define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT
107 /* Order in this table matches order in PIH_ISR. That is,
108 * BIT(n) in PIH_ISR is sih_modules[n].
110 static const struct sih sih_modules[6] = {
113 .module = TWL4030_MODULE_GPIO,
114 .control_offset = REG_GPIO_SIH_CTRL,
116 .bits = TWL4030_GPIO_MAX,
118 /* Note: *all* of these IRQs default to no-trigger */
119 .edr_offset = REG_GPIO_EDR1,
122 .isr_offset = REG_GPIO_ISR1A,
123 .imr_offset = REG_GPIO_IMR1A,
125 .isr_offset = REG_GPIO_ISR1B,
126 .imr_offset = REG_GPIO_IMR1B,
132 SIH_INITIALIZER(KEYPAD_KEYP, 4)
136 .module = TWL4030_MODULE_INTERRUPTS,
137 .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL,
140 .edr_offset = TWL4030_INTERRUPTS_BCIEDR1,
141 /* Note: most of these IRQs default to no-trigger */
144 .isr_offset = TWL4030_INTERRUPTS_BCIISR1A,
145 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A,
147 .isr_offset = TWL4030_INTERRUPTS_BCIISR1B,
148 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B,
153 SIH_INITIALIZER(MADC, 4)
156 /* USB doesn't use the same SIH organization */
162 SIH_INITIALIZER(INT_PWR, 8)
164 /* there are no SIH modules #6 or #7 ... */
167 #undef TWL4030_MODULE_KEYPAD_KEYP
168 #undef TWL4030_MODULE_INT_PWR
169 #undef TWL4030_INT_PWR_EDR
171 /*----------------------------------------------------------------------*/
173 static unsigned twl4030_irq_base;
175 static struct completion irq_event;
178 * This thread processes interrupts reported by the Primary Interrupt Handler.
180 static int twl4030_irq_thread(void *data)
182 long irq = (long)data;
183 irq_desc_t *desc = irq_desc + irq;
184 static unsigned i2c_errors;
185 const static unsigned max_i2c_errors = 100;
187 current->flags |= PF_NOFREEZE;
189 while (!kthread_should_stop()) {
194 /* Wait for IRQ, then read PIH irq status (also blocking) */
195 wait_for_completion_interruptible(&irq_event);
197 ret = twl4030_i2c_read_u8(TWL4030_MODULE_PIH, &pih_isr,
200 pr_warning("twl4030: I2C error %d reading PIH ISR\n",
202 if (++i2c_errors >= max_i2c_errors) {
203 printk(KERN_ERR "Maximum I2C error count"
204 " exceeded. Terminating %s.\n",
208 complete(&irq_event);
212 /* these handlers deal with the relevant SIH irq status */
214 for (module_irq = twl4030_irq_base;
216 pih_isr >>= 1, module_irq++) {
218 irq_desc_t *d = irq_desc + module_irq;
220 /* These can't be masked ... always warn
221 * if we get any surprises.
223 if (d->status & IRQ_DISABLED)
224 note_interrupt(module_irq, d,
227 d->handle_irq(module_irq, d);
232 desc->chip->unmask(irq);
239 * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt.
240 * This is a chained interrupt, so there is no desc->action method for it.
241 * Now we need to query the interrupt controller in the twl4030 to determine
242 * which module is generating the interrupt request. However, we can't do i2c
243 * transactions in interrupt context, so we must defer that work to a kernel
244 * thread. All we do here is acknowledge and mask the interrupt and wakeup
247 static void handle_twl4030_pih(unsigned int irq, irq_desc_t *desc)
249 /* Acknowledge, clear *AND* mask the interrupt... */
250 desc->chip->ack(irq);
251 complete(&irq_event);
254 static struct task_struct *start_twl4030_irq_thread(long irq)
256 struct task_struct *thread;
258 init_completion(&irq_event);
259 thread = kthread_run(twl4030_irq_thread, (void *)irq, "twl4030-irq");
261 pr_err("twl4030: could not create irq %ld thread!\n", irq);
266 /*----------------------------------------------------------------------*/
269 * twl4030_init_sih_modules() ... start from a known state where no
270 * IRQs will be coming in, and where we can quickly enable them then
271 * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL.
273 * NOTE: we don't touch EDR registers here; they stay with hardware
274 * defaults or whatever the last value was. Note that when both EDR
275 * bits for an IRQ are clear, that's as if its IMR bit is set...
277 static int twl4030_init_sih_modules(unsigned line)
279 const struct sih *sih;
284 /* line 0 == int1_n signal; line 1 == int2_n signal */
290 /* disable all interrupts on our line */
291 memset(buf, 0xff, sizeof buf);
293 for (i = 0; i < ARRAY_SIZE(sih_modules); i++, sih++) {
295 /* skip USB -- it's funky */
299 status = twl4030_i2c_write(sih->module, buf,
300 sih->mask[line].imr_offset, sih->bytes_ixr);
302 pr_err("twl4030: err %d initializing %s %s\n",
303 status, sih->name, "IMR");
305 /* Maybe disable "exclusive" mode; buffer second pending irq;
306 * set Clear-On-Read (COR) bit.
308 * NOTE that sometimes COR polarity is documented as being
309 * inverted: for MADC and BCI, COR=1 means "clear on write".
310 * And for PWR_INT it's not documented...
313 status = twl4030_i2c_write_u8(sih->module,
314 TWL4030_SIH_CTRL_COR_MASK,
315 sih->control_offset);
317 pr_err("twl4030: err %d initializing %s %s\n",
318 status, sih->name, "SIH_CTRL");
323 for (i = 0; i < ARRAY_SIZE(sih_modules); i++, sih++) {
331 /* Clear pending interrupt status. Either the read was
332 * enough, or we need to write those bits. Repeat, in
333 * case an IRQ is pending (PENDDIS=0) ... that's not
334 * uncommon with PWR_INT.PWRON.
336 for (j = 0; j < 2; j++) {
337 status = twl4030_i2c_read(sih->module, rxbuf,
338 sih->mask[line].isr_offset, sih->bytes_ixr);
340 pr_err("twl4030: err %d initializing %s %s\n",
341 status, sih->name, "ISR");
344 status = twl4030_i2c_write(sih->module, buf,
345 sih->mask[line].isr_offset,
347 /* else COR=1 means read sufficed.
348 * (for most SIH modules...)
356 static inline void activate_irq(int irq)
359 /* ARM requires an extra step to clear IRQ_NOREQUEST, which it
360 * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE.
362 set_irq_flags(irq, IRQF_VALID);
364 /* same effect on other architectures */
365 set_irq_noprobe(irq);
369 /* FIXME pass in which interrupt line we'll use ... */
370 #define twl_irq_line 0
372 int twl_init_irq(int irq_num, unsigned irq_base, unsigned irq_end)
374 static struct irq_chip twl4030_irq_chip;
380 * Mask and clear all TWL4030 interrupts since initially we do
381 * not have any TWL4030 module interrupt handlers present
383 status = twl4030_init_sih_modules(twl_irq_line);
387 twl4030_irq_base = irq_base;
389 /* install an irq handler for each of the SIH modules;
390 * clone dummy irq_chip since PIH can't *do* anything
392 twl4030_irq_chip = dummy_irq_chip;
393 twl4030_irq_chip.name = "twl4030";
395 for (i = irq_base; i < irq_end; i++) {
396 set_irq_chip_and_handler(i, &twl4030_irq_chip,
401 /* install an irq handler to demultiplex the TWL4030 interrupt */
402 set_irq_data(irq_num, start_twl4030_irq_thread(irq_num));
403 set_irq_chained_handler(irq_num, handle_twl4030_pih);
408 int twl_exit_irq(void)
410 /* FIXME undo twl_init_irq() */
411 if (twl4030_irq_base) {
412 pr_err("twl4030: can't yet clean up IRQs?\n");