drivers/isdn/hardware/mISDN/hfcpci.c

   1 /*
   2  *
   3  * hfcpci.c     low level driver for CCD's hfc-pci based cards
   4  *
   5  * Author     Werner Cornelius (werner@isdn4linux.de)
   6  *            based on existing driver for CCD hfc ISA cards
   7  *            type approval valid for HFC-S PCI A based card
   8  *
   9  * Copyright 1999  by Werner Cornelius (werner@isdn-development.de)
  10  * Copyright 2008  by Karsten Keil <kkeil@novell.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2, or (at your option)
  15  * any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  * Module options:
  27  *
  28  * debug:
  29  *      NOTE: only one poll value must be given for all cards
  30  *      See hfc_pci.h for debug flags.
  31  *
  32  * poll:
  33  *      NOTE: only one poll value must be given for all cards
  34  *      Give the number of samples for each fifo process.
  35  *      By default 128 is used. Decrease to reduce delay, increase to
  36  *      reduce cpu load. If unsure, don't mess with it!
  37  *      A value of 128 will use controller's interrupt. Other values will
  38  *      use kernel timer, because the controller will not allow lower values
  39  *      than 128.
  40  *      Also note that the value depends on the kernel timer frequency.
  41  *      If kernel uses a frequency of 1000 Hz, steps of 8 samples are possible.
  42  *      If the kernel uses 100 Hz, steps of 80 samples are possible.
  43  *      If the kernel uses 300 Hz, steps of about 26 samples are possible.
  44  *
  45  */
  46
  47 #include <linux/module.h>
  48 #include <linux/pci.h>
  49 #include <linux/delay.h>
  50 #include <linux/mISDNhw.h>
  51
  52 #include "hfc_pci.h"
  53
  54 static const char *hfcpci_revision = "2.0";
  55
  56 static int HFC_cnt;
  57 static uint debug;
  58 static uint poll, tics;
  59 struct timer_list hfc_tl;
  60 u32     hfc_jiffies;
  61
  62 MODULE_AUTHOR("Karsten Keil");
  63 MODULE_LICENSE("GPL");
  64 module_param(debug, uint, 0);
  65 module_param(poll, uint, S_IRUGO | S_IWUSR);
  66
  67 static LIST_HEAD(HFClist);
  68 static DEFINE_RWLOCK(HFClock);
  69
  70 enum {
  71         HFC_CCD_2BD0,
  72         HFC_CCD_B000,
  73         HFC_CCD_B006,
  74         HFC_CCD_B007,
  75         HFC_CCD_B008,
  76         HFC_CCD_B009,
  77         HFC_CCD_B00A,
  78         HFC_CCD_B00B,
  79         HFC_CCD_B00C,
  80         HFC_CCD_B100,
  81         HFC_CCD_B700,
  82         HFC_CCD_B701,
  83         HFC_ASUS_0675,
  84         HFC_BERKOM_A1T,
  85         HFC_BERKOM_TCONCEPT,
  86         HFC_ANIGMA_MC145575,
  87         HFC_ZOLTRIX_2BD0,
  88         HFC_DIGI_DF_M_IOM2_E,
  89         HFC_DIGI_DF_M_E,
  90         HFC_DIGI_DF_M_IOM2_A,
  91         HFC_DIGI_DF_M_A,
  92         HFC_ABOCOM_2BD1,
  93         HFC_SITECOM_DC105V2,
  94 };
  95
  96 struct hfcPCI_hw {
  97         unsigned char           cirm;
  98         unsigned char           ctmt;
  99         unsigned char           clkdel;
 100         unsigned char           states;
 101         unsigned char           conn;
 102         unsigned char           mst_m;
 103         unsigned char           int_m1;
 104         unsigned char           int_m2;
 105         unsigned char           sctrl;
 106         unsigned char           sctrl_r;
 107         unsigned char           sctrl_e;
 108         unsigned char           trm;
 109         unsigned char           fifo_en;
 110         unsigned char           bswapped;
 111         unsigned char           protocol;
 112         int                     nt_timer;
 113         unsigned char __iomem   *pci_io; /* start of PCI IO memory */
 114         dma_addr_t              dmahandle;
 115         void                    *fifos; /* FIFO memory */
 116         int                     last_bfifo_cnt[2];
 117             /* marker saving last b-fifo frame count */
 118         struct timer_list       timer;
 119 };
 120
 121 #define HFC_CFG_MASTER          1
 122 #define HFC_CFG_SLAVE           2
 123 #define HFC_CFG_PCM             3
 124 #define HFC_CFG_2HFC            4
 125 #define HFC_CFG_SLAVEHFC        5
 126 #define HFC_CFG_NEG_F0          6
 127 #define HFC_CFG_SW_DD_DU        7
 128
 129 #define FLG_HFC_TIMER_T1        16
 130 #define FLG_HFC_TIMER_T3        17
 131
 132 #define NT_T1_COUNT     1120    /* number of 3.125ms interrupts (3.5s) */
 133 #define NT_T3_COUNT     31      /* number of 3.125ms interrupts (97 ms) */
 134 #define CLKDEL_TE       0x0e    /* CLKDEL in TE mode */
 135 #define CLKDEL_NT       0x6c    /* CLKDEL in NT mode */
 136
 137
 138 struct hfc_pci {
 139         struct list_head        list;
 140         u_char                  subtype;
 141         u_char                  chanlimit;
 142         u_char                  initdone;
 143         u_long                  cfg;
 144         u_int                   irq;
 145         u_int                   irqcnt;
 146         struct pci_dev          *pdev;
 147         struct hfcPCI_hw        hw;
 148         spinlock_t              lock;   /* card lock */
 149         struct dchannel         dch;
 150         struct bchannel         bch[2];
 151 };
 152
 153 /* Interface functions */
 154 static void
 155 enable_hwirq(struct hfc_pci *hc)
 156 {
 157         hc->hw.int_m2 |= HFCPCI_IRQ_ENABLE;
 158         Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
 159 }
 160
 161 static void
 162 disable_hwirq(struct hfc_pci *hc)
 163 {
 164         hc->hw.int_m2 &= ~((u_char)HFCPCI_IRQ_ENABLE);
 165         Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
 166 }
 167
 168 /*
 169  * free hardware resources used by driver
 170  */
 171 static void
 172 release_io_hfcpci(struct hfc_pci *hc)
 173 {
 174         /* disable memory mapped ports + busmaster */
 175         pci_write_config_word(hc->pdev, PCI_COMMAND, 0);
 176         del_timer(&hc->hw.timer);
 177         pci_free_consistent(hc->pdev, 0x8000, hc->hw.fifos, hc->hw.dmahandle);
 178         iounmap(hc->hw.pci_io);
 179 }
 180
 181 /*
 182  * set mode (NT or TE)
 183  */
 184 static void
 185 hfcpci_setmode(struct hfc_pci *hc)
 186 {
 187         if (hc->hw.protocol == ISDN_P_NT_S0) {
 188                 hc->hw.clkdel = CLKDEL_NT;      /* ST-Bit delay for NT-Mode */
 189                 hc->hw.sctrl |= SCTRL_MODE_NT;  /* NT-MODE */
 190                 hc->hw.states = 1;              /* G1 */
 191         } else {
 192                 hc->hw.clkdel = CLKDEL_TE;      /* ST-Bit delay for TE-Mode */
 193                 hc->hw.sctrl &= ~SCTRL_MODE_NT; /* TE-MODE */
 194                 hc->hw.states = 2;              /* F2 */
 195         }
 196         Write_hfc(hc, HFCPCI_CLKDEL, hc->hw.clkdel);
 197         Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | hc->hw.states);
 198         udelay(10);
 199         Write_hfc(hc, HFCPCI_STATES, hc->hw.states | 0x40); /* Deactivate */
 200         Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
 201 }
 202
 203 /*
 204  * function called to reset the HFC PCI chip. A complete software reset of chip
 205  * and fifos is done.
 206  */
 207 static void
 208 reset_hfcpci(struct hfc_pci *hc)
 209 {
 210         u_char  val;
 211         int     cnt = 0;
 212
 213         printk(KERN_DEBUG "reset_hfcpci: entered\n");
 214         val = Read_hfc(hc, HFCPCI_CHIP_ID);
 215         printk(KERN_INFO "HFC_PCI: resetting HFC ChipId(%x)\n", val);
 216         /* enable memory mapped ports, disable busmaster */
 217         pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
 218         disable_hwirq(hc);
 219         /* enable memory ports + busmaster */
 220         pci_write_config_word(hc->pdev, PCI_COMMAND,
 221             PCI_ENA_MEMIO + PCI_ENA_MASTER);
 222         val = Read_hfc(hc, HFCPCI_STATUS);
 223         printk(KERN_DEBUG "HFC-PCI status(%x) before reset\n", val);
 224         hc->hw.cirm = HFCPCI_RESET;     /* Reset On */
 225         Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
 226         set_current_state(TASK_UNINTERRUPTIBLE);
 227         mdelay(10);                     /* Timeout 10ms */
 228         hc->hw.cirm = 0;                /* Reset Off */
 229         Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
 230         val = Read_hfc(hc, HFCPCI_STATUS);
 231         printk(KERN_DEBUG "HFC-PCI status(%x) after reset\n", val);
 232         while (cnt < 50000) { /* max 50000 us */
 233                 udelay(5);
 234                 cnt += 5;
 235                 val = Read_hfc(hc, HFCPCI_STATUS);
 236                 if (!(val & 2))
 237                         break;
 238         }
 239         printk(KERN_DEBUG "HFC-PCI status(%x) after %dus\n", val, cnt);
 240
 241         hc->hw.fifo_en = 0x30;  /* only D fifos enabled */
 242
 243         hc->hw.bswapped = 0;    /* no exchange */
 244         hc->hw.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
 245         hc->hw.trm = HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */
 246         hc->hw.sctrl = 0x40;    /* set tx_lo mode, error in datasheet ! */
 247         hc->hw.sctrl_r = 0;
 248         hc->hw.sctrl_e = HFCPCI_AUTO_AWAKE;     /* S/T Auto awake */
 249         hc->hw.mst_m = 0;
 250         if (test_bit(HFC_CFG_MASTER, &hc->cfg))
 251                 hc->hw.mst_m |= HFCPCI_MASTER;  /* HFC Master Mode */
 252         if (test_bit(HFC_CFG_NEG_F0, &hc->cfg))
 253                 hc->hw.mst_m |= HFCPCI_F0_NEGATIV;
 254         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 255         Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
 256         Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
 257         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
 258
 259         hc->hw.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
 260             HFCPCI_INTS_L1STATE | HFCPCI_INTS_TIMER;
 261         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 262
 263         /* Clear already pending ints */
 264         if (Read_hfc(hc, HFCPCI_INT_S1));
 265
 266         /* set NT/TE mode */
 267         hfcpci_setmode(hc);
 268
 269         Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
 270         Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
 271
 272         /*
 273          * Init GCI/IOM2 in master mode
 274          * Slots 0 and 1 are set for B-chan 1 and 2
 275          * D- and monitor/CI channel are not enabled
 276          * STIO1 is used as output for data, B1+B2 from ST->IOM+HFC
 277          * STIO2 is used as data input, B1+B2 from IOM->ST
 278          * ST B-channel send disabled -> continous 1s
 279          * The IOM slots are always enabled
 280          */
 281         if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
 282                 /* set data flow directions: connect B1,B2: HFC to/from PCM */
 283                 hc->hw.conn = 0x09;
 284         } else {
 285                 hc->hw.conn = 0x36;     /* set data flow directions */
 286                 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
 287                         Write_hfc(hc, HFCPCI_B1_SSL, 0xC0);
 288                         Write_hfc(hc, HFCPCI_B2_SSL, 0xC1);
 289                         Write_hfc(hc, HFCPCI_B1_RSL, 0xC0);
 290                         Write_hfc(hc, HFCPCI_B2_RSL, 0xC1);
 291                 } else {
 292                         Write_hfc(hc, HFCPCI_B1_SSL, 0x80);
 293                         Write_hfc(hc, HFCPCI_B2_SSL, 0x81);
 294                         Write_hfc(hc, HFCPCI_B1_RSL, 0x80);
 295                         Write_hfc(hc, HFCPCI_B2_RSL, 0x81);
 296                 }
 297         }
 298         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
 299         val = Read_hfc(hc, HFCPCI_INT_S2);
 300 }
 301
 302 /*
 303  * Timer function called when kernel timer expires
 304  */
 305 static void
 306 hfcpci_Timer(struct hfc_pci *hc)
 307 {
 308         hc->hw.timer.expires = jiffies + 75;
 309         /* WD RESET */
 310 /*
 311  *      WriteReg(hc, HFCD_DATA, HFCD_CTMT, hc->hw.ctmt | 0x80);
 312  *      add_timer(&hc->hw.timer);
 313  */
 314 }
 315
 316
 317 /*
 318  * select a b-channel entry matching and active
 319  */
 320 static struct bchannel *
 321 Sel_BCS(struct hfc_pci *hc, int channel)
 322 {
 323         if (test_bit(FLG_ACTIVE, &hc->bch[0].Flags) &&
 324                 (hc->bch[0].nr & channel))
 325                 return &hc->bch[0];
 326         else if (test_bit(FLG_ACTIVE, &hc->bch[1].Flags) &&
 327                 (hc->bch[1].nr & channel))
 328                 return &hc->bch[1];
 329         else
 330                 return NULL;
 331 }
 332
 333 /*
 334  * clear the desired B-channel rx fifo
 335  */
 336 static void
 337 hfcpci_clear_fifo_rx(struct hfc_pci *hc, int fifo)
 338 {
 339         u_char          fifo_state;
 340         struct bzfifo   *bzr;
 341
 342         if (fifo) {
 343                 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
 344                 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2RX;
 345         } else {
 346                 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
 347                 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1RX;
 348         }
 349         if (fifo_state)
 350                 hc->hw.fifo_en ^= fifo_state;
 351         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 352         hc->hw.last_bfifo_cnt[fifo] = 0;
 353         bzr->f1 = MAX_B_FRAMES;
 354         bzr->f2 = bzr->f1;      /* init F pointers to remain constant */
 355         bzr->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
 356         bzr->za[MAX_B_FRAMES].z2 = cpu_to_le16(
 357             le16_to_cpu(bzr->za[MAX_B_FRAMES].z1));
 358         if (fifo_state)
 359                 hc->hw.fifo_en |= fifo_state;
 360         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 361 }
 362
 363 /*
 364  * clear the desired B-channel tx fifo
 365  */
 366 static void hfcpci_clear_fifo_tx(struct hfc_pci *hc, int fifo)
 367 {
 368         u_char          fifo_state;
 369         struct bzfifo   *bzt;
 370
 371         if (fifo) {
 372                 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
 373                 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2TX;
 374         } else {
 375                 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
 376                 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1TX;
 377         }
 378         if (fifo_state)
 379                 hc->hw.fifo_en ^= fifo_state;
 380         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 381         if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
 382                 printk(KERN_DEBUG "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) "
 383                     "z1(%x) z2(%x) state(%x)\n",
 384                     fifo, bzt->f1, bzt->f2,
 385                     le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
 386                     le16_to_cpu(bzt->za[MAX_B_FRAMES].z2),
 387                     fifo_state);
 388         bzt->f2 = MAX_B_FRAMES;
 389         bzt->f1 = bzt->f2;      /* init F pointers to remain constant */
 390         bzt->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
 391         bzt->za[MAX_B_FRAMES].z2 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 2);
 392         if (fifo_state)
 393                 hc->hw.fifo_en |= fifo_state;
 394         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 395         if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
 396                 printk(KERN_DEBUG
 397                     "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) z1(%x) z2(%x)\n",
 398                     fifo, bzt->f1, bzt->f2,
 399                     le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
 400                     le16_to_cpu(bzt->za[MAX_B_FRAMES].z2));
 401 }
 402
 403 /*
 404  * read a complete B-frame out of the buffer
 405  */
 406 static void
 407 hfcpci_empty_bfifo(struct bchannel *bch, struct bzfifo *bz,
 408     u_char *bdata, int count)
 409 {
 410         u_char          *ptr, *ptr1, new_f2;
 411         int             total, maxlen, new_z2;
 412         struct zt       *zp;
 413
 414         if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
 415                 printk(KERN_DEBUG "hfcpci_empty_fifo\n");
 416         zp = &bz->za[bz->f2];   /* point to Z-Regs */
 417         new_z2 = le16_to_cpu(zp->z2) + count;   /* new position in fifo */
 418         if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
 419                 new_z2 -= B_FIFO_SIZE;  /* buffer wrap */
 420         new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
 421         if ((count > MAX_DATA_SIZE + 3) || (count < 4) ||
 422             (*(bdata + (le16_to_cpu(zp->z1) - B_SUB_VAL)))) {
 423                 if (bch->debug & DEBUG_HW)
 424                         printk(KERN_DEBUG "hfcpci_empty_fifo: incoming packet "
 425                             "invalid length %d or crc\n", count);
 426 #ifdef ERROR_STATISTIC
 427                 bch->err_inv++;
 428 #endif
 429                 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
 430                 bz->f2 = new_f2;        /* next buffer */
 431         } else {
 432                 bch->rx_skb = mI_alloc_skb(count - 3, GFP_ATOMIC);
 433                 if (!bch->rx_skb) {
 434                         printk(KERN_WARNING "HFCPCI: receive out of memory\n");
 435                         return;
 436                 }
 437                 total = count;
 438                 count -= 3;
 439                 ptr = skb_put(bch->rx_skb, count);
 440
 441                 if (le16_to_cpu(zp->z2) + count <= B_FIFO_SIZE + B_SUB_VAL)
 442                         maxlen = count;         /* complete transfer */
 443                 else
 444                         maxlen = B_FIFO_SIZE + B_SUB_VAL -
 445                             le16_to_cpu(zp->z2);        /* maximum */
 446
 447                 ptr1 = bdata + (le16_to_cpu(zp->z2) - B_SUB_VAL);
 448                     /* start of data */
 449                 memcpy(ptr, ptr1, maxlen);      /* copy data */
 450                 count -= maxlen;
 451
 452                 if (count) {    /* rest remaining */
 453                         ptr += maxlen;
 454                         ptr1 = bdata;   /* start of buffer */
 455                         memcpy(ptr, ptr1, count);       /* rest */
 456                 }
 457                 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
 458                 bz->f2 = new_f2;        /* next buffer */
 459                 recv_Bchannel(bch);
 460         }
 461 }
 462
 463 /*
 464  * D-channel receive procedure
 465  */
 466 static int
 467 receive_dmsg(struct hfc_pci *hc)
 468 {
 469         struct dchannel *dch = &hc->dch;
 470         int             maxlen;
 471         int             rcnt, total;
 472         int             count = 5;
 473         u_char          *ptr, *ptr1;
 474         struct dfifo    *df;
 475         struct zt       *zp;
 476
 477         df = &((union fifo_area *)(hc->hw.fifos))->d_chan.d_rx;
 478         while (((df->f1 & D_FREG_MASK) != (df->f2 & D_FREG_MASK)) && count--) {
 479                 zp = &df->za[df->f2 & D_FREG_MASK];
 480                 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
 481                 if (rcnt < 0)
 482                         rcnt += D_FIFO_SIZE;
 483                 rcnt++;
 484                 if (dch->debug & DEBUG_HW_DCHANNEL)
 485                         printk(KERN_DEBUG
 486                             "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)\n",
 487                                 df->f1, df->f2,
 488                                 le16_to_cpu(zp->z1),
 489                                 le16_to_cpu(zp->z2),
 490                                 rcnt);
 491
 492                 if ((rcnt > MAX_DFRAME_LEN + 3) || (rcnt < 4) ||
 493                     (df->data[le16_to_cpu(zp->z1)])) {
 494                         if (dch->debug & DEBUG_HW)
 495                                 printk(KERN_DEBUG
 496                                     "empty_fifo hfcpci paket inv. len "
 497                                     "%d or crc %d\n",
 498                                     rcnt,
 499                                     df->data[le16_to_cpu(zp->z1)]);
 500 #ifdef ERROR_STATISTIC
 501                         cs->err_rx++;
 502 #endif
 503                         df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
 504                             (MAX_D_FRAMES + 1); /* next buffer */
 505                         df->za[df->f2 & D_FREG_MASK].z2 =
 506                             cpu_to_le16((le16_to_cpu(zp->z2) + rcnt) & (D_FIFO_SIZE - 1));
 507                 } else {
 508                         dch->rx_skb = mI_alloc_skb(rcnt - 3, GFP_ATOMIC);
 509                         if (!dch->rx_skb) {
 510                                 printk(KERN_WARNING
 511                                     "HFC-PCI: D receive out of memory\n");
 512                                 break;
 513                         }
 514                         total = rcnt;
 515                         rcnt -= 3;
 516                         ptr = skb_put(dch->rx_skb, rcnt);
 517
 518                         if (le16_to_cpu(zp->z2) + rcnt <= D_FIFO_SIZE)
 519                                 maxlen = rcnt;  /* complete transfer */
 520                         else
 521                                 maxlen = D_FIFO_SIZE - le16_to_cpu(zp->z2);
 522                                     /* maximum */
 523
 524                         ptr1 = df->data + le16_to_cpu(zp->z2);
 525                             /* start of data */
 526                         memcpy(ptr, ptr1, maxlen);      /* copy data */
 527                         rcnt -= maxlen;
 528
 529                         if (rcnt) {     /* rest remaining */
 530                                 ptr += maxlen;
 531                                 ptr1 = df->data;        /* start of buffer */
 532                                 memcpy(ptr, ptr1, rcnt);        /* rest */
 533                         }
 534                         df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
 535                             (MAX_D_FRAMES + 1); /* next buffer */
 536                         df->za[df->f2 & D_FREG_MASK].z2 = cpu_to_le16((
 537                             le16_to_cpu(zp->z2) + total) & (D_FIFO_SIZE - 1));
 538                         recv_Dchannel(dch);
 539                 }
 540         }
 541         return 1;
 542 }
 543
 544 /*
 545  * check for transparent receive data and read max one 'poll' size if avail
 546  */
 547 static void
 548 hfcpci_empty_fifo_trans(struct bchannel *bch, struct bzfifo *bz, u_char *bdata)
 549 {
 550          __le16 *z1r, *z2r;
 551         int             new_z2, fcnt, maxlen;
 552         u_char          *ptr, *ptr1;
 553
 554         z1r = &bz->za[MAX_B_FRAMES].z1;         /* pointer to z reg */
 555         z2r = z1r + 1;
 556
 557         fcnt = le16_to_cpu(*z1r) - le16_to_cpu(*z2r);
 558         if (!fcnt)
 559                 return; /* no data avail */
 560
 561         if (fcnt <= 0)
 562                 fcnt += B_FIFO_SIZE;    /* bytes actually buffered */
 563         new_z2 = le16_to_cpu(*z2r) + fcnt;      /* new position in fifo */
 564         if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
 565                 new_z2 -= B_FIFO_SIZE;  /* buffer wrap */
 566
 567         if (fcnt > MAX_DATA_SIZE) {     /* flush, if oversized */
 568                 *z2r = cpu_to_le16(new_z2);             /* new position */
 569                 return;
 570         }
 571
 572         bch->rx_skb = mI_alloc_skb(fcnt, GFP_ATOMIC);
 573         if (bch->rx_skb) {
 574                 ptr = skb_put(bch->rx_skb, fcnt);
 575                 if (le16_to_cpu(*z2r) + fcnt <= B_FIFO_SIZE + B_SUB_VAL)
 576                         maxlen = fcnt;  /* complete transfer */
 577                 else
 578                         maxlen = B_FIFO_SIZE + B_SUB_VAL - le16_to_cpu(*z2r);
 579                             /* maximum */
 580
 581                 ptr1 = bdata + (le16_to_cpu(*z2r) - B_SUB_VAL);
 582                     /* start of data */
 583                 memcpy(ptr, ptr1, maxlen);      /* copy data */
 584                 fcnt -= maxlen;
 585
 586                 if (fcnt) {     /* rest remaining */
 587                         ptr += maxlen;
 588                         ptr1 = bdata;   /* start of buffer */
 589                         memcpy(ptr, ptr1, fcnt);        /* rest */
 590                 }
 591                 recv_Bchannel(bch);
 592         } else
 593                 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
 594
 595         *z2r = cpu_to_le16(new_z2);             /* new position */
 596 }
 597
 598 /*
 599  * B-channel main receive routine
 600  */
 601 static void
 602 main_rec_hfcpci(struct bchannel *bch)
 603 {
 604         struct hfc_pci  *hc = bch->hw;
 605         int             rcnt, real_fifo;
 606         int             receive = 0, count = 5;
 607         struct bzfifo   *bz;
 608         u_char          *bdata;
 609         struct zt       *zp;
 610
 611         if ((bch->nr & 2) && (!hc->hw.bswapped)) {
 612                 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
 613                 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b2;
 614                 real_fifo = 1;
 615         } else {
 616                 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
 617                 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b1;
 618                 real_fifo = 0;
 619         }
 620 Begin:
 621         count--;
 622         if (bz->f1 != bz->f2) {
 623                 if (bch->debug & DEBUG_HW_BCHANNEL)
 624                         printk(KERN_DEBUG "hfcpci rec ch(%x) f1(%d) f2(%d)\n",
 625                             bch->nr, bz->f1, bz->f2);
 626                 zp = &bz->za[bz->f2];
 627
 628                 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
 629                 if (rcnt < 0)
 630                         rcnt += B_FIFO_SIZE;
 631                 rcnt++;
 632                 if (bch->debug & DEBUG_HW_BCHANNEL)
 633                         printk(KERN_DEBUG
 634                             "hfcpci rec ch(%x) z1(%x) z2(%x) cnt(%d)\n",
 635                             bch->nr, le16_to_cpu(zp->z1),
 636                             le16_to_cpu(zp->z2), rcnt);
 637                 hfcpci_empty_bfifo(bch, bz, bdata, rcnt);
 638                 rcnt = bz->f1 - bz->f2;
 639                 if (rcnt < 0)
 640                         rcnt += MAX_B_FRAMES + 1;
 641                 if (hc->hw.last_bfifo_cnt[real_fifo] > rcnt + 1) {
 642                         rcnt = 0;
 643                         hfcpci_clear_fifo_rx(hc, real_fifo);
 644                 }
 645                 hc->hw.last_bfifo_cnt[real_fifo] = rcnt;
 646                 if (rcnt > 1)
 647                         receive = 1;
 648                 else
 649                         receive = 0;
 650         } else if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
 651                 hfcpci_empty_fifo_trans(bch, bz, bdata);
 652                 return;
 653         } else
 654                 receive = 0;
 655         if (count && receive)
 656                 goto Begin;
 657
 658 }
 659
 660 /*
 661  * D-channel send routine
 662  */
 663 static void
 664 hfcpci_fill_dfifo(struct hfc_pci *hc)
 665 {
 666         struct dchannel *dch = &hc->dch;
 667         int             fcnt;
 668         int             count, new_z1, maxlen;
 669         struct dfifo    *df;
 670         u_char          *src, *dst, new_f1;
 671
 672         if ((dch->debug & DEBUG_HW_DCHANNEL) && !(dch->debug & DEBUG_HW_DFIFO))
 673                 printk(KERN_DEBUG "%s\n", __func__);
 674
 675         if (!dch->tx_skb)
 676                 return;
 677         count = dch->tx_skb->len - dch->tx_idx;
 678         if (count <= 0)
 679                 return;
 680         df = &((union fifo_area *) (hc->hw.fifos))->d_chan.d_tx;
 681
 682         if (dch->debug & DEBUG_HW_DFIFO)
 683                 printk(KERN_DEBUG "%s:f1(%d) f2(%d) z1(f1)(%x)\n", __func__,
 684                     df->f1, df->f2,
 685                     le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1));
 686         fcnt = df->f1 - df->f2; /* frame count actually buffered */
 687         if (fcnt < 0)
 688                 fcnt += (MAX_D_FRAMES + 1);     /* if wrap around */
 689         if (fcnt > (MAX_D_FRAMES - 1)) {
 690                 if (dch->debug & DEBUG_HW_DCHANNEL)
 691                         printk(KERN_DEBUG
 692                             "hfcpci_fill_Dfifo more as 14 frames\n");
 693 #ifdef ERROR_STATISTIC
 694                 cs->err_tx++;
 695 #endif
 696                 return;
 697         }
 698         /* now determine free bytes in FIFO buffer */
 699         maxlen = le16_to_cpu(df->za[df->f2 & D_FREG_MASK].z2) -
 700             le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) - 1;
 701         if (maxlen <= 0)
 702                 maxlen += D_FIFO_SIZE;  /* count now contains available bytes */
 703
 704         if (dch->debug & DEBUG_HW_DCHANNEL)
 705                 printk(KERN_DEBUG "hfcpci_fill_Dfifo count(%d/%d)\n",
 706                         count, maxlen);
 707         if (count > maxlen) {
 708                 if (dch->debug & DEBUG_HW_DCHANNEL)
 709                         printk(KERN_DEBUG "hfcpci_fill_Dfifo no fifo mem\n");
 710                 return;
 711         }
 712         new_z1 = (le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) + count) &
 713             (D_FIFO_SIZE - 1);
 714         new_f1 = ((df->f1 + 1) & D_FREG_MASK) | (D_FREG_MASK + 1);
 715         src = dch->tx_skb->data + dch->tx_idx;  /* source pointer */
 716         dst = df->data + le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
 717         maxlen = D_FIFO_SIZE - le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
 718             /* end fifo */
 719         if (maxlen > count)
 720                 maxlen = count; /* limit size */
 721         memcpy(dst, src, maxlen);       /* first copy */
 722
 723         count -= maxlen;        /* remaining bytes */
 724         if (count) {
 725                 dst = df->data; /* start of buffer */
 726                 src += maxlen;  /* new position */
 727                 memcpy(dst, src, count);
 728         }
 729         df->za[new_f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
 730             /* for next buffer */
 731         df->za[df->f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
 732             /* new pos actual buffer */
 733         df->f1 = new_f1;        /* next frame */
 734         dch->tx_idx = dch->tx_skb->len;
 735 }
 736
 737 /*
 738  * B-channel send routine
 739  */
 740 static void
 741 hfcpci_fill_fifo(struct bchannel *bch)
 742 {
 743         struct hfc_pci  *hc = bch->hw;
 744         int             maxlen, fcnt;
 745         int             count, new_z1;
 746         struct bzfifo   *bz;
 747         u_char          *bdata;
 748         u_char          new_f1, *src, *dst;
 749         __le16 *z1t, *z2t;
 750
 751         if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
 752                 printk(KERN_DEBUG "%s\n", __func__);
 753         if ((!bch->tx_skb) || bch->tx_skb->len <= 0)
 754                 return;
 755         count = bch->tx_skb->len - bch->tx_idx;
 756         if ((bch->nr & 2) && (!hc->hw.bswapped)) {
 757                 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
 758                 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b2;
 759         } else {
 760                 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
 761                 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b1;
 762         }
 763
 764         if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
 765                 z1t = &bz->za[MAX_B_FRAMES].z1;
 766                 z2t = z1t + 1;
 767                 if (bch->debug & DEBUG_HW_BCHANNEL)
 768                         printk(KERN_DEBUG "hfcpci_fill_fifo_trans ch(%x) "
 769                             "cnt(%d) z1(%x) z2(%x)\n", bch->nr, count,
 770                             le16_to_cpu(*z1t), le16_to_cpu(*z2t));
 771                 fcnt = le16_to_cpu(*z2t) - le16_to_cpu(*z1t);
 772                 if (fcnt <= 0)
 773                         fcnt += B_FIFO_SIZE;
 774                             /* fcnt contains available bytes in fifo */
 775                 fcnt = B_FIFO_SIZE - fcnt;
 776                     /* remaining bytes to send (bytes in fifo) */
 777
 778                 /* "fill fifo if empty" feature */
 779                 if (test_bit(FLG_FILLEMPTY, &bch->Flags) && !fcnt) {
 780                         /* printk(KERN_DEBUG "%s: buffer empty, so we have "
 781                                 "underrun\n", __func__); */
 782                         /* fill buffer, to prevent future underrun */
 783                         count = HFCPCI_FILLEMPTY;
 784                         new_z1 = le16_to_cpu(*z1t) + count;
 785                            /* new buffer Position */
 786                         if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
 787                                 new_z1 -= B_FIFO_SIZE;  /* buffer wrap */
 788                         dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
 789                         maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
 790                             /* end of fifo */
 791                         if (bch->debug & DEBUG_HW_BFIFO)
 792                                 printk(KERN_DEBUG "hfcpci_FFt fillempty "
 793                                     "fcnt(%d) maxl(%d) nz1(%x) dst(%p)\n",
 794                                     fcnt, maxlen, new_z1, dst);
 795                         fcnt += count;
 796                         if (maxlen > count)
 797                                 maxlen = count;         /* limit size */
 798                         memset(dst, 0x2a, maxlen);      /* first copy */
 799                         count -= maxlen;                /* remaining bytes */
 800                         if (count) {
 801                                 dst = bdata;            /* start of buffer */
 802                                 memset(dst, 0x2a, count);
 803                         }
 804                         *z1t = cpu_to_le16(new_z1);     /* now send data */
 805                 }
 806
 807 next_t_frame:
 808                 count = bch->tx_skb->len - bch->tx_idx;
 809                 /* maximum fill shall be poll*2 */
 810                 if (count > (poll << 1) - fcnt)
 811                         count = (poll << 1) - fcnt;
 812                 if (count <= 0)
 813                         return;
 814                 /* data is suitable for fifo */
 815                 new_z1 = le16_to_cpu(*z1t) + count;
 816                     /* new buffer Position */
 817                 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
 818                         new_z1 -= B_FIFO_SIZE;  /* buffer wrap */
 819                 src = bch->tx_skb->data + bch->tx_idx;
 820                     /* source pointer */
 821                 dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
 822                 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
 823                     /* end of fifo */
 824                 if (bch->debug & DEBUG_HW_BFIFO)
 825                         printk(KERN_DEBUG "hfcpci_FFt fcnt(%d) "
 826                             "maxl(%d) nz1(%x) dst(%p)\n",
 827                             fcnt, maxlen, new_z1, dst);
 828                 fcnt += count;
 829                 bch->tx_idx += count;
 830                 if (maxlen > count)
 831                         maxlen = count;         /* limit size */
 832                 memcpy(dst, src, maxlen);       /* first copy */
 833                 count -= maxlen;        /* remaining bytes */
 834                 if (count) {
 835                         dst = bdata;    /* start of buffer */
 836                         src += maxlen;  /* new position */
 837                         memcpy(dst, src, count);
 838                 }
 839                 *z1t = cpu_to_le16(new_z1);     /* now send data */
 840                 if (bch->tx_idx < bch->tx_skb->len)
 841                         return;
 842                 /* send confirm, on trans, free on hdlc. */
 843                 if (test_bit(FLG_TRANSPARENT, &bch->Flags))
 844                         confirm_Bsend(bch);
 845                 dev_kfree_skb(bch->tx_skb);
 846                 if (get_next_bframe(bch))
 847                         goto next_t_frame;
 848                 return;
 849         }
 850         if (bch->debug & DEBUG_HW_BCHANNEL)
 851                 printk(KERN_DEBUG
 852                     "%s: ch(%x) f1(%d) f2(%d) z1(f1)(%x)\n",
 853                     __func__, bch->nr, bz->f1, bz->f2,
 854                     bz->za[bz->f1].z1);
 855         fcnt = bz->f1 - bz->f2; /* frame count actually buffered */
 856         if (fcnt < 0)
 857                 fcnt += (MAX_B_FRAMES + 1);     /* if wrap around */
 858         if (fcnt > (MAX_B_FRAMES - 1)) {
 859                 if (bch->debug & DEBUG_HW_BCHANNEL)
 860                         printk(KERN_DEBUG
 861                             "hfcpci_fill_Bfifo more as 14 frames\n");
 862                 return;
 863         }
 864         /* now determine free bytes in FIFO buffer */
 865         maxlen = le16_to_cpu(bz->za[bz->f2].z2) -
 866             le16_to_cpu(bz->za[bz->f1].z1) - 1;
 867         if (maxlen <= 0)
 868                 maxlen += B_FIFO_SIZE;  /* count now contains available bytes */
 869
 870         if (bch->debug & DEBUG_HW_BCHANNEL)
 871                 printk(KERN_DEBUG "hfcpci_fill_fifo ch(%x) count(%d/%d)\n",
 872                         bch->nr, count, maxlen);
 873
 874         if (maxlen < count) {
 875                 if (bch->debug & DEBUG_HW_BCHANNEL)
 876                         printk(KERN_DEBUG "hfcpci_fill_fifo no fifo mem\n");
 877                 return;
 878         }
 879         new_z1 = le16_to_cpu(bz->za[bz->f1].z1) + count;
 880             /* new buffer Position */
 881         if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
 882                 new_z1 -= B_FIFO_SIZE;  /* buffer wrap */
 883
 884         new_f1 = ((bz->f1 + 1) & MAX_B_FRAMES);
 885         src = bch->tx_skb->data + bch->tx_idx;  /* source pointer */
 886         dst = bdata + (le16_to_cpu(bz->za[bz->f1].z1) - B_SUB_VAL);
 887         maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(bz->za[bz->f1].z1);
 888             /* end fifo */
 889         if (maxlen > count)
 890                 maxlen = count; /* limit size */
 891         memcpy(dst, src, maxlen);       /* first copy */
 892
 893         count -= maxlen;        /* remaining bytes */
 894         if (count) {
 895                 dst = bdata;    /* start of buffer */
 896                 src += maxlen;  /* new position */
 897                 memcpy(dst, src, count);
 898         }
 899         bz->za[new_f1].z1 = cpu_to_le16(new_z1);        /* for next buffer */
 900         bz->f1 = new_f1;        /* next frame */
 901         dev_kfree_skb(bch->tx_skb);
 902         get_next_bframe(bch);
 903 }
 904
 905
 906
 907 /*
 908  * handle L1 state changes TE
 909  */
 910
 911 static void
 912 ph_state_te(struct dchannel *dch)
 913 {
 914         if (dch->debug)
 915                 printk(KERN_DEBUG "%s: TE newstate %x\n",
 916                         __func__, dch->state);
 917         switch (dch->state) {
 918         case 0:
 919                 l1_event(dch->l1, HW_RESET_IND);
 920                 break;
 921         case 3:
 922                 l1_event(dch->l1, HW_DEACT_IND);
 923                 break;
 924         case 5:
 925         case 8:
 926                 l1_event(dch->l1, ANYSIGNAL);
 927                 break;
 928         case 6:
 929                 l1_event(dch->l1, INFO2);
 930                 break;
 931         case 7:
 932                 l1_event(dch->l1, INFO4_P8);
 933                 break;
 934         }
 935 }
 936
 937 /*
 938  * handle L1 state changes NT
 939  */
 940
 941 static void
 942 handle_nt_timer3(struct dchannel *dch) {
 943         struct hfc_pci  *hc = dch->hw;
 944
 945         test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
 946         hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
 947         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 948         hc->hw.nt_timer = 0;
 949         test_and_set_bit(FLG_ACTIVE, &dch->Flags);
 950         if (test_bit(HFC_CFG_MASTER, &hc->cfg))
 951                 hc->hw.mst_m |= HFCPCI_MASTER;
 952         Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
 953         _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
 954             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
 955 }
 956
 957 static void
 958 ph_state_nt(struct dchannel *dch)
 959 {
 960         struct hfc_pci  *hc = dch->hw;
 961
 962         if (dch->debug)
 963                 printk(KERN_DEBUG "%s: NT newstate %x\n",
 964                         __func__, dch->state);
 965         switch (dch->state) {
 966         case 2:
 967                 if (hc->hw.nt_timer < 0) {
 968                         hc->hw.nt_timer = 0;
 969                         test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
 970                         test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
 971                         hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
 972                         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 973                         /* Clear already pending ints */
 974                         if (Read_hfc(hc, HFCPCI_INT_S1));
 975                         Write_hfc(hc, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
 976                         udelay(10);
 977                         Write_hfc(hc, HFCPCI_STATES, 4);
 978                         dch->state = 4;
 979                 } else if (hc->hw.nt_timer == 0) {
 980                         hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
 981                         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 982                         hc->hw.nt_timer = NT_T1_COUNT;
 983                         hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
 984                         hc->hw.ctmt |= HFCPCI_TIM3_125;
 985                         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
 986                                 HFCPCI_CLTIMER);
 987                         test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
 988                         test_and_set_bit(FLG_HFC_TIMER_T1, &dch->Flags);
 989                         /* allow G2 -> G3 transition */
 990                         Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
 991                 } else {
 992                         Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
 993                 }
 994                 break;
 995         case 1:
 996                 hc->hw.nt_timer = 0;
 997                 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
 998                 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
 999                 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1000                 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1001                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
1002                 hc->hw.mst_m &= ~HFCPCI_MASTER;
1003                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1004                 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1005                 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
1006                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
1007                 break;
1008         case 4:
1009                 hc->hw.nt_timer = 0;
1010                 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
1011                 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1012                 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1013                 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1014                 break;
1015         case 3:
1016                 if (!test_and_set_bit(FLG_HFC_TIMER_T3, &dch->Flags)) {
1017                         if (!test_and_clear_bit(FLG_L2_ACTIVATED,
1018                             &dch->Flags)) {
1019                                 handle_nt_timer3(dch);
1020                                 break;
1021                         }
1022                         test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1023                         hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
1024                         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1025                         hc->hw.nt_timer = NT_T3_COUNT;
1026                         hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
1027                         hc->hw.ctmt |= HFCPCI_TIM3_125;
1028                         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
1029                                 HFCPCI_CLTIMER);
1030                 }
1031                 break;
1032         }
1033 }
1034
1035 static void
1036 ph_state(struct dchannel *dch)
1037 {
1038         struct hfc_pci  *hc = dch->hw;
1039
1040         if (hc->hw.protocol == ISDN_P_NT_S0) {
1041                 if (test_bit(FLG_HFC_TIMER_T3, &dch->Flags) &&
1042                     hc->hw.nt_timer < 0)
1043                         handle_nt_timer3(dch);
1044                 else
1045                         ph_state_nt(dch);
1046         } else
1047                 ph_state_te(dch);
1048 }
1049
1050 /*
1051  * Layer 1 callback function
1052  */
1053 static int
1054 hfc_l1callback(struct dchannel *dch, u_int cmd)
1055 {
1056         struct hfc_pci          *hc = dch->hw;
1057
1058         switch (cmd) {
1059         case INFO3_P8:
1060         case INFO3_P10:
1061                 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1062                         hc->hw.mst_m |= HFCPCI_MASTER;
1063                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1064                 break;
1065         case HW_RESET_REQ:
1066                 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3);
1067                 /* HFC ST 3 */
1068                 udelay(6);
1069                 Write_hfc(hc, HFCPCI_STATES, 3);        /* HFC ST 2 */
1070                 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1071                         hc->hw.mst_m |= HFCPCI_MASTER;
1072                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1073                 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1074                    HFCPCI_DO_ACTION);
1075                 l1_event(dch->l1, HW_POWERUP_IND);
1076                 break;
1077         case HW_DEACT_REQ:
1078                 hc->hw.mst_m &= ~HFCPCI_MASTER;
1079                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1080                 skb_queue_purge(&dch->squeue);
1081                 if (dch->tx_skb) {
1082                         dev_kfree_skb(dch->tx_skb);
1083                         dch->tx_skb = NULL;
1084                 }
1085                 dch->tx_idx = 0;
1086                 if (dch->rx_skb) {
1087                         dev_kfree_skb(dch->rx_skb);
1088                         dch->rx_skb = NULL;
1089                 }
1090                 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1091                 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1092                         del_timer(&dch->timer);
1093                 break;
1094         case HW_POWERUP_REQ:
1095                 Write_hfc(hc, HFCPCI_STATES, HFCPCI_DO_ACTION);
1096                 break;
1097         case PH_ACTIVATE_IND:
1098                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
1099                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1100                         GFP_ATOMIC);
1101                 break;
1102         case PH_DEACTIVATE_IND:
1103                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
1104                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1105                         GFP_ATOMIC);
1106                 break;
1107         default:
1108                 if (dch->debug & DEBUG_HW)
1109                         printk(KERN_DEBUG "%s: unknown command %x\n",
1110                             __func__, cmd);
1111                 return -1;
1112         }
1113         return 0;
1114 }
1115
1116 /*
1117  * Interrupt handler
1118  */
1119 static inline void
1120 tx_birq(struct bchannel *bch)
1121 {
1122         if (bch->tx_skb && bch->tx_idx < bch->tx_skb->len)
1123                 hfcpci_fill_fifo(bch);
1124         else {
1125                 if (bch->tx_skb)
1126                         dev_kfree_skb(bch->tx_skb);
1127                 if (get_next_bframe(bch))
1128                         hfcpci_fill_fifo(bch);
1129         }
1130 }
1131
1132 static inline void
1133 tx_dirq(struct dchannel *dch)
1134 {
1135         if (dch->tx_skb && dch->tx_idx < dch->tx_skb->len)
1136                 hfcpci_fill_dfifo(dch->hw);
1137         else {
1138                 if (dch->tx_skb)
1139                         dev_kfree_skb(dch->tx_skb);
1140                 if (get_next_dframe(dch))
1141                         hfcpci_fill_dfifo(dch->hw);
1142         }
1143 }
1144
1145 static irqreturn_t
1146 hfcpci_int(int intno, void *dev_id)
1147 {
1148         struct hfc_pci  *hc = dev_id;
1149         u_char          exval;
1150         struct bchannel *bch;
1151         u_char          val, stat;
1152
1153         spin_lock(&hc->lock);
1154         if (!(hc->hw.int_m2 & 0x08)) {
1155                 spin_unlock(&hc->lock);
1156                 return IRQ_NONE; /* not initialised */
1157         }
1158         stat = Read_hfc(hc, HFCPCI_STATUS);
1159         if (HFCPCI_ANYINT & stat) {
1160                 val = Read_hfc(hc, HFCPCI_INT_S1);
1161                 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1162                         printk(KERN_DEBUG
1163                             "HFC-PCI: stat(%02x) s1(%02x)\n", stat, val);
1164         } else {
1165                 /* shared */
1166                 spin_unlock(&hc->lock);
1167                 return IRQ_NONE;
1168         }
1169         hc->irqcnt++;
1170
1171         if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1172                 printk(KERN_DEBUG "HFC-PCI irq %x\n", val);
1173         val &= hc->hw.int_m1;
1174         if (val & 0x40) {       /* state machine irq */
1175                 exval = Read_hfc(hc, HFCPCI_STATES) & 0xf;
1176                 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1177                         printk(KERN_DEBUG "ph_state chg %d->%d\n",
1178                                 hc->dch.state, exval);
1179                 hc->dch.state = exval;
1180                 schedule_event(&hc->dch, FLG_PHCHANGE);
1181                 val &= ~0x40;
1182         }
1183         if (val & 0x80) {       /* timer irq */
1184                 if (hc->hw.protocol == ISDN_P_NT_S0) {
1185                         if ((--hc->hw.nt_timer) < 0)
1186                                 schedule_event(&hc->dch, FLG_PHCHANGE);
1187                 }
1188                 val &= ~0x80;
1189                 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt | HFCPCI_CLTIMER);
1190         }
1191         if (val & 0x08) {       /* B1 rx */
1192                 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1193                 if (bch)
1194                         main_rec_hfcpci(bch);
1195                 else if (hc->dch.debug)
1196                         printk(KERN_DEBUG "hfcpci spurious 0x08 IRQ\n");
1197         }
1198         if (val & 0x10) {       /* B2 rx */
1199                 bch = Sel_BCS(hc, 2);
1200                 if (bch)
1201                         main_rec_hfcpci(bch);
1202                 else if (hc->dch.debug)
1203                         printk(KERN_DEBUG "hfcpci spurious 0x10 IRQ\n");
1204         }
1205         if (val & 0x01) {       /* B1 tx */
1206                 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1207                 if (bch)
1208                         tx_birq(bch);
1209                 else if (hc->dch.debug)
1210                         printk(KERN_DEBUG "hfcpci spurious 0x01 IRQ\n");
1211         }
1212         if (val & 0x02) {       /* B2 tx */
1213                 bch = Sel_BCS(hc, 2);
1214                 if (bch)
1215                         tx_birq(bch);
1216                 else if (hc->dch.debug)
1217                         printk(KERN_DEBUG "hfcpci spurious 0x02 IRQ\n");
1218         }
1219         if (val & 0x20)         /* D rx */
1220                 receive_dmsg(hc);
1221         if (val & 0x04) {       /* D tx */
1222                 if (test_and_clear_bit(FLG_BUSY_TIMER, &hc->dch.Flags))
1223                         del_timer(&hc->dch.timer);
1224                 tx_dirq(&hc->dch);
1225         }
1226         spin_unlock(&hc->lock);
1227         return IRQ_HANDLED;
1228 }
1229
1230 static void
1231 hfcpci_softirq(void *arg)
1232 {
1233         u_long          flags;
1234         struct bchannel *bch;
1235         struct hfc_pci  *hc;
1236
1237         write_lock_irqsave(&HFClock, flags);
1238         list_for_each_entry(hc, &HFClist, list) {
1239                 if (hc->hw.int_m2 & HFCPCI_IRQ_ENABLE) {
1240                         spin_lock(&hc->lock);
1241                         bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1242                         if (bch && bch->state == ISDN_P_B_RAW) { /* B1 rx&tx */
1243                                 main_rec_hfcpci(bch);
1244                                 tx_birq(bch);
1245                         }
1246                         bch = Sel_BCS(hc, hc->hw.bswapped ? 1 : 2);
1247                         if (bch && bch->state == ISDN_P_B_RAW) { /* B2 rx&tx */
1248                                 main_rec_hfcpci(bch);
1249                                 tx_birq(bch);
1250                         }
1251                         spin_unlock(&hc->lock);
1252                 }
1253         }
1254         write_unlock_irqrestore(&HFClock, flags);
1255
1256         /* if next event would be in the past ... */
1257         if ((s32)(hfc_jiffies + tics - jiffies) <= 0)
1258                 hfc_jiffies = jiffies + 1;
1259         else
1260                 hfc_jiffies += tics;
1261         hfc_tl.expires = hfc_jiffies;
1262         add_timer(&hfc_tl);
1263 }
1264
1265 /*
1266  * timer callback for D-chan busy resolution. Currently no function
1267  */
1268 static void
1269 hfcpci_dbusy_timer(struct hfc_pci *hc)
1270 {
1271 }
1272
1273 /*
1274  * activate/deactivate hardware for selected channels and mode
1275  */
1276 static int
1277 mode_hfcpci(struct bchannel *bch, int bc, int protocol)
1278 {
1279         struct hfc_pci  *hc = bch->hw;
1280         int             fifo2;
1281         u_char          rx_slot = 0, tx_slot = 0, pcm_mode;
1282
1283         if (bch->debug & DEBUG_HW_BCHANNEL)
1284                 printk(KERN_DEBUG
1285                     "HFCPCI bchannel protocol %x-->%x ch %x-->%x\n",
1286                     bch->state, protocol, bch->nr, bc);
1287
1288         fifo2 = bc;
1289         pcm_mode = (bc>>24) & 0xff;
1290         if (pcm_mode) { /* PCM SLOT USE */
1291                 if (!test_bit(HFC_CFG_PCM, &hc->cfg))
1292                         printk(KERN_WARNING
1293                             "%s: pcm channel id without HFC_CFG_PCM\n",
1294                             __func__);
1295                 rx_slot = (bc>>8) & 0xff;
1296                 tx_slot = (bc>>16) & 0xff;
1297                 bc = bc & 0xff;
1298         } else if (test_bit(HFC_CFG_PCM, &hc->cfg) &&
1299             (protocol > ISDN_P_NONE))
1300                 printk(KERN_WARNING "%s: no pcm channel id but HFC_CFG_PCM\n",
1301                     __func__);
1302         if (hc->chanlimit > 1) {
1303                 hc->hw.bswapped = 0;    /* B1 and B2 normal mode */
1304                 hc->hw.sctrl_e &= ~0x80;
1305         } else {
1306                 if (bc & 2) {
1307                         if (protocol != ISDN_P_NONE) {
1308                                 hc->hw.bswapped = 1; /* B1 and B2 exchanged */
1309                                 hc->hw.sctrl_e |= 0x80;
1310                         } else {
1311                                 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1312                                 hc->hw.sctrl_e &= ~0x80;
1313                         }
1314                         fifo2 = 1;
1315                 } else {
1316                         hc->hw.bswapped = 0;    /* B1 and B2 normal mode */
1317                         hc->hw.sctrl_e &= ~0x80;
1318                 }
1319         }
1320         switch (protocol) {
1321         case (-1): /* used for init */
1322                 bch->state = -1;
1323                 bch->nr = bc;
1324         case (ISDN_P_NONE):
1325                 if (bch->state == ISDN_P_NONE)
1326                         return 0;
1327                 if (bc & 2) {
1328                         hc->hw.sctrl &= ~SCTRL_B2_ENA;
1329                         hc->hw.sctrl_r &= ~SCTRL_B2_ENA;
1330                 } else {
1331                         hc->hw.sctrl &= ~SCTRL_B1_ENA;
1332                         hc->hw.sctrl_r &= ~SCTRL_B1_ENA;
1333                 }
1334                 if (fifo2 & 2) {
1335                         hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B2;
1336                         hc->hw.int_m1 &= ~(HFCPCI_INTS_B2TRANS +
1337                                 HFCPCI_INTS_B2REC);
1338                 } else {
1339                         hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B1;
1340                         hc->hw.int_m1 &= ~(HFCPCI_INTS_B1TRANS +
1341                                 HFCPCI_INTS_B1REC);
1342                 }
1343 #ifdef REVERSE_BITORDER
1344                 if (bch->nr & 2)
1345                         hc->hw.cirm &= 0x7f;
1346                 else
1347                         hc->hw.cirm &= 0xbf;
1348 #endif
1349                 bch->state = ISDN_P_NONE;
1350                 bch->nr = bc;
1351                 test_and_clear_bit(FLG_HDLC, &bch->Flags);
1352                 test_and_clear_bit(FLG_TRANSPARENT, &bch->Flags);
1353                 break;
1354         case (ISDN_P_B_RAW):
1355                 bch->state = protocol;
1356                 bch->nr = bc;
1357                 hfcpci_clear_fifo_rx(hc, (fifo2 & 2)?1:0);
1358                 hfcpci_clear_fifo_tx(hc, (fifo2 & 2)?1:0);
1359                 if (bc & 2) {
1360                         hc->hw.sctrl |= SCTRL_B2_ENA;
1361                         hc->hw.sctrl_r |= SCTRL_B2_ENA;
1362 #ifdef REVERSE_BITORDER
1363                         hc->hw.cirm |= 0x80;
1364 #endif
1365                 } else {
1366                         hc->hw.sctrl |= SCTRL_B1_ENA;
1367                         hc->hw.sctrl_r |= SCTRL_B1_ENA;
1368 #ifdef REVERSE_BITORDER
1369                         hc->hw.cirm |= 0x40;
1370 #endif
1371                 }
1372                 if (fifo2 & 2) {
1373                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1374                         if (!tics)
1375                                 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS +
1376                                     HFCPCI_INTS_B2REC);
1377                         hc->hw.ctmt |= 2;
1378                         hc->hw.conn &= ~0x18;
1379                 } else {
1380                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1381                         if (!tics)
1382                                 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS +
1383                                     HFCPCI_INTS_B1REC);
1384                         hc->hw.ctmt |= 1;
1385                         hc->hw.conn &= ~0x03;
1386                 }
1387                 test_and_set_bit(FLG_TRANSPARENT, &bch->Flags);
1388                 break;
1389         case (ISDN_P_B_HDLC):
1390                 bch->state = protocol;
1391                 bch->nr = bc;
1392                 hfcpci_clear_fifo_rx(hc, (fifo2 & 2)?1:0);
1393                 hfcpci_clear_fifo_tx(hc, (fifo2 & 2)?1:0);
1394                 if (bc & 2) {
1395                         hc->hw.sctrl |= SCTRL_B2_ENA;
1396                         hc->hw.sctrl_r |= SCTRL_B2_ENA;
1397                 } else {
1398                         hc->hw.sctrl |= SCTRL_B1_ENA;
1399                         hc->hw.sctrl_r |= SCTRL_B1_ENA;
1400                 }
1401                 if (fifo2 & 2) {
1402                         hc->hw.last_bfifo_cnt[1] = 0;
1403                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1404                         hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS +
1405                             HFCPCI_INTS_B2REC);
1406                         hc->hw.ctmt &= ~2;
1407                         hc->hw.conn &= ~0x18;
1408                 } else {
1409                         hc->hw.last_bfifo_cnt[0] = 0;
1410                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1411                         hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS +
1412                             HFCPCI_INTS_B1REC);
1413                         hc->hw.ctmt &= ~1;
1414                         hc->hw.conn &= ~0x03;
1415                 }
1416                 test_and_set_bit(FLG_HDLC, &bch->Flags);
1417                 break;
1418         default:
1419                 printk(KERN_DEBUG "prot not known %x\n", protocol);
1420                 return -ENOPROTOOPT;
1421         }
1422         if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
1423                 if ((protocol == ISDN_P_NONE) ||
1424                         (protocol == -1)) {     /* init case */
1425                         rx_slot = 0;
1426                         tx_slot = 0;
1427                 } else {
1428                         if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
1429                                 rx_slot |= 0xC0;
1430                                 tx_slot |= 0xC0;
1431                         } else {
1432                                 rx_slot |= 0x80;
1433                                 tx_slot |= 0x80;
1434                         }
1435                 }
1436                 if (bc & 2) {
1437                         hc->hw.conn &= 0xc7;
1438                         hc->hw.conn |= 0x08;
1439                         printk(KERN_DEBUG "%s: Write_hfc: B2_SSL 0x%x\n",
1440                                 __func__, tx_slot);
1441                         printk(KERN_DEBUG "%s: Write_hfc: B2_RSL 0x%x\n",
1442                                 __func__, rx_slot);
1443                         Write_hfc(hc, HFCPCI_B2_SSL, tx_slot);
1444                         Write_hfc(hc, HFCPCI_B2_RSL, rx_slot);
1445                 } else {
1446                         hc->hw.conn &= 0xf8;
1447                         hc->hw.conn |= 0x01;
1448                         printk(KERN_DEBUG "%s: Write_hfc: B1_SSL 0x%x\n",
1449                                 __func__, tx_slot);
1450                         printk(KERN_DEBUG "%s: Write_hfc: B1_RSL 0x%x\n",
1451                                 __func__, rx_slot);
1452                         Write_hfc(hc, HFCPCI_B1_SSL, tx_slot);
1453                         Write_hfc(hc, HFCPCI_B1_RSL, rx_slot);
1454                 }
1455         }
1456         Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
1457         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1458         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1459         Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
1460         Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1461         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1462         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1463 #ifdef REVERSE_BITORDER
1464         Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1465 #endif
1466         return 0;
1467 }
1468
1469 static int
1470 set_hfcpci_rxtest(struct bchannel *bch, int protocol, int chan)
1471 {
1472         struct hfc_pci  *hc = bch->hw;
1473
1474         if (bch->debug & DEBUG_HW_BCHANNEL)
1475                 printk(KERN_DEBUG
1476                     "HFCPCI bchannel test rx protocol %x-->%x ch %x-->%x\n",
1477                     bch->state, protocol, bch->nr, chan);
1478         if (bch->nr != chan) {
1479                 printk(KERN_DEBUG
1480                     "HFCPCI rxtest wrong channel parameter %x/%x\n",
1481                     bch->nr, chan);
1482                 return -EINVAL;
1483         }
1484         switch (protocol) {
1485         case (ISDN_P_B_RAW):
1486                 bch->state = protocol;
1487                 hfcpci_clear_fifo_rx(hc, (chan & 2)?1:0);
1488                 if (chan & 2) {
1489                         hc->hw.sctrl_r |= SCTRL_B2_ENA;
1490                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1491                         if (!tics)
1492                                 hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1493                         hc->hw.ctmt |= 2;
1494                         hc->hw.conn &= ~0x18;
1495 #ifdef REVERSE_BITORDER
1496                         hc->hw.cirm |= 0x80;
1497 #endif
1498                 } else {
1499                         hc->hw.sctrl_r |= SCTRL_B1_ENA;
1500                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1501                         if (!tics)
1502                                 hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1503                         hc->hw.ctmt |= 1;
1504                         hc->hw.conn &= ~0x03;
1505 #ifdef REVERSE_BITORDER
1506                         hc->hw.cirm |= 0x40;
1507 #endif
1508                 }
1509                 break;
1510         case (ISDN_P_B_HDLC):
1511                 bch->state = protocol;
1512                 hfcpci_clear_fifo_rx(hc, (chan & 2)?1:0);
1513                 if (chan & 2) {
1514                         hc->hw.sctrl_r |= SCTRL_B2_ENA;
1515                         hc->hw.last_bfifo_cnt[1] = 0;
1516                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1517                         hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1518                         hc->hw.ctmt &= ~2;
1519                         hc->hw.conn &= ~0x18;
1520                 } else {
1521                         hc->hw.sctrl_r |= SCTRL_B1_ENA;
1522                         hc->hw.last_bfifo_cnt[0] = 0;
1523                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1524                         hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1525                         hc->hw.ctmt &= ~1;
1526                         hc->hw.conn &= ~0x03;
1527                 }
1528                 break;
1529         default:
1530                 printk(KERN_DEBUG "prot not known %x\n", protocol);
1531                 return -ENOPROTOOPT;
1532         }
1533         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1534         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1535         Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1536         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1537         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1538 #ifdef REVERSE_BITORDER
1539         Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1540 #endif
1541         return 0;
1542 }
1543
1544 static void
1545 deactivate_bchannel(struct bchannel *bch)
1546 {
1547         struct hfc_pci  *hc = bch->hw;
1548         u_long          flags;
1549
1550         spin_lock_irqsave(&hc->lock, flags);
1551         if (test_and_clear_bit(FLG_TX_NEXT, &bch->Flags)) {
1552                 dev_kfree_skb(bch->next_skb);
1553                 bch->next_skb = NULL;
1554         }
1555         if (bch->tx_skb) {
1556                 dev_kfree_skb(bch->tx_skb);
1557                 bch->tx_skb = NULL;
1558         }
1559         bch->tx_idx = 0;
1560         if (bch->rx_skb) {
1561                 dev_kfree_skb(bch->rx_skb);
1562                 bch->rx_skb = NULL;
1563         }
1564         mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1565         test_and_clear_bit(FLG_ACTIVE, &bch->Flags);
1566         test_and_clear_bit(FLG_TX_BUSY, &bch->Flags);
1567         spin_unlock_irqrestore(&hc->lock, flags);
1568 }
1569
1570 /*
1571  * Layer 1 B-channel hardware access
1572  */
1573 static int
1574 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
1575 {
1576         int     ret = 0;
1577
1578         switch (cq->op) {
1579         case MISDN_CTRL_GETOP:
1580                 cq->op = MISDN_CTRL_FILL_EMPTY;
1581                 break;
1582         case MISDN_CTRL_FILL_EMPTY: /* fill fifo, if empty */
1583                 test_and_set_bit(FLG_FILLEMPTY, &bch->Flags);
1584                 if (debug & DEBUG_HW_OPEN)
1585                         printk(KERN_DEBUG "%s: FILL_EMPTY request (nr=%d "
1586                                 "off=%d)\n", __func__, bch->nr, !!cq->p1);
1587                 break;
1588         default:
1589                 printk(KERN_WARNING "%s: unknown Op %x\n", __func__, cq->op);
1590                 ret = -EINVAL;
1591                 break;
1592         }
1593         return ret;
1594 }
1595 static int
1596 hfc_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1597 {
1598         struct bchannel *bch = container_of(ch, struct bchannel, ch);
1599         struct hfc_pci  *hc = bch->hw;
1600         int             ret = -EINVAL;
1601         u_long          flags;
1602
1603         if (bch->debug & DEBUG_HW)
1604                 printk(KERN_DEBUG "%s: cmd:%x %p\n", __func__, cmd, arg);
1605         switch (cmd) {
1606         case HW_TESTRX_RAW:
1607                 spin_lock_irqsave(&hc->lock, flags);
1608                 ret = set_hfcpci_rxtest(bch, ISDN_P_B_RAW, (int)(long)arg);
1609                 spin_unlock_irqrestore(&hc->lock, flags);
1610                 break;
1611         case HW_TESTRX_HDLC:
1612                 spin_lock_irqsave(&hc->lock, flags);
1613                 ret = set_hfcpci_rxtest(bch, ISDN_P_B_HDLC, (int)(long)arg);
1614                 spin_unlock_irqrestore(&hc->lock, flags);
1615                 break;
1616         case HW_TESTRX_OFF:
1617                 spin_lock_irqsave(&hc->lock, flags);
1618                 mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1619                 spin_unlock_irqrestore(&hc->lock, flags);
1620                 ret = 0;
1621                 break;
1622         case CLOSE_CHANNEL:
1623                 test_and_clear_bit(FLG_OPEN, &bch->Flags);
1624                 if (test_bit(FLG_ACTIVE, &bch->Flags))
1625                         deactivate_bchannel(bch);
1626                 ch->protocol = ISDN_P_NONE;
1627                 ch->peer = NULL;
1628                 module_put(THIS_MODULE);
1629                 ret = 0;
1630                 break;
1631         case CONTROL_CHANNEL:
1632                 ret = channel_bctrl(bch, arg);
1633                 break;
1634         default:
1635                 printk(KERN_WARNING "%s: unknown prim(%x)\n",
1636                         __func__, cmd);
1637         }
1638         return ret;
1639 }
1640
1641 /*
1642  * Layer2 -> Layer 1 Dchannel data
1643  */
1644 static int
1645 hfcpci_l2l1D(struct mISDNchannel *ch, struct sk_buff *skb)
1646 {
1647         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
1648         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
1649         struct hfc_pci          *hc = dch->hw;
1650         int                     ret = -EINVAL;
1651         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
1652         unsigned int            id;
1653         u_long                  flags;
1654
1655         switch (hh->prim) {
1656         case PH_DATA_REQ:
1657                 spin_lock_irqsave(&hc->lock, flags);
1658                 ret = dchannel_senddata(dch, skb);
1659                 if (ret > 0) { /* direct TX */
1660                         id = hh->id; /* skb can be freed */
1661                         hfcpci_fill_dfifo(dch->hw);
1662                         ret = 0;
1663                         spin_unlock_irqrestore(&hc->lock, flags);
1664                         queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1665                 } else
1666                         spin_unlock_irqrestore(&hc->lock, flags);
1667                 return ret;
1668         case PH_ACTIVATE_REQ:
1669                 spin_lock_irqsave(&hc->lock, flags);
1670                 if (hc->hw.protocol == ISDN_P_NT_S0) {
1671                         ret = 0;
1672                         if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1673                                 hc->hw.mst_m |= HFCPCI_MASTER;
1674                         Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1675                         if (test_bit(FLG_ACTIVE, &dch->Flags)) {
1676                                 spin_unlock_irqrestore(&hc->lock, flags);
1677                                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
1678                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
1679                                 break;
1680                         }
1681                         test_and_set_bit(FLG_L2_ACTIVATED, &dch->Flags);
1682                         Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1683                             HFCPCI_DO_ACTION | 1);
1684                 } else
1685                         ret = l1_event(dch->l1, hh->prim);
1686                 spin_unlock_irqrestore(&hc->lock, flags);
1687                 break;
1688         case PH_DEACTIVATE_REQ:
1689                 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1690                 spin_lock_irqsave(&hc->lock, flags);
1691                 if (hc->hw.protocol == ISDN_P_NT_S0) {
1692                         /* prepare deactivation */
1693                         Write_hfc(hc, HFCPCI_STATES, 0x40);
1694                         skb_queue_purge(&dch->squeue);
1695                         if (dch->tx_skb) {
1696                                 dev_kfree_skb(dch->tx_skb);
1697                                 dch->tx_skb = NULL;
1698                         }
1699                         dch->tx_idx = 0;
1700                         if (dch->rx_skb) {
1701                                 dev_kfree_skb(dch->rx_skb);
1702                                 dch->rx_skb = NULL;
1703                         }
1704                         test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1705                         if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1706                                 del_timer(&dch->timer);
1707 #ifdef FIXME
1708                         if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
1709                                 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
1710 #endif
1711                         hc->hw.mst_m &= ~HFCPCI_MASTER;
1712                         Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1713                         ret = 0;
1714                 } else {
1715                         ret = l1_event(dch->l1, hh->prim);
1716                 }
1717                 spin_unlock_irqrestore(&hc->lock, flags);
1718                 break;
1719         }
1720         if (!ret)
1721                 dev_kfree_skb(skb);
1722         return ret;
1723 }
1724
1725 /*
1726  * Layer2 -> Layer 1 Bchannel data
1727  */
1728 static int
1729 hfcpci_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
1730 {
1731         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
1732         struct hfc_pci          *hc = bch->hw;
1733         int                     ret = -EINVAL;
1734         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
1735         unsigned int            id;
1736         u_long                  flags;
1737
1738         switch (hh->prim) {
1739         case PH_DATA_REQ:
1740                 spin_lock_irqsave(&hc->lock, flags);
1741                 ret = bchannel_senddata(bch, skb);
1742                 if (ret > 0) { /* direct TX */
1743                         id = hh->id; /* skb can be freed */
1744                         hfcpci_fill_fifo(bch);
1745                         ret = 0;
1746                         spin_unlock_irqrestore(&hc->lock, flags);
1747                         if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1748                                 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1749                 } else
1750                         spin_unlock_irqrestore(&hc->lock, flags);
1751                 return ret;
1752         case PH_ACTIVATE_REQ:
1753                 spin_lock_irqsave(&hc->lock, flags);
1754                 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
1755                         ret = mode_hfcpci(bch, bch->nr, ch->protocol);
1756                 else
1757                         ret = 0;
1758                 spin_unlock_irqrestore(&hc->lock, flags);
1759                 if (!ret)
1760                         _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
1761                                 NULL, GFP_KERNEL);
1762                 break;
1763         case PH_DEACTIVATE_REQ:
1764                 deactivate_bchannel(bch);
1765                 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
1766                         NULL, GFP_KERNEL);
1767                 ret = 0;
1768                 break;
1769         }
1770         if (!ret)
1771                 dev_kfree_skb(skb);
1772         return ret;
1773 }
1774
1775 /*
1776  * called for card init message
1777  */
1778
1779 static void
1780 inithfcpci(struct hfc_pci *hc)
1781 {
1782         printk(KERN_DEBUG "inithfcpci: entered\n");
1783         hc->dch.timer.function = (void *) hfcpci_dbusy_timer;
1784         hc->dch.timer.data = (long) &hc->dch;
1785         init_timer(&hc->dch.timer);
1786         hc->chanlimit = 2;
1787         mode_hfcpci(&hc->bch[0], 1, -1);
1788         mode_hfcpci(&hc->bch[1], 2, -1);
1789 }
1790
1791
1792 static int
1793 init_card(struct hfc_pci *hc)
1794 {
1795         int     cnt = 3;
1796         u_long  flags;
1797
1798         printk(KERN_DEBUG "init_card: entered\n");
1799
1800
1801         spin_lock_irqsave(&hc->lock, flags);
1802         disable_hwirq(hc);
1803         spin_unlock_irqrestore(&hc->lock, flags);
1804         if (request_irq(hc->irq, hfcpci_int, IRQF_SHARED, "HFC PCI", hc)) {
1805                 printk(KERN_WARNING
1806                     "mISDN: couldn't get interrupt %d\n", hc->irq);
1807                 return -EIO;
1808         }
1809         spin_lock_irqsave(&hc->lock, flags);
1810         reset_hfcpci(hc);
1811         while (cnt) {
1812                 inithfcpci(hc);
1813                 /*
1814                  * Finally enable IRQ output
1815                  * this is only allowed, if an IRQ routine is allready
1816                  * established for this HFC, so don't do that earlier
1817                  */
1818                 enable_hwirq(hc);
1819                 spin_unlock_irqrestore(&hc->lock, flags);
1820                 /* Timeout 80ms */
1821                 current->state = TASK_UNINTERRUPTIBLE;
1822                 schedule_timeout((80*HZ)/1000);
1823                 printk(KERN_INFO "HFC PCI: IRQ %d count %d\n",
1824                         hc->irq, hc->irqcnt);
1825                 /* now switch timer interrupt off */
1826                 spin_lock_irqsave(&hc->lock, flags);
1827                 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1828                 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1829                 /* reinit mode reg */
1830                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1831                 if (!hc->irqcnt) {
1832                         printk(KERN_WARNING
1833                             "HFC PCI: IRQ(%d) getting no interrupts "
1834                             "during init %d\n", hc->irq, 4 - cnt);
1835                         if (cnt == 1) {
1836                                 spin_unlock_irqrestore(&hc->lock, flags);
1837                                 return -EIO;
1838                         } else {
1839                                 reset_hfcpci(hc);
1840                                 cnt--;
1841                         }
1842                 } else {
1843                         spin_unlock_irqrestore(&hc->lock, flags);
1844                         hc->initdone = 1;
1845                         return 0;
1846                 }
1847         }
1848         disable_hwirq(hc);
1849         spin_unlock_irqrestore(&hc->lock, flags);
1850         free_irq(hc->irq, hc);
1851         return -EIO;
1852 }
1853
1854 static int
1855 channel_ctrl(struct hfc_pci *hc, struct mISDN_ctrl_req *cq)
1856 {
1857         int     ret = 0;
1858         u_char  slot;
1859
1860         switch (cq->op) {
1861         case MISDN_CTRL_GETOP:
1862                 cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_CONNECT |
1863                     MISDN_CTRL_DISCONNECT;
1864                 break;
1865         case MISDN_CTRL_LOOP:
1866                 /* channel 0 disabled loop */
1867                 if (cq->channel < 0 || cq->channel > 2) {
1868                         ret = -EINVAL;
1869                         break;
1870                 }
1871                 if (cq->channel & 1) {
1872                         if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1873                                 slot = 0xC0;
1874                         else
1875                                 slot = 0x80;
1876                         printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1877                             __func__, slot);
1878                         Write_hfc(hc, HFCPCI_B1_SSL, slot);
1879                         Write_hfc(hc, HFCPCI_B1_RSL, slot);
1880                         hc->hw.conn = (hc->hw.conn & ~7) | 6;
1881                         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1882                 }
1883                 if (cq->channel & 2) {
1884                         if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1885                                 slot = 0xC1;
1886                         else
1887                                 slot = 0x81;
1888                         printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1889                             __func__, slot);
1890                         Write_hfc(hc, HFCPCI_B2_SSL, slot);
1891                         Write_hfc(hc, HFCPCI_B2_RSL, slot);
1892                         hc->hw.conn = (hc->hw.conn & ~0x38) | 0x30;
1893                         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1894                 }
1895                 if (cq->channel & 3)
1896                         hc->hw.trm |= 0x80;     /* enable IOM-loop */
1897                 else {
1898                         hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1899                         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1900                         hc->hw.trm &= 0x7f;     /* disable IOM-loop */
1901                 }
1902                 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1903                 break;
1904         case MISDN_CTRL_CONNECT:
1905                 if (cq->channel == cq->p1) {
1906                         ret = -EINVAL;
1907                         break;
1908                 }
1909                 if (cq->channel < 1 || cq->channel > 2 ||
1910                     cq->p1 < 1 || cq->p1 > 2) {
1911                         ret = -EINVAL;
1912                         break;
1913                 }
1914                 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1915                         slot = 0xC0;
1916                 else
1917                         slot = 0x80;
1918                 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1919                     __func__, slot);
1920                 Write_hfc(hc, HFCPCI_B1_SSL, slot);
1921                 Write_hfc(hc, HFCPCI_B2_RSL, slot);
1922                 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1923                         slot = 0xC1;
1924                 else
1925                         slot = 0x81;
1926                 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1927                     __func__, slot);
1928                 Write_hfc(hc, HFCPCI_B2_SSL, slot);
1929                 Write_hfc(hc, HFCPCI_B1_RSL, slot);
1930                 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x36;
1931                 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1932                 hc->hw.trm |= 0x80;
1933                 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1934                 break;
1935         case MISDN_CTRL_DISCONNECT:
1936                 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1937                 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1938                 hc->hw.trm &= 0x7f;     /* disable IOM-loop */
1939                 break;
1940         default:
1941                 printk(KERN_WARNING "%s: unknown Op %x\n",
1942                     __func__, cq->op);
1943                 ret = -EINVAL;
1944                 break;
1945         }
1946         return ret;
1947 }
1948
1949 static int
1950 open_dchannel(struct hfc_pci *hc, struct mISDNchannel *ch,
1951     struct channel_req *rq)
1952 {
1953         int err = 0;
1954
1955         if (debug & DEBUG_HW_OPEN)
1956                 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
1957                     hc->dch.dev.id, __builtin_return_address(0));
1958         if (rq->protocol == ISDN_P_NONE)
1959                 return -EINVAL;
1960         if (rq->adr.channel == 1) {
1961                 /* TODO: E-Channel */
1962                 return -EINVAL;
1963         }
1964         if (!hc->initdone) {
1965                 if (rq->protocol == ISDN_P_TE_S0) {
1966                         err = create_l1(&hc->dch, hfc_l1callback);
1967                         if (err)
1968                                 return err;
1969                 }
1970                 hc->hw.protocol = rq->protocol;
1971                 ch->protocol = rq->protocol;
1972                 err = init_card(hc);
1973                 if (err)
1974                         return err;
1975         } else {
1976                 if (rq->protocol != ch->protocol) {
1977                         if (hc->hw.protocol == ISDN_P_TE_S0)
1978                                 l1_event(hc->dch.l1, CLOSE_CHANNEL);
1979                         hc->hw.protocol = rq->protocol;
1980                         ch->protocol = rq->protocol;
1981                         hfcpci_setmode(hc);
1982                 }
1983         }
1984
1985         if (((ch->protocol == ISDN_P_NT_S0) && (hc->dch.state == 3)) ||
1986             ((ch->protocol == ISDN_P_TE_S0) && (hc->dch.state == 7))) {
1987                 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY,
1988                     0, NULL, GFP_KERNEL);
1989         }
1990         rq->ch = ch;
1991         if (!try_module_get(THIS_MODULE))
1992                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1993         return 0;
1994 }
1995
1996 static int
1997 open_bchannel(struct hfc_pci *hc, struct channel_req *rq)
1998 {
1999         struct bchannel         *bch;
2000
2001         if (rq->adr.channel > 2)
2002                 return -EINVAL;
2003         if (rq->protocol == ISDN_P_NONE)
2004                 return -EINVAL;
2005         bch = &hc->bch[rq->adr.channel - 1];
2006         if (test_and_set_bit(FLG_OPEN, &bch->Flags))
2007                 return -EBUSY; /* b-channel can be only open once */
2008         test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
2009         bch->ch.protocol = rq->protocol;
2010         rq->ch = &bch->ch; /* TODO: E-channel */
2011         if (!try_module_get(THIS_MODULE))
2012                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
2013         return 0;
2014 }
2015
2016 /*
2017  * device control function
2018  */
2019 static int
2020 hfc_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
2021 {
2022         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
2023         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
2024         struct hfc_pci          *hc = dch->hw;
2025         struct channel_req      *rq;
2026         int                     err = 0;
2027
2028         if (dch->debug & DEBUG_HW)
2029                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
2030                     __func__, cmd, arg);
2031         switch (cmd) {
2032         case OPEN_CHANNEL:
2033                 rq = arg;
2034                 if ((rq->protocol == ISDN_P_TE_S0) ||
2035                     (rq->protocol == ISDN_P_NT_S0))
2036                         err = open_dchannel(hc, ch, rq);
2037                 else
2038                         err = open_bchannel(hc, rq);
2039                 break;
2040         case CLOSE_CHANNEL:
2041                 if (debug & DEBUG_HW_OPEN)
2042                         printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
2043                             __func__, hc->dch.dev.id,
2044                             __builtin_return_address(0));
2045                 module_put(THIS_MODULE);
2046                 break;
2047         case CONTROL_CHANNEL:
2048                 err = channel_ctrl(hc, arg);
2049                 break;
2050         default:
2051                 if (dch->debug & DEBUG_HW)
2052                         printk(KERN_DEBUG "%s: unknown command %x\n",
2053                             __func__, cmd);
2054                 return -EINVAL;
2055         }
2056         return err;
2057 }
2058
2059 static int
2060 setup_hw(struct hfc_pci *hc)
2061 {
2062         void    *buffer;
2063
2064         printk(KERN_INFO "mISDN: HFC-PCI driver %s\n", hfcpci_revision);
2065         hc->hw.cirm = 0;
2066         hc->dch.state = 0;
2067         pci_set_master(hc->pdev);
2068         if (!hc->irq) {
2069                 printk(KERN_WARNING "HFC-PCI: No IRQ for PCI card found\n");
2070                 return 1;
2071         }
2072         hc->hw.pci_io = (char __iomem *)(unsigned long)hc->pdev->resource[1].start;
2073
2074         if (!hc->hw.pci_io) {
2075                 printk(KERN_WARNING "HFC-PCI: No IO-Mem for PCI card found\n");
2076                 return 1;
2077         }
2078         /* Allocate memory for FIFOS */
2079         /* the memory needs to be on a 32k boundary within the first 4G */
2080         pci_set_dma_mask(hc->pdev, 0xFFFF8000);
2081         buffer = pci_alloc_consistent(hc->pdev, 0x8000, &hc->hw.dmahandle);
2082         /* We silently assume the address is okay if nonzero */
2083         if (!buffer) {
2084                 printk(KERN_WARNING
2085                     "HFC-PCI: Error allocating memory for FIFO!\n");
2086                 return 1;
2087         }
2088         hc->hw.fifos = buffer;
2089         pci_write_config_dword(hc->pdev, 0x80, hc->hw.dmahandle);
2090         hc->hw.pci_io = ioremap((ulong) hc->hw.pci_io, 256);
2091         printk(KERN_INFO
2092                 "HFC-PCI: defined at mem %#lx fifo %#lx(%#lx) IRQ %d HZ %d\n",
2093                 (u_long) hc->hw.pci_io, (u_long) hc->hw.fifos,
2094                 (u_long) hc->hw.dmahandle, hc->irq, HZ);
2095         /* enable memory mapped ports, disable busmaster */
2096         pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
2097         hc->hw.int_m2 = 0;
2098         disable_hwirq(hc);
2099         hc->hw.int_m1 = 0;
2100         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
2101         /* At this point the needed PCI config is done */
2102         /* fifos are still not enabled */
2103         hc->hw.timer.function = (void *) hfcpci_Timer;
2104         hc->hw.timer.data = (long) hc;
2105         init_timer(&hc->hw.timer);
2106         /* default PCM master */
2107         test_and_set_bit(HFC_CFG_MASTER, &hc->cfg);
2108         return 0;
2109 }
2110
2111 static void
2112 release_card(struct hfc_pci *hc) {
2113         u_long  flags;
2114
2115         spin_lock_irqsave(&hc->lock, flags);
2116         hc->hw.int_m2 = 0; /* interrupt output off ! */
2117         disable_hwirq(hc);
2118         mode_hfcpci(&hc->bch[0], 1, ISDN_P_NONE);
2119         mode_hfcpci(&hc->bch[1], 2, ISDN_P_NONE);
2120         if (hc->dch.timer.function != NULL) {
2121                 del_timer(&hc->dch.timer);
2122                 hc->dch.timer.function = NULL;
2123         }
2124         spin_unlock_irqrestore(&hc->lock, flags);
2125         if (hc->hw.protocol == ISDN_P_TE_S0)
2126                 l1_event(hc->dch.l1, CLOSE_CHANNEL);
2127         if (hc->initdone)
2128                 free_irq(hc->irq, hc);
2129         release_io_hfcpci(hc); /* must release after free_irq! */
2130         mISDN_unregister_device(&hc->dch.dev);
2131         mISDN_freebchannel(&hc->bch[1]);
2132         mISDN_freebchannel(&hc->bch[0]);
2133         mISDN_freedchannel(&hc->dch);
2134         list_del(&hc->list);
2135         pci_set_drvdata(hc->pdev, NULL);
2136         kfree(hc);
2137 }
2138
2139 static int
2140 setup_card(struct hfc_pci *card)
2141 {
2142         int             err = -EINVAL;
2143         u_int           i;
2144         u_long          flags;
2145         char            name[MISDN_MAX_IDLEN];
2146
2147         card->dch.debug = debug;
2148         spin_lock_init(&card->lock);
2149         mISDN_initdchannel(&card->dch, MAX_DFRAME_LEN_L1, ph_state);
2150         card->dch.hw = card;
2151         card->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
2152         card->dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
2153             (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
2154         card->dch.dev.D.send = hfcpci_l2l1D;
2155         card->dch.dev.D.ctrl = hfc_dctrl;
2156         card->dch.dev.nrbchan = 2;
2157         for (i = 0; i < 2; i++) {
2158                 card->bch[i].nr = i + 1;
2159                 set_channelmap(i + 1, card->dch.dev.channelmap);
2160                 card->bch[i].debug = debug;
2161                 mISDN_initbchannel(&card->bch[i], MAX_DATA_MEM);
2162                 card->bch[i].hw = card;
2163                 card->bch[i].ch.send = hfcpci_l2l1B;
2164                 card->bch[i].ch.ctrl = hfc_bctrl;
2165                 card->bch[i].ch.nr = i + 1;
2166                 list_add(&card->bch[i].ch.list, &card->dch.dev.bchannels);
2167         }
2168         err = setup_hw(card);
2169         if (err)
2170                 goto error;
2171         snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-pci.%d", HFC_cnt + 1);
2172         err = mISDN_register_device(&card->dch.dev, name);
2173         if (err)
2174                 goto error;
2175         HFC_cnt++;
2176         write_lock_irqsave(&HFClock, flags);
2177         list_add_tail(&card->list, &HFClist);
2178         write_unlock_irqrestore(&HFClock, flags);
2179         printk(KERN_INFO "HFC %d cards installed\n", HFC_cnt);
2180         return 0;
2181 error:
2182         mISDN_freebchannel(&card->bch[1]);
2183         mISDN_freebchannel(&card->bch[0]);
2184         mISDN_freedchannel(&card->dch);
2185         kfree(card);
2186         return err;
2187 }
2188
2189 /* private data in the PCI devices list */
2190 struct _hfc_map {
2191         u_int   subtype;
2192         u_int   flag;
2193         char    *name;
2194 };
2195
2196 static const struct _hfc_map hfc_map[] =
2197 {
2198         {HFC_CCD_2BD0, 0, "CCD/Billion/Asuscom 2BD0"},
2199         {HFC_CCD_B000, 0, "Billion B000"},
2200         {HFC_CCD_B006, 0, "Billion B006"},
2201         {HFC_CCD_B007, 0, "Billion B007"},
2202         {HFC_CCD_B008, 0, "Billion B008"},
2203         {HFC_CCD_B009, 0, "Billion B009"},
2204         {HFC_CCD_B00A, 0, "Billion B00A"},
2205         {HFC_CCD_B00B, 0, "Billion B00B"},
2206         {HFC_CCD_B00C, 0, "Billion B00C"},
2207         {HFC_CCD_B100, 0, "Seyeon B100"},
2208         {HFC_CCD_B700, 0, "Primux II S0 B700"},
2209         {HFC_CCD_B701, 0, "Primux II S0 NT B701"},
2210         {HFC_ABOCOM_2BD1, 0, "Abocom/Magitek 2BD1"},
2211         {HFC_ASUS_0675, 0, "Asuscom/Askey 675"},
2212         {HFC_BERKOM_TCONCEPT, 0, "German telekom T-Concept"},
2213         {HFC_BERKOM_A1T, 0, "German telekom A1T"},
2214         {HFC_ANIGMA_MC145575, 0, "Motorola MC145575"},
2215         {HFC_ZOLTRIX_2BD0, 0, "Zoltrix 2BD0"},
2216         {HFC_DIGI_DF_M_IOM2_E, 0,
2217             "Digi International DataFire Micro V IOM2 (Europe)"},
2218         {HFC_DIGI_DF_M_E, 0,
2219             "Digi International DataFire Micro V (Europe)"},
2220         {HFC_DIGI_DF_M_IOM2_A, 0,
2221             "Digi International DataFire Micro V IOM2 (North America)"},
2222         {HFC_DIGI_DF_M_A, 0,
2223             "Digi International DataFire Micro V (North America)"},
2224         {HFC_SITECOM_DC105V2, 0, "Sitecom Connectivity DC-105 ISDN TA"},
2225         {},
2226 };
2227
2228 static struct pci_device_id hfc_ids[] =
2229 {
2230         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_2BD0,
2231                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[0]},
2232         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B000,
2233                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[1]},
2234         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B006,
2235                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[2]},
2236         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B007,
2237                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[3]},
2238         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B008,
2239                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[4]},
2240         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B009,
2241                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[5]},
2242         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00A,
2243                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[6]},
2244         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00B,
2245                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[7]},
2246         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00C,
2247                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[8]},
2248         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B100,
2249                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[9]},
2250         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B700,
2251                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[10]},
2252         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B701,
2253                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[11]},
2254         {PCI_VENDOR_ID_ABOCOM, PCI_DEVICE_ID_ABOCOM_2BD1,
2255                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[12]},
2256         {PCI_VENDOR_ID_ASUSTEK, PCI_DEVICE_ID_ASUSTEK_0675,
2257                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[13]},
2258         {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_T_CONCEPT,
2259                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[14]},
2260         {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_A1T,
2261                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[15]},
2262         {PCI_VENDOR_ID_ANIGMA, PCI_DEVICE_ID_ANIGMA_MC145575,
2263                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[16]},
2264         {PCI_VENDOR_ID_ZOLTRIX, PCI_DEVICE_ID_ZOLTRIX_2BD0,
2265                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[17]},
2266         {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E,
2267                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[18]},
2268         {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_E,
2269                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[19]},
2270         {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A,
2271                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[20]},
2272         {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_A,
2273                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[21]},
2274         {PCI_VENDOR_ID_SITECOM, PCI_DEVICE_ID_SITECOM_DC105V2,
2275                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[22]},
2276         {},
2277 };
2278
2279 static int __devinit
2280 hfc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2281 {
2282         int             err = -ENOMEM;
2283         struct hfc_pci  *card;
2284         struct _hfc_map *m = (struct _hfc_map *)ent->driver_data;
2285
2286         card = kzalloc(sizeof(struct hfc_pci), GFP_ATOMIC);
2287         if (!card) {
2288                 printk(KERN_ERR "No kmem for HFC card\n");
2289                 return err;
2290         }
2291         card->pdev = pdev;
2292         card->subtype = m->subtype;
2293         err = pci_enable_device(pdev);
2294         if (err) {
2295                 kfree(card);
2296                 return err;
2297         }
2298
2299         printk(KERN_INFO "mISDN_hfcpci: found adapter %s at %s\n",
2300                m->name, pci_name(pdev));
2301
2302         card->irq = pdev->irq;
2303         pci_set_drvdata(pdev, card);
2304         err = setup_card(card);
2305         if (err)
2306                 pci_set_drvdata(pdev, NULL);
2307         return err;
2308 }
2309
2310 static void __devexit
2311 hfc_remove_pci(struct pci_dev *pdev)
2312 {
2313         struct hfc_pci  *card = pci_get_drvdata(pdev);
2314         u_long          flags;
2315
2316         if (card) {
2317                 write_lock_irqsave(&HFClock, flags);
2318                 release_card(card);
2319                 write_unlock_irqrestore(&HFClock, flags);
2320         } else
2321                 if (debug)
2322                         printk(KERN_WARNING "%s: drvdata allready removed\n",
2323                             __func__);
2324 }
2325
2326
2327 static struct pci_driver hfc_driver = {
2328         .name = "hfcpci",
2329         .probe = hfc_probe,
2330         .remove = __devexit_p(hfc_remove_pci),
2331         .id_table = hfc_ids,
2332 };
2333
2334 static int __init
2335 HFC_init(void)
2336 {
2337         int             err;
2338
2339         if (!poll)
2340                 poll = HFCPCI_BTRANS_THRESHOLD;
2341
2342         if (poll != HFCPCI_BTRANS_THRESHOLD) {
2343                 tics = poll * HZ / 8000;
2344                 if (tics < 1)
2345                         tics = 1;
2346                 poll = tics * 8000 / HZ;
2347                 if (poll > 256 || poll < 8) {
2348                         printk(KERN_ERR "%s: Wrong poll value %d not in range "
2349                                 "of 8..256.\n", __func__, poll);
2350                         err = -EINVAL;
2351                         return err;
2352                 }
2353         }
2354         if (poll != HFCPCI_BTRANS_THRESHOLD) {
2355                 printk(KERN_INFO "%s: Using alternative poll value of %d\n",
2356                         __func__, poll);
2357                 hfc_tl.function = (void *)hfcpci_softirq;
2358                 hfc_tl.data = 0;
2359                 init_timer(&hfc_tl);
2360                 hfc_tl.expires = jiffies + tics;
2361                 hfc_jiffies = hfc_tl.expires;
2362                 add_timer(&hfc_tl);
2363         } else
2364                 tics = 0; /* indicate the use of controller's timer */
2365
2366         err = pci_register_driver(&hfc_driver);
2367         if (err) {
2368                 if (timer_pending(&hfc_tl))
2369                         del_timer(&hfc_tl);
2370         }
2371
2372         return err;
2373 }
2374
2375 static void __exit
2376 HFC_cleanup(void)
2377 {
2378         struct hfc_pci  *card, *next;
2379
2380         if (timer_pending(&hfc_tl))
2381                 del_timer(&hfc_tl);
2382
2383         list_for_each_entry_safe(card, next, &HFClist, list) {
2384                 release_card(card);
2385         }
2386         pci_unregister_driver(&hfc_driver);
2387 }
2388
2389 module_init(HFC_init);
2390 module_exit(HFC_cleanup);