drivers/isdn/hardware/mISDN/hfcpci.c

   1 /*
   2  *
   3  * hfcpci.c     low level driver for CCD's hfc-pci based cards
   4  *
   5  * Author     Werner Cornelius (werner@isdn4linux.de)
   6  *            based on existing driver for CCD hfc ISA cards
   7  *            type approval valid for HFC-S PCI A based card
   8  *
   9  * Copyright 1999  by Werner Cornelius (werner@isdn-development.de)
  10  * Copyright 2008  by Karsten Keil <kkeil@novell.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2, or (at your option)
  15  * any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  */
  27
  28 #include <linux/module.h>
  29 #include <linux/pci.h>
  30 #include <linux/delay.h>
  31 #include <linux/mISDNhw.h>
  32
  33 #include "hfc_pci.h"
  34
  35 static const char *hfcpci_revision = "2.0";
  36
  37 #define MAX_CARDS       8
  38 static int HFC_cnt;
  39 static uint debug;
  40
  41 MODULE_AUTHOR("Karsten Keil");
  42 MODULE_LICENSE("GPL");
  43 module_param(debug, uint, 0);
  44
  45 static LIST_HEAD(HFClist);
  46 static DEFINE_RWLOCK(HFClock);
  47
  48 enum {
  49         HFC_CCD_2BD0,
  50         HFC_CCD_B000,
  51         HFC_CCD_B006,
  52         HFC_CCD_B007,
  53         HFC_CCD_B008,
  54         HFC_CCD_B009,
  55         HFC_CCD_B00A,
  56         HFC_CCD_B00B,
  57         HFC_CCD_B00C,
  58         HFC_CCD_B100,
  59         HFC_CCD_B700,
  60         HFC_CCD_B701,
  61         HFC_ASUS_0675,
  62         HFC_BERKOM_A1T,
  63         HFC_BERKOM_TCONCEPT,
  64         HFC_ANIGMA_MC145575,
  65         HFC_ZOLTRIX_2BD0,
  66         HFC_DIGI_DF_M_IOM2_E,
  67         HFC_DIGI_DF_M_E,
  68         HFC_DIGI_DF_M_IOM2_A,
  69         HFC_DIGI_DF_M_A,
  70         HFC_ABOCOM_2BD1,
  71         HFC_SITECOM_DC105V2,
  72 };
  73
  74 struct hfcPCI_hw {
  75         unsigned char           cirm;
  76         unsigned char           ctmt;
  77         unsigned char           clkdel;
  78         unsigned char           states;
  79         unsigned char           conn;
  80         unsigned char           mst_m;
  81         unsigned char           int_m1;
  82         unsigned char           int_m2;
  83         unsigned char           sctrl;
  84         unsigned char           sctrl_r;
  85         unsigned char           sctrl_e;
  86         unsigned char           trm;
  87         unsigned char           fifo_en;
  88         unsigned char           bswapped;
  89         unsigned char           protocol;
  90         int                     nt_timer;
  91         unsigned char __iomem   *pci_io; /* start of PCI IO memory */
  92         dma_addr_t              dmahandle;
  93         void                    *fifos; /* FIFO memory */
  94         int                     last_bfifo_cnt[2];
  95             /* marker saving last b-fifo frame count */
  96         struct timer_list       timer;
  97 };
  98
  99 #define HFC_CFG_MASTER          1
 100 #define HFC_CFG_SLAVE           2
 101 #define HFC_CFG_PCM             3
 102 #define HFC_CFG_2HFC            4
 103 #define HFC_CFG_SLAVEHFC        5
 104 #define HFC_CFG_NEG_F0          6
 105 #define HFC_CFG_SW_DD_DU        7
 106
 107 #define FLG_HFC_TIMER_T1        16
 108 #define FLG_HFC_TIMER_T3        17
 109
 110 #define NT_T1_COUNT     1120    /* number of 3.125ms interrupts (3.5s) */
 111 #define NT_T3_COUNT     31      /* number of 3.125ms interrupts (97 ms) */
 112 #define CLKDEL_TE       0x0e    /* CLKDEL in TE mode */
 113 #define CLKDEL_NT       0x6c    /* CLKDEL in NT mode */
 114
 115
 116 struct hfc_pci {
 117         struct list_head        list;
 118         u_char                  subtype;
 119         u_char                  chanlimit;
 120         u_char                  initdone;
 121         u_long                  cfg;
 122         u_int                   irq;
 123         u_int                   irqcnt;
 124         struct pci_dev          *pdev;
 125         struct hfcPCI_hw        hw;
 126         spinlock_t              lock;   /* card lock */
 127         struct dchannel         dch;
 128         struct bchannel         bch[2];
 129 };
 130
 131 /* Interface functions */
 132 static void
 133 enable_hwirq(struct hfc_pci *hc)
 134 {
 135         hc->hw.int_m2 |= HFCPCI_IRQ_ENABLE;
 136         Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
 137 }
 138
 139 static void
 140 disable_hwirq(struct hfc_pci *hc)
 141 {
 142         hc->hw.int_m2 &= ~((u_char)HFCPCI_IRQ_ENABLE);
 143         Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
 144 }
 145
 146 /*
 147  * free hardware resources used by driver
 148  */
 149 static void
 150 release_io_hfcpci(struct hfc_pci *hc)
 151 {
 152         /* disable memory mapped ports + busmaster */
 153         pci_write_config_word(hc->pdev, PCI_COMMAND, 0);
 154         del_timer(&hc->hw.timer);
 155         pci_free_consistent(hc->pdev, 0x8000, hc->hw.fifos, hc->hw.dmahandle);
 156         iounmap(hc->hw.pci_io);
 157 }
 158
 159 /*
 160  * set mode (NT or TE)
 161  */
 162 static void
 163 hfcpci_setmode(struct hfc_pci *hc)
 164 {
 165         if (hc->hw.protocol == ISDN_P_NT_S0) {
 166                 hc->hw.clkdel = CLKDEL_NT;      /* ST-Bit delay for NT-Mode */
 167                 hc->hw.sctrl |= SCTRL_MODE_NT;  /* NT-MODE */
 168                 hc->hw.states = 1;              /* G1 */
 169         } else {
 170                 hc->hw.clkdel = CLKDEL_TE;      /* ST-Bit delay for TE-Mode */
 171                 hc->hw.sctrl &= ~SCTRL_MODE_NT; /* TE-MODE */
 172                 hc->hw.states = 2;              /* F2 */
 173         }
 174         Write_hfc(hc, HFCPCI_CLKDEL, hc->hw.clkdel);
 175         Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | hc->hw.states);
 176         udelay(10);
 177         Write_hfc(hc, HFCPCI_STATES, hc->hw.states | 0x40); /* Deactivate */
 178         Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
 179 }
 180
 181 /*
 182  * function called to reset the HFC PCI chip. A complete software reset of chip
 183  * and fifos is done.
 184  */
 185 static void
 186 reset_hfcpci(struct hfc_pci *hc)
 187 {
 188         u_char  val;
 189         int     cnt = 0;
 190
 191         printk(KERN_DEBUG "reset_hfcpci: entered\n");
 192         val = Read_hfc(hc, HFCPCI_CHIP_ID);
 193         printk(KERN_INFO "HFC_PCI: resetting HFC ChipId(%x)\n", val);
 194         /* enable memory mapped ports, disable busmaster */
 195         pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
 196         disable_hwirq(hc);
 197         /* enable memory ports + busmaster */
 198         pci_write_config_word(hc->pdev, PCI_COMMAND,
 199             PCI_ENA_MEMIO + PCI_ENA_MASTER);
 200         val = Read_hfc(hc, HFCPCI_STATUS);
 201         printk(KERN_DEBUG "HFC-PCI status(%x) before reset\n", val);
 202         hc->hw.cirm = HFCPCI_RESET;     /* Reset On */
 203         Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
 204         set_current_state(TASK_UNINTERRUPTIBLE);
 205         mdelay(10);                     /* Timeout 10ms */
 206         hc->hw.cirm = 0;                /* Reset Off */
 207         Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
 208         val = Read_hfc(hc, HFCPCI_STATUS);
 209         printk(KERN_DEBUG "HFC-PCI status(%x) after reset\n", val);
 210         while (cnt < 50000) { /* max 50000 us */
 211                 udelay(5);
 212                 cnt += 5;
 213                 val = Read_hfc(hc, HFCPCI_STATUS);
 214                 if (!(val & 2))
 215                         break;
 216         }
 217         printk(KERN_DEBUG "HFC-PCI status(%x) after %dus\n", val, cnt);
 218
 219         hc->hw.fifo_en = 0x30;  /* only D fifos enabled */
 220
 221         hc->hw.bswapped = 0;    /* no exchange */
 222         hc->hw.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
 223         hc->hw.trm = HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */
 224         hc->hw.sctrl = 0x40;    /* set tx_lo mode, error in datasheet ! */
 225         hc->hw.sctrl_r = 0;
 226         hc->hw.sctrl_e = HFCPCI_AUTO_AWAKE;     /* S/T Auto awake */
 227         hc->hw.mst_m = 0;
 228         if (test_bit(HFC_CFG_MASTER, &hc->cfg))
 229                 hc->hw.mst_m |= HFCPCI_MASTER;  /* HFC Master Mode */
 230         if (test_bit(HFC_CFG_NEG_F0, &hc->cfg))
 231                 hc->hw.mst_m |= HFCPCI_F0_NEGATIV;
 232         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 233         Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
 234         Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
 235         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
 236
 237         hc->hw.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
 238             HFCPCI_INTS_L1STATE | HFCPCI_INTS_TIMER;
 239         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 240
 241         /* Clear already pending ints */
 242         if (Read_hfc(hc, HFCPCI_INT_S1));
 243
 244         /* set NT/TE mode */
 245         hfcpci_setmode(hc);
 246
 247         Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
 248         Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
 249
 250         /*
 251          * Init GCI/IOM2 in master mode
 252          * Slots 0 and 1 are set for B-chan 1 and 2
 253          * D- and monitor/CI channel are not enabled
 254          * STIO1 is used as output for data, B1+B2 from ST->IOM+HFC
 255          * STIO2 is used as data input, B1+B2 from IOM->ST
 256          * ST B-channel send disabled -> continous 1s
 257          * The IOM slots are always enabled
 258          */
 259         if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
 260                 /* set data flow directions: connect B1,B2: HFC to/from PCM */
 261                 hc->hw.conn = 0x09;
 262         } else {
 263                 hc->hw.conn = 0x36;     /* set data flow directions */
 264                 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
 265                         Write_hfc(hc, HFCPCI_B1_SSL, 0xC0);
 266                         Write_hfc(hc, HFCPCI_B2_SSL, 0xC1);
 267                         Write_hfc(hc, HFCPCI_B1_RSL, 0xC0);
 268                         Write_hfc(hc, HFCPCI_B2_RSL, 0xC1);
 269                 } else {
 270                         Write_hfc(hc, HFCPCI_B1_SSL, 0x80);
 271                         Write_hfc(hc, HFCPCI_B2_SSL, 0x81);
 272                         Write_hfc(hc, HFCPCI_B1_RSL, 0x80);
 273                         Write_hfc(hc, HFCPCI_B2_RSL, 0x81);
 274                 }
 275         }
 276         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
 277         val = Read_hfc(hc, HFCPCI_INT_S2);
 278 }
 279
 280 /*
 281  * Timer function called when kernel timer expires
 282  */
 283 static void
 284 hfcpci_Timer(struct hfc_pci *hc)
 285 {
 286         hc->hw.timer.expires = jiffies + 75;
 287         /* WD RESET */
 288 /*
 289  *      WriteReg(hc, HFCD_DATA, HFCD_CTMT, hc->hw.ctmt | 0x80);
 290  *      add_timer(&hc->hw.timer);
 291  */
 292 }
 293
 294
 295 /*
 296  * select a b-channel entry matching and active
 297  */
 298 static struct bchannel *
 299 Sel_BCS(struct hfc_pci *hc, int channel)
 300 {
 301         if (test_bit(FLG_ACTIVE, &hc->bch[0].Flags) &&
 302                 (hc->bch[0].nr & channel))
 303                 return &hc->bch[0];
 304         else if (test_bit(FLG_ACTIVE, &hc->bch[1].Flags) &&
 305                 (hc->bch[1].nr & channel))
 306                 return &hc->bch[1];
 307         else
 308                 return NULL;
 309 }
 310
 311 /*
 312  * clear the desired B-channel rx fifo
 313  */
 314 static void
 315 hfcpci_clear_fifo_rx(struct hfc_pci *hc, int fifo)
 316 {
 317         u_char          fifo_state;
 318         struct bzfifo   *bzr;
 319
 320         if (fifo) {
 321                 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
 322                 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2RX;
 323         } else {
 324                 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
 325                 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1RX;
 326         }
 327         if (fifo_state)
 328                 hc->hw.fifo_en ^= fifo_state;
 329         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 330         hc->hw.last_bfifo_cnt[fifo] = 0;
 331         bzr->f1 = MAX_B_FRAMES;
 332         bzr->f2 = bzr->f1;      /* init F pointers to remain constant */
 333         bzr->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
 334         bzr->za[MAX_B_FRAMES].z2 = cpu_to_le16(
 335             le16_to_cpu(bzr->za[MAX_B_FRAMES].z1));
 336         if (fifo_state)
 337                 hc->hw.fifo_en |= fifo_state;
 338         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 339 }
 340
 341 /*
 342  * clear the desired B-channel tx fifo
 343  */
 344 static void hfcpci_clear_fifo_tx(struct hfc_pci *hc, int fifo)
 345 {
 346         u_char          fifo_state;
 347         struct bzfifo   *bzt;
 348
 349         if (fifo) {
 350                 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
 351                 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2TX;
 352         } else {
 353                 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
 354                 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1TX;
 355         }
 356         if (fifo_state)
 357                 hc->hw.fifo_en ^= fifo_state;
 358         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 359         if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
 360                 printk(KERN_DEBUG "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) "
 361                     "z1(%x) z2(%x) state(%x)\n",
 362                     fifo, bzt->f1, bzt->f2,
 363                     le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
 364                     le16_to_cpu(bzt->za[MAX_B_FRAMES].z2),
 365                     fifo_state);
 366         bzt->f2 = MAX_B_FRAMES;
 367         bzt->f1 = bzt->f2;      /* init F pointers to remain constant */
 368         bzt->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
 369         bzt->za[MAX_B_FRAMES].z2 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 2);
 370         if (fifo_state)
 371                 hc->hw.fifo_en |= fifo_state;
 372         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 373         if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
 374                 printk(KERN_DEBUG
 375                     "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) z1(%x) z2(%x)\n",
 376                     fifo, bzt->f1, bzt->f2,
 377                     le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
 378                     le16_to_cpu(bzt->za[MAX_B_FRAMES].z2));
 379 }
 380
 381 /*
 382  * read a complete B-frame out of the buffer
 383  */
 384 static void
 385 hfcpci_empty_bfifo(struct bchannel *bch, struct bzfifo *bz,
 386     u_char *bdata, int count)
 387 {
 388         u_char          *ptr, *ptr1, new_f2;
 389         int             total, maxlen, new_z2;
 390         struct zt       *zp;
 391
 392         if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
 393                 printk(KERN_DEBUG "hfcpci_empty_fifo\n");
 394         zp = &bz->za[bz->f2];   /* point to Z-Regs */
 395         new_z2 = le16_to_cpu(zp->z2) + count;   /* new position in fifo */
 396         if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
 397                 new_z2 -= B_FIFO_SIZE;  /* buffer wrap */
 398         new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
 399         if ((count > MAX_DATA_SIZE + 3) || (count < 4) ||
 400             (*(bdata + (le16_to_cpu(zp->z1) - B_SUB_VAL)))) {
 401                 if (bch->debug & DEBUG_HW)
 402                         printk(KERN_DEBUG "hfcpci_empty_fifo: incoming packet "
 403                             "invalid length %d or crc\n", count);
 404 #ifdef ERROR_STATISTIC
 405                 bch->err_inv++;
 406 #endif
 407                 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
 408                 bz->f2 = new_f2;        /* next buffer */
 409         } else {
 410                 bch->rx_skb = mI_alloc_skb(count - 3, GFP_ATOMIC);
 411                 if (!bch->rx_skb) {
 412                         printk(KERN_WARNING "HFCPCI: receive out of memory\n");
 413                         return;
 414                 }
 415                 total = count;
 416                 count -= 3;
 417                 ptr = skb_put(bch->rx_skb, count);
 418
 419                 if (le16_to_cpu(zp->z2) + count <= B_FIFO_SIZE + B_SUB_VAL)
 420                         maxlen = count;         /* complete transfer */
 421                 else
 422                         maxlen = B_FIFO_SIZE + B_SUB_VAL -
 423                             le16_to_cpu(zp->z2);        /* maximum */
 424
 425                 ptr1 = bdata + (le16_to_cpu(zp->z2) - B_SUB_VAL);
 426                     /* start of data */
 427                 memcpy(ptr, ptr1, maxlen);      /* copy data */
 428                 count -= maxlen;
 429
 430                 if (count) {    /* rest remaining */
 431                         ptr += maxlen;
 432                         ptr1 = bdata;   /* start of buffer */
 433                         memcpy(ptr, ptr1, count);       /* rest */
 434                 }
 435                 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
 436                 bz->f2 = new_f2;        /* next buffer */
 437                 recv_Bchannel(bch);
 438         }
 439 }
 440
 441 /*
 442  * D-channel receive procedure
 443  */
 444 static int
 445 receive_dmsg(struct hfc_pci *hc)
 446 {
 447         struct dchannel *dch = &hc->dch;
 448         int             maxlen;
 449         int             rcnt, total;
 450         int             count = 5;
 451         u_char          *ptr, *ptr1;
 452         struct dfifo    *df;
 453         struct zt       *zp;
 454
 455         df = &((union fifo_area *)(hc->hw.fifos))->d_chan.d_rx;
 456         while (((df->f1 & D_FREG_MASK) != (df->f2 & D_FREG_MASK)) && count--) {
 457                 zp = &df->za[df->f2 & D_FREG_MASK];
 458                 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
 459                 if (rcnt < 0)
 460                         rcnt += D_FIFO_SIZE;
 461                 rcnt++;
 462                 if (dch->debug & DEBUG_HW_DCHANNEL)
 463                         printk(KERN_DEBUG
 464                             "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)\n",
 465                                 df->f1, df->f2,
 466                                 le16_to_cpu(zp->z1),
 467                                 le16_to_cpu(zp->z2),
 468                                 rcnt);
 469
 470                 if ((rcnt > MAX_DFRAME_LEN + 3) || (rcnt < 4) ||
 471                     (df->data[le16_to_cpu(zp->z1)])) {
 472                         if (dch->debug & DEBUG_HW)
 473                                 printk(KERN_DEBUG
 474                                     "empty_fifo hfcpci paket inv. len "
 475                                     "%d or crc %d\n",
 476                                     rcnt,
 477                                     df->data[le16_to_cpu(zp->z1)]);
 478 #ifdef ERROR_STATISTIC
 479                         cs->err_rx++;
 480 #endif
 481                         df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
 482                             (MAX_D_FRAMES + 1); /* next buffer */
 483                         df->za[df->f2 & D_FREG_MASK].z2 =
 484                             cpu_to_le16((le16_to_cpu(zp->z2) + rcnt) & (D_FIFO_SIZE - 1));
 485                 } else {
 486                         dch->rx_skb = mI_alloc_skb(rcnt - 3, GFP_ATOMIC);
 487                         if (!dch->rx_skb) {
 488                                 printk(KERN_WARNING
 489                                     "HFC-PCI: D receive out of memory\n");
 490                                 break;
 491                         }
 492                         total = rcnt;
 493                         rcnt -= 3;
 494                         ptr = skb_put(dch->rx_skb, rcnt);
 495
 496                         if (le16_to_cpu(zp->z2) + rcnt <= D_FIFO_SIZE)
 497                                 maxlen = rcnt;  /* complete transfer */
 498                         else
 499                                 maxlen = D_FIFO_SIZE - le16_to_cpu(zp->z2);
 500                                     /* maximum */
 501
 502                         ptr1 = df->data + le16_to_cpu(zp->z2);
 503                             /* start of data */
 504                         memcpy(ptr, ptr1, maxlen);      /* copy data */
 505                         rcnt -= maxlen;
 506
 507                         if (rcnt) {     /* rest remaining */
 508                                 ptr += maxlen;
 509                                 ptr1 = df->data;        /* start of buffer */
 510                                 memcpy(ptr, ptr1, rcnt);        /* rest */
 511                         }
 512                         df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
 513                             (MAX_D_FRAMES + 1); /* next buffer */
 514                         df->za[df->f2 & D_FREG_MASK].z2 = cpu_to_le16((
 515                             le16_to_cpu(zp->z2) + total) & (D_FIFO_SIZE - 1));
 516                         recv_Dchannel(dch);
 517                 }
 518         }
 519         return 1;
 520 }
 521
 522 /*
 523  * check for transparent receive data and read max one threshold size if avail
 524  */
 525 static int
 526 hfcpci_empty_fifo_trans(struct bchannel *bch, struct bzfifo *bz, u_char *bdata)
 527 {
 528          __le16 *z1r, *z2r;
 529         int             new_z2, fcnt, maxlen;
 530         u_char          *ptr, *ptr1;
 531
 532         z1r = &bz->za[MAX_B_FRAMES].z1;         /* pointer to z reg */
 533         z2r = z1r + 1;
 534
 535         fcnt = le16_to_cpu(*z1r) - le16_to_cpu(*z2r);
 536         if (!fcnt)
 537                 return 0;       /* no data avail */
 538
 539         if (fcnt <= 0)
 540                 fcnt += B_FIFO_SIZE;    /* bytes actually buffered */
 541         if (fcnt > HFCPCI_BTRANS_THRESHOLD)
 542                 fcnt = HFCPCI_BTRANS_THRESHOLD;         /* limit size */
 543
 544         new_z2 = le16_to_cpu(*z2r) + fcnt;      /* new position in fifo */
 545         if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
 546                 new_z2 -= B_FIFO_SIZE;  /* buffer wrap */
 547
 548         bch->rx_skb = mI_alloc_skb(fcnt, GFP_ATOMIC);
 549         if (bch->rx_skb) {
 550                 ptr = skb_put(bch->rx_skb, fcnt);
 551                 if (le16_to_cpu(*z2r) + fcnt <= B_FIFO_SIZE + B_SUB_VAL)
 552                         maxlen = fcnt;  /* complete transfer */
 553                 else
 554                         maxlen = B_FIFO_SIZE + B_SUB_VAL - le16_to_cpu(*z2r);
 555                             /* maximum */
 556
 557                 ptr1 = bdata + (le16_to_cpu(*z2r) - B_SUB_VAL);
 558                     /* start of data */
 559                 memcpy(ptr, ptr1, maxlen);      /* copy data */
 560                 fcnt -= maxlen;
 561
 562                 if (fcnt) {     /* rest remaining */
 563                         ptr += maxlen;
 564                         ptr1 = bdata;   /* start of buffer */
 565                         memcpy(ptr, ptr1, fcnt);        /* rest */
 566                 }
 567                 recv_Bchannel(bch);
 568         } else
 569                 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
 570
 571         *z2r = cpu_to_le16(new_z2);             /* new position */
 572         return 1;
 573 }
 574
 575 /*
 576  * B-channel main receive routine
 577  */
 578 static void
 579 main_rec_hfcpci(struct bchannel *bch)
 580 {
 581         struct hfc_pci  *hc = bch->hw;
 582         int             rcnt, real_fifo;
 583         int             receive, count = 5;
 584         struct bzfifo   *bz;
 585         u_char          *bdata;
 586         struct zt       *zp;
 587
 588
 589         if ((bch->nr & 2) && (!hc->hw.bswapped)) {
 590                 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
 591                 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b2;
 592                 real_fifo = 1;
 593         } else {
 594                 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
 595                 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b1;
 596                 real_fifo = 0;
 597         }
 598 Begin:
 599         count--;
 600         if (bz->f1 != bz->f2) {
 601                 if (bch->debug & DEBUG_HW_BCHANNEL)
 602                         printk(KERN_DEBUG "hfcpci rec ch(%x) f1(%d) f2(%d)\n",
 603                             bch->nr, bz->f1, bz->f2);
 604                 zp = &bz->za[bz->f2];
 605
 606                 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
 607                 if (rcnt < 0)
 608                         rcnt += B_FIFO_SIZE;
 609                 rcnt++;
 610                 if (bch->debug & DEBUG_HW_BCHANNEL)
 611                         printk(KERN_DEBUG
 612                             "hfcpci rec ch(%x) z1(%x) z2(%x) cnt(%d)\n",
 613                             bch->nr, le16_to_cpu(zp->z1),
 614                             le16_to_cpu(zp->z2), rcnt);
 615                 hfcpci_empty_bfifo(bch, bz, bdata, rcnt);
 616                 rcnt = bz->f1 - bz->f2;
 617                 if (rcnt < 0)
 618                         rcnt += MAX_B_FRAMES + 1;
 619                 if (hc->hw.last_bfifo_cnt[real_fifo] > rcnt + 1) {
 620                         rcnt = 0;
 621                         hfcpci_clear_fifo_rx(hc, real_fifo);
 622                 }
 623                 hc->hw.last_bfifo_cnt[real_fifo] = rcnt;
 624                 if (rcnt > 1)
 625                         receive = 1;
 626                 else
 627                         receive = 0;
 628         } else if (test_bit(FLG_TRANSPARENT, &bch->Flags))
 629                 receive = hfcpci_empty_fifo_trans(bch, bz, bdata);
 630         else
 631                 receive = 0;
 632         if (count && receive)
 633                 goto Begin;
 634
 635 }
 636
 637 /*
 638  * D-channel send routine
 639  */
 640 static void
 641 hfcpci_fill_dfifo(struct hfc_pci *hc)
 642 {
 643         struct dchannel *dch = &hc->dch;
 644         int             fcnt;
 645         int             count, new_z1, maxlen;
 646         struct dfifo    *df;
 647         u_char          *src, *dst, new_f1;
 648
 649         if ((dch->debug & DEBUG_HW_DCHANNEL) && !(dch->debug & DEBUG_HW_DFIFO))
 650                 printk(KERN_DEBUG "%s\n", __func__);
 651
 652         if (!dch->tx_skb)
 653                 return;
 654         count = dch->tx_skb->len - dch->tx_idx;
 655         if (count <= 0)
 656                 return;
 657         df = &((union fifo_area *) (hc->hw.fifos))->d_chan.d_tx;
 658
 659         if (dch->debug & DEBUG_HW_DFIFO)
 660                 printk(KERN_DEBUG "%s:f1(%d) f2(%d) z1(f1)(%x)\n", __func__,
 661                     df->f1, df->f2,
 662                     le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1));
 663         fcnt = df->f1 - df->f2; /* frame count actually buffered */
 664         if (fcnt < 0)
 665                 fcnt += (MAX_D_FRAMES + 1);     /* if wrap around */
 666         if (fcnt > (MAX_D_FRAMES - 1)) {
 667                 if (dch->debug & DEBUG_HW_DCHANNEL)
 668                         printk(KERN_DEBUG
 669                             "hfcpci_fill_Dfifo more as 14 frames\n");
 670 #ifdef ERROR_STATISTIC
 671                 cs->err_tx++;
 672 #endif
 673                 return;
 674         }
 675         /* now determine free bytes in FIFO buffer */
 676         maxlen = le16_to_cpu(df->za[df->f2 & D_FREG_MASK].z2) -
 677             le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) - 1;
 678         if (maxlen <= 0)
 679                 maxlen += D_FIFO_SIZE;  /* count now contains available bytes */
 680
 681         if (dch->debug & DEBUG_HW_DCHANNEL)
 682                 printk(KERN_DEBUG "hfcpci_fill_Dfifo count(%d/%d)\n",
 683                         count, maxlen);
 684         if (count > maxlen) {
 685                 if (dch->debug & DEBUG_HW_DCHANNEL)
 686                         printk(KERN_DEBUG "hfcpci_fill_Dfifo no fifo mem\n");
 687                 return;
 688         }
 689         new_z1 = (le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) + count) &
 690             (D_FIFO_SIZE - 1);
 691         new_f1 = ((df->f1 + 1) & D_FREG_MASK) | (D_FREG_MASK + 1);
 692         src = dch->tx_skb->data + dch->tx_idx;  /* source pointer */
 693         dst = df->data + le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
 694         maxlen = D_FIFO_SIZE - le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
 695             /* end fifo */
 696         if (maxlen > count)
 697                 maxlen = count; /* limit size */
 698         memcpy(dst, src, maxlen);       /* first copy */
 699
 700         count -= maxlen;        /* remaining bytes */
 701         if (count) {
 702                 dst = df->data; /* start of buffer */
 703                 src += maxlen;  /* new position */
 704                 memcpy(dst, src, count);
 705         }
 706         df->za[new_f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
 707             /* for next buffer */
 708         df->za[df->f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
 709             /* new pos actual buffer */
 710         df->f1 = new_f1;        /* next frame */
 711         dch->tx_idx = dch->tx_skb->len;
 712 }
 713
 714 /*
 715  * B-channel send routine
 716  */
 717 static void
 718 hfcpci_fill_fifo(struct bchannel *bch)
 719 {
 720         struct hfc_pci  *hc = bch->hw;
 721         int             maxlen, fcnt;
 722         int             count, new_z1;
 723         struct bzfifo   *bz;
 724         u_char          *bdata;
 725         u_char          new_f1, *src, *dst;
 726         __le16 *z1t, *z2t;
 727
 728         if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
 729                 printk(KERN_DEBUG "%s\n", __func__);
 730         if ((!bch->tx_skb) || bch->tx_skb->len <= 0)
 731                 return;
 732         count = bch->tx_skb->len - bch->tx_idx;
 733         if ((bch->nr & 2) && (!hc->hw.bswapped)) {
 734                 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
 735                 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b2;
 736         } else {
 737                 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
 738                 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b1;
 739         }
 740
 741         if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
 742                 z1t = &bz->za[MAX_B_FRAMES].z1;
 743                 z2t = z1t + 1;
 744                 if (bch->debug & DEBUG_HW_BCHANNEL)
 745                         printk(KERN_DEBUG "hfcpci_fill_fifo_trans ch(%x) "
 746                             "cnt(%d) z1(%x) z2(%x)\n", bch->nr, count,
 747                             le16_to_cpu(*z1t), le16_to_cpu(*z2t));
 748                 fcnt = le16_to_cpu(*z2t) - le16_to_cpu(*z1t);
 749                 if (fcnt <= 0)
 750                         fcnt += B_FIFO_SIZE;
 751                             /* fcnt contains available bytes in fifo */
 752                 fcnt = B_FIFO_SIZE - fcnt;
 753                     /* remaining bytes to send (bytes in fifo) */
 754
 755                 /* "fill fifo if empty" feature */
 756                 if (test_bit(FLG_FILLEMPTY, &bch->Flags) && !fcnt) {
 757                         /* printk(KERN_DEBUG "%s: buffer empty, so we have "
 758                                 "underrun\n", __func__); */
 759                         /* fill buffer, to prevent future underrun */
 760                         count = HFCPCI_FILLEMPTY;
 761                         new_z1 = le16_to_cpu(*z1t) + count;
 762                            /* new buffer Position */
 763                         if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
 764                                 new_z1 -= B_FIFO_SIZE;  /* buffer wrap */
 765                         dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
 766                         maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
 767                             /* end of fifo */
 768                         if (bch->debug & DEBUG_HW_BFIFO)
 769                                 printk(KERN_DEBUG "hfcpci_FFt fillempty "
 770                                     "fcnt(%d) maxl(%d) nz1(%x) dst(%p)\n",
 771                                     fcnt, maxlen, new_z1, dst);
 772                         fcnt += count;
 773                         if (maxlen > count)
 774                                 maxlen = count;         /* limit size */
 775                         memset(dst, 0x2a, maxlen);      /* first copy */
 776                         count -= maxlen;                /* remaining bytes */
 777                         if (count) {
 778                                 dst = bdata;            /* start of buffer */
 779                                 memset(dst, 0x2a, count);
 780                         }
 781                         *z1t = cpu_to_le16(new_z1);     /* now send data */
 782                 }
 783
 784 next_t_frame:
 785                 count = bch->tx_skb->len - bch->tx_idx;
 786                 /* maximum fill shall be HFCPCI_BTRANS_MAX */
 787                 if (count > HFCPCI_BTRANS_MAX - fcnt)
 788                         count = HFCPCI_BTRANS_MAX - fcnt;
 789                 if (count <= 0)
 790                         return;
 791                 /* data is suitable for fifo */
 792                 new_z1 = le16_to_cpu(*z1t) + count;
 793                     /* new buffer Position */
 794                 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
 795                         new_z1 -= B_FIFO_SIZE;  /* buffer wrap */
 796                 src = bch->tx_skb->data + bch->tx_idx;
 797                     /* source pointer */
 798                 dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
 799                 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
 800                     /* end of fifo */
 801                 if (bch->debug & DEBUG_HW_BFIFO)
 802                         printk(KERN_DEBUG "hfcpci_FFt fcnt(%d) "
 803                             "maxl(%d) nz1(%x) dst(%p)\n",
 804                             fcnt, maxlen, new_z1, dst);
 805                 fcnt += count;
 806                 bch->tx_idx += count;
 807                 if (maxlen > count)
 808                         maxlen = count;         /* limit size */
 809                 memcpy(dst, src, maxlen);       /* first copy */
 810                 count -= maxlen;        /* remaining bytes */
 811                 if (count) {
 812                         dst = bdata;    /* start of buffer */
 813                         src += maxlen;  /* new position */
 814                         memcpy(dst, src, count);
 815                 }
 816                 *z1t = cpu_to_le16(new_z1);     /* now send data */
 817                 if (bch->tx_idx < bch->tx_skb->len)
 818                         return;
 819                 /* send confirm, on trans, free on hdlc. */
 820                 if (test_bit(FLG_TRANSPARENT, &bch->Flags))
 821                         confirm_Bsend(bch);
 822                 dev_kfree_skb(bch->tx_skb);
 823                 if (get_next_bframe(bch))
 824                         goto next_t_frame;
 825                 return;
 826         }
 827         if (bch->debug & DEBUG_HW_BCHANNEL)
 828                 printk(KERN_DEBUG
 829                     "%s: ch(%x) f1(%d) f2(%d) z1(f1)(%x)\n",
 830                     __func__, bch->nr, bz->f1, bz->f2,
 831                     bz->za[bz->f1].z1);
 832         fcnt = bz->f1 - bz->f2; /* frame count actually buffered */
 833         if (fcnt < 0)
 834                 fcnt += (MAX_B_FRAMES + 1);     /* if wrap around */
 835         if (fcnt > (MAX_B_FRAMES - 1)) {
 836                 if (bch->debug & DEBUG_HW_BCHANNEL)
 837                         printk(KERN_DEBUG
 838                             "hfcpci_fill_Bfifo more as 14 frames\n");
 839                 return;
 840         }
 841         /* now determine free bytes in FIFO buffer */
 842         maxlen = le16_to_cpu(bz->za[bz->f2].z2) -
 843             le16_to_cpu(bz->za[bz->f1].z1) - 1;
 844         if (maxlen <= 0)
 845                 maxlen += B_FIFO_SIZE;  /* count now contains available bytes */
 846
 847         if (bch->debug & DEBUG_HW_BCHANNEL)
 848                 printk(KERN_DEBUG "hfcpci_fill_fifo ch(%x) count(%d/%d)\n",
 849                         bch->nr, count, maxlen);
 850
 851         if (maxlen < count) {
 852                 if (bch->debug & DEBUG_HW_BCHANNEL)
 853                         printk(KERN_DEBUG "hfcpci_fill_fifo no fifo mem\n");
 854                 return;
 855         }
 856         new_z1 = le16_to_cpu(bz->za[bz->f1].z1) + count;
 857             /* new buffer Position */
 858         if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
 859                 new_z1 -= B_FIFO_SIZE;  /* buffer wrap */
 860
 861         new_f1 = ((bz->f1 + 1) & MAX_B_FRAMES);
 862         src = bch->tx_skb->data + bch->tx_idx;  /* source pointer */
 863         dst = bdata + (le16_to_cpu(bz->za[bz->f1].z1) - B_SUB_VAL);
 864         maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(bz->za[bz->f1].z1);
 865             /* end fifo */
 866         if (maxlen > count)
 867                 maxlen = count; /* limit size */
 868         memcpy(dst, src, maxlen);       /* first copy */
 869
 870         count -= maxlen;        /* remaining bytes */
 871         if (count) {
 872                 dst = bdata;    /* start of buffer */
 873                 src += maxlen;  /* new position */
 874                 memcpy(dst, src, count);
 875         }
 876         bz->za[new_f1].z1 = cpu_to_le16(new_z1);        /* for next buffer */
 877         bz->f1 = new_f1;        /* next frame */
 878         dev_kfree_skb(bch->tx_skb);
 879         get_next_bframe(bch);
 880 }
 881
 882
 883
 884 /*
 885  * handle L1 state changes TE
 886  */
 887
 888 static void
 889 ph_state_te(struct dchannel *dch)
 890 {
 891         if (dch->debug)
 892                 printk(KERN_DEBUG "%s: TE newstate %x\n",
 893                         __func__, dch->state);
 894         switch (dch->state) {
 895         case 0:
 896                 l1_event(dch->l1, HW_RESET_IND);
 897                 break;
 898         case 3:
 899                 l1_event(dch->l1, HW_DEACT_IND);
 900                 break;
 901         case 5:
 902         case 8:
 903                 l1_event(dch->l1, ANYSIGNAL);
 904                 break;
 905         case 6:
 906                 l1_event(dch->l1, INFO2);
 907                 break;
 908         case 7:
 909                 l1_event(dch->l1, INFO4_P8);
 910                 break;
 911         }
 912 }
 913
 914 /*
 915  * handle L1 state changes NT
 916  */
 917
 918 static void
 919 handle_nt_timer3(struct dchannel *dch) {
 920         struct hfc_pci  *hc = dch->hw;
 921
 922         test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
 923         hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
 924         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 925         hc->hw.nt_timer = 0;
 926         test_and_set_bit(FLG_ACTIVE, &dch->Flags);
 927         if (test_bit(HFC_CFG_MASTER, &hc->cfg))
 928                 hc->hw.mst_m |= HFCPCI_MASTER;
 929         Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
 930         _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
 931             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
 932 }
 933
 934 static void
 935 ph_state_nt(struct dchannel *dch)
 936 {
 937         struct hfc_pci  *hc = dch->hw;
 938
 939         if (dch->debug)
 940                 printk(KERN_DEBUG "%s: NT newstate %x\n",
 941                         __func__, dch->state);
 942         switch (dch->state) {
 943         case 2:
 944                 if (hc->hw.nt_timer < 0) {
 945                         hc->hw.nt_timer = 0;
 946                         test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
 947                         test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
 948                         hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
 949                         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 950                         /* Clear already pending ints */
 951                         if (Read_hfc(hc, HFCPCI_INT_S1));
 952                         Write_hfc(hc, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
 953                         udelay(10);
 954                         Write_hfc(hc, HFCPCI_STATES, 4);
 955                         dch->state = 4;
 956                 } else if (hc->hw.nt_timer == 0) {
 957                         hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
 958                         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 959                         hc->hw.nt_timer = NT_T1_COUNT;
 960                         hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
 961                         hc->hw.ctmt |= HFCPCI_TIM3_125;
 962                         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
 963                                 HFCPCI_CLTIMER);
 964                         test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
 965                         test_and_set_bit(FLG_HFC_TIMER_T1, &dch->Flags);
 966                         /* allow G2 -> G3 transition */
 967                         Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
 968                 } else {
 969                         Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
 970                 }
 971                 break;
 972         case 1:
 973                 hc->hw.nt_timer = 0;
 974                 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
 975                 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
 976                 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
 977                 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 978                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
 979                 hc->hw.mst_m &= ~HFCPCI_MASTER;
 980                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
 981                 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
 982                 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
 983                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
 984                 break;
 985         case 4:
 986                 hc->hw.nt_timer = 0;
 987                 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
 988                 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
 989                 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
 990                 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 991                 break;
 992         case 3:
 993                 if (!test_and_set_bit(FLG_HFC_TIMER_T3, &dch->Flags)) {
 994                         if (!test_and_clear_bit(FLG_L2_ACTIVATED,
 995                             &dch->Flags)) {
 996                                 handle_nt_timer3(dch);
 997                                 break;
 998                         }
 999                         test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1000                         hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
1001                         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1002                         hc->hw.nt_timer = NT_T3_COUNT;
1003                         hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
1004                         hc->hw.ctmt |= HFCPCI_TIM3_125;
1005                         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
1006                                 HFCPCI_CLTIMER);
1007                 }
1008                 break;
1009         }
1010 }
1011
1012 static void
1013 ph_state(struct dchannel *dch)
1014 {
1015         struct hfc_pci  *hc = dch->hw;
1016
1017         if (hc->hw.protocol == ISDN_P_NT_S0) {
1018                 if (test_bit(FLG_HFC_TIMER_T3, &dch->Flags) &&
1019                     hc->hw.nt_timer < 0)
1020                         handle_nt_timer3(dch);
1021                 else
1022                         ph_state_nt(dch);
1023         } else
1024                 ph_state_te(dch);
1025 }
1026
1027 /*
1028  * Layer 1 callback function
1029  */
1030 static int
1031 hfc_l1callback(struct dchannel *dch, u_int cmd)
1032 {
1033         struct hfc_pci          *hc = dch->hw;
1034
1035         switch (cmd) {
1036         case INFO3_P8:
1037         case INFO3_P10:
1038                 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1039                         hc->hw.mst_m |= HFCPCI_MASTER;
1040                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1041                 break;
1042         case HW_RESET_REQ:
1043                 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3);
1044                 /* HFC ST 3 */
1045                 udelay(6);
1046                 Write_hfc(hc, HFCPCI_STATES, 3);        /* HFC ST 2 */
1047                 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1048                         hc->hw.mst_m |= HFCPCI_MASTER;
1049                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1050                 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1051                    HFCPCI_DO_ACTION);
1052                 l1_event(dch->l1, HW_POWERUP_IND);
1053                 break;
1054         case HW_DEACT_REQ:
1055                 hc->hw.mst_m &= ~HFCPCI_MASTER;
1056                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1057                 skb_queue_purge(&dch->squeue);
1058                 if (dch->tx_skb) {
1059                         dev_kfree_skb(dch->tx_skb);
1060                         dch->tx_skb = NULL;
1061                 }
1062                 dch->tx_idx = 0;
1063                 if (dch->rx_skb) {
1064                         dev_kfree_skb(dch->rx_skb);
1065                         dch->rx_skb = NULL;
1066                 }
1067                 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1068                 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1069                         del_timer(&dch->timer);
1070                 break;
1071         case HW_POWERUP_REQ:
1072                 Write_hfc(hc, HFCPCI_STATES, HFCPCI_DO_ACTION);
1073                 break;
1074         case PH_ACTIVATE_IND:
1075                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
1076                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1077                         GFP_ATOMIC);
1078                 break;
1079         case PH_DEACTIVATE_IND:
1080                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
1081                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1082                         GFP_ATOMIC);
1083                 break;
1084         default:
1085                 if (dch->debug & DEBUG_HW)
1086                         printk(KERN_DEBUG "%s: unknown command %x\n",
1087                             __func__, cmd);
1088                 return -1;
1089         }
1090         return 0;
1091 }
1092
1093 /*
1094  * Interrupt handler
1095  */
1096 static inline void
1097 tx_birq(struct bchannel *bch)
1098 {
1099         if (bch->tx_skb && bch->tx_idx < bch->tx_skb->len)
1100                 hfcpci_fill_fifo(bch);
1101         else {
1102                 if (bch->tx_skb)
1103                         dev_kfree_skb(bch->tx_skb);
1104                 if (get_next_bframe(bch))
1105                         hfcpci_fill_fifo(bch);
1106         }
1107 }
1108
1109 static inline void
1110 tx_dirq(struct dchannel *dch)
1111 {
1112         if (dch->tx_skb && dch->tx_idx < dch->tx_skb->len)
1113                 hfcpci_fill_dfifo(dch->hw);
1114         else {
1115                 if (dch->tx_skb)
1116                         dev_kfree_skb(dch->tx_skb);
1117                 if (get_next_dframe(dch))
1118                         hfcpci_fill_dfifo(dch->hw);
1119         }
1120 }
1121
1122 static irqreturn_t
1123 hfcpci_int(int intno, void *dev_id)
1124 {
1125         struct hfc_pci  *hc = dev_id;
1126         u_char          exval;
1127         struct bchannel *bch;
1128         u_char          val, stat;
1129
1130         spin_lock(&hc->lock);
1131         if (!(hc->hw.int_m2 & 0x08)) {
1132                 spin_unlock(&hc->lock);
1133                 return IRQ_NONE; /* not initialised */
1134         }
1135         stat = Read_hfc(hc, HFCPCI_STATUS);
1136         if (HFCPCI_ANYINT & stat) {
1137                 val = Read_hfc(hc, HFCPCI_INT_S1);
1138                 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1139                         printk(KERN_DEBUG
1140                             "HFC-PCI: stat(%02x) s1(%02x)\n", stat, val);
1141         } else {
1142                 /* shared */
1143                 spin_unlock(&hc->lock);
1144                 return IRQ_NONE;
1145         }
1146         hc->irqcnt++;
1147
1148         if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1149                 printk(KERN_DEBUG "HFC-PCI irq %x\n", val);
1150         val &= hc->hw.int_m1;
1151         if (val & 0x40) {       /* state machine irq */
1152                 exval = Read_hfc(hc, HFCPCI_STATES) & 0xf;
1153                 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1154                         printk(KERN_DEBUG "ph_state chg %d->%d\n",
1155                                 hc->dch.state, exval);
1156                 hc->dch.state = exval;
1157                 schedule_event(&hc->dch, FLG_PHCHANGE);
1158                 val &= ~0x40;
1159         }
1160         if (val & 0x80) {       /* timer irq */
1161                 if (hc->hw.protocol == ISDN_P_NT_S0) {
1162                         if ((--hc->hw.nt_timer) < 0)
1163                                 schedule_event(&hc->dch, FLG_PHCHANGE);
1164                 }
1165                 val &= ~0x80;
1166                 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt | HFCPCI_CLTIMER);
1167         }
1168         if (val & 0x08) {
1169                 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1170                 if (bch)
1171                         main_rec_hfcpci(bch);
1172                 else if (hc->dch.debug)
1173                         printk(KERN_DEBUG "hfcpci spurious 0x08 IRQ\n");
1174         }
1175         if (val & 0x10) {
1176                 bch = Sel_BCS(hc, 2);
1177                 if (bch)
1178                         main_rec_hfcpci(bch);
1179                 else if (hc->dch.debug)
1180                         printk(KERN_DEBUG "hfcpci spurious 0x10 IRQ\n");
1181         }
1182         if (val & 0x01) {
1183                 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1184                 if (bch)
1185                         tx_birq(bch);
1186                 else if (hc->dch.debug)
1187                         printk(KERN_DEBUG "hfcpci spurious 0x01 IRQ\n");
1188         }
1189         if (val & 0x02) {
1190                 bch = Sel_BCS(hc, 2);
1191                 if (bch)
1192                         tx_birq(bch);
1193                 else if (hc->dch.debug)
1194                         printk(KERN_DEBUG "hfcpci spurious 0x02 IRQ\n");
1195         }
1196         if (val & 0x20)
1197                 receive_dmsg(hc);
1198         if (val & 0x04) {       /* dframe transmitted */
1199                 if (test_and_clear_bit(FLG_BUSY_TIMER, &hc->dch.Flags))
1200                         del_timer(&hc->dch.timer);
1201                 tx_dirq(&hc->dch);
1202         }
1203         spin_unlock(&hc->lock);
1204         return IRQ_HANDLED;
1205 }
1206
1207 /*
1208  * timer callback for D-chan busy resolution. Currently no function
1209  */
1210 static void
1211 hfcpci_dbusy_timer(struct hfc_pci *hc)
1212 {
1213 }
1214
1215 /*
1216  * activate/deactivate hardware for selected channels and mode
1217  */
1218 static int
1219 mode_hfcpci(struct bchannel *bch, int bc, int protocol)
1220 {
1221         struct hfc_pci  *hc = bch->hw;
1222         int             fifo2;
1223         u_char          rx_slot = 0, tx_slot = 0, pcm_mode;
1224
1225         if (bch->debug & DEBUG_HW_BCHANNEL)
1226                 printk(KERN_DEBUG
1227                     "HFCPCI bchannel protocol %x-->%x ch %x-->%x\n",
1228                     bch->state, protocol, bch->nr, bc);
1229
1230         fifo2 = bc;
1231         pcm_mode = (bc>>24) & 0xff;
1232         if (pcm_mode) { /* PCM SLOT USE */
1233                 if (!test_bit(HFC_CFG_PCM, &hc->cfg))
1234                         printk(KERN_WARNING
1235                             "%s: pcm channel id without HFC_CFG_PCM\n",
1236                             __func__);
1237                 rx_slot = (bc>>8) & 0xff;
1238                 tx_slot = (bc>>16) & 0xff;
1239                 bc = bc & 0xff;
1240         } else if (test_bit(HFC_CFG_PCM, &hc->cfg) &&
1241             (protocol > ISDN_P_NONE))
1242                 printk(KERN_WARNING "%s: no pcm channel id but HFC_CFG_PCM\n",
1243                     __func__);
1244         if (hc->chanlimit > 1) {
1245                 hc->hw.bswapped = 0;    /* B1 and B2 normal mode */
1246                 hc->hw.sctrl_e &= ~0x80;
1247         } else {
1248                 if (bc & 2) {
1249                         if (protocol != ISDN_P_NONE) {
1250                                 hc->hw.bswapped = 1; /* B1 and B2 exchanged */
1251                                 hc->hw.sctrl_e |= 0x80;
1252                         } else {
1253                                 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1254                                 hc->hw.sctrl_e &= ~0x80;
1255                         }
1256                         fifo2 = 1;
1257                 } else {
1258                         hc->hw.bswapped = 0;    /* B1 and B2 normal mode */
1259                         hc->hw.sctrl_e &= ~0x80;
1260                 }
1261         }
1262         switch (protocol) {
1263         case (-1): /* used for init */
1264                 bch->state = -1;
1265                 bch->nr = bc;
1266         case (ISDN_P_NONE):
1267                 if (bch->state == ISDN_P_NONE)
1268                         return 0;
1269                 if (bc & 2) {
1270                         hc->hw.sctrl &= ~SCTRL_B2_ENA;
1271                         hc->hw.sctrl_r &= ~SCTRL_B2_ENA;
1272                 } else {
1273                         hc->hw.sctrl &= ~SCTRL_B1_ENA;
1274                         hc->hw.sctrl_r &= ~SCTRL_B1_ENA;
1275                 }
1276                 if (fifo2 & 2) {
1277                         hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B2;
1278                         hc->hw.int_m1 &= ~(HFCPCI_INTS_B2TRANS +
1279                                 HFCPCI_INTS_B2REC);
1280                 } else {
1281                         hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B1;
1282                         hc->hw.int_m1 &= ~(HFCPCI_INTS_B1TRANS +
1283                                 HFCPCI_INTS_B1REC);
1284                 }
1285 #ifdef REVERSE_BITORDER
1286                 if (bch->nr & 2)
1287                         hc->hw.cirm &= 0x7f;
1288                 else
1289                         hc->hw.cirm &= 0xbf;
1290 #endif
1291                 bch->state = ISDN_P_NONE;
1292                 bch->nr = bc;
1293                 test_and_clear_bit(FLG_HDLC, &bch->Flags);
1294                 test_and_clear_bit(FLG_TRANSPARENT, &bch->Flags);
1295                 break;
1296         case (ISDN_P_B_RAW):
1297                 bch->state = protocol;
1298                 bch->nr = bc;
1299                 hfcpci_clear_fifo_rx(hc, (fifo2 & 2)?1:0);
1300                 hfcpci_clear_fifo_tx(hc, (fifo2 & 2)?1:0);
1301                 if (bc & 2) {
1302                         hc->hw.sctrl |= SCTRL_B2_ENA;
1303                         hc->hw.sctrl_r |= SCTRL_B2_ENA;
1304 #ifdef REVERSE_BITORDER
1305                         hc->hw.cirm |= 0x80;
1306 #endif
1307                 } else {
1308                         hc->hw.sctrl |= SCTRL_B1_ENA;
1309                         hc->hw.sctrl_r |= SCTRL_B1_ENA;
1310 #ifdef REVERSE_BITORDER
1311                         hc->hw.cirm |= 0x40;
1312 #endif
1313                 }
1314                 if (fifo2 & 2) {
1315                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1316                         hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS +
1317                             HFCPCI_INTS_B2REC);
1318                         hc->hw.ctmt |= 2;
1319                         hc->hw.conn &= ~0x18;
1320                 } else {
1321                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1322                         hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS +
1323                             HFCPCI_INTS_B1REC);
1324                         hc->hw.ctmt |= 1;
1325                         hc->hw.conn &= ~0x03;
1326                 }
1327                 test_and_set_bit(FLG_TRANSPARENT, &bch->Flags);
1328                 break;
1329         case (ISDN_P_B_HDLC):
1330                 bch->state = protocol;
1331                 bch->nr = bc;
1332                 hfcpci_clear_fifo_rx(hc, (fifo2 & 2)?1:0);
1333                 hfcpci_clear_fifo_tx(hc, (fifo2 & 2)?1:0);
1334                 if (bc & 2) {
1335                         hc->hw.sctrl |= SCTRL_B2_ENA;
1336                         hc->hw.sctrl_r |= SCTRL_B2_ENA;
1337                 } else {
1338                         hc->hw.sctrl |= SCTRL_B1_ENA;
1339                         hc->hw.sctrl_r |= SCTRL_B1_ENA;
1340                 }
1341                 if (fifo2 & 2) {
1342                         hc->hw.last_bfifo_cnt[1] = 0;
1343                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1344                         hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS +
1345                             HFCPCI_INTS_B2REC);
1346                         hc->hw.ctmt &= ~2;
1347                         hc->hw.conn &= ~0x18;
1348                 } else {
1349                         hc->hw.last_bfifo_cnt[0] = 0;
1350                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1351                         hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS +
1352                             HFCPCI_INTS_B1REC);
1353                         hc->hw.ctmt &= ~1;
1354                         hc->hw.conn &= ~0x03;
1355                 }
1356                 test_and_set_bit(FLG_HDLC, &bch->Flags);
1357                 break;
1358         default:
1359                 printk(KERN_DEBUG "prot not known %x\n", protocol);
1360                 return -ENOPROTOOPT;
1361         }
1362         if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
1363                 if ((protocol == ISDN_P_NONE) ||
1364                         (protocol == -1)) {     /* init case */
1365                         rx_slot = 0;
1366                         tx_slot = 0;
1367                 } else {
1368                         if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
1369                                 rx_slot |= 0xC0;
1370                                 tx_slot |= 0xC0;
1371                         } else {
1372                                 rx_slot |= 0x80;
1373                                 tx_slot |= 0x80;
1374                         }
1375                 }
1376                 if (bc & 2) {
1377                         hc->hw.conn &= 0xc7;
1378                         hc->hw.conn |= 0x08;
1379                         printk(KERN_DEBUG "%s: Write_hfc: B2_SSL 0x%x\n",
1380                                 __func__, tx_slot);
1381                         printk(KERN_DEBUG "%s: Write_hfc: B2_RSL 0x%x\n",
1382                                 __func__, rx_slot);
1383                         Write_hfc(hc, HFCPCI_B2_SSL, tx_slot);
1384                         Write_hfc(hc, HFCPCI_B2_RSL, rx_slot);
1385                 } else {
1386                         hc->hw.conn &= 0xf8;
1387                         hc->hw.conn |= 0x01;
1388                         printk(KERN_DEBUG "%s: Write_hfc: B1_SSL 0x%x\n",
1389                                 __func__, tx_slot);
1390                         printk(KERN_DEBUG "%s: Write_hfc: B1_RSL 0x%x\n",
1391                                 __func__, rx_slot);
1392                         Write_hfc(hc, HFCPCI_B1_SSL, tx_slot);
1393                         Write_hfc(hc, HFCPCI_B1_RSL, rx_slot);
1394                 }
1395         }
1396         Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
1397         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1398         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1399         Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
1400         Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1401         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1402         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1403 #ifdef REVERSE_BITORDER
1404         Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1405 #endif
1406         return 0;
1407 }
1408
1409 static int
1410 set_hfcpci_rxtest(struct bchannel *bch, int protocol, int chan)
1411 {
1412         struct hfc_pci  *hc = bch->hw;
1413
1414         if (bch->debug & DEBUG_HW_BCHANNEL)
1415                 printk(KERN_DEBUG
1416                     "HFCPCI bchannel test rx protocol %x-->%x ch %x-->%x\n",
1417                     bch->state, protocol, bch->nr, chan);
1418         if (bch->nr != chan) {
1419                 printk(KERN_DEBUG
1420                     "HFCPCI rxtest wrong channel parameter %x/%x\n",
1421                     bch->nr, chan);
1422                 return -EINVAL;
1423         }
1424         switch (protocol) {
1425         case (ISDN_P_B_RAW):
1426                 bch->state = protocol;
1427                 hfcpci_clear_fifo_rx(hc, (chan & 2)?1:0);
1428                 if (chan & 2) {
1429                         hc->hw.sctrl_r |= SCTRL_B2_ENA;
1430                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1431                         hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1432                         hc->hw.ctmt |= 2;
1433                         hc->hw.conn &= ~0x18;
1434 #ifdef REVERSE_BITORDER
1435                         hc->hw.cirm |= 0x80;
1436 #endif
1437                 } else {
1438                         hc->hw.sctrl_r |= SCTRL_B1_ENA;
1439                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1440                         hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1441                         hc->hw.ctmt |= 1;
1442                         hc->hw.conn &= ~0x03;
1443 #ifdef REVERSE_BITORDER
1444                         hc->hw.cirm |= 0x40;
1445 #endif
1446                 }
1447                 break;
1448         case (ISDN_P_B_HDLC):
1449                 bch->state = protocol;
1450                 hfcpci_clear_fifo_rx(hc, (chan & 2)?1:0);
1451                 if (chan & 2) {
1452                         hc->hw.sctrl_r |= SCTRL_B2_ENA;
1453                         hc->hw.last_bfifo_cnt[1] = 0;
1454                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1455                         hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1456                         hc->hw.ctmt &= ~2;
1457                         hc->hw.conn &= ~0x18;
1458                 } else {
1459                         hc->hw.sctrl_r |= SCTRL_B1_ENA;
1460                         hc->hw.last_bfifo_cnt[0] = 0;
1461                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1462                         hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1463                         hc->hw.ctmt &= ~1;
1464                         hc->hw.conn &= ~0x03;
1465                 }
1466                 break;
1467         default:
1468                 printk(KERN_DEBUG "prot not known %x\n", protocol);
1469                 return -ENOPROTOOPT;
1470         }
1471         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1472         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1473         Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1474         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1475         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1476 #ifdef REVERSE_BITORDER
1477         Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1478 #endif
1479         return 0;
1480 }
1481
1482 static void
1483 deactivate_bchannel(struct bchannel *bch)
1484 {
1485         struct hfc_pci  *hc = bch->hw;
1486         u_long          flags;
1487
1488         spin_lock_irqsave(&hc->lock, flags);
1489         if (test_and_clear_bit(FLG_TX_NEXT, &bch->Flags)) {
1490                 dev_kfree_skb(bch->next_skb);
1491                 bch->next_skb = NULL;
1492         }
1493         if (bch->tx_skb) {
1494                 dev_kfree_skb(bch->tx_skb);
1495                 bch->tx_skb = NULL;
1496         }
1497         bch->tx_idx = 0;
1498         if (bch->rx_skb) {
1499                 dev_kfree_skb(bch->rx_skb);
1500                 bch->rx_skb = NULL;
1501         }
1502         mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1503         test_and_clear_bit(FLG_ACTIVE, &bch->Flags);
1504         test_and_clear_bit(FLG_TX_BUSY, &bch->Flags);
1505         spin_unlock_irqrestore(&hc->lock, flags);
1506 }
1507
1508 /*
1509  * Layer 1 B-channel hardware access
1510  */
1511 static int
1512 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
1513 {
1514         int     ret = 0;
1515
1516         switch (cq->op) {
1517         case MISDN_CTRL_GETOP:
1518                 cq->op = MISDN_CTRL_FILL_EMPTY;
1519                 break;
1520         case MISDN_CTRL_FILL_EMPTY: /* fill fifo, if empty */
1521                 test_and_set_bit(FLG_FILLEMPTY, &bch->Flags);
1522                 if (debug & DEBUG_HW_OPEN)
1523                         printk(KERN_DEBUG "%s: FILL_EMPTY request (nr=%d "
1524                                 "off=%d)\n", __func__, bch->nr, !!cq->p1);
1525                 break;
1526         default:
1527                 printk(KERN_WARNING "%s: unknown Op %x\n", __func__, cq->op);
1528                 ret = -EINVAL;
1529                 break;
1530         }
1531         return ret;
1532 }
1533 static int
1534 hfc_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1535 {
1536         struct bchannel *bch = container_of(ch, struct bchannel, ch);
1537         struct hfc_pci  *hc = bch->hw;
1538         int             ret = -EINVAL;
1539         u_long          flags;
1540
1541         if (bch->debug & DEBUG_HW)
1542                 printk(KERN_DEBUG "%s: cmd:%x %p\n", __func__, cmd, arg);
1543         switch (cmd) {
1544         case HW_TESTRX_RAW:
1545                 spin_lock_irqsave(&hc->lock, flags);
1546                 ret = set_hfcpci_rxtest(bch, ISDN_P_B_RAW, (int)(long)arg);
1547                 spin_unlock_irqrestore(&hc->lock, flags);
1548                 break;
1549         case HW_TESTRX_HDLC:
1550                 spin_lock_irqsave(&hc->lock, flags);
1551                 ret = set_hfcpci_rxtest(bch, ISDN_P_B_HDLC, (int)(long)arg);
1552                 spin_unlock_irqrestore(&hc->lock, flags);
1553                 break;
1554         case HW_TESTRX_OFF:
1555                 spin_lock_irqsave(&hc->lock, flags);
1556                 mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1557                 spin_unlock_irqrestore(&hc->lock, flags);
1558                 ret = 0;
1559                 break;
1560         case CLOSE_CHANNEL:
1561                 test_and_clear_bit(FLG_OPEN, &bch->Flags);
1562                 if (test_bit(FLG_ACTIVE, &bch->Flags))
1563                         deactivate_bchannel(bch);
1564                 ch->protocol = ISDN_P_NONE;
1565                 ch->peer = NULL;
1566                 module_put(THIS_MODULE);
1567                 ret = 0;
1568                 break;
1569         case CONTROL_CHANNEL:
1570                 ret = channel_bctrl(bch, arg);
1571                 break;
1572         default:
1573                 printk(KERN_WARNING "%s: unknown prim(%x)\n",
1574                         __func__, cmd);
1575         }
1576         return ret;
1577 }
1578
1579 /*
1580  * Layer2 -> Layer 1 Dchannel data
1581  */
1582 static int
1583 hfcpci_l2l1D(struct mISDNchannel *ch, struct sk_buff *skb)
1584 {
1585         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
1586         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
1587         struct hfc_pci          *hc = dch->hw;
1588         int                     ret = -EINVAL;
1589         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
1590         unsigned int            id;
1591         u_long                  flags;
1592
1593         switch (hh->prim) {
1594         case PH_DATA_REQ:
1595                 spin_lock_irqsave(&hc->lock, flags);
1596                 ret = dchannel_senddata(dch, skb);
1597                 if (ret > 0) { /* direct TX */
1598                         id = hh->id; /* skb can be freed */
1599                         hfcpci_fill_dfifo(dch->hw);
1600                         ret = 0;
1601                         spin_unlock_irqrestore(&hc->lock, flags);
1602                         queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1603                 } else
1604                         spin_unlock_irqrestore(&hc->lock, flags);
1605                 return ret;
1606         case PH_ACTIVATE_REQ:
1607                 spin_lock_irqsave(&hc->lock, flags);
1608                 if (hc->hw.protocol == ISDN_P_NT_S0) {
1609                         ret = 0;
1610                         if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1611                                 hc->hw.mst_m |= HFCPCI_MASTER;
1612                         Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1613                         if (test_bit(FLG_ACTIVE, &dch->Flags)) {
1614                                 spin_unlock_irqrestore(&hc->lock, flags);
1615                                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
1616                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
1617                                 break;
1618                         }
1619                         test_and_set_bit(FLG_L2_ACTIVATED, &dch->Flags);
1620                         Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1621                             HFCPCI_DO_ACTION | 1);
1622                 } else
1623                         ret = l1_event(dch->l1, hh->prim);
1624                 spin_unlock_irqrestore(&hc->lock, flags);
1625                 break;
1626         case PH_DEACTIVATE_REQ:
1627                 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1628                 spin_lock_irqsave(&hc->lock, flags);
1629                 if (hc->hw.protocol == ISDN_P_NT_S0) {
1630                         /* prepare deactivation */
1631                         Write_hfc(hc, HFCPCI_STATES, 0x40);
1632                         skb_queue_purge(&dch->squeue);
1633                         if (dch->tx_skb) {
1634                                 dev_kfree_skb(dch->tx_skb);
1635                                 dch->tx_skb = NULL;
1636                         }
1637                         dch->tx_idx = 0;
1638                         if (dch->rx_skb) {
1639                                 dev_kfree_skb(dch->rx_skb);
1640                                 dch->rx_skb = NULL;
1641                         }
1642                         test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1643                         if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1644                                 del_timer(&dch->timer);
1645 #ifdef FIXME
1646                         if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
1647                                 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
1648 #endif
1649                         hc->hw.mst_m &= ~HFCPCI_MASTER;
1650                         Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1651                         ret = 0;
1652                 } else {
1653                         ret = l1_event(dch->l1, hh->prim);
1654                 }
1655                 spin_unlock_irqrestore(&hc->lock, flags);
1656                 break;
1657         }
1658         if (!ret)
1659                 dev_kfree_skb(skb);
1660         return ret;
1661 }
1662
1663 /*
1664  * Layer2 -> Layer 1 Bchannel data
1665  */
1666 static int
1667 hfcpci_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
1668 {
1669         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
1670         struct hfc_pci          *hc = bch->hw;
1671         int                     ret = -EINVAL;
1672         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
1673         unsigned int            id;
1674         u_long                  flags;
1675
1676         switch (hh->prim) {
1677         case PH_DATA_REQ:
1678                 spin_lock_irqsave(&hc->lock, flags);
1679                 ret = bchannel_senddata(bch, skb);
1680                 if (ret > 0) { /* direct TX */
1681                         id = hh->id; /* skb can be freed */
1682                         hfcpci_fill_fifo(bch);
1683                         ret = 0;
1684                         spin_unlock_irqrestore(&hc->lock, flags);
1685                         if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1686                                 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1687                 } else
1688                         spin_unlock_irqrestore(&hc->lock, flags);
1689                 return ret;
1690         case PH_ACTIVATE_REQ:
1691                 spin_lock_irqsave(&hc->lock, flags);
1692                 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
1693                         ret = mode_hfcpci(bch, bch->nr, ch->protocol);
1694                 else
1695                         ret = 0;
1696                 spin_unlock_irqrestore(&hc->lock, flags);
1697                 if (!ret)
1698                         _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
1699                                 NULL, GFP_KERNEL);
1700                 break;
1701         case PH_DEACTIVATE_REQ:
1702                 deactivate_bchannel(bch);
1703                 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
1704                         NULL, GFP_KERNEL);
1705                 ret = 0;
1706                 break;
1707         }
1708         if (!ret)
1709                 dev_kfree_skb(skb);
1710         return ret;
1711 }
1712
1713 /*
1714  * called for card init message
1715  */
1716
1717 static void
1718 inithfcpci(struct hfc_pci *hc)
1719 {
1720         printk(KERN_DEBUG "inithfcpci: entered\n");
1721         hc->dch.timer.function = (void *) hfcpci_dbusy_timer;
1722         hc->dch.timer.data = (long) &hc->dch;
1723         init_timer(&hc->dch.timer);
1724         hc->chanlimit = 2;
1725         mode_hfcpci(&hc->bch[0], 1, -1);
1726         mode_hfcpci(&hc->bch[1], 2, -1);
1727 }
1728
1729
1730 static int
1731 init_card(struct hfc_pci *hc)
1732 {
1733         int     cnt = 3;
1734         u_long  flags;
1735
1736         printk(KERN_DEBUG "init_card: entered\n");
1737
1738
1739         spin_lock_irqsave(&hc->lock, flags);
1740         disable_hwirq(hc);
1741         spin_unlock_irqrestore(&hc->lock, flags);
1742         if (request_irq(hc->irq, hfcpci_int, IRQF_SHARED, "HFC PCI", hc)) {
1743                 printk(KERN_WARNING
1744                     "mISDN: couldn't get interrupt %d\n", hc->irq);
1745                 return -EIO;
1746         }
1747         spin_lock_irqsave(&hc->lock, flags);
1748         reset_hfcpci(hc);
1749         while (cnt) {
1750                 inithfcpci(hc);
1751                 /*
1752                  * Finally enable IRQ output
1753                  * this is only allowed, if an IRQ routine is allready
1754                  * established for this HFC, so don't do that earlier
1755                  */
1756                 enable_hwirq(hc);
1757                 spin_unlock_irqrestore(&hc->lock, flags);
1758                 /* Timeout 80ms */
1759                 current->state = TASK_UNINTERRUPTIBLE;
1760                 schedule_timeout((80*HZ)/1000);
1761                 printk(KERN_INFO "HFC PCI: IRQ %d count %d\n",
1762                         hc->irq, hc->irqcnt);
1763                 /* now switch timer interrupt off */
1764                 spin_lock_irqsave(&hc->lock, flags);
1765                 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1766                 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1767                 /* reinit mode reg */
1768                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1769                 if (!hc->irqcnt) {
1770                         printk(KERN_WARNING
1771                             "HFC PCI: IRQ(%d) getting no interrupts "
1772                             "during init %d\n", hc->irq, 4 - cnt);
1773                         if (cnt == 1) {
1774                                 spin_unlock_irqrestore(&hc->lock, flags);
1775                                 return -EIO;
1776                         } else {
1777                                 reset_hfcpci(hc);
1778                                 cnt--;
1779                         }
1780                 } else {
1781                         spin_unlock_irqrestore(&hc->lock, flags);
1782                         hc->initdone = 1;
1783                         return 0;
1784                 }
1785         }
1786         disable_hwirq(hc);
1787         spin_unlock_irqrestore(&hc->lock, flags);
1788         free_irq(hc->irq, hc);
1789         return -EIO;
1790 }
1791
1792 static int
1793 channel_ctrl(struct hfc_pci *hc, struct mISDN_ctrl_req *cq)
1794 {
1795         int     ret = 0;
1796         u_char  slot;
1797
1798         switch (cq->op) {
1799         case MISDN_CTRL_GETOP:
1800                 cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_CONNECT |
1801                     MISDN_CTRL_DISCONNECT;
1802                 break;
1803         case MISDN_CTRL_LOOP:
1804                 /* channel 0 disabled loop */
1805                 if (cq->channel < 0 || cq->channel > 2) {
1806                         ret = -EINVAL;
1807                         break;
1808                 }
1809                 if (cq->channel & 1) {
1810                         if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1811                                 slot = 0xC0;
1812                         else
1813                                 slot = 0x80;
1814                         printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1815                             __func__, slot);
1816                         Write_hfc(hc, HFCPCI_B1_SSL, slot);
1817                         Write_hfc(hc, HFCPCI_B1_RSL, slot);
1818                         hc->hw.conn = (hc->hw.conn & ~7) | 6;
1819                         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1820                 }
1821                 if (cq->channel & 2) {
1822                         if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1823                                 slot = 0xC1;
1824                         else
1825                                 slot = 0x81;
1826                         printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1827                             __func__, slot);
1828                         Write_hfc(hc, HFCPCI_B2_SSL, slot);
1829                         Write_hfc(hc, HFCPCI_B2_RSL, slot);
1830                         hc->hw.conn = (hc->hw.conn & ~0x38) | 0x30;
1831                         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1832                 }
1833                 if (cq->channel & 3)
1834                         hc->hw.trm |= 0x80;     /* enable IOM-loop */
1835                 else {
1836                         hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1837                         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1838                         hc->hw.trm &= 0x7f;     /* disable IOM-loop */
1839                 }
1840                 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1841                 break;
1842         case MISDN_CTRL_CONNECT:
1843                 if (cq->channel == cq->p1) {
1844                         ret = -EINVAL;
1845                         break;
1846                 }
1847                 if (cq->channel < 1 || cq->channel > 2 ||
1848                     cq->p1 < 1 || cq->p1 > 2) {
1849                         ret = -EINVAL;
1850                         break;
1851                 }
1852                 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1853                         slot = 0xC0;
1854                 else
1855                         slot = 0x80;
1856                 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1857                     __func__, slot);
1858                 Write_hfc(hc, HFCPCI_B1_SSL, slot);
1859                 Write_hfc(hc, HFCPCI_B2_RSL, slot);
1860                 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1861                         slot = 0xC1;
1862                 else
1863                         slot = 0x81;
1864                 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1865                     __func__, slot);
1866                 Write_hfc(hc, HFCPCI_B2_SSL, slot);
1867                 Write_hfc(hc, HFCPCI_B1_RSL, slot);
1868                 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x36;
1869                 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1870                 hc->hw.trm |= 0x80;
1871                 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1872                 break;
1873         case MISDN_CTRL_DISCONNECT:
1874                 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1875                 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1876                 hc->hw.trm &= 0x7f;     /* disable IOM-loop */
1877                 break;
1878         default:
1879                 printk(KERN_WARNING "%s: unknown Op %x\n",
1880                     __func__, cq->op);
1881                 ret = -EINVAL;
1882                 break;
1883         }
1884         return ret;
1885 }
1886
1887 static int
1888 open_dchannel(struct hfc_pci *hc, struct mISDNchannel *ch,
1889     struct channel_req *rq)
1890 {
1891         int err = 0;
1892
1893         if (debug & DEBUG_HW_OPEN)
1894                 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
1895                     hc->dch.dev.id, __builtin_return_address(0));
1896         if (rq->protocol == ISDN_P_NONE)
1897                 return -EINVAL;
1898         if (!hc->initdone) {
1899                 if (rq->protocol == ISDN_P_TE_S0) {
1900                         err = create_l1(&hc->dch, hfc_l1callback);
1901                         if (err)
1902                                 return err;
1903                 }
1904                 hc->hw.protocol = rq->protocol;
1905                 ch->protocol = rq->protocol;
1906                 err = init_card(hc);
1907                 if (err)
1908                         return err;
1909         } else {
1910                 if (rq->protocol != ch->protocol) {
1911                         if (hc->hw.protocol == ISDN_P_TE_S0)
1912                                 l1_event(hc->dch.l1, CLOSE_CHANNEL);
1913                         hc->hw.protocol = rq->protocol;
1914                         ch->protocol = rq->protocol;
1915                         hfcpci_setmode(hc);
1916                 }
1917         }
1918
1919         if (((ch->protocol == ISDN_P_NT_S0) && (hc->dch.state == 3)) ||
1920             ((ch->protocol == ISDN_P_TE_S0) && (hc->dch.state == 7))) {
1921                 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY,
1922                     0, NULL, GFP_KERNEL);
1923         }
1924         rq->ch = ch;
1925         if (!try_module_get(THIS_MODULE))
1926                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1927         return 0;
1928 }
1929
1930 static int
1931 open_bchannel(struct hfc_pci *hc, struct channel_req *rq)
1932 {
1933         struct bchannel         *bch;
1934
1935         if (rq->adr.channel > 2)
1936                 return -EINVAL;
1937         if (rq->protocol == ISDN_P_NONE)
1938                 return -EINVAL;
1939         bch = &hc->bch[rq->adr.channel - 1];
1940         if (test_and_set_bit(FLG_OPEN, &bch->Flags))
1941                 return -EBUSY; /* b-channel can be only open once */
1942         test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
1943         bch->ch.protocol = rq->protocol;
1944         rq->ch = &bch->ch; /* TODO: E-channel */
1945         if (!try_module_get(THIS_MODULE))
1946                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1947         return 0;
1948 }
1949
1950 /*
1951  * device control function
1952  */
1953 static int
1954 hfc_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1955 {
1956         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
1957         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
1958         struct hfc_pci          *hc = dch->hw;
1959         struct channel_req      *rq;
1960         int                     err = 0;
1961
1962         if (dch->debug & DEBUG_HW)
1963                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
1964                     __func__, cmd, arg);
1965         switch (cmd) {
1966         case OPEN_CHANNEL:
1967                 rq = arg;
1968                 if (rq->adr.channel == 0)
1969                         err = open_dchannel(hc, ch, rq);
1970                 else
1971                         err = open_bchannel(hc, rq);
1972                 break;
1973         case CLOSE_CHANNEL:
1974                 if (debug & DEBUG_HW_OPEN)
1975                         printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
1976                             __func__, hc->dch.dev.id,
1977                             __builtin_return_address(0));
1978                 module_put(THIS_MODULE);
1979                 break;
1980         case CONTROL_CHANNEL:
1981                 err = channel_ctrl(hc, arg);
1982                 break;
1983         default:
1984                 if (dch->debug & DEBUG_HW)
1985                         printk(KERN_DEBUG "%s: unknown command %x\n",
1986                             __func__, cmd);
1987                 return -EINVAL;
1988         }
1989         return err;
1990 }
1991
1992 static int
1993 setup_hw(struct hfc_pci *hc)
1994 {
1995         void    *buffer;
1996
1997         printk(KERN_INFO "mISDN: HFC-PCI driver %s\n", hfcpci_revision);
1998         hc->hw.cirm = 0;
1999         hc->dch.state = 0;
2000         pci_set_master(hc->pdev);
2001         if (!hc->irq) {
2002                 printk(KERN_WARNING "HFC-PCI: No IRQ for PCI card found\n");
2003                 return 1;
2004         }
2005         hc->hw.pci_io = (char __iomem *)(unsigned long)hc->pdev->resource[1].start;
2006
2007         if (!hc->hw.pci_io) {
2008                 printk(KERN_WARNING "HFC-PCI: No IO-Mem for PCI card found\n");
2009                 return 1;
2010         }
2011         /* Allocate memory for FIFOS */
2012         /* the memory needs to be on a 32k boundary within the first 4G */
2013         pci_set_dma_mask(hc->pdev, 0xFFFF8000);
2014         buffer = pci_alloc_consistent(hc->pdev, 0x8000, &hc->hw.dmahandle);
2015         /* We silently assume the address is okay if nonzero */
2016         if (!buffer) {
2017                 printk(KERN_WARNING
2018                     "HFC-PCI: Error allocating memory for FIFO!\n");
2019                 return 1;
2020         }
2021         hc->hw.fifos = buffer;
2022         pci_write_config_dword(hc->pdev, 0x80, hc->hw.dmahandle);
2023         hc->hw.pci_io = ioremap((ulong) hc->hw.pci_io, 256);
2024         printk(KERN_INFO
2025                 "HFC-PCI: defined at mem %#lx fifo %#lx(%#lx) IRQ %d HZ %d\n",
2026                 (u_long) hc->hw.pci_io, (u_long) hc->hw.fifos,
2027                 (u_long) hc->hw.dmahandle, hc->irq, HZ);
2028         /* enable memory mapped ports, disable busmaster */
2029         pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
2030         hc->hw.int_m2 = 0;
2031         disable_hwirq(hc);
2032         hc->hw.int_m1 = 0;
2033         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
2034         /* At this point the needed PCI config is done */
2035         /* fifos are still not enabled */
2036         hc->hw.timer.function = (void *) hfcpci_Timer;
2037         hc->hw.timer.data = (long) hc;
2038         init_timer(&hc->hw.timer);
2039         /* default PCM master */
2040         test_and_set_bit(HFC_CFG_MASTER, &hc->cfg);
2041         return 0;
2042 }
2043
2044 static void
2045 release_card(struct hfc_pci *hc) {
2046         u_long  flags;
2047
2048         spin_lock_irqsave(&hc->lock, flags);
2049         hc->hw.int_m2 = 0; /* interrupt output off ! */
2050         disable_hwirq(hc);
2051         mode_hfcpci(&hc->bch[0], 1, ISDN_P_NONE);
2052         mode_hfcpci(&hc->bch[1], 2, ISDN_P_NONE);
2053         if (hc->dch.timer.function != NULL) {
2054                 del_timer(&hc->dch.timer);
2055                 hc->dch.timer.function = NULL;
2056         }
2057         spin_unlock_irqrestore(&hc->lock, flags);
2058         if (hc->hw.protocol == ISDN_P_TE_S0)
2059                 l1_event(hc->dch.l1, CLOSE_CHANNEL);
2060         if (hc->initdone)
2061                 free_irq(hc->irq, hc);
2062         release_io_hfcpci(hc); /* must release after free_irq! */
2063         mISDN_unregister_device(&hc->dch.dev);
2064         mISDN_freebchannel(&hc->bch[1]);
2065         mISDN_freebchannel(&hc->bch[0]);
2066         mISDN_freedchannel(&hc->dch);
2067         list_del(&hc->list);
2068         pci_set_drvdata(hc->pdev, NULL);
2069         kfree(hc);
2070 }
2071
2072 static int
2073 setup_card(struct hfc_pci *card)
2074 {
2075         int             err = -EINVAL;
2076         u_int           i;
2077         u_long          flags;
2078         char            name[MISDN_MAX_IDLEN];
2079
2080         if (HFC_cnt >= MAX_CARDS)
2081                 return -EINVAL; /* maybe better value */
2082
2083         card->dch.debug = debug;
2084         spin_lock_init(&card->lock);
2085         mISDN_initdchannel(&card->dch, MAX_DFRAME_LEN_L1, ph_state);
2086         card->dch.hw = card;
2087         card->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
2088         card->dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
2089             (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
2090         card->dch.dev.D.send = hfcpci_l2l1D;
2091         card->dch.dev.D.ctrl = hfc_dctrl;
2092         card->dch.dev.nrbchan = 2;
2093         for (i = 0; i < 2; i++) {
2094                 card->bch[i].nr = i + 1;
2095                 set_channelmap(i + 1, card->dch.dev.channelmap);
2096                 card->bch[i].debug = debug;
2097                 mISDN_initbchannel(&card->bch[i], MAX_DATA_MEM);
2098                 card->bch[i].hw = card;
2099                 card->bch[i].ch.send = hfcpci_l2l1B;
2100                 card->bch[i].ch.ctrl = hfc_bctrl;
2101                 card->bch[i].ch.nr = i + 1;
2102                 list_add(&card->bch[i].ch.list, &card->dch.dev.bchannels);
2103         }
2104         err = setup_hw(card);
2105         if (err)
2106                 goto error;
2107         snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-pci.%d", HFC_cnt + 1);
2108         err = mISDN_register_device(&card->dch.dev, name);
2109         if (err)
2110                 goto error;
2111         HFC_cnt++;
2112         write_lock_irqsave(&HFClock, flags);
2113         list_add_tail(&card->list, &HFClist);
2114         write_unlock_irqrestore(&HFClock, flags);
2115         printk(KERN_INFO "HFC %d cards installed\n", HFC_cnt);
2116         return 0;
2117 error:
2118         mISDN_freebchannel(&card->bch[1]);
2119         mISDN_freebchannel(&card->bch[0]);
2120         mISDN_freedchannel(&card->dch);
2121         kfree(card);
2122         return err;
2123 }
2124
2125 /* private data in the PCI devices list */
2126 struct _hfc_map {
2127         u_int   subtype;
2128         u_int   flag;
2129         char    *name;
2130 };
2131
2132 static const struct _hfc_map hfc_map[] =
2133 {
2134         {HFC_CCD_2BD0, 0, "CCD/Billion/Asuscom 2BD0"},
2135         {HFC_CCD_B000, 0, "Billion B000"},
2136         {HFC_CCD_B006, 0, "Billion B006"},
2137         {HFC_CCD_B007, 0, "Billion B007"},
2138         {HFC_CCD_B008, 0, "Billion B008"},
2139         {HFC_CCD_B009, 0, "Billion B009"},
2140         {HFC_CCD_B00A, 0, "Billion B00A"},
2141         {HFC_CCD_B00B, 0, "Billion B00B"},
2142         {HFC_CCD_B00C, 0, "Billion B00C"},
2143         {HFC_CCD_B100, 0, "Seyeon B100"},
2144         {HFC_CCD_B700, 0, "Primux II S0 B700"},
2145         {HFC_CCD_B701, 0, "Primux II S0 NT B701"},
2146         {HFC_ABOCOM_2BD1, 0, "Abocom/Magitek 2BD1"},
2147         {HFC_ASUS_0675, 0, "Asuscom/Askey 675"},
2148         {HFC_BERKOM_TCONCEPT, 0, "German telekom T-Concept"},
2149         {HFC_BERKOM_A1T, 0, "German telekom A1T"},
2150         {HFC_ANIGMA_MC145575, 0, "Motorola MC145575"},
2151         {HFC_ZOLTRIX_2BD0, 0, "Zoltrix 2BD0"},
2152         {HFC_DIGI_DF_M_IOM2_E, 0,
2153             "Digi International DataFire Micro V IOM2 (Europe)"},
2154         {HFC_DIGI_DF_M_E, 0,
2155             "Digi International DataFire Micro V (Europe)"},
2156         {HFC_DIGI_DF_M_IOM2_A, 0,
2157             "Digi International DataFire Micro V IOM2 (North America)"},
2158         {HFC_DIGI_DF_M_A, 0,
2159             "Digi International DataFire Micro V (North America)"},
2160         {HFC_SITECOM_DC105V2, 0, "Sitecom Connectivity DC-105 ISDN TA"},
2161         {},
2162 };
2163
2164 static struct pci_device_id hfc_ids[] =
2165 {
2166         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_2BD0,
2167                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[0]},
2168         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B000,
2169                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[1]},
2170         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B006,
2171                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[2]},
2172         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B007,
2173                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[3]},
2174         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B008,
2175                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[4]},
2176         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B009,
2177                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[5]},
2178         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00A,
2179                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[6]},
2180         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00B,
2181                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[7]},
2182         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00C,
2183                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[8]},
2184         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B100,
2185                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[9]},
2186         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B700,
2187                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[10]},
2188         {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B701,
2189                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[11]},
2190         {PCI_VENDOR_ID_ABOCOM, PCI_DEVICE_ID_ABOCOM_2BD1,
2191                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[12]},
2192         {PCI_VENDOR_ID_ASUSTEK, PCI_DEVICE_ID_ASUSTEK_0675,
2193                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[13]},
2194         {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_T_CONCEPT,
2195                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[14]},
2196         {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_A1T,
2197                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[15]},
2198         {PCI_VENDOR_ID_ANIGMA, PCI_DEVICE_ID_ANIGMA_MC145575,
2199                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[16]},
2200         {PCI_VENDOR_ID_ZOLTRIX, PCI_DEVICE_ID_ZOLTRIX_2BD0,
2201                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[17]},
2202         {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E,
2203                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[18]},
2204         {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_E,
2205                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[19]},
2206         {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A,
2207                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[20]},
2208         {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_A,
2209                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[21]},
2210         {PCI_VENDOR_ID_SITECOM, PCI_DEVICE_ID_SITECOM_DC105V2,
2211                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[22]},
2212         {},
2213 };
2214
2215 static int __devinit
2216 hfc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2217 {
2218         int             err = -ENOMEM;
2219         struct hfc_pci  *card;
2220         struct _hfc_map *m = (struct _hfc_map *)ent->driver_data;
2221
2222         card = kzalloc(sizeof(struct hfc_pci), GFP_ATOMIC);
2223         if (!card) {
2224                 printk(KERN_ERR "No kmem for HFC card\n");
2225                 return err;
2226         }
2227         card->pdev = pdev;
2228         card->subtype = m->subtype;
2229         err = pci_enable_device(pdev);
2230         if (err) {
2231                 kfree(card);
2232                 return err;
2233         }
2234
2235         printk(KERN_INFO "mISDN_hfcpci: found adapter %s at %s\n",
2236                m->name, pci_name(pdev));
2237
2238         card->irq = pdev->irq;
2239         pci_set_drvdata(pdev, card);
2240         err = setup_card(card);
2241         if (err)
2242                 pci_set_drvdata(pdev, NULL);
2243         return err;
2244 }
2245
2246 static void __devexit
2247 hfc_remove_pci(struct pci_dev *pdev)
2248 {
2249         struct hfc_pci  *card = pci_get_drvdata(pdev);
2250         u_long          flags;
2251
2252         if (card) {
2253                 write_lock_irqsave(&HFClock, flags);
2254                 release_card(card);
2255                 write_unlock_irqrestore(&HFClock, flags);
2256         } else
2257                 if (debug)
2258                         printk(KERN_WARNING "%s: drvdata allready removed\n",
2259                             __func__);
2260 }
2261
2262
2263 static struct pci_driver hfc_driver = {
2264         .name = "hfcpci",
2265         .probe = hfc_probe,
2266         .remove = __devexit_p(hfc_remove_pci),
2267         .id_table = hfc_ids,
2268 };
2269
2270 static int __init
2271 HFC_init(void)
2272 {
2273         int             err;
2274
2275         err = pci_register_driver(&hfc_driver);
2276         return err;
2277 }
2278
2279 static void __exit
2280 HFC_cleanup(void)
2281 {
2282         struct hfc_pci  *card, *next;
2283
2284         list_for_each_entry_safe(card, next, &HFClist, list) {
2285                 release_card(card);
2286         }
2287         pci_unregister_driver(&hfc_driver);
2288 }
2289
2290 module_init(HFC_init);
2291 module_exit(HFC_cleanup);