drivers/i2c/busses/i2c-omap.c

   1 /*
   2  * TI OMAP I2C master mode driver
   3  *
   4  * Copyright (C) 2003 MontaVista Software, Inc.
   5  * Copyright (C) 2005 Nokia Corporation
   6  * Copyright (C) 2004 - 2007 Texas Instruments.
   7  *
   8  * Originally written by MontaVista Software, Inc.
   9  * Additional contributions by:
  10  *      Tony Lindgren <tony@atomide.com>
  11  *      Imre Deak <imre.deak@nokia.com>
  12  *      Juha Yrjölä <juha.yrjola@solidboot.com>
  13  *      Syed Khasim <x0khasim@ti.com>
  14  *      Nishant Menon <nm@ti.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 2 of the License, or
  19  * (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  29  */
  30
  31 #include <linux/module.h>
  32 #include <linux/delay.h>
  33 #include <linux/i2c.h>
  34 #include <linux/err.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/completion.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/clk.h>
  39 #include <linux/io.h>
  40
  41 /* I2C controller revisions */
  42 #define OMAP_I2C_REV_2                  0x20
  43
  44 /* I2C controller revisions present on specific hardware */
  45 #define OMAP_I2C_REV_ON_2430            0x36
  46 #define OMAP_I2C_REV_ON_3430            0x3C
  47
  48 /* timeout waiting for the controller to respond */
  49 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
  50
  51 #define OMAP_I2C_REV_REG                0x00
  52 #define OMAP_I2C_IE_REG                 0x04
  53 #define OMAP_I2C_STAT_REG               0x08
  54 #define OMAP_I2C_IV_REG                 0x0c
  55 #define OMAP_I2C_SYSS_REG               0x10
  56 #define OMAP_I2C_BUF_REG                0x14
  57 #define OMAP_I2C_CNT_REG                0x18
  58 #define OMAP_I2C_DATA_REG               0x1c
  59 #define OMAP_I2C_SYSC_REG               0x20
  60 #define OMAP_I2C_CON_REG                0x24
  61 #define OMAP_I2C_OA_REG                 0x28
  62 #define OMAP_I2C_SA_REG                 0x2c
  63 #define OMAP_I2C_PSC_REG                0x30
  64 #define OMAP_I2C_SCLL_REG               0x34
  65 #define OMAP_I2C_SCLH_REG               0x38
  66 #define OMAP_I2C_SYSTEST_REG            0x3c
  67 #define OMAP_I2C_BUFSTAT_REG            0x40
  68
  69 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
  70 #define OMAP_I2C_IE_XDR         (1 << 14)       /* TX Buffer drain int enable */
  71 #define OMAP_I2C_IE_RDR         (1 << 13)       /* RX Buffer drain int enable */
  72 #define OMAP_I2C_IE_XRDY        (1 << 4)        /* TX data ready int enable */
  73 #define OMAP_I2C_IE_RRDY        (1 << 3)        /* RX data ready int enable */
  74 #define OMAP_I2C_IE_ARDY        (1 << 2)        /* Access ready int enable */
  75 #define OMAP_I2C_IE_NACK        (1 << 1)        /* No ack interrupt enable */
  76 #define OMAP_I2C_IE_AL          (1 << 0)        /* Arbitration lost int ena */
  77
  78 /* I2C Status Register (OMAP_I2C_STAT): */
  79 #define OMAP_I2C_STAT_XDR       (1 << 14)       /* TX Buffer draining */
  80 #define OMAP_I2C_STAT_RDR       (1 << 13)       /* RX Buffer draining */
  81 #define OMAP_I2C_STAT_BB        (1 << 12)       /* Bus busy */
  82 #define OMAP_I2C_STAT_ROVR      (1 << 11)       /* Receive overrun */
  83 #define OMAP_I2C_STAT_XUDF      (1 << 10)       /* Transmit underflow */
  84 #define OMAP_I2C_STAT_AAS       (1 << 9)        /* Address as slave */
  85 #define OMAP_I2C_STAT_AD0       (1 << 8)        /* Address zero */
  86 #define OMAP_I2C_STAT_XRDY      (1 << 4)        /* Transmit data ready */
  87 #define OMAP_I2C_STAT_RRDY      (1 << 3)        /* Receive data ready */
  88 #define OMAP_I2C_STAT_ARDY      (1 << 2)        /* Register access ready */
  89 #define OMAP_I2C_STAT_NACK      (1 << 1)        /* No ack interrupt enable */
  90 #define OMAP_I2C_STAT_AL        (1 << 0)        /* Arbitration lost int ena */
  91
  92 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
  93 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)       /* RX DMA channel enable */
  94 #define OMAP_I2C_BUF_RXFIF_CLR  (1 << 14)       /* RX FIFO Clear */
  95 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)        /* TX DMA channel enable */
  96 #define OMAP_I2C_BUF_TXFIF_CLR  (1 << 6)        /* TX FIFO Clear */
  97
  98 /* I2C Configuration Register (OMAP_I2C_CON): */
  99 #define OMAP_I2C_CON_EN         (1 << 15)       /* I2C module enable */
 100 #define OMAP_I2C_CON_BE         (1 << 14)       /* Big endian mode */
 101 #define OMAP_I2C_CON_OPMODE_HS  (1 << 12)       /* High Speed support */
 102 #define OMAP_I2C_CON_STB        (1 << 11)       /* Start byte mode (master) */
 103 #define OMAP_I2C_CON_MST        (1 << 10)       /* Master/slave mode */
 104 #define OMAP_I2C_CON_TRX        (1 << 9)        /* TX/RX mode (master only) */
 105 #define OMAP_I2C_CON_XA         (1 << 8)        /* Expand address */
 106 #define OMAP_I2C_CON_RM         (1 << 2)        /* Repeat mode (master only) */
 107 #define OMAP_I2C_CON_STP        (1 << 1)        /* Stop cond (master only) */
 108 #define OMAP_I2C_CON_STT        (1 << 0)        /* Start condition (master) */
 109
 110 /* I2C SCL time value when Master */
 111 #define OMAP_I2C_SCLL_HSSCLL    8
 112 #define OMAP_I2C_SCLH_HSSCLH    8
 113
 114 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
 115 #ifdef DEBUG
 116 #define OMAP_I2C_SYSTEST_ST_EN          (1 << 15)       /* System test enable */
 117 #define OMAP_I2C_SYSTEST_FREE           (1 << 14)       /* Free running mode */
 118 #define OMAP_I2C_SYSTEST_TMODE_MASK     (3 << 12)       /* Test mode select */
 119 #define OMAP_I2C_SYSTEST_TMODE_SHIFT    (12)            /* Test mode select */
 120 #define OMAP_I2C_SYSTEST_SCL_I          (1 << 3)        /* SCL line sense in */
 121 #define OMAP_I2C_SYSTEST_SCL_O          (1 << 2)        /* SCL line drive out */
 122 #define OMAP_I2C_SYSTEST_SDA_I          (1 << 1)        /* SDA line sense in */
 123 #define OMAP_I2C_SYSTEST_SDA_O          (1 << 0)        /* SDA line drive out */
 124 #endif
 125
 126 /* OCP_SYSSTATUS bit definitions */
 127 #define SYSS_RESETDONE_MASK             (1 << 0)
 128
 129 /* OCP_SYSCONFIG bit definitions */
 130 #define SYSC_CLOCKACTIVITY_MASK         (0x3 << 8)
 131 #define SYSC_SIDLEMODE_MASK             (0x3 << 3)
 132 #define SYSC_ENAWAKEUP_MASK             (1 << 2)
 133 #define SYSC_SOFTRESET_MASK             (1 << 1)
 134 #define SYSC_AUTOIDLE_MASK              (1 << 0)
 135
 136 #define SYSC_IDLEMODE_SMART             0x2
 137 #define SYSC_CLOCKACTIVITY_FCLK         0x2
 138
 139
 140 struct omap_i2c_dev {
 141         struct device           *dev;
 142         void __iomem            *base;          /* virtual */
 143         int                     irq;
 144         struct clk              *iclk;          /* Interface clock */
 145         struct clk              *fclk;          /* Functional clock */
 146         struct completion       cmd_complete;
 147         struct resource         *ioarea;
 148         u32                     speed;          /* Speed of bus in Khz */
 149         u16                     cmd_err;
 150         u8                      *buf;
 151         size_t                  buf_len;
 152         struct i2c_adapter      adapter;
 153         u8                      fifo_size;      /* use as flag and value
 154                                                  * fifo_size==0 implies no fifo
 155                                                  * if set, should be trsh+1
 156                                                  */
 157         u8                      rev;
 158         unsigned                b_hw:1;         /* bad h/w fixes */
 159         unsigned                idle:1;
 160         u16                     iestate;        /* Saved interrupt register */
 161 };
 162
 163 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
 164                                       int reg, u16 val)
 165 {
 166         __raw_writew(val, i2c_dev->base + reg);
 167 }
 168
 169 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
 170 {
 171         return __raw_readw(i2c_dev->base + reg);
 172 }
 173
 174 static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
 175 {
 176         if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
 177                 dev->iclk = clk_get(dev->dev, "i2c_ick");
 178                 if (IS_ERR(dev->iclk)) {
 179                         dev->iclk = NULL;
 180                         return -ENODEV;
 181                 }
 182         }
 183
 184         dev->fclk = clk_get(dev->dev, "i2c_fck");
 185         if (IS_ERR(dev->fclk)) {
 186                 if (dev->iclk != NULL) {
 187                         clk_put(dev->iclk);
 188                         dev->iclk = NULL;
 189                 }
 190                 dev->fclk = NULL;
 191                 return -ENODEV;
 192         }
 193
 194         return 0;
 195 }
 196
 197 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
 198 {
 199         clk_put(dev->fclk);
 200         dev->fclk = NULL;
 201         if (dev->iclk != NULL) {
 202                 clk_put(dev->iclk);
 203                 dev->iclk = NULL;
 204         }
 205 }
 206
 207 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
 208 {
 209         WARN_ON(!dev->idle);
 210
 211         if (dev->iclk != NULL)
 212                 clk_enable(dev->iclk);
 213         clk_enable(dev->fclk);
 214         dev->idle = 0;
 215         if (dev->iestate)
 216                 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
 217 }
 218
 219 static void omap_i2c_idle(struct omap_i2c_dev *dev)
 220 {
 221         u16 iv;
 222
 223         WARN_ON(dev->idle);
 224
 225         dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 226         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
 227         if (dev->rev < OMAP_I2C_REV_2) {
 228                 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
 229         } else {
 230                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
 231
 232                 /* Flush posted write before the dev->idle store occurs */
 233                 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 234         }
 235         dev->idle = 1;
 236         clk_disable(dev->fclk);
 237         if (dev->iclk != NULL)
 238                 clk_disable(dev->iclk);
 239 }
 240
 241 static int omap_i2c_init(struct omap_i2c_dev *dev)
 242 {
 243         u16 psc = 0, scll = 0, sclh = 0;
 244         u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
 245         unsigned long fclk_rate = 12000000;
 246         unsigned long timeout;
 247         unsigned long internal_clk = 0;
 248
 249         if (dev->rev >= OMAP_I2C_REV_2) {
 250                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
 251                 /* For some reason we need to set the EN bit before the
 252                  * reset done bit gets set. */
 253                 timeout = jiffies + OMAP_I2C_TIMEOUT;
 254                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 255                 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
 256                          SYSS_RESETDONE_MASK)) {
 257                         if (time_after(jiffies, timeout)) {
 258                                 dev_warn(dev->dev, "timeout waiting "
 259                                                 "for controller reset\n");
 260                                 return -ETIMEDOUT;
 261                         }
 262                         msleep(1);
 263                 }
 264
 265                 /* SYSC register is cleared by the reset; rewrite it */
 266                 if (dev->rev == OMAP_I2C_REV_ON_2430) {
 267
 268                         omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
 269                                            SYSC_AUTOIDLE_MASK);
 270
 271                 } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
 272                         u32 v;
 273
 274                         v = SYSC_AUTOIDLE_MASK;
 275                         v |= SYSC_ENAWAKEUP_MASK;
 276                         v |= (SYSC_IDLEMODE_SMART <<
 277                               __ffs(SYSC_SIDLEMODE_MASK));
 278                         v |= (SYSC_CLOCKACTIVITY_FCLK <<
 279                               __ffs(SYSC_CLOCKACTIVITY_MASK));
 280
 281                         omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, v);
 282
 283                 }
 284         }
 285         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 286
 287         if (cpu_class_is_omap1()) {
 288                 struct clk *armxor_ck;
 289
 290                 armxor_ck = clk_get(NULL, "armxor_ck");
 291                 if (IS_ERR(armxor_ck))
 292                         dev_warn(dev->dev, "Could not get armxor_ck\n");
 293                 else {
 294                         fclk_rate = clk_get_rate(armxor_ck);
 295                         clk_put(armxor_ck);
 296                 }
 297                 /* TRM for 5912 says the I2C clock must be prescaled to be
 298                  * between 7 - 12 MHz. The XOR input clock is typically
 299                  * 12, 13 or 19.2 MHz. So we should have code that produces:
 300                  *
 301                  * XOR MHz      Divider         Prescaler
 302                  * 12           1               0
 303                  * 13           2               1
 304                  * 19.2         2               1
 305                  */
 306                 if (fclk_rate > 12000000)
 307                         psc = fclk_rate / 12000000;
 308         }
 309
 310         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 311
 312                 /* HSI2C controller internal clk rate should be 19.2 Mhz */
 313                 internal_clk = 19200;
 314                 fclk_rate = clk_get_rate(dev->fclk) / 1000;
 315
 316                 /* Compute prescaler divisor */
 317                 psc = fclk_rate / internal_clk;
 318                 psc = psc - 1;
 319
 320                 /* If configured for High Speed */
 321                 if (dev->speed > 400) {
 322                         /* For first phase of HS mode */
 323                         fsscll = internal_clk / (400 * 2) - 6;
 324                         fssclh = internal_clk / (400 * 2) - 6;
 325
 326                         /* For second phase of HS mode */
 327                         hsscll = fclk_rate / (dev->speed * 2) - 6;
 328                         hssclh = fclk_rate / (dev->speed * 2) - 6;
 329                 } else {
 330                         /* To handle F/S modes */
 331                         fsscll = internal_clk / (dev->speed * 2) - 6;
 332                         fssclh = internal_clk / (dev->speed * 2) - 6;
 333                 }
 334                 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
 335                 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
 336         } else {
 337                 /* Program desired operating rate */
 338                 fclk_rate /= (psc + 1) * 1000;
 339                 if (psc > 2)
 340                         psc = 2;
 341                 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
 342                 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
 343         }
 344
 345         /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
 346         omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
 347
 348         /* SCL low and high time values */
 349         omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
 350         omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
 351
 352         if (dev->fifo_size)
 353                 /* Note: setup required fifo size - 1 */
 354                 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
 355                                         (dev->fifo_size - 1) << 8 | /* RTRSH */
 356                                         OMAP_I2C_BUF_RXFIF_CLR |
 357                                         (dev->fifo_size - 1) | /* XTRSH */
 358                                         OMAP_I2C_BUF_TXFIF_CLR);
 359
 360         /* Take the I2C module out of reset: */
 361         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 362
 363         /* Enable interrupts */
 364         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
 365                         (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
 366                         OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
 367                         OMAP_I2C_IE_AL)  | ((dev->fifo_size) ?
 368                                 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
 369         return 0;
 370 }
 371
 372 /*
 373  * Waiting on Bus Busy
 374  */
 375 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
 376 {
 377         unsigned long timeout;
 378
 379         timeout = jiffies + OMAP_I2C_TIMEOUT;
 380         while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
 381                 if (time_after(jiffies, timeout)) {
 382                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 383                         return -ETIMEDOUT;
 384                 }
 385                 msleep(1);
 386         }
 387
 388         return 0;
 389 }
 390
 391 /*
 392  * Low level master read/write transaction.
 393  */
 394 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 395                              struct i2c_msg *msg, int stop)
 396 {
 397         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 398         int r;
 399         u16 w;
 400
 401         dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 402                 msg->addr, msg->len, msg->flags, stop);
 403
 404         if (msg->len == 0)
 405                 return -EINVAL;
 406
 407         omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
 408
 409         /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
 410         dev->buf = msg->buf;
 411         dev->buf_len = msg->len;
 412
 413         omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
 414
 415         /* Clear the FIFO Buffers */
 416         w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
 417         w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
 418         omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
 419
 420         init_completion(&dev->cmd_complete);
 421         dev->cmd_err = 0;
 422
 423         w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 424
 425         /* High speed configuration */
 426         if (dev->speed > 400)
 427                 w |= OMAP_I2C_CON_OPMODE_HS;
 428
 429         if (msg->flags & I2C_M_TEN)
 430                 w |= OMAP_I2C_CON_XA;
 431         if (!(msg->flags & I2C_M_RD))
 432                 w |= OMAP_I2C_CON_TRX;
 433
 434         if (!dev->b_hw && stop)
 435                 w |= OMAP_I2C_CON_STP;
 436
 437         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 438
 439         /*
 440          * Don't write stt and stp together on some hardware.
 441          */
 442         if (dev->b_hw && stop) {
 443                 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
 444                 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 445                 while (con & OMAP_I2C_CON_STT) {
 446                         con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 447
 448                         /* Let the user know if i2c is in a bad state */
 449                         if (time_after(jiffies, delay)) {
 450                                 dev_err(dev->dev, "controller timed out "
 451                                 "waiting for start condition to finish\n");
 452                                 return -ETIMEDOUT;
 453                         }
 454                         cpu_relax();
 455                 }
 456
 457                 w |= OMAP_I2C_CON_STP;
 458                 w &= ~OMAP_I2C_CON_STT;
 459                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 460         }
 461
 462         /*
 463          * REVISIT: We should abort the transfer on signals, but the bus goes
 464          * into arbitration and we're currently unable to recover from it.
 465          */
 466         r = wait_for_completion_timeout(&dev->cmd_complete,
 467                                         OMAP_I2C_TIMEOUT);
 468         dev->buf_len = 0;
 469         if (r < 0)
 470                 return r;
 471         if (r == 0) {
 472                 dev_err(dev->dev, "controller timed out\n");
 473                 omap_i2c_init(dev);
 474                 return -ETIMEDOUT;
 475         }
 476
 477         if (likely(!dev->cmd_err))
 478                 return 0;
 479
 480         /* We have an error */
 481         if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
 482                             OMAP_I2C_STAT_XUDF)) {
 483                 omap_i2c_init(dev);
 484                 return -EIO;
 485         }
 486
 487         if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
 488                 if (msg->flags & I2C_M_IGNORE_NAK)
 489                         return 0;
 490                 if (stop) {
 491                         w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 492                         w |= OMAP_I2C_CON_STP;
 493                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 494                 }
 495                 return -EREMOTEIO;
 496         }
 497         return -EIO;
 498 }
 499
 500
 501 /*
 502  * Prepare controller for a transaction and call omap_i2c_xfer_msg
 503  * to do the work during IRQ processing.
 504  */
 505 static int
 506 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 507 {
 508         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 509         int i;
 510         int r;
 511
 512         omap_i2c_unidle(dev);
 513
 514         r = omap_i2c_wait_for_bb(dev);
 515         if (r < 0)
 516                 goto out;
 517
 518         for (i = 0; i < num; i++) {
 519                 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 520                 if (r != 0)
 521                         break;
 522         }
 523
 524         if (r == 0)
 525                 r = num;
 526 out:
 527         omap_i2c_idle(dev);
 528         return r;
 529 }
 530
 531 static u32
 532 omap_i2c_func(struct i2c_adapter *adap)
 533 {
 534         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 535 }
 536
 537 static inline void
 538 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
 539 {
 540         dev->cmd_err |= err;
 541         complete(&dev->cmd_complete);
 542 }
 543
 544 static inline void
 545 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
 546 {
 547         omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 548 }
 549
 550 /* rev1 devices are apparently only on some 15xx */
 551 #ifdef CONFIG_ARCH_OMAP15XX
 552
 553 static irqreturn_t
 554 omap_i2c_rev1_isr(int this_irq, void *dev_id)
 555 {
 556         struct omap_i2c_dev *dev = dev_id;
 557         u16 iv, w;
 558
 559         if (dev->idle)
 560                 return IRQ_NONE;
 561
 562         iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
 563         switch (iv) {
 564         case 0x00:      /* None */
 565                 break;
 566         case 0x01:      /* Arbitration lost */
 567                 dev_err(dev->dev, "Arbitration lost\n");
 568                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
 569                 break;
 570         case 0x02:      /* No acknowledgement */
 571                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
 572                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
 573                 break;
 574         case 0x03:      /* Register access ready */
 575                 omap_i2c_complete_cmd(dev, 0);
 576                 break;
 577         case 0x04:      /* Receive data ready */
 578                 if (dev->buf_len) {
 579                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 580                         *dev->buf++ = w;
 581                         dev->buf_len--;
 582                         if (dev->buf_len) {
 583                                 *dev->buf++ = w >> 8;
 584                                 dev->buf_len--;
 585                         }
 586                 } else
 587                         dev_err(dev->dev, "RRDY IRQ while no data requested\n");
 588                 break;
 589         case 0x05:      /* Transmit data ready */
 590                 if (dev->buf_len) {
 591                         w = *dev->buf++;
 592                         dev->buf_len--;
 593                         if (dev->buf_len) {
 594                                 w |= *dev->buf++ << 8;
 595                                 dev->buf_len--;
 596                         }
 597                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 598                 } else
 599                         dev_err(dev->dev, "XRDY IRQ while no data to send\n");
 600                 break;
 601         default:
 602                 return IRQ_NONE;
 603         }
 604
 605         return IRQ_HANDLED;
 606 }
 607 #else
 608 #define omap_i2c_rev1_isr               NULL
 609 #endif
 610
 611 static irqreturn_t
 612 omap_i2c_isr(int this_irq, void *dev_id)
 613 {
 614         struct omap_i2c_dev *dev = dev_id;
 615         u16 bits;
 616         u16 stat, w;
 617         int err, count = 0;
 618
 619         if (dev->idle)
 620                 return IRQ_NONE;
 621
 622         bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 623         while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
 624                 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 625                 if (count++ == 100) {
 626                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 627                         break;
 628                 }
 629
 630                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 631
 632                 err = 0;
 633                 if (stat & OMAP_I2C_STAT_NACK) {
 634                         err |= OMAP_I2C_STAT_NACK;
 635                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
 636                                            OMAP_I2C_CON_STP);
 637                 }
 638                 if (stat & OMAP_I2C_STAT_AL) {
 639                         dev_err(dev->dev, "Arbitration lost\n");
 640                         err |= OMAP_I2C_STAT_AL;
 641                 }
 642                 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
 643                                         OMAP_I2C_STAT_AL))
 644                         omap_i2c_complete_cmd(dev, err);
 645                 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
 646                         u8 num_bytes = 1;
 647                         if (dev->fifo_size) {
 648                                 if (stat & OMAP_I2C_STAT_RRDY)
 649                                         num_bytes = dev->fifo_size;
 650                                 else
 651                                         num_bytes = omap_i2c_read_reg(dev,
 652                                                         OMAP_I2C_BUFSTAT_REG);
 653                         }
 654                         while (num_bytes) {
 655                                 num_bytes--;
 656                                 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 657                                 if (dev->buf_len) {
 658                                         *dev->buf++ = w;
 659                                         dev->buf_len--;
 660                                         /* Data reg from 2430 is 8 bit wide */
 661                                         if (!cpu_is_omap2430() &&
 662                                                         !cpu_is_omap34xx()) {
 663                                                 if (dev->buf_len) {
 664                                                         *dev->buf++ = w >> 8;
 665                                                         dev->buf_len--;
 666                                                 }
 667                                         }
 668                                 } else {
 669                                         if (stat & OMAP_I2C_STAT_RRDY)
 670                                                 dev_err(dev->dev,
 671                                                         "RRDY IRQ while no data"
 672                                                                 " requested\n");
 673                                         if (stat & OMAP_I2C_STAT_RDR)
 674                                                 dev_err(dev->dev,
 675                                                         "RDR IRQ while no data"
 676                                                                 " requested\n");
 677                                         break;
 678                                 }
 679                         }
 680                         omap_i2c_ack_stat(dev,
 681                                 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
 682                         continue;
 683                 }
 684                 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
 685                         u8 num_bytes = 1;
 686                         if (dev->fifo_size) {
 687                                 if (stat & OMAP_I2C_STAT_XRDY)
 688                                         num_bytes = dev->fifo_size;
 689                                 else
 690                                         num_bytes = omap_i2c_read_reg(dev,
 691                                                         OMAP_I2C_BUFSTAT_REG);
 692                         }
 693                         while (num_bytes) {
 694                                 num_bytes--;
 695                                 w = 0;
 696                                 if (dev->buf_len) {
 697                                         w = *dev->buf++;
 698                                         dev->buf_len--;
 699                                         /* Data reg from  2430 is 8 bit wide */
 700                                         if (!cpu_is_omap2430() &&
 701                                                         !cpu_is_omap34xx()) {
 702                                                 if (dev->buf_len) {
 703                                                         w |= *dev->buf++ << 8;
 704                                                         dev->buf_len--;
 705                                                 }
 706                                         }
 707                                 } else {
 708                                         if (stat & OMAP_I2C_STAT_XRDY)
 709                                                 dev_err(dev->dev,
 710                                                         "XRDY IRQ while no "
 711                                                         "data to send\n");
 712                                         if (stat & OMAP_I2C_STAT_XDR)
 713                                                 dev_err(dev->dev,
 714                                                         "XDR IRQ while no "
 715                                                         "data to send\n");
 716                                         break;
 717                                 }
 718                                 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 719                         }
 720                         omap_i2c_ack_stat(dev,
 721                                 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
 722                         continue;
 723                 }
 724                 if (stat & OMAP_I2C_STAT_ROVR) {
 725                         dev_err(dev->dev, "Receive overrun\n");
 726                         dev->cmd_err |= OMAP_I2C_STAT_ROVR;
 727                 }
 728                 if (stat & OMAP_I2C_STAT_XUDF) {
 729                         dev_err(dev->dev, "Transmit underflow\n");
 730                         dev->cmd_err |= OMAP_I2C_STAT_XUDF;
 731                 }
 732         }
 733
 734         return count ? IRQ_HANDLED : IRQ_NONE;
 735 }
 736
 737 static const struct i2c_algorithm omap_i2c_algo = {
 738         .master_xfer    = omap_i2c_xfer,
 739         .functionality  = omap_i2c_func,
 740 };
 741
 742 static int __init
 743 omap_i2c_probe(struct platform_device *pdev)
 744 {
 745         struct omap_i2c_dev     *dev;
 746         struct i2c_adapter      *adap;
 747         struct resource         *mem, *irq, *ioarea;
 748         void *isr;
 749         int r;
 750         u32 speed = 0;
 751
 752         /* NOTE: driver uses the static register mapping */
 753         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 754         if (!mem) {
 755                 dev_err(&pdev->dev, "no mem resource?\n");
 756                 return -ENODEV;
 757         }
 758         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 759         if (!irq) {
 760                 dev_err(&pdev->dev, "no irq resource?\n");
 761                 return -ENODEV;
 762         }
 763
 764         ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
 765                         pdev->name);
 766         if (!ioarea) {
 767                 dev_err(&pdev->dev, "I2C region already claimed\n");
 768                 return -EBUSY;
 769         }
 770
 771         dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
 772         if (!dev) {
 773                 r = -ENOMEM;
 774                 goto err_release_region;
 775         }
 776
 777         if (pdev->dev.platform_data != NULL)
 778                 speed = *(u32 *)pdev->dev.platform_data;
 779         else
 780                 speed = 100;    /* Defualt speed */
 781
 782         dev->speed = speed;
 783         dev->idle = 1;
 784         dev->dev = &pdev->dev;
 785         dev->irq = irq->start;
 786         dev->base = ioremap(mem->start, mem->end - mem->start + 1);
 787         if (!dev->base) {
 788                 r = -ENOMEM;
 789                 goto err_free_mem;
 790         }
 791
 792         platform_set_drvdata(pdev, dev);
 793
 794         if ((r = omap_i2c_get_clocks(dev)) != 0)
 795                 goto err_iounmap;
 796
 797         omap_i2c_unidle(dev);
 798
 799         dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
 800
 801         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 802                 u16 s;
 803
 804                 /* Set up the fifo size - Get total size */
 805                 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
 806                 dev->fifo_size = 0x8 << s;
 807
 808                 /*
 809                  * Set up notification threshold as half the total available
 810                  * size. This is to ensure that we can handle the status on int
 811                  * call back latencies.
 812                  */
 813                 dev->fifo_size = (dev->fifo_size / 2);
 814                 dev->b_hw = 1; /* Enable hardware fixes */
 815         }
 816
 817         /* reset ASAP, clearing any IRQs */
 818         omap_i2c_init(dev);
 819
 820         isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr;
 821         r = request_irq(dev->irq, isr, 0, pdev->name, dev);
 822
 823         if (r) {
 824                 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
 825                 goto err_unuse_clocks;
 826         }
 827
 828         dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
 829                  pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
 830
 831         omap_i2c_idle(dev);
 832
 833         adap = &dev->adapter;
 834         i2c_set_adapdata(adap, dev);
 835         adap->owner = THIS_MODULE;
 836         adap->class = I2C_CLASS_HWMON;
 837         strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
 838         adap->algo = &omap_i2c_algo;
 839         adap->dev.parent = &pdev->dev;
 840
 841         /* i2c device drivers may be active on return from add_adapter() */
 842         adap->nr = pdev->id;
 843         r = i2c_add_numbered_adapter(adap);
 844         if (r) {
 845                 dev_err(dev->dev, "failure adding adapter\n");
 846                 goto err_free_irq;
 847         }
 848
 849         return 0;
 850
 851 err_free_irq:
 852         free_irq(dev->irq, dev);
 853 err_unuse_clocks:
 854         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 855         omap_i2c_idle(dev);
 856         omap_i2c_put_clocks(dev);
 857 err_iounmap:
 858         iounmap(dev->base);
 859 err_free_mem:
 860         platform_set_drvdata(pdev, NULL);
 861         kfree(dev);
 862 err_release_region:
 863         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 864
 865         return r;
 866 }
 867
 868 static int
 869 omap_i2c_remove(struct platform_device *pdev)
 870 {
 871         struct omap_i2c_dev     *dev = platform_get_drvdata(pdev);
 872         struct resource         *mem;
 873
 874         platform_set_drvdata(pdev, NULL);
 875
 876         free_irq(dev->irq, dev);
 877         i2c_del_adapter(&dev->adapter);
 878         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 879         omap_i2c_put_clocks(dev);
 880         iounmap(dev->base);
 881         kfree(dev);
 882         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 883         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 884         return 0;
 885 }
 886
 887 static struct platform_driver omap_i2c_driver = {
 888         .probe          = omap_i2c_probe,
 889         .remove         = omap_i2c_remove,
 890         .driver         = {
 891                 .name   = "i2c_omap",
 892                 .owner  = THIS_MODULE,
 893         },
 894 };
 895
 896 /* I2C may be needed to bring up other drivers */
 897 static int __init
 898 omap_i2c_init_driver(void)
 899 {
 900         return platform_driver_register(&omap_i2c_driver);
 901 }
 902 subsys_initcall(omap_i2c_init_driver);
 903
 904 static void __exit omap_i2c_exit_driver(void)
 905 {
 906         platform_driver_unregister(&omap_i2c_driver);
 907 }
 908 module_exit(omap_i2c_exit_driver);
 909
 910 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
 911 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
 912 MODULE_LICENSE("GPL");
 913 MODULE_ALIAS("platform:i2c_omap");