2 * TI OMAP I2C master mode driver
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2005 Nokia Corporation
6 * Copyright (C) 2004 - 2007 Texas Instruments.
8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
31 #include <linux/module.h>
32 #include <linux/delay.h>
33 #include <linux/i2c.h>
34 #include <linux/err.h>
35 #include <linux/interrupt.h>
36 #include <linux/completion.h>
37 #include <linux/platform_device.h>
38 #include <linux/clk.h>
41 /* timeout waiting for the controller to respond */
42 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
44 #define OMAP_I2C_REV_REG 0x00
45 #define OMAP_I2C_IE_REG 0x04
46 #define OMAP_I2C_STAT_REG 0x08
47 #define OMAP_I2C_IV_REG 0x0c
48 #define OMAP_I2C_SYSS_REG 0x10
49 #define OMAP_I2C_BUF_REG 0x14
50 #define OMAP_I2C_CNT_REG 0x18
51 #define OMAP_I2C_DATA_REG 0x1c
52 #define OMAP_I2C_SYSC_REG 0x20
53 #define OMAP_I2C_CON_REG 0x24
54 #define OMAP_I2C_OA_REG 0x28
55 #define OMAP_I2C_SA_REG 0x2c
56 #define OMAP_I2C_PSC_REG 0x30
57 #define OMAP_I2C_SCLL_REG 0x34
58 #define OMAP_I2C_SCLH_REG 0x38
59 #define OMAP_I2C_SYSTEST_REG 0x3c
60 #define OMAP_I2C_BUFSTAT_REG 0x40
62 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
63 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
64 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
65 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
66 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
67 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
68 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
69 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
71 /* I2C Status Register (OMAP_I2C_STAT): */
72 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
73 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
74 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
75 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
76 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
77 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
78 #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
79 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
80 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
81 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
82 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
83 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
85 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
86 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
87 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
88 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
89 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
91 /* I2C Configuration Register (OMAP_I2C_CON): */
92 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
93 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
94 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
95 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
96 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
97 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
98 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
99 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
100 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
101 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
103 /* I2C SCL time value when Master */
104 #define OMAP_I2C_SCLL_HSSCLL 8
105 #define OMAP_I2C_SCLH_HSSCLH 8
107 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
109 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
110 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
111 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
112 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
113 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
114 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
115 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
116 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
119 /* I2C System Status register (OMAP_I2C_SYSS): */
120 #define OMAP_I2C_SYSS_RDONE (1 << 0) /* Reset Done */
122 /* I2C System Configuration Register (OMAP_I2C_SYSC): */
123 #define OMAP_I2C_SYSC_SRST (1 << 1) /* Soft Reset */
125 struct omap_i2c_dev {
127 void __iomem *base; /* virtual */
129 struct clk *iclk; /* Interface clock */
130 struct clk *fclk; /* Functional clock */
131 struct completion cmd_complete;
132 struct resource *ioarea;
133 u32 speed; /* Speed of bus in Khz */
137 struct i2c_adapter adapter;
138 u8 fifo_size; /* use as flag and value
139 * fifo_size==0 implies no fifo
140 * if set, should be trsh+1
143 unsigned b_hw:1; /* bad h/w fixes */
145 u16 iestate; /* Saved interrupt register */
148 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
151 __raw_writew(val, i2c_dev->base + reg);
154 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
156 return __raw_readw(i2c_dev->base + reg);
159 static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
161 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
162 dev->iclk = clk_get(dev->dev, "i2c_ick");
163 if (IS_ERR(dev->iclk)) {
168 /* For I2C operations on 2430 we need 96Mhz clock */
169 if (cpu_is_omap2430()) {
170 dev->fclk = clk_get(dev->dev, "i2chs_fck");
171 if (IS_ERR(dev->fclk)) {
172 if (dev->iclk != NULL) {
180 dev->fclk = clk_get(dev->dev, "i2c_fck");
181 if (IS_ERR(dev->fclk)) {
182 if (dev->iclk != NULL) {
193 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
197 if (dev->iclk != NULL) {
203 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
207 if (dev->iclk != NULL)
208 clk_enable(dev->iclk);
209 clk_enable(dev->fclk);
212 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
215 static void omap_i2c_idle(struct omap_i2c_dev *dev)
221 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
222 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
224 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
226 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
228 * The wmb() is to ensure that the I2C interrupt mask write
229 * reaches the I2C controller before the dev->idle store
234 clk_disable(dev->fclk);
235 if (dev->iclk != NULL)
236 clk_disable(dev->iclk);
239 static int omap_i2c_init(struct omap_i2c_dev *dev)
241 u16 psc = 0, scll = 0, sclh = 0;
242 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
243 unsigned long fclk_rate = 12000000;
244 unsigned long timeout;
245 unsigned long internal_clk = 0;
248 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
249 /* For some reason we need to set the EN bit before the
250 * reset done bit gets set. */
251 timeout = jiffies + OMAP_I2C_TIMEOUT;
252 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
253 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
254 OMAP_I2C_SYSS_RDONE)) {
255 if (time_after(jiffies, timeout)) {
256 dev_warn(dev->dev, "timeout waiting "
257 "for controller reset\n");
263 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
265 if (cpu_class_is_omap1()) {
266 struct clk *armxor_ck;
268 armxor_ck = clk_get(NULL, "armxor_ck");
269 if (IS_ERR(armxor_ck))
270 dev_warn(dev->dev, "Could not get armxor_ck\n");
272 fclk_rate = clk_get_rate(armxor_ck);
275 /* TRM for 5912 says the I2C clock must be prescaled to be
276 * between 7 - 12 MHz. The XOR input clock is typically
277 * 12, 13 or 19.2 MHz. So we should have code that produces:
279 * XOR MHz Divider Prescaler
284 if (fclk_rate > 12000000)
285 psc = fclk_rate / 12000000;
288 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
290 /* HSI2C controller internal clk rate should be 19.2 Mhz */
291 internal_clk = 19200;
292 fclk_rate = clk_get_rate(dev->fclk) / 1000;
294 /* Compute prescaler divisor */
295 psc = fclk_rate / internal_clk;
298 /* If configured for High Speed */
299 if (dev->speed > 400) {
300 /* For first phase of HS mode */
301 fsscll = internal_clk / (400 * 2) - 6;
302 fssclh = internal_clk / (400 * 2) - 6;
304 /* For second phase of HS mode */
305 hsscll = fclk_rate / (dev->speed * 2) - 6;
306 hssclh = fclk_rate / (dev->speed * 2) - 6;
308 /* To handle F/S modes */
309 fsscll = internal_clk / (dev->speed * 2) - 6;
310 fssclh = internal_clk / (dev->speed * 2) - 6;
312 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
313 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
315 /* Program desired operating rate */
316 fclk_rate /= (psc + 1) * 1000;
319 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
320 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
323 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
324 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
326 /* SCL low and high time values */
327 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
328 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
331 /* Note: setup required fifo size - 1 */
332 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
333 (dev->fifo_size - 1) << 8 | /* RTRSH */
334 OMAP_I2C_BUF_RXFIF_CLR |
335 (dev->fifo_size - 1) | /* XTRSH */
336 OMAP_I2C_BUF_TXFIF_CLR);
338 /* Take the I2C module out of reset: */
339 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
341 /* Enable interrupts */
342 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
343 (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
344 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
345 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
346 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
351 * Waiting on Bus Busy
353 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
355 unsigned long timeout;
357 timeout = jiffies + OMAP_I2C_TIMEOUT;
358 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
359 if (time_after(jiffies, timeout)) {
360 dev_warn(dev->dev, "timeout waiting for bus ready\n");
370 * Low level master read/write transaction.
372 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
373 struct i2c_msg *msg, int stop)
375 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
379 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
380 msg->addr, msg->len, msg->flags, stop);
385 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
387 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
389 dev->buf_len = msg->len;
391 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
393 /* Clear the FIFO Buffers */
394 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
395 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
396 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
398 init_completion(&dev->cmd_complete);
401 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
403 /* High speed configuration */
404 if (dev->speed > 400)
405 w |= OMAP_I2C_CON_OPMODE_HS;
407 if (msg->flags & I2C_M_TEN)
408 w |= OMAP_I2C_CON_XA;
409 if (!(msg->flags & I2C_M_RD))
410 w |= OMAP_I2C_CON_TRX;
412 if (!dev->b_hw && stop)
413 w |= OMAP_I2C_CON_STP;
415 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
418 * Don't write stt and stp together on some hardware
420 if (dev->b_hw && stop) {
421 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
422 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
423 while (con & OMAP_I2C_CON_STT) {
424 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
426 /* Let the user know if i2c is in a bad state */
427 if (time_after(jiffies, delay)) {
428 dev_err(dev->dev, "controller timed out "
429 "waiting for start condition to finish\n");
435 w |= OMAP_I2C_CON_STP;
436 w &= ~OMAP_I2C_CON_STT;
437 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
439 r = wait_for_completion_timeout(&dev->cmd_complete,
445 dev_err(dev->dev, "controller timed out\n");
450 if (likely(!dev->cmd_err))
453 /* We have an error */
454 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
455 OMAP_I2C_STAT_XUDF)) {
460 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
461 if (msg->flags & I2C_M_IGNORE_NAK)
464 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
465 w |= OMAP_I2C_CON_STP;
466 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
475 * Prepare controller for a transaction and call omap_i2c_xfer_msg
476 * to do the work during IRQ processing.
479 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
481 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
485 omap_i2c_unidle(dev);
487 r = omap_i2c_wait_for_bb(dev);
491 for (i = 0; i < num; i++) {
492 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
505 omap_i2c_func(struct i2c_adapter *adap)
507 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
511 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
514 complete(&dev->cmd_complete);
518 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
520 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
523 /* rev1 devices are apparently only on some 15xx */
524 #ifdef CONFIG_ARCH_OMAP15XX
527 omap_i2c_rev1_isr(int this_irq, void *dev_id)
529 struct omap_i2c_dev *dev = dev_id;
535 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
537 case 0x00: /* None */
539 case 0x01: /* Arbitration lost */
540 dev_err(dev->dev, "Arbitration lost\n");
541 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
543 case 0x02: /* No acknowledgement */
544 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
545 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
547 case 0x03: /* Register access ready */
548 omap_i2c_complete_cmd(dev, 0);
550 case 0x04: /* Receive data ready */
552 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
556 *dev->buf++ = w >> 8;
560 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
562 case 0x05: /* Transmit data ready */
567 w |= *dev->buf++ << 8;
570 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
572 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
581 #define omap_i2c_rev1_isr 0
585 omap_i2c_isr(int this_irq, void *dev_id)
587 struct omap_i2c_dev *dev = dev_id;
595 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
596 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
597 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
598 if (count++ == 100) {
599 dev_warn(dev->dev, "Too much work in one IRQ\n");
603 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
606 if (stat & OMAP_I2C_STAT_NACK) {
607 err |= OMAP_I2C_STAT_NACK;
608 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
611 if (stat & OMAP_I2C_STAT_AL) {
612 dev_err(dev->dev, "Arbitration lost\n");
613 err |= OMAP_I2C_STAT_AL;
615 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
617 omap_i2c_complete_cmd(dev, err);
618 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
620 if (dev->fifo_size) {
621 if (stat & OMAP_I2C_STAT_RRDY)
622 num_bytes = dev->fifo_size;
624 num_bytes = omap_i2c_read_reg(dev,
625 OMAP_I2C_BUFSTAT_REG);
629 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
633 /* Data reg from 2430 is 8 bit wide */
634 if (!cpu_is_omap2430() &&
635 !cpu_is_omap34xx()) {
637 *dev->buf++ = w >> 8;
642 if (stat & OMAP_I2C_STAT_RRDY)
644 "RRDY IRQ while no data"
646 if (stat & OMAP_I2C_STAT_RDR)
648 "RDR IRQ while no data"
653 omap_i2c_ack_stat(dev,
654 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
657 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
659 if (dev->fifo_size) {
660 if (stat & OMAP_I2C_STAT_XRDY)
661 num_bytes = dev->fifo_size;
663 num_bytes = omap_i2c_read_reg(dev,
664 OMAP_I2C_BUFSTAT_REG);
672 /* Data reg from 2430 is 8 bit wide */
673 if (!cpu_is_omap2430() &&
674 !cpu_is_omap34xx()) {
676 w |= *dev->buf++ << 8;
681 if (stat & OMAP_I2C_STAT_XRDY)
685 if (stat & OMAP_I2C_STAT_XDR)
691 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
693 omap_i2c_ack_stat(dev,
694 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
697 if (stat & OMAP_I2C_STAT_ROVR) {
698 dev_err(dev->dev, "Receive overrun\n");
699 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
701 if (stat & OMAP_I2C_STAT_XUDF) {
702 dev_err(dev->dev, "Transmit underflow\n");
703 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
707 return count ? IRQ_HANDLED : IRQ_NONE;
710 static const struct i2c_algorithm omap_i2c_algo = {
711 .master_xfer = omap_i2c_xfer,
712 .functionality = omap_i2c_func,
716 omap_i2c_probe(struct platform_device *pdev)
718 struct omap_i2c_dev *dev;
719 struct i2c_adapter *adap;
720 struct resource *mem, *irq, *ioarea;
724 /* NOTE: driver uses the static register mapping */
725 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
727 dev_err(&pdev->dev, "no mem resource?\n");
730 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
732 dev_err(&pdev->dev, "no irq resource?\n");
736 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
739 dev_err(&pdev->dev, "I2C region already claimed\n");
743 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
746 goto err_release_region;
749 if (pdev->dev.platform_data != NULL)
750 speed = (u32 *) pdev->dev.platform_data;
752 *speed = 100; /* Defualt speed */
756 dev->dev = &pdev->dev;
757 dev->irq = irq->start;
758 dev->base = ioremap(mem->start, mem->end - mem->start + 1);
764 platform_set_drvdata(pdev, dev);
766 r = omap_i2c_get_clocks(dev);
770 omap_i2c_unidle(dev);
772 if (cpu_is_omap15xx())
773 dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20;
775 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
778 /* Set up the fifo size - Get total size */
779 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
780 dev->fifo_size = 0x8 << s;
783 * Set up notification threshold as half the total available
784 * size. This is to ensure that we can handle the status on int
785 * call back latencies.
787 dev->fifo_size = (dev->fifo_size / 2);
788 dev->b_hw = 1; /* Enable hardware fixes */
791 /* reset ASAP, clearing any IRQs */
794 r = request_irq(dev->irq, dev->rev1 ? omap_i2c_rev1_isr : omap_i2c_isr,
798 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
799 goto err_unuse_clocks;
801 r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
802 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
803 pdev->id, r >> 4, r & 0xf, dev->speed);
807 adap = &dev->adapter;
808 i2c_set_adapdata(adap, dev);
809 adap->owner = THIS_MODULE;
810 adap->class = I2C_CLASS_HWMON;
811 strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
812 adap->algo = &omap_i2c_algo;
813 adap->dev.parent = &pdev->dev;
815 /* i2c device drivers may be active on return from add_adapter() */
817 r = i2c_add_numbered_adapter(adap);
819 dev_err(dev->dev, "failure adding adapter\n");
826 free_irq(dev->irq, dev);
828 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
830 omap_i2c_put_clocks(dev);
834 platform_set_drvdata(pdev, NULL);
837 release_mem_region(mem->start, (mem->end - mem->start) + 1);
843 omap_i2c_remove(struct platform_device *pdev)
845 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
846 struct resource *mem;
848 platform_set_drvdata(pdev, NULL);
850 free_irq(dev->irq, dev);
851 i2c_del_adapter(&dev->adapter);
852 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
853 omap_i2c_put_clocks(dev);
856 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
857 release_mem_region(mem->start, (mem->end - mem->start) + 1);
861 static struct platform_driver omap_i2c_driver = {
862 .probe = omap_i2c_probe,
863 .remove = omap_i2c_remove,
866 .owner = THIS_MODULE,
870 /* I2C may be needed to bring up other drivers */
872 omap_i2c_init_driver(void)
874 return platform_driver_register(&omap_i2c_driver);
876 subsys_initcall(omap_i2c_init_driver);
878 static void __devexit omap_i2c_exit_driver(void)
880 platform_driver_unregister(&omap_i2c_driver);
882 module_exit(omap_i2c_exit_driver);
884 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
885 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
886 MODULE_LICENSE("GPL");
887 MODULE_ALIAS("platform:i2c_omap");