drivers/i2c/busses/i2c-omap.c

   1 /*
   2  * linux/drivers/i2c/i2c-omap.c
   3  *
   4  * TI OMAP I2C master mode driver
   5  *
   6  * Copyright (C) 2003 MontaVista Software, Inc.
   7  * Copyright (C) 2004 Texas Instruments.
   8  *
   9  * Updated to work with multiple I2C interfaces on 24xx by
  10  * Tony Lindgren <tony@atomide.com> and Imre Deak <imre.deak@nokia.com>
  11  * Copyright (C) 2005 Nokia Corporation
  12  *
  13  * Cleaned up by Juha Yrjölä <juha.yrjola@nokia.com>
  14  *
  15  * ----------------------------------------------------------------------------
  16  * This file was highly leveraged from i2c-elektor.c:
  17  *
  18  * Copyright 1995-97 Simon G. Vogl
  19  *           1998-99 Hans Berglund
  20  *
  21  * With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and even
  22  * Frodo Looijaard <frodol@dds.nl>
  23  *
  24  * This program is free software; you can redistribute it and/or modify
  25  * it under the terms of the GNU General Public License as published by
  26  * the Free Software Foundation; either version 2 of the License, or
  27  * (at your option) any later version.
  28  *
  29  * This program is distributed in the hope that it will be useful,
  30  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  31  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  32  * GNU General Public License for more details.
  33  *
  34  * You should have received a copy of the GNU General Public License
  35  * along with this program; if not, write to the Free Software
  36  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  37  */
  38
  39 // #define DEBUG
  40
  41 #include <linux/module.h>
  42 #include <linux/delay.h>
  43 #include <linux/i2c.h>
  44 #include <linux/err.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/completion.h>
  47 #include <linux/platform_device.h>
  48 #include <linux/clk.h>
  49
  50 #include <asm/io.h>
  51
  52 /* ----- global defines ----------------------------------------------- */
  53 static const char driver_name[] = "i2c_omap";
  54
  55 #define MODULE_NAME "OMAP I2C"
  56 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) /* timeout waiting for the controller to respond */
  57
  58 #define DEFAULT_OWN             1       /* default own I2C address */
  59 #define MAX_MESSAGES            65536   /* max number of messages */
  60
  61 #define OMAP_I2C_REV_REG                0x00
  62 #define OMAP_I2C_IE_REG                 0x04
  63 #define OMAP_I2C_STAT_REG               0x08
  64 #define OMAP_I2C_IV_REG                 0x0c
  65 #define OMAP_I2C_SYSS_REG               0x10
  66 #define OMAP_I2C_BUF_REG                0x14
  67 #define OMAP_I2C_CNT_REG                0x18
  68 #define OMAP_I2C_DATA_REG               0x1c
  69 #define OMAP_I2C_SYSC_REG               0x20
  70 #define OMAP_I2C_CON_REG                0x24
  71 #define OMAP_I2C_OA_REG                 0x28
  72 #define OMAP_I2C_SA_REG                 0x2c
  73 #define OMAP_I2C_PSC_REG                0x30
  74 #define OMAP_I2C_SCLL_REG               0x34
  75 #define OMAP_I2C_SCLH_REG               0x38
  76 #define OMAP_I2C_SYSTEST_REG            0x3c
  77
  78 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
  79 #define OMAP_I2C_IE_XRDY        (1 << 4)        /* TX data ready int enable */
  80 #define OMAP_I2C_IE_RRDY        (1 << 3)        /* RX data ready int enable */
  81 #define OMAP_I2C_IE_ARDY        (1 << 2)        /* Access ready int enable */
  82 #define OMAP_I2C_IE_NACK        (1 << 1)        /* No ack interrupt enable */
  83 #define OMAP_I2C_IE_AL          (1 << 0)        /* Arbitration lost int ena */
  84
  85 /* I2C Status Register (OMAP_I2C_STAT): */
  86 #define OMAP_I2C_STAT_SBD       (1 << 15)       /* Single byte data */
  87 #define OMAP_I2C_STAT_BB        (1 << 12)       /* Bus busy */
  88 #define OMAP_I2C_STAT_ROVR      (1 << 11)       /* Receive overrun */
  89 #define OMAP_I2C_STAT_XUDF      (1 << 10)       /* Transmit underflow */
  90 #define OMAP_I2C_STAT_AAS       (1 << 9)        /* Address as slave */
  91 #define OMAP_I2C_STAT_AD0       (1 << 8)        /* Address zero */
  92 #define OMAP_I2C_STAT_XRDY      (1 << 4)        /* Transmit data ready */
  93 #define OMAP_I2C_STAT_RRDY      (1 << 3)        /* Receive data ready */
  94 #define OMAP_I2C_STAT_ARDY      (1 << 2)        /* Register access ready */
  95 #define OMAP_I2C_STAT_NACK      (1 << 1)        /* No ack interrupt enable */
  96 #define OMAP_I2C_STAT_AL        (1 << 0)        /* Arbitration lost int ena */
  97
  98 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
  99 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)       /* RX DMA channel enable */
 100 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)        /* TX DMA channel enable */
 101
 102 /* I2C Configuration Register (OMAP_I2C_CON): */
 103 #define OMAP_I2C_CON_EN         (1 << 15)       /* I2C module enable */
 104 #define OMAP_I2C_CON_BE         (1 << 14)       /* Big endian mode */
 105 #define OMAP_I2C_CON_STB        (1 << 11)       /* Start byte mode (master) */
 106 #define OMAP_I2C_CON_MST        (1 << 10)       /* Master/slave mode */
 107 #define OMAP_I2C_CON_TRX        (1 << 9)        /* TX/RX mode (master only) */
 108 #define OMAP_I2C_CON_XA         (1 << 8)        /* Expand address */
 109 #define OMAP_I2C_CON_RM         (1 << 2)        /* Repeat mode (master only) */
 110 #define OMAP_I2C_CON_STP        (1 << 1)        /* Stop cond (master only) */
 111 #define OMAP_I2C_CON_STT        (1 << 0)        /* Start condition (master) */
 112
 113 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
 114 #define OMAP_I2C_SYSTEST_ST_EN          (1 << 15)       /* System test enable */
 115 #define OMAP_I2C_SYSTEST_FREE           (1 << 14)       /* Free running mode */
 116 #define OMAP_I2C_SYSTEST_TMODE_MASK     (3 << 12)       /* Test mode select */
 117 #define OMAP_I2C_SYSTEST_TMODE_SHIFT    (12)            /* Test mode select */
 118 #define OMAP_I2C_SYSTEST_SCL_I          (1 << 3)        /* SCL line sense in */
 119 #define OMAP_I2C_SYSTEST_SCL_O          (1 << 2)        /* SCL line drive out */
 120 #define OMAP_I2C_SYSTEST_SDA_I          (1 << 1)        /* SDA line sense in */
 121 #define OMAP_I2C_SYSTEST_SDA_O          (1 << 0)        /* SDA line drive out */
 122
 123 /* I2C System Status register (OMAP_I2C_SYSS): */
 124 #define OMAP_I2C_SYSS_RDONE             1               /* Reset Done */
 125
 126 /* I2C System Configuration Register (OMAP_I2C_SYSC): */
 127 #define OMAP_I2C_SYSC_SRST              (1 << 1)        /* Soft Reset */
 128
 129 /* REVISIT: Use platform_data instead of module parameters */
 130 static int clock = 100; /* Default: Fast Mode = 400 KHz, Standard = 100 KHz */
 131 module_param(clock, int, 0);
 132 MODULE_PARM_DESC(clock, "Set I2C clock in kHz: 100 or 400 (Fast Mode)");
 133
 134 static int own;
 135 module_param(own, int, 0);
 136 MODULE_PARM_DESC(own, "Address of OMAP I2C master (0 for default == 1)");
 137
 138 struct omap_i2c_dev {
 139         struct device           *dev;
 140         void __iomem            *base;          /* virtual */
 141         int                     irq;
 142         struct clk              *iclk;          /* Interface clock */
 143         struct clk              *fclk;          /* Functional clock */
 144         struct completion       cmd_complete;
 145         u16                     cmd_err;
 146         u8                      *buf;
 147         size_t                  buf_len;
 148         struct i2c_adapter      adapter;
 149         unsigned                rev1:1;
 150         u8                      own_address;
 151 };
 152
 153 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
 154                                       int reg, u16 val)
 155 {
 156         __raw_writew(val, i2c_dev->base + reg);
 157 }
 158
 159 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
 160 {
 161         return __raw_readw(i2c_dev->base + reg);
 162 }
 163
 164 static int omap_i2c_get_clocks(struct omap_i2c_dev *dev)
 165 {
 166         if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
 167                 dev->iclk = clk_get(dev->dev, "i2c_ick");
 168                 if (IS_ERR(dev->iclk))
 169                         return -ENODEV;
 170         }
 171
 172         dev->fclk = clk_get(dev->dev, "i2c_fck");
 173         if (IS_ERR(dev->fclk)) {
 174                 if (dev->iclk != NULL)
 175                         clk_put(dev->iclk);
 176                 return -ENODEV;
 177         }
 178
 179         return 0;
 180 }
 181
 182 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
 183 {
 184         clk_put(dev->fclk);
 185         dev->fclk = NULL;
 186         if (dev->iclk != NULL) {
 187                 clk_put(dev->iclk);
 188                 dev->iclk = NULL;
 189         }
 190 }
 191
 192 static void omap_i2c_enable_clocks(struct omap_i2c_dev *dev)
 193 {
 194         if (dev->iclk != NULL)
 195                 clk_enable(dev->iclk);
 196         clk_enable(dev->fclk);
 197 }
 198
 199 static void omap_i2c_disable_clocks(struct omap_i2c_dev *dev)
 200 {
 201         if (dev->iclk != NULL)
 202                 clk_disable(dev->iclk);
 203         clk_disable(dev->fclk);
 204 }
 205
 206 static void omap_i2c_reset(struct omap_i2c_dev *dev)
 207 {
 208         u16 psc;
 209         unsigned long fclk_rate;
 210
 211         if (!dev->rev1) {
 212                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
 213                 /* For some reason we need to set the EN bit before the
 214                  * reset done bit gets set. */
 215                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 216                 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) & 0x01));
 217         }
 218         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 219
 220         if (cpu_class_is_omap1()) {
 221                 struct clk *armxor_ck;
 222                 unsigned long armxor_rate;
 223
 224                 armxor_ck = clk_get(NULL, "armxor_ck");
 225                 if (IS_ERR(armxor_ck)) {
 226                         printk(KERN_WARNING "i2c: Could not get armxor_ck\n");
 227                         armxor_rate = 12000000;
 228                 } else {
 229                         armxor_rate = clk_get_rate(armxor_ck);
 230                         clk_put(armxor_ck);
 231                 }
 232
 233                 if (armxor_rate > 16000000)
 234                         psc = (armxor_rate + 8000000) / 12000000;
 235                 else
 236                         psc = 0;
 237
 238                 fclk_rate = armxor_rate;
 239         } else if (cpu_class_is_omap2()) {
 240                 fclk_rate = 12000000;
 241                 psc = 0;
 242         }
 243
 244         /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
 245         omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
 246
 247         /* Program desired operating rate */
 248         fclk_rate /= (psc + 1) * 1000;
 249         if (psc > 2)
 250                 psc = 2;
 251
 252         omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG,
 253                            fclk_rate / (clock * 2) - 7 + psc);
 254         omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG,
 255                            fclk_rate / (clock * 2) - 7 + psc);
 256
 257         /* Set Own Address: */
 258         omap_i2c_write_reg(dev, OMAP_I2C_OA_REG, dev->own_address);
 259
 260         /* Take the I2C module out of reset: */
 261         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 262
 263         /* Enable interrupts */
 264         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
 265                            (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
 266                             OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
 267                             OMAP_I2C_IE_AL));
 268 }
 269
 270 /*
 271  * Waiting on Bus Busy
 272  */
 273 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
 274 {
 275         unsigned long timeout;
 276
 277         timeout = jiffies + OMAP_I2C_TIMEOUT;
 278         while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
 279                 if (time_after(jiffies, timeout)) {
 280                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 281                         return -ETIMEDOUT;
 282                 }
 283                 msleep(1);
 284         }
 285
 286         return 0;
 287 }
 288
 289 /*
 290  * Low level master read/write transaction.
 291  */
 292 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 293                              struct i2c_msg *msg, int stop)
 294 {
 295         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 296         int r;
 297         u16 w;
 298         u8 zero_byte = 0;
 299
 300         dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 301                 msg->addr, msg->len, msg->flags, stop);
 302
 303         omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
 304
 305         /* Sigh, seems we can't do zero length transactions. Thus, we
 306          * can't probe for devices w/o actually sending/receiving at least
 307          * a single byte. So we'll set count to 1 for the zero length
 308          * transaction case and hope we don't cause grief for some
 309          * arbitrary device due to random byte write/read during
 310          * probes.
 311          */
 312         /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
 313         if (msg->len == 0) {
 314                 dev->buf = &zero_byte;
 315                 dev->buf_len = 1;
 316         } else {
 317                 dev->buf = msg->buf;
 318                 dev->buf_len = msg->len;
 319         }
 320         omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
 321
 322         init_completion(&dev->cmd_complete);
 323         dev->cmd_err = 0;
 324
 325         w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 326         if (msg->flags & I2C_M_TEN)
 327                 w |= OMAP_I2C_CON_XA;
 328         if (!(msg->flags & I2C_M_RD))
 329                 w |= OMAP_I2C_CON_TRX;
 330         if (stop)
 331                 w |= OMAP_I2C_CON_STP;
 332         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 333
 334         r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
 335                                                       OMAP_I2C_TIMEOUT);
 336         dev->buf_len = 0;
 337         if (r < 0)
 338                 return r;
 339         if (r == 0) {
 340                 dev_err(dev->dev, "controller timed out\n");
 341                 omap_i2c_reset(dev);
 342                 return -ETIMEDOUT;
 343         }
 344
 345         if (likely(!dev->cmd_err))
 346                 return 0;
 347
 348         /* We have an error */
 349         if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
 350                 if (msg->flags & I2C_M_IGNORE_NAK)
 351                         return 0;
 352                 if (stop) {
 353                         u16 w;
 354
 355                         w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 356                         w |= OMAP_I2C_CON_STP;
 357                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 358                 }
 359                 return -EREMOTEIO;
 360         }
 361         if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
 362                             OMAP_I2C_STAT_XUDF))
 363                 omap_i2c_reset(dev);
 364         return -EIO;
 365 }
 366
 367
 368 /*
 369  * Prepare controller for a transaction and call omap_i2c_xfer_msg
 370  * to do the work during IRQ processing.
 371  */
 372 static int
 373 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 374 {
 375         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 376         int i;
 377         int r = 0;
 378
 379         if (num < 1 || num > MAX_MESSAGES)
 380                 return -EINVAL;
 381
 382         /* Check for valid parameters in messages */
 383         for (i = 0; i < num; i++)
 384                 if (msgs[i].buf == NULL)
 385                         return -EINVAL;
 386
 387         omap_i2c_enable_clocks(dev);
 388
 389         /* REVISIT: initialize and use adap->retries */
 390         if ((r = omap_i2c_wait_for_bb(dev)) < 0)
 391                 goto out;
 392
 393         for (i = 0; i < num; i++) {
 394                 dev_dbg(dev->dev, "msg: %d, addr: 0x%04x, len: %d, flags: 0x%x\n",
 395                         i, msgs[i].addr, msgs[i].len, msgs[i].flags);
 396                 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 397                 if (r != 0)
 398                         break;
 399         }
 400
 401         if (r == 0)
 402                 r = num;
 403 out:
 404         omap_i2c_disable_clocks(dev);
 405         return r;
 406 }
 407
 408 static u32
 409 omap_i2c_func(struct i2c_adapter *adap)
 410 {
 411         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 412 }
 413
 414 static inline void
 415 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
 416 {
 417         dev->cmd_err |= err;
 418         complete(&dev->cmd_complete);
 419 }
 420
 421 static inline void
 422 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
 423 {
 424         omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 425 }
 426
 427 #ifdef CONFIG_ARCH_OMAP15XX
 428 static irqreturn_t
 429 omap_i2c_rev1_isr(int this_irq, void *dev_id, struct pt_regs *regs)
 430 {
 431         struct omap_i2c_dev *dev = dev_id;
 432         u16 iv, w;
 433
 434         iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
 435         switch (iv) {
 436         case 0x00:      /* None */
 437                 break;
 438         case 0x01:      /* Arbitration lost */
 439                 dev_err(dev->dev, "Arbitration lost\n");
 440                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
 441                 break;
 442         case 0x02:      /* No acknowledgement */
 443                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
 444                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
 445                 break;
 446         case 0x03:      /* Register access ready */
 447                 omap_i2c_complete_cmd(dev, 0);
 448                 break;
 449         case 0x04:      /* Receive data ready */
 450                 if (dev->buf_len) {
 451                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 452                         *dev->buf++ = w;
 453                         dev->buf_len--;
 454                         if (dev->buf_len) {
 455                                 *dev->buf++ = w >> 8;
 456                                 dev->buf_len--;
 457                         }
 458                 } else
 459                         dev_err(dev->dev, "RRDY IRQ while no data requested\n");
 460                 break;
 461         case 0x05:      /* Transmit data ready */
 462                 if (dev->buf_len) {
 463                         w = *dev->buf++;
 464                         dev->buf_len--;
 465                         if (dev->buf_len) {
 466                                 w |= *dev->buf++ << 8;
 467                                 dev->buf_len--;
 468                         }
 469                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 470                 } else
 471                         dev_err(dev->dev, "XRDY IRQ while no data to send\n");
 472                 break;
 473         default:
 474                 return IRQ_NONE;
 475         }
 476
 477         return IRQ_HANDLED;
 478 }
 479 #endif
 480
 481 static irqreturn_t
 482 omap_i2c_isr(int this_irq, void *dev_id, struct pt_regs *regs)
 483 {
 484         struct omap_i2c_dev *dev = dev_id;
 485         u16 bits;
 486         u16 stat, w;
 487         int count = 0;
 488
 489         bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 490         while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
 491                 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 492                 if (count++ == 100) {
 493                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 494                         break;
 495                 }
 496
 497                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 498
 499                 if (stat & OMAP_I2C_STAT_ARDY) {
 500                         omap_i2c_complete_cmd(dev, 0);
 501                         continue;
 502                 }
 503                 if (stat & OMAP_I2C_STAT_RRDY) {
 504                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 505                         if (dev->buf_len) {
 506                                 *dev->buf++ = w;
 507                                 dev->buf_len--;
 508                                 if (dev->buf_len) {
 509                                         *dev->buf++ = w >> 8;
 510                                         dev->buf_len--;
 511                                 }
 512                         } else
 513                                 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
 514                         omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
 515                         continue;
 516                 }
 517                 if (stat & OMAP_I2C_STAT_XRDY) {
 518                         int bail_out = 0;
 519
 520                         w = 0;
 521                         if (dev->buf_len) {
 522                                 w = *dev->buf++;
 523                                 dev->buf_len--;
 524                                 if (dev->buf_len) {
 525                                         w |= *dev->buf++ << 8;
 526                                         dev->buf_len--;
 527                                 }
 528                         } else
 529                                 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
 530 #if 0
 531                         if (!(stat & OMAP_I2C_STAT_BB)) {
 532                                 dev_warn(dev->dev, "XRDY while bus not busy\n");
 533                                 bail_out = 1;
 534                         }
 535 #endif
 536                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 537                         omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
 538                         if (bail_out)
 539                                 omap_i2c_complete_cmd(dev, 1 << 15);
 540                         continue;
 541                 }
 542                 if (stat & OMAP_I2C_STAT_ROVR) {
 543                         dev_err(dev->dev, "Receive overrun\n");
 544                         dev->cmd_err |= OMAP_I2C_STAT_ROVR;
 545                 }
 546                 if (stat & OMAP_I2C_STAT_XUDF) {
 547                         dev_err(dev->dev, "Transmit overflow\n");
 548                         dev->cmd_err |= OMAP_I2C_STAT_XUDF;
 549                 }
 550                 if (stat & OMAP_I2C_STAT_NACK) {
 551                         omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
 552                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
 553                 }
 554                 if (stat & OMAP_I2C_STAT_AL) {
 555                         dev_err(dev->dev, "Arbitration lost\n");
 556                         omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
 557                 }
 558         }
 559
 560         return count ? IRQ_HANDLED : IRQ_NONE;
 561 }
 562
 563 static struct i2c_algorithm omap_i2c_algo = {
 564         .master_xfer    = omap_i2c_xfer,
 565         .functionality  = omap_i2c_func,
 566 };
 567
 568 static int
 569 omap_i2c_probe(struct platform_device *pdev)
 570 {
 571         struct omap_i2c_dev     *dev;
 572         struct i2c_adapter      *adap;
 573         struct resource         *mem, *irq;
 574         int r;
 575
 576         /* NOTE: driver uses the static register mapping */
 577         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 578         if (!mem) {
 579                 dev_err(&pdev->dev, "no mem resource?\n");
 580                 return -ENODEV;
 581         }
 582         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 583         if (!irq) {
 584                 dev_err(&pdev->dev, "no irq resource?\n");
 585                 return -ENODEV;
 586         }
 587
 588         r = (int) request_mem_region(mem->start, (mem->end - mem->start) + 1,
 589                         driver_name);
 590         if (!r) {
 591                 dev_err(&pdev->dev, "I2C region already claimed\n");
 592                 return -EBUSY;
 593         }
 594
 595         if (clock > 200)
 596                 clock = 400;    /* Fast mode */
 597         else
 598                 clock = 100;    /* Standard mode */
 599
 600         dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
 601         if (!dev) {
 602                 r = -ENOMEM;
 603                 goto do_release_region;
 604         }
 605
 606         /* FIXME: Get own address from platform_data */
 607         if (own >= 1 && own < 0x7f)
 608                 dev->own_address = own;
 609         else
 610                 own = DEFAULT_OWN;
 611
 612         dev->dev = &pdev->dev;
 613         dev->irq = irq->start;
 614         dev->base = (void __iomem *) IO_ADDRESS(mem->start);
 615         platform_set_drvdata(pdev, dev);
 616
 617         if ((r = omap_i2c_get_clocks(dev)) != 0)
 618                 goto do_free_mem;
 619
 620         omap_i2c_enable_clocks(dev);
 621
 622 #ifdef CONFIG_ARCH_OMAP15XX
 623         dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20;
 624 #endif
 625
 626         /* reset ASAP, clearing any IRQs */
 627         omap_i2c_reset(dev);
 628
 629 #ifdef CONFIG_ARCH_OMAP15XX
 630         r = request_irq(dev->irq, dev->rev1 ? omap_i2c_rev1_isr : omap_i2c_isr,
 631                         0, driver_name, dev);
 632 #else
 633         r = request_irq(dev->irq, omap_i2c_isr, 0, driver_name, dev);
 634 #endif
 635         if (r) {
 636                 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
 637                 goto do_unuse_clocks;
 638         }
 639         r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
 640         dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
 641                  pdev->id - 1, r >> 4, r & 0xf, clock);
 642
 643         adap = &dev->adapter;
 644         i2c_set_adapdata(adap, dev);
 645         adap->owner = THIS_MODULE;
 646         adap->class = I2C_CLASS_HWMON;
 647         strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
 648         adap->algo = &omap_i2c_algo;
 649         adap->dev.parent = &pdev->dev;
 650
 651         /* i2c device drivers may be active on return from add_adapter() */
 652         r = i2c_add_adapter(adap);
 653         if (r) {
 654                 dev_err(dev->dev, "failure adding adapter\n");
 655                 goto do_free_irq;
 656         }
 657
 658         omap_i2c_disable_clocks(dev);
 659
 660         return 0;
 661
 662 do_free_irq:
 663         free_irq(dev->irq, dev);
 664 do_unuse_clocks:
 665         omap_i2c_disable_clocks(dev);
 666         omap_i2c_put_clocks(dev);
 667 do_free_mem:
 668         kfree(dev);
 669 do_release_region:
 670         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 671         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 672
 673         return r;
 674 }
 675
 676 static int
 677 omap_i2c_remove(struct platform_device *pdev)
 678 {
 679         struct omap_i2c_dev     *dev = platform_get_drvdata(pdev);
 680         struct resource         *mem;
 681
 682         free_irq(dev->irq, dev);
 683         i2c_del_adapter(&dev->adapter);
 684         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 685         omap_i2c_put_clocks(dev);
 686         kfree(dev);
 687         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 688         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 689         return 0;
 690 }
 691
 692 static struct platform_driver omap_i2c_driver = {
 693         .probe          = omap_i2c_probe,
 694         .remove         = omap_i2c_remove,
 695         .driver         = {
 696                 .name   = (char *)driver_name,
 697         },
 698 };
 699
 700 /* I2C may be needed to bring up other drivers */
 701 static int __init
 702 omap_i2c_init_driver(void)
 703 {
 704         return platform_driver_register(&omap_i2c_driver);
 705 }
 706 subsys_initcall(omap_i2c_init_driver);
 707
 708 static void __exit omap_i2c_exit_driver(void)
 709 {
 710         platform_driver_unregister(&omap_i2c_driver);
 711 }
 712 module_exit(omap_i2c_exit_driver);
 713
 714 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
 715 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
 716 MODULE_LICENSE("GPL");