drivers/i2c/busses/i2c-omap.c

   1 /*
   2  * TI OMAP I2C master mode driver
   3  *
   4  * Copyright (C) 2003 MontaVista Software, Inc.
   5  * Copyright (C) 2005 Nokia Corporation
   6  * Copyright (C) 2004 - 2007 Texas Instruments.
   7  *
   8  * Originally written by MontaVista Software, Inc.
   9  * Additional contributions by:
  10  *      Tony Lindgren <tony@atomide.com>
  11  *      Imre Deak <imre.deak@nokia.com>
  12  *      Juha Yrjölä <juha.yrjola@solidboot.com>
  13  *      Syed Khasim <x0khasim@ti.com>
  14  *      Nishant Menon <nm@ti.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 2 of the License, or
  19  * (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  29  */
  30
  31 #include <linux/module.h>
  32 #include <linux/delay.h>
  33 #include <linux/i2c.h>
  34 #include <linux/err.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/completion.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/clk.h>
  39 #include <linux/io.h>
  40
  41 /* I2C controller revisions */
  42 #define OMAP_I2C_REV_2                  0x20
  43
  44 /* I2C controller revisions present on specific hardware */
  45 #define OMAP_I2C_REV_ON_2430            0x36
  46 #define OMAP_I2C_REV_ON_3430            0x3C
  47
  48 /* timeout waiting for the controller to respond */
  49 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
  50
  51 #define OMAP_I2C_REV_REG                0x00
  52 #define OMAP_I2C_IE_REG                 0x04
  53 #define OMAP_I2C_STAT_REG               0x08
  54 #define OMAP_I2C_IV_REG                 0x0c
  55 #define OMAP_I2C_SYSS_REG               0x10
  56 #define OMAP_I2C_BUF_REG                0x14
  57 #define OMAP_I2C_CNT_REG                0x18
  58 #define OMAP_I2C_DATA_REG               0x1c
  59 #define OMAP_I2C_SYSC_REG               0x20
  60 #define OMAP_I2C_CON_REG                0x24
  61 #define OMAP_I2C_OA_REG                 0x28
  62 #define OMAP_I2C_SA_REG                 0x2c
  63 #define OMAP_I2C_PSC_REG                0x30
  64 #define OMAP_I2C_SCLL_REG               0x34
  65 #define OMAP_I2C_SCLH_REG               0x38
  66 #define OMAP_I2C_SYSTEST_REG            0x3c
  67 #define OMAP_I2C_BUFSTAT_REG            0x40
  68
  69 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
  70 #define OMAP_I2C_IE_XDR         (1 << 14)       /* TX Buffer drain int enable */
  71 #define OMAP_I2C_IE_RDR         (1 << 13)       /* RX Buffer drain int enable */
  72 #define OMAP_I2C_IE_XRDY        (1 << 4)        /* TX data ready int enable */
  73 #define OMAP_I2C_IE_RRDY        (1 << 3)        /* RX data ready int enable */
  74 #define OMAP_I2C_IE_ARDY        (1 << 2)        /* Access ready int enable */
  75 #define OMAP_I2C_IE_NACK        (1 << 1)        /* No ack interrupt enable */
  76 #define OMAP_I2C_IE_AL          (1 << 0)        /* Arbitration lost int ena */
  77
  78 /* I2C Status Register (OMAP_I2C_STAT): */
  79 #define OMAP_I2C_STAT_XDR       (1 << 14)       /* TX Buffer draining */
  80 #define OMAP_I2C_STAT_RDR       (1 << 13)       /* RX Buffer draining */
  81 #define OMAP_I2C_STAT_BB        (1 << 12)       /* Bus busy */
  82 #define OMAP_I2C_STAT_ROVR      (1 << 11)       /* Receive overrun */
  83 #define OMAP_I2C_STAT_XUDF      (1 << 10)       /* Transmit underflow */
  84 #define OMAP_I2C_STAT_AAS       (1 << 9)        /* Address as slave */
  85 #define OMAP_I2C_STAT_AD0       (1 << 8)        /* Address zero */
  86 #define OMAP_I2C_STAT_XRDY      (1 << 4)        /* Transmit data ready */
  87 #define OMAP_I2C_STAT_RRDY      (1 << 3)        /* Receive data ready */
  88 #define OMAP_I2C_STAT_ARDY      (1 << 2)        /* Register access ready */
  89 #define OMAP_I2C_STAT_NACK      (1 << 1)        /* No ack interrupt enable */
  90 #define OMAP_I2C_STAT_AL        (1 << 0)        /* Arbitration lost int ena */
  91
  92 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
  93 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)       /* RX DMA channel enable */
  94 #define OMAP_I2C_BUF_RXFIF_CLR  (1 << 14)       /* RX FIFO Clear */
  95 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)        /* TX DMA channel enable */
  96 #define OMAP_I2C_BUF_TXFIF_CLR  (1 << 6)        /* TX FIFO Clear */
  97
  98 /* I2C Configuration Register (OMAP_I2C_CON): */
  99 #define OMAP_I2C_CON_EN         (1 << 15)       /* I2C module enable */
 100 #define OMAP_I2C_CON_BE         (1 << 14)       /* Big endian mode */
 101 #define OMAP_I2C_CON_OPMODE_HS  (1 << 12)       /* High Speed support */
 102 #define OMAP_I2C_CON_STB        (1 << 11)       /* Start byte mode (master) */
 103 #define OMAP_I2C_CON_MST        (1 << 10)       /* Master/slave mode */
 104 #define OMAP_I2C_CON_TRX        (1 << 9)        /* TX/RX mode (master only) */
 105 #define OMAP_I2C_CON_XA         (1 << 8)        /* Expand address */
 106 #define OMAP_I2C_CON_RM         (1 << 2)        /* Repeat mode (master only) */
 107 #define OMAP_I2C_CON_STP        (1 << 1)        /* Stop cond (master only) */
 108 #define OMAP_I2C_CON_STT        (1 << 0)        /* Start condition (master) */
 109
 110 /* I2C SCL time value when Master */
 111 #define OMAP_I2C_SCLL_HSSCLL    8
 112 #define OMAP_I2C_SCLH_HSSCLH    8
 113
 114 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
 115 #ifdef DEBUG
 116 #define OMAP_I2C_SYSTEST_ST_EN          (1 << 15)       /* System test enable */
 117 #define OMAP_I2C_SYSTEST_FREE           (1 << 14)       /* Free running mode */
 118 #define OMAP_I2C_SYSTEST_TMODE_MASK     (3 << 12)       /* Test mode select */
 119 #define OMAP_I2C_SYSTEST_TMODE_SHIFT    (12)            /* Test mode select */
 120 #define OMAP_I2C_SYSTEST_SCL_I          (1 << 3)        /* SCL line sense in */
 121 #define OMAP_I2C_SYSTEST_SCL_O          (1 << 2)        /* SCL line drive out */
 122 #define OMAP_I2C_SYSTEST_SDA_I          (1 << 1)        /* SDA line sense in */
 123 #define OMAP_I2C_SYSTEST_SDA_O          (1 << 0)        /* SDA line drive out */
 124 #endif
 125
 126 /* I2C System Status register (OMAP_I2C_SYSS): */
 127 #define OMAP_I2C_SYSS_RDONE             (1 << 0)        /* Reset Done */
 128
 129 /* I2C System Configuration Register (OMAP_I2C_SYSC): */
 130 #define OMAP_I2C_SYSC_SRST              (1 << 1)        /* Soft Reset */
 131
 132 struct omap_i2c_dev {
 133         struct device           *dev;
 134         void __iomem            *base;          /* virtual */
 135         int                     irq;
 136         struct clk              *iclk;          /* Interface clock */
 137         struct clk              *fclk;          /* Functional clock */
 138         struct completion       cmd_complete;
 139         struct resource         *ioarea;
 140         u32                     speed;          /* Speed of bus in Khz */
 141         u16                     cmd_err;
 142         u8                      *buf;
 143         size_t                  buf_len;
 144         struct i2c_adapter      adapter;
 145         u8                      fifo_size;      /* use as flag and value
 146                                                  * fifo_size==0 implies no fifo
 147                                                  * if set, should be trsh+1
 148                                                  */
 149         u8                      rev;
 150         unsigned                b_hw:1;         /* bad h/w fixes */
 151         unsigned                idle:1;
 152         u16                     iestate;        /* Saved interrupt register */
 153 };
 154
 155 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
 156                                       int reg, u16 val)
 157 {
 158         __raw_writew(val, i2c_dev->base + reg);
 159 }
 160
 161 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
 162 {
 163         return __raw_readw(i2c_dev->base + reg);
 164 }
 165
 166 static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
 167 {
 168         if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
 169                 dev->iclk = clk_get(dev->dev, "i2c_ick");
 170                 if (IS_ERR(dev->iclk)) {
 171                         dev->iclk = NULL;
 172                         return -ENODEV;
 173                 }
 174         }
 175
 176         dev->fclk = clk_get(dev->dev, "i2c_fck");
 177         if (IS_ERR(dev->fclk)) {
 178                 if (dev->iclk != NULL) {
 179                         clk_put(dev->iclk);
 180                         dev->iclk = NULL;
 181                 }
 182                 dev->fclk = NULL;
 183                 return -ENODEV;
 184         }
 185
 186         return 0;
 187 }
 188
 189 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
 190 {
 191         clk_put(dev->fclk);
 192         dev->fclk = NULL;
 193         if (dev->iclk != NULL) {
 194                 clk_put(dev->iclk);
 195                 dev->iclk = NULL;
 196         }
 197 }
 198
 199 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
 200 {
 201         WARN_ON(!dev->idle);
 202
 203         if (dev->iclk != NULL)
 204                 clk_enable(dev->iclk);
 205         clk_enable(dev->fclk);
 206         dev->idle = 0;
 207         if (dev->iestate)
 208                 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
 209 }
 210
 211 static void omap_i2c_idle(struct omap_i2c_dev *dev)
 212 {
 213         u16 iv;
 214
 215         WARN_ON(dev->idle);
 216
 217         dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 218         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
 219         if (dev->rev < OMAP_I2C_REV_2) {
 220                 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
 221         } else {
 222                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
 223
 224                 /* Flush posted write before the dev->idle store occurs */
 225                 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 226         }
 227         dev->idle = 1;
 228         clk_disable(dev->fclk);
 229         if (dev->iclk != NULL)
 230                 clk_disable(dev->iclk);
 231 }
 232
 233 static int omap_i2c_init(struct omap_i2c_dev *dev)
 234 {
 235         u16 psc = 0, scll = 0, sclh = 0;
 236         u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
 237         unsigned long fclk_rate = 12000000;
 238         unsigned long timeout;
 239         unsigned long internal_clk = 0;
 240
 241         if (dev->rev >= OMAP_I2C_REV_2) {
 242                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
 243                 /* For some reason we need to set the EN bit before the
 244                  * reset done bit gets set. */
 245                 timeout = jiffies + OMAP_I2C_TIMEOUT;
 246                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 247                 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
 248                          OMAP_I2C_SYSS_RDONE)) {
 249                         if (time_after(jiffies, timeout)) {
 250                                 dev_warn(dev->dev, "timeout waiting "
 251                                                 "for controller reset\n");
 252                                 return -ETIMEDOUT;
 253                         }
 254                         msleep(1);
 255                 }
 256         }
 257         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 258
 259         if (cpu_class_is_omap1()) {
 260                 struct clk *armxor_ck;
 261
 262                 armxor_ck = clk_get(NULL, "armxor_ck");
 263                 if (IS_ERR(armxor_ck))
 264                         dev_warn(dev->dev, "Could not get armxor_ck\n");
 265                 else {
 266                         fclk_rate = clk_get_rate(armxor_ck);
 267                         clk_put(armxor_ck);
 268                 }
 269                 /* TRM for 5912 says the I2C clock must be prescaled to be
 270                  * between 7 - 12 MHz. The XOR input clock is typically
 271                  * 12, 13 or 19.2 MHz. So we should have code that produces:
 272                  *
 273                  * XOR MHz      Divider         Prescaler
 274                  * 12           1               0
 275                  * 13           2               1
 276                  * 19.2         2               1
 277                  */
 278                 if (fclk_rate > 12000000)
 279                         psc = fclk_rate / 12000000;
 280         }
 281
 282         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 283
 284                 /* HSI2C controller internal clk rate should be 19.2 Mhz */
 285                 internal_clk = 19200;
 286                 fclk_rate = clk_get_rate(dev->fclk) / 1000;
 287
 288                 /* Compute prescaler divisor */
 289                 psc = fclk_rate / internal_clk;
 290                 psc = psc - 1;
 291
 292                 /* If configured for High Speed */
 293                 if (dev->speed > 400) {
 294                         /* For first phase of HS mode */
 295                         fsscll = internal_clk / (400 * 2) - 6;
 296                         fssclh = internal_clk / (400 * 2) - 6;
 297
 298                         /* For second phase of HS mode */
 299                         hsscll = fclk_rate / (dev->speed * 2) - 6;
 300                         hssclh = fclk_rate / (dev->speed * 2) - 6;
 301                 } else {
 302                         /* To handle F/S modes */
 303                         fsscll = internal_clk / (dev->speed * 2) - 6;
 304                         fssclh = internal_clk / (dev->speed * 2) - 6;
 305                 }
 306                 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
 307                 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
 308         } else {
 309                 /* Program desired operating rate */
 310                 fclk_rate /= (psc + 1) * 1000;
 311                 if (psc > 2)
 312                         psc = 2;
 313                 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
 314                 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
 315         }
 316
 317         /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
 318         omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
 319
 320         /* SCL low and high time values */
 321         omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
 322         omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
 323
 324         if (dev->fifo_size)
 325                 /* Note: setup required fifo size - 1 */
 326                 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
 327                                         (dev->fifo_size - 1) << 8 | /* RTRSH */
 328                                         OMAP_I2C_BUF_RXFIF_CLR |
 329                                         (dev->fifo_size - 1) | /* XTRSH */
 330                                         OMAP_I2C_BUF_TXFIF_CLR);
 331
 332         /* Take the I2C module out of reset: */
 333         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 334
 335         /* Enable interrupts */
 336         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
 337                         (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
 338                         OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
 339                         OMAP_I2C_IE_AL)  | ((dev->fifo_size) ?
 340                                 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
 341         return 0;
 342 }
 343
 344 /*
 345  * Waiting on Bus Busy
 346  */
 347 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
 348 {
 349         unsigned long timeout;
 350
 351         timeout = jiffies + OMAP_I2C_TIMEOUT;
 352         while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
 353                 if (time_after(jiffies, timeout)) {
 354                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 355                         return -ETIMEDOUT;
 356                 }
 357                 msleep(1);
 358         }
 359
 360         return 0;
 361 }
 362
 363 /*
 364  * Low level master read/write transaction.
 365  */
 366 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 367                              struct i2c_msg *msg, int stop)
 368 {
 369         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 370         int r;
 371         u16 w;
 372
 373         dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 374                 msg->addr, msg->len, msg->flags, stop);
 375
 376         if (msg->len == 0)
 377                 return -EINVAL;
 378
 379         omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
 380
 381         /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
 382         dev->buf = msg->buf;
 383         dev->buf_len = msg->len;
 384
 385         omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
 386
 387         /* Clear the FIFO Buffers */
 388         w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
 389         w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
 390         omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
 391
 392         init_completion(&dev->cmd_complete);
 393         dev->cmd_err = 0;
 394
 395         w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 396
 397         /* High speed configuration */
 398         if (dev->speed > 400)
 399                 w |= OMAP_I2C_CON_OPMODE_HS;
 400
 401         if (msg->flags & I2C_M_TEN)
 402                 w |= OMAP_I2C_CON_XA;
 403         if (!(msg->flags & I2C_M_RD))
 404                 w |= OMAP_I2C_CON_TRX;
 405
 406         if (!dev->b_hw && stop)
 407                 w |= OMAP_I2C_CON_STP;
 408
 409         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 410
 411         /*
 412          * Don't write stt and stp together on some hardware.
 413          */
 414         if (dev->b_hw && stop) {
 415                 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
 416                 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 417                 while (con & OMAP_I2C_CON_STT) {
 418                         con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 419
 420                         /* Let the user know if i2c is in a bad state */
 421                         if (time_after(jiffies, delay)) {
 422                                 dev_err(dev->dev, "controller timed out "
 423                                 "waiting for start condition to finish\n");
 424                                 return -ETIMEDOUT;
 425                         }
 426                         cpu_relax();
 427                 }
 428
 429                 w |= OMAP_I2C_CON_STP;
 430                 w &= ~OMAP_I2C_CON_STT;
 431                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 432         }
 433
 434         /*
 435          * REVISIT: We should abort the transfer on signals, but the bus goes
 436          * into arbitration and we're currently unable to recover from it.
 437          */
 438         r = wait_for_completion_timeout(&dev->cmd_complete,
 439                                         OMAP_I2C_TIMEOUT);
 440         dev->buf_len = 0;
 441         if (r < 0)
 442                 return r;
 443         if (r == 0) {
 444                 dev_err(dev->dev, "controller timed out\n");
 445                 omap_i2c_init(dev);
 446                 return -ETIMEDOUT;
 447         }
 448
 449         if (likely(!dev->cmd_err))
 450                 return 0;
 451
 452         /* We have an error */
 453         if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
 454                             OMAP_I2C_STAT_XUDF)) {
 455                 omap_i2c_init(dev);
 456                 return -EIO;
 457         }
 458
 459         if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
 460                 if (msg->flags & I2C_M_IGNORE_NAK)
 461                         return 0;
 462                 if (stop) {
 463                         w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 464                         w |= OMAP_I2C_CON_STP;
 465                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 466                 }
 467                 return -EREMOTEIO;
 468         }
 469         return -EIO;
 470 }
 471
 472
 473 /*
 474  * Prepare controller for a transaction and call omap_i2c_xfer_msg
 475  * to do the work during IRQ processing.
 476  */
 477 static int
 478 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 479 {
 480         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 481         int i;
 482         int r;
 483
 484         omap_i2c_unidle(dev);
 485
 486         r = omap_i2c_wait_for_bb(dev);
 487         if (r < 0)
 488                 goto out;
 489
 490         for (i = 0; i < num; i++) {
 491                 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 492                 if (r != 0)
 493                         break;
 494         }
 495
 496         if (r == 0)
 497                 r = num;
 498 out:
 499         omap_i2c_idle(dev);
 500         return r;
 501 }
 502
 503 static u32
 504 omap_i2c_func(struct i2c_adapter *adap)
 505 {
 506         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 507 }
 508
 509 static inline void
 510 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
 511 {
 512         dev->cmd_err |= err;
 513         complete(&dev->cmd_complete);
 514 }
 515
 516 static inline void
 517 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
 518 {
 519         omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 520 }
 521
 522 /* rev1 devices are apparently only on some 15xx */
 523 #ifdef CONFIG_ARCH_OMAP15XX
 524
 525 static irqreturn_t
 526 omap_i2c_rev1_isr(int this_irq, void *dev_id)
 527 {
 528         struct omap_i2c_dev *dev = dev_id;
 529         u16 iv, w;
 530
 531         if (dev->idle)
 532                 return IRQ_NONE;
 533
 534         iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
 535         switch (iv) {
 536         case 0x00:      /* None */
 537                 break;
 538         case 0x01:      /* Arbitration lost */
 539                 dev_err(dev->dev, "Arbitration lost\n");
 540                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
 541                 break;
 542         case 0x02:      /* No acknowledgement */
 543                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
 544                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
 545                 break;
 546         case 0x03:      /* Register access ready */
 547                 omap_i2c_complete_cmd(dev, 0);
 548                 break;
 549         case 0x04:      /* Receive data ready */
 550                 if (dev->buf_len) {
 551                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 552                         *dev->buf++ = w;
 553                         dev->buf_len--;
 554                         if (dev->buf_len) {
 555                                 *dev->buf++ = w >> 8;
 556                                 dev->buf_len--;
 557                         }
 558                 } else
 559                         dev_err(dev->dev, "RRDY IRQ while no data requested\n");
 560                 break;
 561         case 0x05:      /* Transmit data ready */
 562                 if (dev->buf_len) {
 563                         w = *dev->buf++;
 564                         dev->buf_len--;
 565                         if (dev->buf_len) {
 566                                 w |= *dev->buf++ << 8;
 567                                 dev->buf_len--;
 568                         }
 569                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 570                 } else
 571                         dev_err(dev->dev, "XRDY IRQ while no data to send\n");
 572                 break;
 573         default:
 574                 return IRQ_NONE;
 575         }
 576
 577         return IRQ_HANDLED;
 578 }
 579 #else
 580 #define omap_i2c_rev1_isr               NULL
 581 #endif
 582
 583 static irqreturn_t
 584 omap_i2c_isr(int this_irq, void *dev_id)
 585 {
 586         struct omap_i2c_dev *dev = dev_id;
 587         u16 bits;
 588         u16 stat, w;
 589         int err, count = 0;
 590
 591         if (dev->idle)
 592                 return IRQ_NONE;
 593
 594         bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 595         while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
 596                 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 597                 if (count++ == 100) {
 598                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 599                         break;
 600                 }
 601
 602                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 603
 604                 err = 0;
 605                 if (stat & OMAP_I2C_STAT_NACK) {
 606                         err |= OMAP_I2C_STAT_NACK;
 607                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
 608                                            OMAP_I2C_CON_STP);
 609                 }
 610                 if (stat & OMAP_I2C_STAT_AL) {
 611                         dev_err(dev->dev, "Arbitration lost\n");
 612                         err |= OMAP_I2C_STAT_AL;
 613                 }
 614                 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
 615                                         OMAP_I2C_STAT_AL))
 616                         omap_i2c_complete_cmd(dev, err);
 617                 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
 618                         u8 num_bytes = 1;
 619                         if (dev->fifo_size) {
 620                                 if (stat & OMAP_I2C_STAT_RRDY)
 621                                         num_bytes = dev->fifo_size;
 622                                 else
 623                                         num_bytes = omap_i2c_read_reg(dev,
 624                                                         OMAP_I2C_BUFSTAT_REG);
 625                         }
 626                         while (num_bytes) {
 627                                 num_bytes--;
 628                                 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 629                                 if (dev->buf_len) {
 630                                         *dev->buf++ = w;
 631                                         dev->buf_len--;
 632                                         /* Data reg from 2430 is 8 bit wide */
 633                                         if (!cpu_is_omap2430() &&
 634                                                         !cpu_is_omap34xx()) {
 635                                                 if (dev->buf_len) {
 636                                                         *dev->buf++ = w >> 8;
 637                                                         dev->buf_len--;
 638                                                 }
 639                                         }
 640                                 } else {
 641                                         if (stat & OMAP_I2C_STAT_RRDY)
 642                                                 dev_err(dev->dev,
 643                                                         "RRDY IRQ while no data"
 644                                                                 " requested\n");
 645                                         if (stat & OMAP_I2C_STAT_RDR)
 646                                                 dev_err(dev->dev,
 647                                                         "RDR IRQ while no data"
 648                                                                 " requested\n");
 649                                         break;
 650                                 }
 651                         }
 652                         omap_i2c_ack_stat(dev,
 653                                 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
 654                         continue;
 655                 }
 656                 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
 657                         u8 num_bytes = 1;
 658                         if (dev->fifo_size) {
 659                                 if (stat & OMAP_I2C_STAT_XRDY)
 660                                         num_bytes = dev->fifo_size;
 661                                 else
 662                                         num_bytes = omap_i2c_read_reg(dev,
 663                                                         OMAP_I2C_BUFSTAT_REG);
 664                         }
 665                         while (num_bytes) {
 666                                 num_bytes--;
 667                                 w = 0;
 668                                 if (dev->buf_len) {
 669                                         w = *dev->buf++;
 670                                         dev->buf_len--;
 671                                         /* Data reg from  2430 is 8 bit wide */
 672                                         if (!cpu_is_omap2430() &&
 673                                                         !cpu_is_omap34xx()) {
 674                                                 if (dev->buf_len) {
 675                                                         w |= *dev->buf++ << 8;
 676                                                         dev->buf_len--;
 677                                                 }
 678                                         }
 679                                 } else {
 680                                         if (stat & OMAP_I2C_STAT_XRDY)
 681                                                 dev_err(dev->dev,
 682                                                         "XRDY IRQ while no "
 683                                                         "data to send\n");
 684                                         if (stat & OMAP_I2C_STAT_XDR)
 685                                                 dev_err(dev->dev,
 686                                                         "XDR IRQ while no "
 687                                                         "data to send\n");
 688                                         break;
 689                                 }
 690                                 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 691                         }
 692                         omap_i2c_ack_stat(dev,
 693                                 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
 694                         continue;
 695                 }
 696                 if (stat & OMAP_I2C_STAT_ROVR) {
 697                         dev_err(dev->dev, "Receive overrun\n");
 698                         dev->cmd_err |= OMAP_I2C_STAT_ROVR;
 699                 }
 700                 if (stat & OMAP_I2C_STAT_XUDF) {
 701                         dev_err(dev->dev, "Transmit underflow\n");
 702                         dev->cmd_err |= OMAP_I2C_STAT_XUDF;
 703                 }
 704         }
 705
 706         return count ? IRQ_HANDLED : IRQ_NONE;
 707 }
 708
 709 static const struct i2c_algorithm omap_i2c_algo = {
 710         .master_xfer    = omap_i2c_xfer,
 711         .functionality  = omap_i2c_func,
 712 };
 713
 714 static int __init
 715 omap_i2c_probe(struct platform_device *pdev)
 716 {
 717         struct omap_i2c_dev     *dev;
 718         struct i2c_adapter      *adap;
 719         struct resource         *mem, *irq, *ioarea;
 720         void *isr;
 721         int r;
 722         u32 speed = 0;
 723
 724         /* NOTE: driver uses the static register mapping */
 725         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 726         if (!mem) {
 727                 dev_err(&pdev->dev, "no mem resource?\n");
 728                 return -ENODEV;
 729         }
 730         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 731         if (!irq) {
 732                 dev_err(&pdev->dev, "no irq resource?\n");
 733                 return -ENODEV;
 734         }
 735
 736         ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
 737                         pdev->name);
 738         if (!ioarea) {
 739                 dev_err(&pdev->dev, "I2C region already claimed\n");
 740                 return -EBUSY;
 741         }
 742
 743         dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
 744         if (!dev) {
 745                 r = -ENOMEM;
 746                 goto err_release_region;
 747         }
 748
 749         if (pdev->dev.platform_data != NULL)
 750                 speed = *(u32 *)pdev->dev.platform_data;
 751         else
 752                 speed = 100;    /* Defualt speed */
 753
 754         dev->speed = speed;
 755         dev->idle = 1;
 756         dev->dev = &pdev->dev;
 757         dev->irq = irq->start;
 758         dev->base = ioremap(mem->start, mem->end - mem->start + 1);
 759         if (!dev->base) {
 760                 r = -ENOMEM;
 761                 goto err_free_mem;
 762         }
 763
 764         platform_set_drvdata(pdev, dev);
 765
 766         if ((r = omap_i2c_get_clocks(dev)) != 0)
 767                 goto err_iounmap;
 768
 769         omap_i2c_unidle(dev);
 770
 771         dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
 772
 773         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 774                 u16 s;
 775
 776                 /* Set up the fifo size - Get total size */
 777                 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
 778                 dev->fifo_size = 0x8 << s;
 779
 780                 /*
 781                  * Set up notification threshold as half the total available
 782                  * size. This is to ensure that we can handle the status on int
 783                  * call back latencies.
 784                  */
 785                 dev->fifo_size = (dev->fifo_size / 2);
 786                 dev->b_hw = 1; /* Enable hardware fixes */
 787         }
 788
 789         /* reset ASAP, clearing any IRQs */
 790         omap_i2c_init(dev);
 791
 792         isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr;
 793         r = request_irq(dev->irq, isr, 0, pdev->name, dev);
 794
 795         if (r) {
 796                 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
 797                 goto err_unuse_clocks;
 798         }
 799
 800         dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
 801                  pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
 802
 803         omap_i2c_idle(dev);
 804
 805         adap = &dev->adapter;
 806         i2c_set_adapdata(adap, dev);
 807         adap->owner = THIS_MODULE;
 808         adap->class = I2C_CLASS_HWMON;
 809         strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
 810         adap->algo = &omap_i2c_algo;
 811         adap->dev.parent = &pdev->dev;
 812
 813         /* i2c device drivers may be active on return from add_adapter() */
 814         adap->nr = pdev->id;
 815         r = i2c_add_numbered_adapter(adap);
 816         if (r) {
 817                 dev_err(dev->dev, "failure adding adapter\n");
 818                 goto err_free_irq;
 819         }
 820
 821         return 0;
 822
 823 err_free_irq:
 824         free_irq(dev->irq, dev);
 825 err_unuse_clocks:
 826         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 827         omap_i2c_idle(dev);
 828         omap_i2c_put_clocks(dev);
 829 err_iounmap:
 830         iounmap(dev->base);
 831 err_free_mem:
 832         platform_set_drvdata(pdev, NULL);
 833         kfree(dev);
 834 err_release_region:
 835         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 836
 837         return r;
 838 }
 839
 840 static int
 841 omap_i2c_remove(struct platform_device *pdev)
 842 {
 843         struct omap_i2c_dev     *dev = platform_get_drvdata(pdev);
 844         struct resource         *mem;
 845
 846         platform_set_drvdata(pdev, NULL);
 847
 848         free_irq(dev->irq, dev);
 849         i2c_del_adapter(&dev->adapter);
 850         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 851         omap_i2c_put_clocks(dev);
 852         iounmap(dev->base);
 853         kfree(dev);
 854         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 855         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 856         return 0;
 857 }
 858
 859 static struct platform_driver omap_i2c_driver = {
 860         .probe          = omap_i2c_probe,
 861         .remove         = omap_i2c_remove,
 862         .driver         = {
 863                 .name   = "i2c_omap",
 864                 .owner  = THIS_MODULE,
 865         },
 866 };
 867
 868 /* I2C may be needed to bring up other drivers */
 869 static int __init
 870 omap_i2c_init_driver(void)
 871 {
 872         return platform_driver_register(&omap_i2c_driver);
 873 }
 874 subsys_initcall(omap_i2c_init_driver);
 875
 876 static void __exit omap_i2c_exit_driver(void)
 877 {
 878         platform_driver_unregister(&omap_i2c_driver);
 879 }
 880 module_exit(omap_i2c_exit_driver);
 881
 882 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
 883 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
 884 MODULE_LICENSE("GPL");
 885 MODULE_ALIAS("platform:i2c_omap");