drivers/i2c/busses/i2c-omap.c

   1 /*
   2  * TI OMAP I2C master mode driver
   3  *
   4  * Copyright (C) 2003 MontaVista Software, Inc.
   5  * Copyright (C) 2005 Nokia Corporation
   6  * Copyright (C) 2004 - 2007 Texas Instruments.
   7  *
   8  * Originally written by MontaVista Software, Inc.
   9  * Additional contributions by:
  10  *      Tony Lindgren <tony@atomide.com>
  11  *      Imre Deak <imre.deak@nokia.com>
  12  *      Juha Yrjölä <juha.yrjola@solidboot.com>
  13  *      Syed Khasim <x0khasim@ti.com>
  14  *      Nishant Menon <nm@ti.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 2 of the License, or
  19  * (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  29  */
  30
  31 #include <linux/module.h>
  32 #include <linux/delay.h>
  33 #include <linux/i2c.h>
  34 #include <linux/err.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/completion.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/clk.h>
  39 #include <linux/io.h>
  40
  41 /* timeout waiting for the controller to respond */
  42 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
  43
  44 #define OMAP_I2C_REV_REG                0x00
  45 #define OMAP_I2C_IE_REG                 0x04
  46 #define OMAP_I2C_STAT_REG               0x08
  47 #define OMAP_I2C_IV_REG                 0x0c
  48 #define OMAP_I2C_SYSS_REG               0x10
  49 #define OMAP_I2C_BUF_REG                0x14
  50 #define OMAP_I2C_CNT_REG                0x18
  51 #define OMAP_I2C_DATA_REG               0x1c
  52 #define OMAP_I2C_SYSC_REG               0x20
  53 #define OMAP_I2C_CON_REG                0x24
  54 #define OMAP_I2C_OA_REG                 0x28
  55 #define OMAP_I2C_SA_REG                 0x2c
  56 #define OMAP_I2C_PSC_REG                0x30
  57 #define OMAP_I2C_SCLL_REG               0x34
  58 #define OMAP_I2C_SCLH_REG               0x38
  59 #define OMAP_I2C_SYSTEST_REG            0x3c
  60 #define OMAP_I2C_BUFSTAT_REG            0x40
  61
  62 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
  63 #define OMAP_I2C_IE_XDR         (1 << 14)       /* TX Buffer drain int enable */
  64 #define OMAP_I2C_IE_RDR         (1 << 13)       /* RX Buffer drain int enable */
  65 #define OMAP_I2C_IE_XRDY        (1 << 4)        /* TX data ready int enable */
  66 #define OMAP_I2C_IE_RRDY        (1 << 3)        /* RX data ready int enable */
  67 #define OMAP_I2C_IE_ARDY        (1 << 2)        /* Access ready int enable */
  68 #define OMAP_I2C_IE_NACK        (1 << 1)        /* No ack interrupt enable */
  69 #define OMAP_I2C_IE_AL          (1 << 0)        /* Arbitration lost int ena */
  70
  71 /* I2C Status Register (OMAP_I2C_STAT): */
  72 #define OMAP_I2C_STAT_XDR       (1 << 14)       /* TX Buffer draining */
  73 #define OMAP_I2C_STAT_RDR       (1 << 13)       /* RX Buffer draining */
  74 #define OMAP_I2C_STAT_BB        (1 << 12)       /* Bus busy */
  75 #define OMAP_I2C_STAT_ROVR      (1 << 11)       /* Receive overrun */
  76 #define OMAP_I2C_STAT_XUDF      (1 << 10)       /* Transmit underflow */
  77 #define OMAP_I2C_STAT_AAS       (1 << 9)        /* Address as slave */
  78 #define OMAP_I2C_STAT_AD0       (1 << 8)        /* Address zero */
  79 #define OMAP_I2C_STAT_XRDY      (1 << 4)        /* Transmit data ready */
  80 #define OMAP_I2C_STAT_RRDY      (1 << 3)        /* Receive data ready */
  81 #define OMAP_I2C_STAT_ARDY      (1 << 2)        /* Register access ready */
  82 #define OMAP_I2C_STAT_NACK      (1 << 1)        /* No ack interrupt enable */
  83 #define OMAP_I2C_STAT_AL        (1 << 0)        /* Arbitration lost int ena */
  84
  85 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
  86 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)       /* RX DMA channel enable */
  87 #define OMAP_I2C_BUF_RXFIF_CLR  (1 << 14)       /* RX FIFO Clear */
  88 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)        /* TX DMA channel enable */
  89 #define OMAP_I2C_BUF_TXFIF_CLR  (1 << 6)        /* TX FIFO Clear */
  90
  91 /* I2C Configuration Register (OMAP_I2C_CON): */
  92 #define OMAP_I2C_CON_EN         (1 << 15)       /* I2C module enable */
  93 #define OMAP_I2C_CON_BE         (1 << 14)       /* Big endian mode */
  94 #define OMAP_I2C_CON_OPMODE_HS  (1 << 12)       /* High Speed support */
  95 #define OMAP_I2C_CON_STB        (1 << 11)       /* Start byte mode (master) */
  96 #define OMAP_I2C_CON_MST        (1 << 10)       /* Master/slave mode */
  97 #define OMAP_I2C_CON_TRX        (1 << 9)        /* TX/RX mode (master only) */
  98 #define OMAP_I2C_CON_XA         (1 << 8)        /* Expand address */
  99 #define OMAP_I2C_CON_RM         (1 << 2)        /* Repeat mode (master only) */
 100 #define OMAP_I2C_CON_STP        (1 << 1)        /* Stop cond (master only) */
 101 #define OMAP_I2C_CON_STT        (1 << 0)        /* Start condition (master) */
 102
 103 /* I2C SCL time value when Master */
 104 #define OMAP_I2C_SCLL_HSSCLL    8
 105 #define OMAP_I2C_SCLH_HSSCLH    8
 106
 107 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
 108 #ifdef DEBUG
 109 #define OMAP_I2C_SYSTEST_ST_EN          (1 << 15)       /* System test enable */
 110 #define OMAP_I2C_SYSTEST_FREE           (1 << 14)       /* Free running mode */
 111 #define OMAP_I2C_SYSTEST_TMODE_MASK     (3 << 12)       /* Test mode select */
 112 #define OMAP_I2C_SYSTEST_TMODE_SHIFT    (12)            /* Test mode select */
 113 #define OMAP_I2C_SYSTEST_SCL_I          (1 << 3)        /* SCL line sense in */
 114 #define OMAP_I2C_SYSTEST_SCL_O          (1 << 2)        /* SCL line drive out */
 115 #define OMAP_I2C_SYSTEST_SDA_I          (1 << 1)        /* SDA line sense in */
 116 #define OMAP_I2C_SYSTEST_SDA_O          (1 << 0)        /* SDA line drive out */
 117 #endif
 118
 119 /* I2C System Status register (OMAP_I2C_SYSS): */
 120 #define OMAP_I2C_SYSS_RDONE             (1 << 0)        /* Reset Done */
 121
 122 /* I2C System Configuration Register (OMAP_I2C_SYSC): */
 123 #define OMAP_I2C_SYSC_SRST              (1 << 1)        /* Soft Reset */
 124
 125 struct omap_i2c_dev {
 126         struct device           *dev;
 127         void __iomem            *base;          /* virtual */
 128         int                     irq;
 129         struct clk              *iclk;          /* Interface clock */
 130         struct clk              *fclk;          /* Functional clock */
 131         struct completion       cmd_complete;
 132         struct resource         *ioarea;
 133         u32                     speed;          /* Speed of bus in Khz */
 134         u16                     cmd_err;
 135         u8                      *buf;
 136         size_t                  buf_len;
 137         struct i2c_adapter      adapter;
 138         u8                      fifo_size;      /* use as flag and value
 139                                                  * fifo_size==0 implies no fifo
 140                                                  * if set, should be trsh+1
 141                                                  */
 142         unsigned                rev1:1;
 143         unsigned                b_hw:1;         /* bad h/w fixes */
 144         unsigned                idle:1;
 145         u16                     iestate;        /* Saved interrupt register */
 146 };
 147
 148 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
 149                                       int reg, u16 val)
 150 {
 151         __raw_writew(val, i2c_dev->base + reg);
 152 }
 153
 154 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
 155 {
 156         return __raw_readw(i2c_dev->base + reg);
 157 }
 158
 159 static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
 160 {
 161         if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
 162                 dev->iclk = clk_get(dev->dev, "i2c_ick");
 163                 if (IS_ERR(dev->iclk)) {
 164                         dev->iclk = NULL;
 165                         return -ENODEV;
 166                 }
 167         }
 168         /* For I2C operations on 2430 we need 96Mhz clock */
 169         if (cpu_is_omap2430()) {
 170                 dev->fclk = clk_get(dev->dev, "i2chs_fck");
 171                 if (IS_ERR(dev->fclk)) {
 172                         if (dev->iclk != NULL) {
 173                                 clk_put(dev->iclk);
 174                                 dev->iclk = NULL;
 175                         }
 176                         dev->fclk = NULL;
 177                         return -ENODEV;
 178                 }
 179         } else {
 180                 dev->fclk = clk_get(dev->dev, "i2c_fck");
 181                 if (IS_ERR(dev->fclk)) {
 182                         if (dev->iclk != NULL) {
 183                                 clk_put(dev->iclk);
 184                                 dev->iclk = NULL;
 185                         }
 186                         dev->fclk = NULL;
 187                         return -ENODEV;
 188                 }
 189         }
 190         return 0;
 191 }
 192
 193 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
 194 {
 195         clk_put(dev->fclk);
 196         dev->fclk = NULL;
 197         if (dev->iclk != NULL) {
 198                 clk_put(dev->iclk);
 199                 dev->iclk = NULL;
 200         }
 201 }
 202
 203 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
 204 {
 205         if (dev->iclk != NULL)
 206                 clk_enable(dev->iclk);
 207         clk_enable(dev->fclk);
 208         dev->idle = 0;
 209         if (dev->iestate)
 210                 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
 211 }
 212
 213 static void omap_i2c_idle(struct omap_i2c_dev *dev)
 214 {
 215         u16 iv;
 216
 217         dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 218         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
 219         if (dev->rev1)
 220                 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
 221         else
 222                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
 223         /*
 224          * The wmb() is to ensure that the I2C interrupt mask write
 225          * reaches the I2C controller before the dev->idle store
 226          * occurs.
 227          */
 228         wmb();
 229         dev->idle = 1;
 230         clk_disable(dev->fclk);
 231         if (dev->iclk != NULL)
 232                 clk_disable(dev->iclk);
 233 }
 234
 235 static int omap_i2c_init(struct omap_i2c_dev *dev)
 236 {
 237         u16 psc = 0, scll = 0, sclh = 0;
 238         u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
 239         unsigned long fclk_rate = 12000000;
 240         unsigned long timeout;
 241         unsigned long internal_clk = 0;
 242
 243         if (!dev->rev1) {
 244                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
 245                 /* For some reason we need to set the EN bit before the
 246                  * reset done bit gets set. */
 247                 timeout = jiffies + OMAP_I2C_TIMEOUT;
 248                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 249                 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
 250                          OMAP_I2C_SYSS_RDONE)) {
 251                         if (time_after(jiffies, timeout)) {
 252                                 dev_warn(dev->dev, "timeout waiting "
 253                                                 "for controller reset\n");
 254                                 return -ETIMEDOUT;
 255                         }
 256                         msleep(1);
 257                 }
 258         }
 259         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 260
 261         if (cpu_class_is_omap1()) {
 262                 struct clk *armxor_ck;
 263
 264                 armxor_ck = clk_get(NULL, "armxor_ck");
 265                 if (IS_ERR(armxor_ck))
 266                         dev_warn(dev->dev, "Could not get armxor_ck\n");
 267                 else {
 268                         fclk_rate = clk_get_rate(armxor_ck);
 269                         clk_put(armxor_ck);
 270                 }
 271                 /* TRM for 5912 says the I2C clock must be prescaled to be
 272                  * between 7 - 12 MHz. The XOR input clock is typically
 273                  * 12, 13 or 19.2 MHz. So we should have code that produces:
 274                  *
 275                  * XOR MHz      Divider         Prescaler
 276                  * 12           1               0
 277                  * 13           2               1
 278                  * 19.2         2               1
 279                  */
 280                 if (fclk_rate > 12000000)
 281                         psc = fclk_rate / 12000000;
 282         }
 283
 284         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 285
 286                 /* HSI2C controller internal clk rate should be 19.2 Mhz */
 287                 internal_clk = 19200;
 288                 fclk_rate = clk_get_rate(dev->fclk) / 1000;
 289
 290                 /* Compute prescaler divisor */
 291                 psc = fclk_rate / internal_clk;
 292                 psc = psc - 1;
 293
 294                 /* If configured for High Speed */
 295                 if (dev->speed > 400) {
 296                         /* For first phase of HS mode */
 297                         fsscll = internal_clk / (400 * 2) - 6;
 298                         fssclh = internal_clk / (400 * 2) - 6;
 299
 300                         /* For second phase of HS mode */
 301                         hsscll = fclk_rate / (dev->speed * 2) - 6;
 302                         hssclh = fclk_rate / (dev->speed * 2) - 6;
 303                 } else {
 304                         /* To handle F/S modes */
 305                         fsscll = internal_clk / (dev->speed * 2) - 6;
 306                         fssclh = internal_clk / (dev->speed * 2) - 6;
 307                 }
 308                 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
 309                 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
 310         } else {
 311                 /* Program desired operating rate */
 312                 fclk_rate /= (psc + 1) * 1000;
 313                 if (psc > 2)
 314                         psc = 2;
 315                 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
 316                 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
 317         }
 318
 319         /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
 320         omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
 321
 322         /* SCL low and high time values */
 323         omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
 324         omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
 325
 326         if (dev->fifo_size)
 327                 /* Note: setup required fifo size - 1 */
 328                 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
 329                                         (dev->fifo_size - 1) << 8 | /* RTRSH */
 330                                         OMAP_I2C_BUF_RXFIF_CLR |
 331                                         (dev->fifo_size - 1) | /* XTRSH */
 332                                         OMAP_I2C_BUF_TXFIF_CLR);
 333
 334         /* Take the I2C module out of reset: */
 335         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 336
 337         /* Enable interrupts */
 338         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
 339                         (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
 340                         OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
 341                         OMAP_I2C_IE_AL)  | ((dev->fifo_size) ?
 342                                 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
 343         return 0;
 344 }
 345
 346 /*
 347  * Waiting on Bus Busy
 348  */
 349 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
 350 {
 351         unsigned long timeout;
 352
 353         timeout = jiffies + OMAP_I2C_TIMEOUT;
 354         while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
 355                 if (time_after(jiffies, timeout)) {
 356                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 357                         return -ETIMEDOUT;
 358                 }
 359                 msleep(1);
 360         }
 361
 362         return 0;
 363 }
 364
 365 /*
 366  * Low level master read/write transaction.
 367  */
 368 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 369                              struct i2c_msg *msg, int stop)
 370 {
 371         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 372         int r;
 373         u16 w;
 374
 375         dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 376                 msg->addr, msg->len, msg->flags, stop);
 377
 378         if (msg->len == 0)
 379                 return -EINVAL;
 380
 381         omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
 382
 383         /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
 384         dev->buf = msg->buf;
 385         dev->buf_len = msg->len;
 386
 387         omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
 388
 389         /* Clear the FIFO Buffers */
 390         w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
 391         w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
 392         omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
 393
 394         init_completion(&dev->cmd_complete);
 395         dev->cmd_err = 0;
 396
 397         w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 398
 399         /* High speed configuration */
 400         if (dev->speed > 400)
 401                 w |= OMAP_I2C_CON_OPMODE_HS;
 402
 403         if (msg->flags & I2C_M_TEN)
 404                 w |= OMAP_I2C_CON_XA;
 405         if (!(msg->flags & I2C_M_RD))
 406                 w |= OMAP_I2C_CON_TRX;
 407
 408         if (!dev->b_hw && stop)
 409                 w |= OMAP_I2C_CON_STP;
 410
 411         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 412
 413         /*
 414          * Don't write stt and stp together on some hardware
 415          */
 416         if (dev->b_hw && stop) {
 417                 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
 418                 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 419                 while (con & OMAP_I2C_CON_STT) {
 420                         con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 421
 422                         /* Let the user know if i2c is in a bad state */
 423                         if (time_after(jiffies, delay)) {
 424                                 dev_err(dev->dev, "controller timed out "
 425                                 "waiting for start condition to finish\n");
 426                                 return -ETIMEDOUT;
 427                         }
 428                         cpu_relax();
 429                 }
 430
 431                 w |= OMAP_I2C_CON_STP;
 432                 w &= ~OMAP_I2C_CON_STT;
 433                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 434         }
 435         r = wait_for_completion_timeout(&dev->cmd_complete,
 436                                         OMAP_I2C_TIMEOUT);
 437         dev->buf_len = 0;
 438         if (r < 0)
 439                 return r;
 440         if (r == 0) {
 441                 dev_err(dev->dev, "controller timed out\n");
 442                 omap_i2c_init(dev);
 443                 return -ETIMEDOUT;
 444         }
 445
 446         if (likely(!dev->cmd_err))
 447                 return 0;
 448
 449         /* We have an error */
 450         if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
 451                             OMAP_I2C_STAT_XUDF)) {
 452                 omap_i2c_init(dev);
 453                 return -EIO;
 454         }
 455
 456         if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
 457                 if (msg->flags & I2C_M_IGNORE_NAK)
 458                         return 0;
 459                 if (stop) {
 460                         w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 461                         w |= OMAP_I2C_CON_STP;
 462                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 463                 }
 464                 return -EREMOTEIO;
 465         }
 466         return -EIO;
 467 }
 468
 469
 470 /*
 471  * Prepare controller for a transaction and call omap_i2c_xfer_msg
 472  * to do the work during IRQ processing.
 473  */
 474 static int
 475 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 476 {
 477         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 478         int i;
 479         int r;
 480
 481         omap_i2c_unidle(dev);
 482
 483         r = omap_i2c_wait_for_bb(dev);
 484         if (r < 0)
 485                 goto out;
 486
 487         for (i = 0; i < num; i++) {
 488                 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 489                 if (r != 0)
 490                         break;
 491         }
 492
 493         if (r == 0)
 494                 r = num;
 495 out:
 496         omap_i2c_idle(dev);
 497         return r;
 498 }
 499
 500 static u32
 501 omap_i2c_func(struct i2c_adapter *adap)
 502 {
 503         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 504 }
 505
 506 static inline void
 507 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
 508 {
 509         dev->cmd_err |= err;
 510         complete(&dev->cmd_complete);
 511 }
 512
 513 static inline void
 514 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
 515 {
 516         omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 517 }
 518
 519 /* rev1 devices are apparently only on some 15xx */
 520 #ifdef CONFIG_ARCH_OMAP15XX
 521
 522 static irqreturn_t
 523 omap_i2c_rev1_isr(int this_irq, void *dev_id)
 524 {
 525         struct omap_i2c_dev *dev = dev_id;
 526         u16 iv, w;
 527
 528         if (dev->idle)
 529                 return IRQ_NONE;
 530
 531         iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
 532         switch (iv) {
 533         case 0x00:      /* None */
 534                 break;
 535         case 0x01:      /* Arbitration lost */
 536                 dev_err(dev->dev, "Arbitration lost\n");
 537                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
 538                 break;
 539         case 0x02:      /* No acknowledgement */
 540                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
 541                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
 542                 break;
 543         case 0x03:      /* Register access ready */
 544                 omap_i2c_complete_cmd(dev, 0);
 545                 break;
 546         case 0x04:      /* Receive data ready */
 547                 if (dev->buf_len) {
 548                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 549                         *dev->buf++ = w;
 550                         dev->buf_len--;
 551                         if (dev->buf_len) {
 552                                 *dev->buf++ = w >> 8;
 553                                 dev->buf_len--;
 554                         }
 555                 } else
 556                         dev_err(dev->dev, "RRDY IRQ while no data requested\n");
 557                 break;
 558         case 0x05:      /* Transmit data ready */
 559                 if (dev->buf_len) {
 560                         w = *dev->buf++;
 561                         dev->buf_len--;
 562                         if (dev->buf_len) {
 563                                 w |= *dev->buf++ << 8;
 564                                 dev->buf_len--;
 565                         }
 566                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 567                 } else
 568                         dev_err(dev->dev, "XRDY IRQ while no data to send\n");
 569                 break;
 570         default:
 571                 return IRQ_NONE;
 572         }
 573
 574         return IRQ_HANDLED;
 575 }
 576 #else
 577 #define omap_i2c_rev1_isr               0
 578 #endif
 579
 580 static irqreturn_t
 581 omap_i2c_isr(int this_irq, void *dev_id)
 582 {
 583         struct omap_i2c_dev *dev = dev_id;
 584         u16 bits;
 585         u16 stat, w;
 586         int err, count = 0;
 587
 588         if (dev->idle)
 589                 return IRQ_NONE;
 590
 591         bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 592         while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
 593                 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 594                 if (count++ == 100) {
 595                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 596                         break;
 597                 }
 598
 599                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 600
 601                 err = 0;
 602                 if (stat & OMAP_I2C_STAT_NACK) {
 603                         err |= OMAP_I2C_STAT_NACK;
 604                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
 605                                            OMAP_I2C_CON_STP);
 606                 }
 607                 if (stat & OMAP_I2C_STAT_AL) {
 608                         dev_err(dev->dev, "Arbitration lost\n");
 609                         err |= OMAP_I2C_STAT_AL;
 610                 }
 611                 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
 612                                         OMAP_I2C_STAT_AL))
 613                         omap_i2c_complete_cmd(dev, err);
 614                 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
 615                         u8 num_bytes = 1;
 616                         if (dev->fifo_size) {
 617                                 if (stat & OMAP_I2C_STAT_RRDY)
 618                                         num_bytes = dev->fifo_size;
 619                                 else
 620                                         num_bytes = omap_i2c_read_reg(dev,
 621                                                         OMAP_I2C_BUFSTAT_REG);
 622                         }
 623                         while (num_bytes) {
 624                                 num_bytes--;
 625                                 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 626                                 if (dev->buf_len) {
 627                                         *dev->buf++ = w;
 628                                         dev->buf_len--;
 629                                         /* Data reg from 2430 is 8 bit wide */
 630                                         if (!cpu_is_omap2430() &&
 631                                                         !cpu_is_omap34xx()) {
 632                                                 if (dev->buf_len) {
 633                                                         *dev->buf++ = w >> 8;
 634                                                         dev->buf_len--;
 635                                                 }
 636                                         }
 637                                 } else {
 638                                         if (stat & OMAP_I2C_STAT_RRDY)
 639                                                 dev_err(dev->dev,
 640                                                         "RRDY IRQ while no data"
 641                                                                 " requested\n");
 642                                         if (stat & OMAP_I2C_STAT_RDR)
 643                                                 dev_err(dev->dev,
 644                                                         "RDR IRQ while no data"
 645                                                                 " requested\n");
 646                                         break;
 647                                 }
 648                         }
 649                         omap_i2c_ack_stat(dev,
 650                                 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
 651                         continue;
 652                 }
 653                 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
 654                         u8 num_bytes = 1;
 655                         if (dev->fifo_size) {
 656                                 if (stat & OMAP_I2C_STAT_XRDY)
 657                                         num_bytes = dev->fifo_size;
 658                                 else
 659                                         num_bytes = omap_i2c_read_reg(dev,
 660                                                         OMAP_I2C_BUFSTAT_REG);
 661                         }
 662                         while (num_bytes) {
 663                                 num_bytes--;
 664                                 w = 0;
 665                                 if (dev->buf_len) {
 666                                         w = *dev->buf++;
 667                                         dev->buf_len--;
 668                                         /* Data reg from  2430 is 8 bit wide */
 669                                         if (!cpu_is_omap2430() &&
 670                                                         !cpu_is_omap34xx()) {
 671                                                 if (dev->buf_len) {
 672                                                         w |= *dev->buf++ << 8;
 673                                                         dev->buf_len--;
 674                                                 }
 675                                         }
 676                                 } else {
 677                                         if (stat & OMAP_I2C_STAT_XRDY)
 678                                                 dev_err(dev->dev,
 679                                                         "XRDY IRQ while no "
 680                                                         "data to send\n");
 681                                         if (stat & OMAP_I2C_STAT_XDR)
 682                                                 dev_err(dev->dev,
 683                                                         "XDR IRQ while no "
 684                                                         "data to send\n");
 685                                         break;
 686                                 }
 687                                 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 688                         }
 689                         omap_i2c_ack_stat(dev,
 690                                 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
 691                         continue;
 692                 }
 693                 if (stat & OMAP_I2C_STAT_ROVR) {
 694                         dev_err(dev->dev, "Receive overrun\n");
 695                         dev->cmd_err |= OMAP_I2C_STAT_ROVR;
 696                 }
 697                 if (stat & OMAP_I2C_STAT_XUDF) {
 698                         dev_err(dev->dev, "Transmit underflow\n");
 699                         dev->cmd_err |= OMAP_I2C_STAT_XUDF;
 700                 }
 701         }
 702
 703         return count ? IRQ_HANDLED : IRQ_NONE;
 704 }
 705
 706 static const struct i2c_algorithm omap_i2c_algo = {
 707         .master_xfer    = omap_i2c_xfer,
 708         .functionality  = omap_i2c_func,
 709 };
 710
 711 static int __init
 712 omap_i2c_probe(struct platform_device *pdev)
 713 {
 714         struct omap_i2c_dev     *dev;
 715         struct i2c_adapter      *adap;
 716         struct resource         *mem, *irq, *ioarea;
 717         int r;
 718         u32 *speed = NULL;
 719
 720         /* NOTE: driver uses the static register mapping */
 721         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 722         if (!mem) {
 723                 dev_err(&pdev->dev, "no mem resource?\n");
 724                 return -ENODEV;
 725         }
 726         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 727         if (!irq) {
 728                 dev_err(&pdev->dev, "no irq resource?\n");
 729                 return -ENODEV;
 730         }
 731
 732         ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
 733                         pdev->name);
 734         if (!ioarea) {
 735                 dev_err(&pdev->dev, "I2C region already claimed\n");
 736                 return -EBUSY;
 737         }
 738
 739         dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
 740         if (!dev) {
 741                 r = -ENOMEM;
 742                 goto err_release_region;
 743         }
 744
 745         if (pdev->dev.platform_data != NULL)
 746                 speed = (u32 *) pdev->dev.platform_data;
 747         else
 748                 *speed = 100; /* Defualt speed */
 749
 750         dev->speed = *speed;
 751         dev->dev = &pdev->dev;
 752         dev->irq = irq->start;
 753         dev->base = ioremap(mem->start, mem->end - mem->start + 1);
 754         if (!dev->base) {
 755                 r = -ENOMEM;
 756                 goto err_free_mem;
 757         }
 758
 759         platform_set_drvdata(pdev, dev);
 760
 761         r = omap_i2c_get_clocks(dev);
 762         if (r != 0)
 763                 goto err_iounmap;
 764
 765         omap_i2c_unidle(dev);
 766
 767         if (cpu_is_omap15xx())
 768                 dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20;
 769
 770         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 771                 u16 s;
 772
 773                 /* Set up the fifo size - Get total size */
 774                 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
 775                 dev->fifo_size = 0x8 << s;
 776
 777                 /*
 778                  * Set up notification threshold as half the total available
 779                  * size. This is to ensure that we can handle the status on int
 780                  * call back latencies.
 781                  */
 782                 dev->fifo_size = (dev->fifo_size / 2);
 783                 dev->b_hw = 1; /* Enable hardware fixes */
 784         }
 785
 786         /* reset ASAP, clearing any IRQs */
 787         omap_i2c_init(dev);
 788
 789         r = request_irq(dev->irq, dev->rev1 ? omap_i2c_rev1_isr : omap_i2c_isr,
 790                         0, pdev->name, dev);
 791
 792         if (r) {
 793                 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
 794                 goto err_unuse_clocks;
 795         }
 796         r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
 797         dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
 798                  pdev->id, r >> 4, r & 0xf, dev->speed);
 799
 800         adap = &dev->adapter;
 801         i2c_set_adapdata(adap, dev);
 802         adap->owner = THIS_MODULE;
 803         adap->class = I2C_CLASS_HWMON;
 804         strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
 805         adap->algo = &omap_i2c_algo;
 806         adap->dev.parent = &pdev->dev;
 807
 808         /* i2c device drivers may be active on return from add_adapter() */
 809         adap->nr = pdev->id;
 810         r = i2c_add_numbered_adapter(adap);
 811         if (r) {
 812                 dev_err(dev->dev, "failure adding adapter\n");
 813                 goto err_free_irq;
 814         }
 815
 816         omap_i2c_idle(dev);
 817
 818         return 0;
 819
 820 err_free_irq:
 821         free_irq(dev->irq, dev);
 822 err_unuse_clocks:
 823         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 824         omap_i2c_idle(dev);
 825         omap_i2c_put_clocks(dev);
 826 err_iounmap:
 827         iounmap(dev->base);
 828 err_free_mem:
 829         platform_set_drvdata(pdev, NULL);
 830         kfree(dev);
 831 err_release_region:
 832         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 833
 834         return r;
 835 }
 836
 837 static int
 838 omap_i2c_remove(struct platform_device *pdev)
 839 {
 840         struct omap_i2c_dev     *dev = platform_get_drvdata(pdev);
 841         struct resource         *mem;
 842
 843         platform_set_drvdata(pdev, NULL);
 844
 845         free_irq(dev->irq, dev);
 846         i2c_del_adapter(&dev->adapter);
 847         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 848         omap_i2c_put_clocks(dev);
 849         iounmap(dev->base);
 850         kfree(dev);
 851         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 852         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 853         return 0;
 854 }
 855
 856 static struct platform_driver omap_i2c_driver = {
 857         .probe          = omap_i2c_probe,
 858         .remove         = omap_i2c_remove,
 859         .driver         = {
 860                 .name   = "i2c_omap",
 861                 .owner  = THIS_MODULE,
 862         },
 863 };
 864
 865 /* I2C may be needed to bring up other drivers */
 866 static int __devinit
 867 omap_i2c_init_driver(void)
 868 {
 869         return platform_driver_register(&omap_i2c_driver);
 870 }
 871 subsys_initcall(omap_i2c_init_driver);
 872
 873 static void __devexit omap_i2c_exit_driver(void)
 874 {
 875         platform_driver_unregister(&omap_i2c_driver);
 876 }
 877 module_exit(omap_i2c_exit_driver);
 878
 879 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
 880 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
 881 MODULE_LICENSE("GPL");
 882 MODULE_ALIAS("platform:i2c_omap");