drivers/char/synclink_gt.c

   1 /*
   2  * $Id: synclink_gt.c,v 4.50 2007/07/25 19:29:25 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink GT serial adapters.
   5  *
   6  * written by Paul Fulghum for Microgate Corporation
   7  * paulkf@microgate.com
   8  *
   9  * Microgate and SyncLink are trademarks of Microgate Corporation
  10  *
  11  * This code is released under the GNU General Public License (GPL)
  12  *
  13  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  14  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  16  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  17  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  18  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  19  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  21  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  22  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  23  * OF THE POSSIBILITY OF SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * DEBUG OUTPUT DEFINITIONS
  28  *
  29  * uncomment lines below to enable specific types of debug output
  30  *
  31  * DBGINFO   information - most verbose output
  32  * DBGERR    serious errors
  33  * DBGBH     bottom half service routine debugging
  34  * DBGISR    interrupt service routine debugging
  35  * DBGDATA   output receive and transmit data
  36  * DBGTBUF   output transmit DMA buffers and registers
  37  * DBGRBUF   output receive DMA buffers and registers
  38  */
  39
  40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  45 //#define DBGTBUF(info) dump_tbufs(info)
  46 //#define DBGRBUF(info) dump_rbufs(info)
  47
  48
  49 #include <linux/module.h>
  50 #include <linux/errno.h>
  51 #include <linux/signal.h>
  52 #include <linux/sched.h>
  53 #include <linux/timer.h>
  54 #include <linux/interrupt.h>
  55 #include <linux/pci.h>
  56 #include <linux/tty.h>
  57 #include <linux/tty_flip.h>
  58 #include <linux/serial.h>
  59 #include <linux/major.h>
  60 #include <linux/string.h>
  61 #include <linux/fcntl.h>
  62 #include <linux/ptrace.h>
  63 #include <linux/ioport.h>
  64 #include <linux/mm.h>
  65 #include <linux/slab.h>
  66 #include <linux/netdevice.h>
  67 #include <linux/vmalloc.h>
  68 #include <linux/init.h>
  69 #include <linux/delay.h>
  70 #include <linux/ioctl.h>
  71 #include <linux/termios.h>
  72 #include <linux/bitops.h>
  73 #include <linux/workqueue.h>
  74 #include <linux/hdlc.h>
  75 #include <linux/synclink.h>
  76
  77 #include <asm/system.h>
  78 #include <asm/io.h>
  79 #include <asm/irq.h>
  80 #include <asm/dma.h>
  81 #include <asm/types.h>
  82 #include <asm/uaccess.h>
  83
  84 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  85 #define SYNCLINK_GENERIC_HDLC 1
  86 #else
  87 #define SYNCLINK_GENERIC_HDLC 0
  88 #endif
  89
  90 /*
  91  * module identification
  92  */
  93 static char *driver_name     = "SyncLink GT";
  94 static char *driver_version  = "$Revision: 4.50 $";
  95 static char *tty_driver_name = "synclink_gt";
  96 static char *tty_dev_prefix  = "ttySLG";
  97 MODULE_LICENSE("GPL");
  98 #define MGSL_MAGIC 0x5401
  99 #define MAX_DEVICES 32
 100
 101 static struct pci_device_id pci_table[] = {
 102         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 103         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 104         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 105         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 106         {0,}, /* terminate list */
 107 };
 108 MODULE_DEVICE_TABLE(pci, pci_table);
 109
 110 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 111 static void remove_one(struct pci_dev *dev);
 112 static struct pci_driver pci_driver = {
 113         .name           = "synclink_gt",
 114         .id_table       = pci_table,
 115         .probe          = init_one,
 116         .remove         = __devexit_p(remove_one),
 117 };
 118
 119 static bool pci_registered;
 120
 121 /*
 122  * module configuration and status
 123  */
 124 static struct slgt_info *slgt_device_list;
 125 static int slgt_device_count;
 126
 127 static int ttymajor;
 128 static int debug_level;
 129 static int maxframe[MAX_DEVICES];
 130
 131 module_param(ttymajor, int, 0);
 132 module_param(debug_level, int, 0);
 133 module_param_array(maxframe, int, NULL, 0);
 134
 135 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 136 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 137 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 138
 139 /*
 140  * tty support and callbacks
 141  */
 142 static struct tty_driver *serial_driver;
 143
 144 static int  open(struct tty_struct *tty, struct file * filp);
 145 static void close(struct tty_struct *tty, struct file * filp);
 146 static void hangup(struct tty_struct *tty);
 147 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 148
 149 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 150 static int put_char(struct tty_struct *tty, unsigned char ch);
 151 static void send_xchar(struct tty_struct *tty, char ch);
 152 static void wait_until_sent(struct tty_struct *tty, int timeout);
 153 static int  write_room(struct tty_struct *tty);
 154 static void flush_chars(struct tty_struct *tty);
 155 static void flush_buffer(struct tty_struct *tty);
 156 static void tx_hold(struct tty_struct *tty);
 157 static void tx_release(struct tty_struct *tty);
 158
 159 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 160 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 161 static int  chars_in_buffer(struct tty_struct *tty);
 162 static void throttle(struct tty_struct * tty);
 163 static void unthrottle(struct tty_struct * tty);
 164 static int set_break(struct tty_struct *tty, int break_state);
 165
 166 /*
 167  * generic HDLC support and callbacks
 168  */
 169 #if SYNCLINK_GENERIC_HDLC
 170 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 171 static void hdlcdev_tx_done(struct slgt_info *info);
 172 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 173 static int  hdlcdev_init(struct slgt_info *info);
 174 static void hdlcdev_exit(struct slgt_info *info);
 175 #endif
 176
 177
 178 /*
 179  * device specific structures, macros and functions
 180  */
 181
 182 #define SLGT_MAX_PORTS 4
 183 #define SLGT_REG_SIZE  256
 184
 185 /*
 186  * conditional wait facility
 187  */
 188 struct cond_wait {
 189         struct cond_wait *next;
 190         wait_queue_head_t q;
 191         wait_queue_t wait;
 192         unsigned int data;
 193 };
 194 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 195 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 196 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 197 static void flush_cond_wait(struct cond_wait **head);
 198
 199 /*
 200  * DMA buffer descriptor and access macros
 201  */
 202 struct slgt_desc
 203 {
 204         __le16 count;
 205         __le16 status;
 206         __le32 pbuf;  /* physical address of data buffer */
 207         __le32 next;  /* physical address of next descriptor */
 208
 209         /* driver book keeping */
 210         char *buf;          /* virtual  address of data buffer */
 211         unsigned int pdesc; /* physical address of this descriptor */
 212         dma_addr_t buf_dma_addr;
 213         unsigned short buf_count;
 214 };
 215
 216 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 217 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 218 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 219 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 220 #define desc_count(a)      (le16_to_cpu((a).count))
 221 #define desc_status(a)     (le16_to_cpu((a).status))
 222 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 223 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 224 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 225 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 226 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 227
 228 struct _input_signal_events {
 229         int ri_up;
 230         int ri_down;
 231         int dsr_up;
 232         int dsr_down;
 233         int dcd_up;
 234         int dcd_down;
 235         int cts_up;
 236         int cts_down;
 237 };
 238
 239 /*
 240  * device instance data structure
 241  */
 242 struct slgt_info {
 243         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 244         struct tty_port port;
 245
 246         struct slgt_info *next_device;  /* device list link */
 247
 248         int magic;
 249
 250         char device_name[25];
 251         struct pci_dev *pdev;
 252
 253         int port_count;  /* count of ports on adapter */
 254         int adapter_num; /* adapter instance number */
 255         int port_num;    /* port instance number */
 256
 257         /* array of pointers to port contexts on this adapter */
 258         struct slgt_info *port_array[SLGT_MAX_PORTS];
 259
 260         int                     line;           /* tty line instance number */
 261
 262         struct mgsl_icount      icount;
 263
 264         int                     timeout;
 265         int                     x_char;         /* xon/xoff character */
 266         unsigned int            read_status_mask;
 267         unsigned int            ignore_status_mask;
 268
 269         wait_queue_head_t       status_event_wait_q;
 270         wait_queue_head_t       event_wait_q;
 271         struct timer_list       tx_timer;
 272         struct timer_list       rx_timer;
 273
 274         unsigned int            gpio_present;
 275         struct cond_wait        *gpio_wait_q;
 276
 277         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 278
 279         struct work_struct task;
 280         u32 pending_bh;
 281         bool bh_requested;
 282         bool bh_running;
 283
 284         int isr_overflow;
 285         bool irq_requested;     /* true if IRQ requested */
 286         bool irq_occurred;      /* for diagnostics use */
 287
 288         /* device configuration */
 289
 290         unsigned int bus_type;
 291         unsigned int irq_level;
 292         unsigned long irq_flags;
 293
 294         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 295         u32 phys_reg_addr;
 296         bool reg_addr_requested;
 297
 298         MGSL_PARAMS params;       /* communications parameters */
 299         u32 idle_mode;
 300         u32 max_frame_size;       /* as set by device config */
 301
 302         unsigned int rbuf_fill_level;
 303         unsigned int if_mode;
 304
 305         /* device status */
 306
 307         bool rx_enabled;
 308         bool rx_restart;
 309
 310         bool tx_enabled;
 311         bool tx_active;
 312
 313         unsigned char signals;    /* serial signal states */
 314         int init_error;  /* initialization error */
 315
 316         unsigned char *tx_buf;
 317         int tx_count;
 318
 319         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 320         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 321         bool drop_rts_on_tx_done;
 322         struct  _input_signal_events    input_signal_events;
 323
 324         int dcd_chkcount;       /* check counts to prevent */
 325         int cts_chkcount;       /* too many IRQs if a signal */
 326         int dsr_chkcount;       /* is floating */
 327         int ri_chkcount;
 328
 329         char *bufs;             /* virtual address of DMA buffer lists */
 330         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 331
 332         unsigned int rbuf_count;
 333         struct slgt_desc *rbufs;
 334         unsigned int rbuf_current;
 335         unsigned int rbuf_index;
 336
 337         unsigned int tbuf_count;
 338         struct slgt_desc *tbufs;
 339         unsigned int tbuf_current;
 340         unsigned int tbuf_start;
 341
 342         unsigned char *tmp_rbuf;
 343         unsigned int tmp_rbuf_count;
 344
 345         /* SPPP/Cisco HDLC device parts */
 346
 347         int netcount;
 348         spinlock_t netlock;
 349 #if SYNCLINK_GENERIC_HDLC
 350         struct net_device *netdev;
 351 #endif
 352
 353 };
 354
 355 static MGSL_PARAMS default_params = {
 356         .mode            = MGSL_MODE_HDLC,
 357         .loopback        = 0,
 358         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 359         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 360         .clock_speed     = 0,
 361         .addr_filter     = 0xff,
 362         .crc_type        = HDLC_CRC_16_CCITT,
 363         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 364         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 365         .data_rate       = 9600,
 366         .data_bits       = 8,
 367         .stop_bits       = 1,
 368         .parity          = ASYNC_PARITY_NONE
 369 };
 370
 371
 372 #define BH_RECEIVE  1
 373 #define BH_TRANSMIT 2
 374 #define BH_STATUS   4
 375 #define IO_PIN_SHUTDOWN_LIMIT 100
 376
 377 #define DMABUFSIZE 256
 378 #define DESC_LIST_SIZE 4096
 379
 380 #define MASK_PARITY  BIT1
 381 #define MASK_FRAMING BIT0
 382 #define MASK_BREAK   BIT14
 383 #define MASK_OVERRUN BIT4
 384
 385 #define GSR   0x00 /* global status */
 386 #define JCR   0x04 /* JTAG control */
 387 #define IODR  0x08 /* GPIO direction */
 388 #define IOER  0x0c /* GPIO interrupt enable */
 389 #define IOVR  0x10 /* GPIO value */
 390 #define IOSR  0x14 /* GPIO interrupt status */
 391 #define TDR   0x80 /* tx data */
 392 #define RDR   0x80 /* rx data */
 393 #define TCR   0x82 /* tx control */
 394 #define TIR   0x84 /* tx idle */
 395 #define TPR   0x85 /* tx preamble */
 396 #define RCR   0x86 /* rx control */
 397 #define VCR   0x88 /* V.24 control */
 398 #define CCR   0x89 /* clock control */
 399 #define BDR   0x8a /* baud divisor */
 400 #define SCR   0x8c /* serial control */
 401 #define SSR   0x8e /* serial status */
 402 #define RDCSR 0x90 /* rx DMA control/status */
 403 #define TDCSR 0x94 /* tx DMA control/status */
 404 #define RDDAR 0x98 /* rx DMA descriptor address */
 405 #define TDDAR 0x9c /* tx DMA descriptor address */
 406
 407 #define RXIDLE      BIT14
 408 #define RXBREAK     BIT14
 409 #define IRQ_TXDATA  BIT13
 410 #define IRQ_TXIDLE  BIT12
 411 #define IRQ_TXUNDER BIT11 /* HDLC */
 412 #define IRQ_RXDATA  BIT10
 413 #define IRQ_RXIDLE  BIT9  /* HDLC */
 414 #define IRQ_RXBREAK BIT9  /* async */
 415 #define IRQ_RXOVER  BIT8
 416 #define IRQ_DSR     BIT7
 417 #define IRQ_CTS     BIT6
 418 #define IRQ_DCD     BIT5
 419 #define IRQ_RI      BIT4
 420 #define IRQ_ALL     0x3ff0
 421 #define IRQ_MASTER  BIT0
 422
 423 #define slgt_irq_on(info, mask) \
 424         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 425 #define slgt_irq_off(info, mask) \
 426         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 427
 428 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 429 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 430 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 431 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 432 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 433 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 434
 435 static void  msc_set_vcr(struct slgt_info *info);
 436
 437 static int  startup(struct slgt_info *info);
 438 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 439 static void shutdown(struct slgt_info *info);
 440 static void program_hw(struct slgt_info *info);
 441 static void change_params(struct slgt_info *info);
 442
 443 static int  register_test(struct slgt_info *info);
 444 static int  irq_test(struct slgt_info *info);
 445 static int  loopback_test(struct slgt_info *info);
 446 static int  adapter_test(struct slgt_info *info);
 447
 448 static void reset_adapter(struct slgt_info *info);
 449 static void reset_port(struct slgt_info *info);
 450 static void async_mode(struct slgt_info *info);
 451 static void sync_mode(struct slgt_info *info);
 452
 453 static void rx_stop(struct slgt_info *info);
 454 static void rx_start(struct slgt_info *info);
 455 static void reset_rbufs(struct slgt_info *info);
 456 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 457 static void rdma_reset(struct slgt_info *info);
 458 static bool rx_get_frame(struct slgt_info *info);
 459 static bool rx_get_buf(struct slgt_info *info);
 460
 461 static void tx_start(struct slgt_info *info);
 462 static void tx_stop(struct slgt_info *info);
 463 static void tx_set_idle(struct slgt_info *info);
 464 static unsigned int free_tbuf_count(struct slgt_info *info);
 465 static unsigned int tbuf_bytes(struct slgt_info *info);
 466 static void reset_tbufs(struct slgt_info *info);
 467 static void tdma_reset(struct slgt_info *info);
 468 static void tdma_start(struct slgt_info *info);
 469 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 470
 471 static void get_signals(struct slgt_info *info);
 472 static void set_signals(struct slgt_info *info);
 473 static void enable_loopback(struct slgt_info *info);
 474 static void set_rate(struct slgt_info *info, u32 data_rate);
 475
 476 static int  bh_action(struct slgt_info *info);
 477 static void bh_handler(struct work_struct *work);
 478 static void bh_transmit(struct slgt_info *info);
 479 static void isr_serial(struct slgt_info *info);
 480 static void isr_rdma(struct slgt_info *info);
 481 static void isr_txeom(struct slgt_info *info, unsigned short status);
 482 static void isr_tdma(struct slgt_info *info);
 483
 484 static int  alloc_dma_bufs(struct slgt_info *info);
 485 static void free_dma_bufs(struct slgt_info *info);
 486 static int  alloc_desc(struct slgt_info *info);
 487 static void free_desc(struct slgt_info *info);
 488 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 489 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 490
 491 static int  alloc_tmp_rbuf(struct slgt_info *info);
 492 static void free_tmp_rbuf(struct slgt_info *info);
 493
 494 static void tx_timeout(unsigned long context);
 495 static void rx_timeout(unsigned long context);
 496
 497 /*
 498  * ioctl handlers
 499  */
 500 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 501 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 502 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 503 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 504 static int  set_txidle(struct slgt_info *info, int idle_mode);
 505 static int  tx_enable(struct slgt_info *info, int enable);
 506 static int  tx_abort(struct slgt_info *info);
 507 static int  rx_enable(struct slgt_info *info, int enable);
 508 static int  modem_input_wait(struct slgt_info *info,int arg);
 509 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 510 static int  tiocmget(struct tty_struct *tty, struct file *file);
 511 static int  tiocmset(struct tty_struct *tty, struct file *file,
 512                      unsigned int set, unsigned int clear);
 513 static int set_break(struct tty_struct *tty, int break_state);
 514 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 515 static int  set_interface(struct slgt_info *info, int if_mode);
 516 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 517 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 518 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 519
 520 /*
 521  * driver functions
 522  */
 523 static void add_device(struct slgt_info *info);
 524 static void device_init(int adapter_num, struct pci_dev *pdev);
 525 static int  claim_resources(struct slgt_info *info);
 526 static void release_resources(struct slgt_info *info);
 527
 528 /*
 529  * DEBUG OUTPUT CODE
 530  */
 531 #ifndef DBGINFO
 532 #define DBGINFO(fmt)
 533 #endif
 534 #ifndef DBGERR
 535 #define DBGERR(fmt)
 536 #endif
 537 #ifndef DBGBH
 538 #define DBGBH(fmt)
 539 #endif
 540 #ifndef DBGISR
 541 #define DBGISR(fmt)
 542 #endif
 543
 544 #ifdef DBGDATA
 545 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 546 {
 547         int i;
 548         int linecount;
 549         printk("%s %s data:\n",info->device_name, label);
 550         while(count) {
 551                 linecount = (count > 16) ? 16 : count;
 552                 for(i=0; i < linecount; i++)
 553                         printk("%02X ",(unsigned char)data[i]);
 554                 for(;i<17;i++)
 555                         printk("   ");
 556                 for(i=0;i<linecount;i++) {
 557                         if (data[i]>=040 && data[i]<=0176)
 558                                 printk("%c",data[i]);
 559                         else
 560                                 printk(".");
 561                 }
 562                 printk("\n");
 563                 data  += linecount;
 564                 count -= linecount;
 565         }
 566 }
 567 #else
 568 #define DBGDATA(info, buf, size, label)
 569 #endif
 570
 571 #ifdef DBGTBUF
 572 static void dump_tbufs(struct slgt_info *info)
 573 {
 574         int i;
 575         printk("tbuf_current=%d\n", info->tbuf_current);
 576         for (i=0 ; i < info->tbuf_count ; i++) {
 577                 printk("%d: count=%04X status=%04X\n",
 578                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 579         }
 580 }
 581 #else
 582 #define DBGTBUF(info)
 583 #endif
 584
 585 #ifdef DBGRBUF
 586 static void dump_rbufs(struct slgt_info *info)
 587 {
 588         int i;
 589         printk("rbuf_current=%d\n", info->rbuf_current);
 590         for (i=0 ; i < info->rbuf_count ; i++) {
 591                 printk("%d: count=%04X status=%04X\n",
 592                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 593         }
 594 }
 595 #else
 596 #define DBGRBUF(info)
 597 #endif
 598
 599 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 600 {
 601 #ifdef SANITY_CHECK
 602         if (!info) {
 603                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 604                 return 1;
 605         }
 606         if (info->magic != MGSL_MAGIC) {
 607                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 608                 return 1;
 609         }
 610 #else
 611         if (!info)
 612                 return 1;
 613 #endif
 614         return 0;
 615 }
 616
 617 /**
 618  * line discipline callback wrappers
 619  *
 620  * The wrappers maintain line discipline references
 621  * while calling into the line discipline.
 622  *
 623  * ldisc_receive_buf  - pass receive data to line discipline
 624  */
 625 static void ldisc_receive_buf(struct tty_struct *tty,
 626                               const __u8 *data, char *flags, int count)
 627 {
 628         struct tty_ldisc *ld;
 629         if (!tty)
 630                 return;
 631         ld = tty_ldisc_ref(tty);
 632         if (ld) {
 633                 if (ld->ops->receive_buf)
 634                         ld->ops->receive_buf(tty, data, flags, count);
 635                 tty_ldisc_deref(ld);
 636         }
 637 }
 638
 639 /* tty callbacks */
 640
 641 static int open(struct tty_struct *tty, struct file *filp)
 642 {
 643         struct slgt_info *info;
 644         int retval, line;
 645         unsigned long flags;
 646
 647         line = tty->index;
 648         if ((line < 0) || (line >= slgt_device_count)) {
 649                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 650                 return -ENODEV;
 651         }
 652
 653         info = slgt_device_list;
 654         while(info && info->line != line)
 655                 info = info->next_device;
 656         if (sanity_check(info, tty->name, "open"))
 657                 return -ENODEV;
 658         if (info->init_error) {
 659                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 660                 return -ENODEV;
 661         }
 662
 663         tty->driver_data = info;
 664         info->port.tty = tty;
 665
 666         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 667
 668         /* If port is closing, signal caller to try again */
 669         if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
 670                 if (info->port.flags & ASYNC_CLOSING)
 671                         interruptible_sleep_on(&info->port.close_wait);
 672                 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
 673                         -EAGAIN : -ERESTARTSYS);
 674                 goto cleanup;
 675         }
 676
 677         info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 678
 679         spin_lock_irqsave(&info->netlock, flags);
 680         if (info->netcount) {
 681                 retval = -EBUSY;
 682                 spin_unlock_irqrestore(&info->netlock, flags);
 683                 goto cleanup;
 684         }
 685         info->port.count++;
 686         spin_unlock_irqrestore(&info->netlock, flags);
 687
 688         if (info->port.count == 1) {
 689                 /* 1st open on this device, init hardware */
 690                 retval = startup(info);
 691                 if (retval < 0)
 692                         goto cleanup;
 693         }
 694
 695         retval = block_til_ready(tty, filp, info);
 696         if (retval) {
 697                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 698                 goto cleanup;
 699         }
 700
 701         retval = 0;
 702
 703 cleanup:
 704         if (retval) {
 705                 if (tty->count == 1)
 706                         info->port.tty = NULL; /* tty layer will release tty struct */
 707                 if(info->port.count)
 708                         info->port.count--;
 709         }
 710
 711         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 712         return retval;
 713 }
 714
 715 static void close(struct tty_struct *tty, struct file *filp)
 716 {
 717         struct slgt_info *info = tty->driver_data;
 718
 719         if (sanity_check(info, tty->name, "close"))
 720                 return;
 721         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 722
 723         if (tty_port_close_start(&info->port, tty, filp) == 0)
 724                 goto cleanup;
 725
 726         if (info->port.flags & ASYNC_INITIALIZED)
 727                 wait_until_sent(tty, info->timeout);
 728         flush_buffer(tty);
 729         tty_ldisc_flush(tty);
 730
 731         shutdown(info);
 732
 733         tty_port_close_end(&info->port, tty);
 734         info->port.tty = NULL;
 735 cleanup:
 736         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 737 }
 738
 739 static void hangup(struct tty_struct *tty)
 740 {
 741         struct slgt_info *info = tty->driver_data;
 742
 743         if (sanity_check(info, tty->name, "hangup"))
 744                 return;
 745         DBGINFO(("%s hangup\n", info->device_name));
 746
 747         flush_buffer(tty);
 748         shutdown(info);
 749
 750         info->port.count = 0;
 751         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
 752         info->port.tty = NULL;
 753
 754         wake_up_interruptible(&info->port.open_wait);
 755 }
 756
 757 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 758 {
 759         struct slgt_info *info = tty->driver_data;
 760         unsigned long flags;
 761
 762         DBGINFO(("%s set_termios\n", tty->driver->name));
 763
 764         change_params(info);
 765
 766         /* Handle transition to B0 status */
 767         if (old_termios->c_cflag & CBAUD &&
 768             !(tty->termios->c_cflag & CBAUD)) {
 769                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 770                 spin_lock_irqsave(&info->lock,flags);
 771                 set_signals(info);
 772                 spin_unlock_irqrestore(&info->lock,flags);
 773         }
 774
 775         /* Handle transition away from B0 status */
 776         if (!(old_termios->c_cflag & CBAUD) &&
 777             tty->termios->c_cflag & CBAUD) {
 778                 info->signals |= SerialSignal_DTR;
 779                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 780                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 781                         info->signals |= SerialSignal_RTS;
 782                 }
 783                 spin_lock_irqsave(&info->lock,flags);
 784                 set_signals(info);
 785                 spin_unlock_irqrestore(&info->lock,flags);
 786         }
 787
 788         /* Handle turning off CRTSCTS */
 789         if (old_termios->c_cflag & CRTSCTS &&
 790             !(tty->termios->c_cflag & CRTSCTS)) {
 791                 tty->hw_stopped = 0;
 792                 tx_release(tty);
 793         }
 794 }
 795
 796 static int write(struct tty_struct *tty,
 797                  const unsigned char *buf, int count)
 798 {
 799         int ret = 0;
 800         struct slgt_info *info = tty->driver_data;
 801         unsigned long flags;
 802         unsigned int bufs_needed;
 803
 804         if (sanity_check(info, tty->name, "write"))
 805                 goto cleanup;
 806         DBGINFO(("%s write count=%d\n", info->device_name, count));
 807
 808         if (!info->tx_buf)
 809                 goto cleanup;
 810
 811         if (count > info->max_frame_size) {
 812                 ret = -EIO;
 813                 goto cleanup;
 814         }
 815
 816         if (!count)
 817                 goto cleanup;
 818
 819         if (!info->tx_active && info->tx_count) {
 820                 /* send accumulated data from send_char() */
 821                 tx_load(info, info->tx_buf, info->tx_count);
 822                 goto start;
 823         }
 824         bufs_needed = (count/DMABUFSIZE);
 825         if (count % DMABUFSIZE)
 826                 ++bufs_needed;
 827         if (bufs_needed > free_tbuf_count(info))
 828                 goto cleanup;
 829
 830         ret = info->tx_count = count;
 831         tx_load(info, buf, count);
 832         goto start;
 833
 834 start:
 835         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 836                 spin_lock_irqsave(&info->lock,flags);
 837                 if (!info->tx_active)
 838                         tx_start(info);
 839                 else
 840                         tdma_start(info);
 841                 spin_unlock_irqrestore(&info->lock,flags);
 842         }
 843
 844 cleanup:
 845         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 846         return ret;
 847 }
 848
 849 static int put_char(struct tty_struct *tty, unsigned char ch)
 850 {
 851         struct slgt_info *info = tty->driver_data;
 852         unsigned long flags;
 853         int ret = 0;
 854
 855         if (sanity_check(info, tty->name, "put_char"))
 856                 return 0;
 857         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 858         if (!info->tx_buf)
 859                 return 0;
 860         spin_lock_irqsave(&info->lock,flags);
 861         if (!info->tx_active && (info->tx_count < info->max_frame_size)) {
 862                 info->tx_buf[info->tx_count++] = ch;
 863                 ret = 1;
 864         }
 865         spin_unlock_irqrestore(&info->lock,flags);
 866         return ret;
 867 }
 868
 869 static void send_xchar(struct tty_struct *tty, char ch)
 870 {
 871         struct slgt_info *info = tty->driver_data;
 872         unsigned long flags;
 873
 874         if (sanity_check(info, tty->name, "send_xchar"))
 875                 return;
 876         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 877         info->x_char = ch;
 878         if (ch) {
 879                 spin_lock_irqsave(&info->lock,flags);
 880                 if (!info->tx_enabled)
 881                         tx_start(info);
 882                 spin_unlock_irqrestore(&info->lock,flags);
 883         }
 884 }
 885
 886 static void wait_until_sent(struct tty_struct *tty, int timeout)
 887 {
 888         struct slgt_info *info = tty->driver_data;
 889         unsigned long orig_jiffies, char_time;
 890
 891         if (!info )
 892                 return;
 893         if (sanity_check(info, tty->name, "wait_until_sent"))
 894                 return;
 895         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 896         if (!(info->port.flags & ASYNC_INITIALIZED))
 897                 goto exit;
 898
 899         orig_jiffies = jiffies;
 900
 901         /* Set check interval to 1/5 of estimated time to
 902          * send a character, and make it at least 1. The check
 903          * interval should also be less than the timeout.
 904          * Note: use tight timings here to satisfy the NIST-PCTS.
 905          */
 906
 907         lock_kernel();
 908
 909         if (info->params.data_rate) {
 910                 char_time = info->timeout/(32 * 5);
 911                 if (!char_time)
 912                         char_time++;
 913         } else
 914                 char_time = 1;
 915
 916         if (timeout)
 917                 char_time = min_t(unsigned long, char_time, timeout);
 918
 919         while (info->tx_active) {
 920                 msleep_interruptible(jiffies_to_msecs(char_time));
 921                 if (signal_pending(current))
 922                         break;
 923                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 924                         break;
 925         }
 926         unlock_kernel();
 927
 928 exit:
 929         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 930 }
 931
 932 static int write_room(struct tty_struct *tty)
 933 {
 934         struct slgt_info *info = tty->driver_data;
 935         int ret;
 936
 937         if (sanity_check(info, tty->name, "write_room"))
 938                 return 0;
 939         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 940         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
 941         return ret;
 942 }
 943
 944 static void flush_chars(struct tty_struct *tty)
 945 {
 946         struct slgt_info *info = tty->driver_data;
 947         unsigned long flags;
 948
 949         if (sanity_check(info, tty->name, "flush_chars"))
 950                 return;
 951         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
 952
 953         if (info->tx_count <= 0 || tty->stopped ||
 954             tty->hw_stopped || !info->tx_buf)
 955                 return;
 956
 957         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
 958
 959         spin_lock_irqsave(&info->lock,flags);
 960         if (!info->tx_active && info->tx_count) {
 961                 tx_load(info, info->tx_buf,info->tx_count);
 962                 tx_start(info);
 963         }
 964         spin_unlock_irqrestore(&info->lock,flags);
 965 }
 966
 967 static void flush_buffer(struct tty_struct *tty)
 968 {
 969         struct slgt_info *info = tty->driver_data;
 970         unsigned long flags;
 971
 972         if (sanity_check(info, tty->name, "flush_buffer"))
 973                 return;
 974         DBGINFO(("%s flush_buffer\n", info->device_name));
 975
 976         spin_lock_irqsave(&info->lock,flags);
 977         if (!info->tx_active)
 978                 info->tx_count = 0;
 979         spin_unlock_irqrestore(&info->lock,flags);
 980
 981         tty_wakeup(tty);
 982 }
 983
 984 /*
 985  * throttle (stop) transmitter
 986  */
 987 static void tx_hold(struct tty_struct *tty)
 988 {
 989         struct slgt_info *info = tty->driver_data;
 990         unsigned long flags;
 991
 992         if (sanity_check(info, tty->name, "tx_hold"))
 993                 return;
 994         DBGINFO(("%s tx_hold\n", info->device_name));
 995         spin_lock_irqsave(&info->lock,flags);
 996         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
 997                 tx_stop(info);
 998         spin_unlock_irqrestore(&info->lock,flags);
 999 }
1000
1001 /*
1002  * release (start) transmitter
1003  */
1004 static void tx_release(struct tty_struct *tty)
1005 {
1006         struct slgt_info *info = tty->driver_data;
1007         unsigned long flags;
1008
1009         if (sanity_check(info, tty->name, "tx_release"))
1010                 return;
1011         DBGINFO(("%s tx_release\n", info->device_name));
1012         spin_lock_irqsave(&info->lock,flags);
1013         if (!info->tx_active && info->tx_count) {
1014                 tx_load(info, info->tx_buf, info->tx_count);
1015                 tx_start(info);
1016         }
1017         spin_unlock_irqrestore(&info->lock,flags);
1018 }
1019
1020 /*
1021  * Service an IOCTL request
1022  *
1023  * Arguments
1024  *
1025  *      tty     pointer to tty instance data
1026  *      file    pointer to associated file object for device
1027  *      cmd     IOCTL command code
1028  *      arg     command argument/context
1029  *
1030  * Return 0 if success, otherwise error code
1031  */
1032 static int ioctl(struct tty_struct *tty, struct file *file,
1033                  unsigned int cmd, unsigned long arg)
1034 {
1035         struct slgt_info *info = tty->driver_data;
1036         struct mgsl_icount cnow;        /* kernel counter temps */
1037         struct serial_icounter_struct __user *p_cuser;  /* user space */
1038         unsigned long flags;
1039         void __user *argp = (void __user *)arg;
1040         int ret;
1041
1042         if (sanity_check(info, tty->name, "ioctl"))
1043                 return -ENODEV;
1044         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1045
1046         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1047             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1048                 if (tty->flags & (1 << TTY_IO_ERROR))
1049                     return -EIO;
1050         }
1051
1052         lock_kernel();
1053
1054         switch (cmd) {
1055         case MGSL_IOCGPARAMS:
1056                 ret = get_params(info, argp);
1057                 break;
1058         case MGSL_IOCSPARAMS:
1059                 ret = set_params(info, argp);
1060                 break;
1061         case MGSL_IOCGTXIDLE:
1062                 ret = get_txidle(info, argp);
1063                 break;
1064         case MGSL_IOCSTXIDLE:
1065                 ret = set_txidle(info, (int)arg);
1066                 break;
1067         case MGSL_IOCTXENABLE:
1068                 ret = tx_enable(info, (int)arg);
1069                 break;
1070         case MGSL_IOCRXENABLE:
1071                 ret = rx_enable(info, (int)arg);
1072                 break;
1073         case MGSL_IOCTXABORT:
1074                 ret = tx_abort(info);
1075                 break;
1076         case MGSL_IOCGSTATS:
1077                 ret = get_stats(info, argp);
1078                 break;
1079         case MGSL_IOCWAITEVENT:
1080                 ret = wait_mgsl_event(info, argp);
1081                 break;
1082         case TIOCMIWAIT:
1083                 ret = modem_input_wait(info,(int)arg);
1084                 break;
1085         case MGSL_IOCGIF:
1086                 ret = get_interface(info, argp);
1087                 break;
1088         case MGSL_IOCSIF:
1089                 ret = set_interface(info,(int)arg);
1090                 break;
1091         case MGSL_IOCSGPIO:
1092                 ret = set_gpio(info, argp);
1093                 break;
1094         case MGSL_IOCGGPIO:
1095                 ret = get_gpio(info, argp);
1096                 break;
1097         case MGSL_IOCWAITGPIO:
1098                 ret = wait_gpio(info, argp);
1099                 break;
1100         case TIOCGICOUNT:
1101                 spin_lock_irqsave(&info->lock,flags);
1102                 cnow = info->icount;
1103                 spin_unlock_irqrestore(&info->lock,flags);
1104                 p_cuser = argp;
1105                 if (put_user(cnow.cts, &p_cuser->cts) ||
1106                     put_user(cnow.dsr, &p_cuser->dsr) ||
1107                     put_user(cnow.rng, &p_cuser->rng) ||
1108                     put_user(cnow.dcd, &p_cuser->dcd) ||
1109                     put_user(cnow.rx, &p_cuser->rx) ||
1110                     put_user(cnow.tx, &p_cuser->tx) ||
1111                     put_user(cnow.frame, &p_cuser->frame) ||
1112                     put_user(cnow.overrun, &p_cuser->overrun) ||
1113                     put_user(cnow.parity, &p_cuser->parity) ||
1114                     put_user(cnow.brk, &p_cuser->brk) ||
1115                     put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1116                         ret = -EFAULT;
1117                 ret = 0;
1118                 break;
1119         default:
1120                 ret = -ENOIOCTLCMD;
1121         }
1122         unlock_kernel();
1123         return ret;
1124 }
1125
1126 /*
1127  * support for 32 bit ioctl calls on 64 bit systems
1128  */
1129 #ifdef CONFIG_COMPAT
1130 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1131 {
1132         struct MGSL_PARAMS32 tmp_params;
1133
1134         DBGINFO(("%s get_params32\n", info->device_name));
1135         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1136         tmp_params.loopback        = info->params.loopback;
1137         tmp_params.flags           = info->params.flags;
1138         tmp_params.encoding        = info->params.encoding;
1139         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1140         tmp_params.addr_filter     = info->params.addr_filter;
1141         tmp_params.crc_type        = info->params.crc_type;
1142         tmp_params.preamble_length = info->params.preamble_length;
1143         tmp_params.preamble        = info->params.preamble;
1144         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1145         tmp_params.data_bits       = info->params.data_bits;
1146         tmp_params.stop_bits       = info->params.stop_bits;
1147         tmp_params.parity          = info->params.parity;
1148         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1149                 return -EFAULT;
1150         return 0;
1151 }
1152
1153 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1154 {
1155         struct MGSL_PARAMS32 tmp_params;
1156
1157         DBGINFO(("%s set_params32\n", info->device_name));
1158         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1159                 return -EFAULT;
1160
1161         spin_lock(&info->lock);
1162         info->params.mode            = tmp_params.mode;
1163         info->params.loopback        = tmp_params.loopback;
1164         info->params.flags           = tmp_params.flags;
1165         info->params.encoding        = tmp_params.encoding;
1166         info->params.clock_speed     = tmp_params.clock_speed;
1167         info->params.addr_filter     = tmp_params.addr_filter;
1168         info->params.crc_type        = tmp_params.crc_type;
1169         info->params.preamble_length = tmp_params.preamble_length;
1170         info->params.preamble        = tmp_params.preamble;
1171         info->params.data_rate       = tmp_params.data_rate;
1172         info->params.data_bits       = tmp_params.data_bits;
1173         info->params.stop_bits       = tmp_params.stop_bits;
1174         info->params.parity          = tmp_params.parity;
1175         spin_unlock(&info->lock);
1176
1177         change_params(info);
1178
1179         return 0;
1180 }
1181
1182 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1183                          unsigned int cmd, unsigned long arg)
1184 {
1185         struct slgt_info *info = tty->driver_data;
1186         int rc = -ENOIOCTLCMD;
1187
1188         if (sanity_check(info, tty->name, "compat_ioctl"))
1189                 return -ENODEV;
1190         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1191
1192         switch (cmd) {
1193
1194         case MGSL_IOCSPARAMS32:
1195                 rc = set_params32(info, compat_ptr(arg));
1196                 break;
1197
1198         case MGSL_IOCGPARAMS32:
1199                 rc = get_params32(info, compat_ptr(arg));
1200                 break;
1201
1202         case MGSL_IOCGPARAMS:
1203         case MGSL_IOCSPARAMS:
1204         case MGSL_IOCGTXIDLE:
1205         case MGSL_IOCGSTATS:
1206         case MGSL_IOCWAITEVENT:
1207         case MGSL_IOCGIF:
1208         case MGSL_IOCSGPIO:
1209         case MGSL_IOCGGPIO:
1210         case MGSL_IOCWAITGPIO:
1211         case TIOCGICOUNT:
1212                 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1213                 break;
1214
1215         case MGSL_IOCSTXIDLE:
1216         case MGSL_IOCTXENABLE:
1217         case MGSL_IOCRXENABLE:
1218         case MGSL_IOCTXABORT:
1219         case TIOCMIWAIT:
1220         case MGSL_IOCSIF:
1221                 rc = ioctl(tty, file, cmd, arg);
1222                 break;
1223         }
1224
1225         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1226         return rc;
1227 }
1228 #else
1229 #define slgt_compat_ioctl NULL
1230 #endif /* ifdef CONFIG_COMPAT */
1231
1232 /*
1233  * proc fs support
1234  */
1235 static inline int line_info(char *buf, struct slgt_info *info)
1236 {
1237         char stat_buf[30];
1238         int ret;
1239         unsigned long flags;
1240
1241         ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1242                       info->device_name, info->phys_reg_addr,
1243                       info->irq_level, info->max_frame_size);
1244
1245         /* output current serial signal states */
1246         spin_lock_irqsave(&info->lock,flags);
1247         get_signals(info);
1248         spin_unlock_irqrestore(&info->lock,flags);
1249
1250         stat_buf[0] = 0;
1251         stat_buf[1] = 0;
1252         if (info->signals & SerialSignal_RTS)
1253                 strcat(stat_buf, "|RTS");
1254         if (info->signals & SerialSignal_CTS)
1255                 strcat(stat_buf, "|CTS");
1256         if (info->signals & SerialSignal_DTR)
1257                 strcat(stat_buf, "|DTR");
1258         if (info->signals & SerialSignal_DSR)
1259                 strcat(stat_buf, "|DSR");
1260         if (info->signals & SerialSignal_DCD)
1261                 strcat(stat_buf, "|CD");
1262         if (info->signals & SerialSignal_RI)
1263                 strcat(stat_buf, "|RI");
1264
1265         if (info->params.mode != MGSL_MODE_ASYNC) {
1266                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1267                                info->icount.txok, info->icount.rxok);
1268                 if (info->icount.txunder)
1269                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1270                 if (info->icount.txabort)
1271                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1272                 if (info->icount.rxshort)
1273                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1274                 if (info->icount.rxlong)
1275                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1276                 if (info->icount.rxover)
1277                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1278                 if (info->icount.rxcrc)
1279                         ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1280         } else {
1281                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1282                                info->icount.tx, info->icount.rx);
1283                 if (info->icount.frame)
1284                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1285                 if (info->icount.parity)
1286                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1287                 if (info->icount.brk)
1288                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1289                 if (info->icount.overrun)
1290                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1291         }
1292
1293         /* Append serial signal status to end */
1294         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1295
1296         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1297                        info->tx_active,info->bh_requested,info->bh_running,
1298                        info->pending_bh);
1299
1300         return ret;
1301 }
1302
1303 /* Called to print information about devices
1304  */
1305 static int read_proc(char *page, char **start, off_t off, int count,
1306                      int *eof, void *data)
1307 {
1308         int len = 0, l;
1309         off_t   begin = 0;
1310         struct slgt_info *info;
1311
1312         len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1313
1314         info = slgt_device_list;
1315         while( info ) {
1316                 l = line_info(page + len, info);
1317                 len += l;
1318                 if (len+begin > off+count)
1319                         goto done;
1320                 if (len+begin < off) {
1321                         begin += len;
1322                         len = 0;
1323                 }
1324                 info = info->next_device;
1325         }
1326
1327         *eof = 1;
1328 done:
1329         if (off >= len+begin)
1330                 return 0;
1331         *start = page + (off-begin);
1332         return ((count < begin+len-off) ? count : begin+len-off);
1333 }
1334
1335 /*
1336  * return count of bytes in transmit buffer
1337  */
1338 static int chars_in_buffer(struct tty_struct *tty)
1339 {
1340         struct slgt_info *info = tty->driver_data;
1341         int count;
1342         if (sanity_check(info, tty->name, "chars_in_buffer"))
1343                 return 0;
1344         count = tbuf_bytes(info);
1345         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1346         return count;
1347 }
1348
1349 /*
1350  * signal remote device to throttle send data (our receive data)
1351  */
1352 static void throttle(struct tty_struct * tty)
1353 {
1354         struct slgt_info *info = tty->driver_data;
1355         unsigned long flags;
1356
1357         if (sanity_check(info, tty->name, "throttle"))
1358                 return;
1359         DBGINFO(("%s throttle\n", info->device_name));
1360         if (I_IXOFF(tty))
1361                 send_xchar(tty, STOP_CHAR(tty));
1362         if (tty->termios->c_cflag & CRTSCTS) {
1363                 spin_lock_irqsave(&info->lock,flags);
1364                 info->signals &= ~SerialSignal_RTS;
1365                 set_signals(info);
1366                 spin_unlock_irqrestore(&info->lock,flags);
1367         }
1368 }
1369
1370 /*
1371  * signal remote device to stop throttling send data (our receive data)
1372  */
1373 static void unthrottle(struct tty_struct * tty)
1374 {
1375         struct slgt_info *info = tty->driver_data;
1376         unsigned long flags;
1377
1378         if (sanity_check(info, tty->name, "unthrottle"))
1379                 return;
1380         DBGINFO(("%s unthrottle\n", info->device_name));
1381         if (I_IXOFF(tty)) {
1382                 if (info->x_char)
1383                         info->x_char = 0;
1384                 else
1385                         send_xchar(tty, START_CHAR(tty));
1386         }
1387         if (tty->termios->c_cflag & CRTSCTS) {
1388                 spin_lock_irqsave(&info->lock,flags);
1389                 info->signals |= SerialSignal_RTS;
1390                 set_signals(info);
1391                 spin_unlock_irqrestore(&info->lock,flags);
1392         }
1393 }
1394
1395 /*
1396  * set or clear transmit break condition
1397  * break_state  -1=set break condition, 0=clear
1398  */
1399 static int set_break(struct tty_struct *tty, int break_state)
1400 {
1401         struct slgt_info *info = tty->driver_data;
1402         unsigned short value;
1403         unsigned long flags;
1404
1405         if (sanity_check(info, tty->name, "set_break"))
1406                 return -EINVAL;
1407         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1408
1409         spin_lock_irqsave(&info->lock,flags);
1410         value = rd_reg16(info, TCR);
1411         if (break_state == -1)
1412                 value |= BIT6;
1413         else
1414                 value &= ~BIT6;
1415         wr_reg16(info, TCR, value);
1416         spin_unlock_irqrestore(&info->lock,flags);
1417         return 0;
1418 }
1419
1420 #if SYNCLINK_GENERIC_HDLC
1421
1422 /**
1423  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1424  * set encoding and frame check sequence (FCS) options
1425  *
1426  * dev       pointer to network device structure
1427  * encoding  serial encoding setting
1428  * parity    FCS setting
1429  *
1430  * returns 0 if success, otherwise error code
1431  */
1432 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1433                           unsigned short parity)
1434 {
1435         struct slgt_info *info = dev_to_port(dev);
1436         unsigned char  new_encoding;
1437         unsigned short new_crctype;
1438
1439         /* return error if TTY interface open */
1440         if (info->port.count)
1441                 return -EBUSY;
1442
1443         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1444
1445         switch (encoding)
1446         {
1447         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1448         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1449         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1450         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1451         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1452         default: return -EINVAL;
1453         }
1454
1455         switch (parity)
1456         {
1457         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1458         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1459         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1460         default: return -EINVAL;
1461         }
1462
1463         info->params.encoding = new_encoding;
1464         info->params.crc_type = new_crctype;
1465
1466         /* if network interface up, reprogram hardware */
1467         if (info->netcount)
1468                 program_hw(info);
1469
1470         return 0;
1471 }
1472
1473 /**
1474  * called by generic HDLC layer to send frame
1475  *
1476  * skb  socket buffer containing HDLC frame
1477  * dev  pointer to network device structure
1478  *
1479  * returns 0 if success, otherwise error code
1480  */
1481 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1482 {
1483         struct slgt_info *info = dev_to_port(dev);
1484         unsigned long flags;
1485
1486         DBGINFO(("%s hdlc_xmit\n", dev->name));
1487
1488         /* stop sending until this frame completes */
1489         netif_stop_queue(dev);
1490
1491         /* copy data to device buffers */
1492         info->tx_count = skb->len;
1493         tx_load(info, skb->data, skb->len);
1494
1495         /* update network statistics */
1496         dev->stats.tx_packets++;
1497         dev->stats.tx_bytes += skb->len;
1498
1499         /* done with socket buffer, so free it */
1500         dev_kfree_skb(skb);
1501
1502         /* save start time for transmit timeout detection */
1503         dev->trans_start = jiffies;
1504
1505         /* start hardware transmitter if necessary */
1506         spin_lock_irqsave(&info->lock,flags);
1507         if (!info->tx_active)
1508                 tx_start(info);
1509         spin_unlock_irqrestore(&info->lock,flags);
1510
1511         return 0;
1512 }
1513
1514 /**
1515  * called by network layer when interface enabled
1516  * claim resources and initialize hardware
1517  *
1518  * dev  pointer to network device structure
1519  *
1520  * returns 0 if success, otherwise error code
1521  */
1522 static int hdlcdev_open(struct net_device *dev)
1523 {
1524         struct slgt_info *info = dev_to_port(dev);
1525         int rc;
1526         unsigned long flags;
1527
1528         if (!try_module_get(THIS_MODULE))
1529                 return -EBUSY;
1530
1531         DBGINFO(("%s hdlcdev_open\n", dev->name));
1532
1533         /* generic HDLC layer open processing */
1534         if ((rc = hdlc_open(dev)))
1535                 return rc;
1536
1537         /* arbitrate between network and tty opens */
1538         spin_lock_irqsave(&info->netlock, flags);
1539         if (info->port.count != 0 || info->netcount != 0) {
1540                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1541                 spin_unlock_irqrestore(&info->netlock, flags);
1542                 return -EBUSY;
1543         }
1544         info->netcount=1;
1545         spin_unlock_irqrestore(&info->netlock, flags);
1546
1547         /* claim resources and init adapter */
1548         if ((rc = startup(info)) != 0) {
1549                 spin_lock_irqsave(&info->netlock, flags);
1550                 info->netcount=0;
1551                 spin_unlock_irqrestore(&info->netlock, flags);
1552                 return rc;
1553         }
1554
1555         /* assert DTR and RTS, apply hardware settings */
1556         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1557         program_hw(info);
1558
1559         /* enable network layer transmit */
1560         dev->trans_start = jiffies;
1561         netif_start_queue(dev);
1562
1563         /* inform generic HDLC layer of current DCD status */
1564         spin_lock_irqsave(&info->lock, flags);
1565         get_signals(info);
1566         spin_unlock_irqrestore(&info->lock, flags);
1567         if (info->signals & SerialSignal_DCD)
1568                 netif_carrier_on(dev);
1569         else
1570                 netif_carrier_off(dev);
1571         return 0;
1572 }
1573
1574 /**
1575  * called by network layer when interface is disabled
1576  * shutdown hardware and release resources
1577  *
1578  * dev  pointer to network device structure
1579  *
1580  * returns 0 if success, otherwise error code
1581  */
1582 static int hdlcdev_close(struct net_device *dev)
1583 {
1584         struct slgt_info *info = dev_to_port(dev);
1585         unsigned long flags;
1586
1587         DBGINFO(("%s hdlcdev_close\n", dev->name));
1588
1589         netif_stop_queue(dev);
1590
1591         /* shutdown adapter and release resources */
1592         shutdown(info);
1593
1594         hdlc_close(dev);
1595
1596         spin_lock_irqsave(&info->netlock, flags);
1597         info->netcount=0;
1598         spin_unlock_irqrestore(&info->netlock, flags);
1599
1600         module_put(THIS_MODULE);
1601         return 0;
1602 }
1603
1604 /**
1605  * called by network layer to process IOCTL call to network device
1606  *
1607  * dev  pointer to network device structure
1608  * ifr  pointer to network interface request structure
1609  * cmd  IOCTL command code
1610  *
1611  * returns 0 if success, otherwise error code
1612  */
1613 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1614 {
1615         const size_t size = sizeof(sync_serial_settings);
1616         sync_serial_settings new_line;
1617         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1618         struct slgt_info *info = dev_to_port(dev);
1619         unsigned int flags;
1620
1621         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1622
1623         /* return error if TTY interface open */
1624         if (info->port.count)
1625                 return -EBUSY;
1626
1627         if (cmd != SIOCWANDEV)
1628                 return hdlc_ioctl(dev, ifr, cmd);
1629
1630         switch(ifr->ifr_settings.type) {
1631         case IF_GET_IFACE: /* return current sync_serial_settings */
1632
1633                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1634                 if (ifr->ifr_settings.size < size) {
1635                         ifr->ifr_settings.size = size; /* data size wanted */
1636                         return -ENOBUFS;
1637                 }
1638
1639                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1640                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1641                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1642                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1643
1644                 switch (flags){
1645                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1646                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1647                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1648                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1649                 default: new_line.clock_type = CLOCK_DEFAULT;
1650                 }
1651
1652                 new_line.clock_rate = info->params.clock_speed;
1653                 new_line.loopback   = info->params.loopback ? 1:0;
1654
1655                 if (copy_to_user(line, &new_line, size))
1656                         return -EFAULT;
1657                 return 0;
1658
1659         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1660
1661                 if(!capable(CAP_NET_ADMIN))
1662                         return -EPERM;
1663                 if (copy_from_user(&new_line, line, size))
1664                         return -EFAULT;
1665
1666                 switch (new_line.clock_type)
1667                 {
1668                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1669                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1670                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1671                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1672                 case CLOCK_DEFAULT:  flags = info->params.flags &
1673                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1674                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1675                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1676                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1677                 default: return -EINVAL;
1678                 }
1679
1680                 if (new_line.loopback != 0 && new_line.loopback != 1)
1681                         return -EINVAL;
1682
1683                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1684                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1685                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1686                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1687                 info->params.flags |= flags;
1688
1689                 info->params.loopback = new_line.loopback;
1690
1691                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1692                         info->params.clock_speed = new_line.clock_rate;
1693                 else
1694                         info->params.clock_speed = 0;
1695
1696                 /* if network interface up, reprogram hardware */
1697                 if (info->netcount)
1698                         program_hw(info);
1699                 return 0;
1700
1701         default:
1702                 return hdlc_ioctl(dev, ifr, cmd);
1703         }
1704 }
1705
1706 /**
1707  * called by network layer when transmit timeout is detected
1708  *
1709  * dev  pointer to network device structure
1710  */
1711 static void hdlcdev_tx_timeout(struct net_device *dev)
1712 {
1713         struct slgt_info *info = dev_to_port(dev);
1714         unsigned long flags;
1715
1716         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1717
1718         dev->stats.tx_errors++;
1719         dev->stats.tx_aborted_errors++;
1720
1721         spin_lock_irqsave(&info->lock,flags);
1722         tx_stop(info);
1723         spin_unlock_irqrestore(&info->lock,flags);
1724
1725         netif_wake_queue(dev);
1726 }
1727
1728 /**
1729  * called by device driver when transmit completes
1730  * reenable network layer transmit if stopped
1731  *
1732  * info  pointer to device instance information
1733  */
1734 static void hdlcdev_tx_done(struct slgt_info *info)
1735 {
1736         if (netif_queue_stopped(info->netdev))
1737                 netif_wake_queue(info->netdev);
1738 }
1739
1740 /**
1741  * called by device driver when frame received
1742  * pass frame to network layer
1743  *
1744  * info  pointer to device instance information
1745  * buf   pointer to buffer contianing frame data
1746  * size  count of data bytes in buf
1747  */
1748 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1749 {
1750         struct sk_buff *skb = dev_alloc_skb(size);
1751         struct net_device *dev = info->netdev;
1752
1753         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1754
1755         if (skb == NULL) {
1756                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1757                 dev->stats.rx_dropped++;
1758                 return;
1759         }
1760
1761         memcpy(skb_put(skb, size), buf, size);
1762
1763         skb->protocol = hdlc_type_trans(skb, dev);
1764
1765         dev->stats.rx_packets++;
1766         dev->stats.rx_bytes += size;
1767
1768         netif_rx(skb);
1769
1770         dev->last_rx = jiffies;
1771 }
1772
1773 /**
1774  * called by device driver when adding device instance
1775  * do generic HDLC initialization
1776  *
1777  * info  pointer to device instance information
1778  *
1779  * returns 0 if success, otherwise error code
1780  */
1781 static int hdlcdev_init(struct slgt_info *info)
1782 {
1783         int rc;
1784         struct net_device *dev;
1785         hdlc_device *hdlc;
1786
1787         /* allocate and initialize network and HDLC layer objects */
1788
1789         if (!(dev = alloc_hdlcdev(info))) {
1790                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1791                 return -ENOMEM;
1792         }
1793
1794         /* for network layer reporting purposes only */
1795         dev->mem_start = info->phys_reg_addr;
1796         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1797         dev->irq       = info->irq_level;
1798
1799         /* network layer callbacks and settings */
1800         dev->do_ioctl       = hdlcdev_ioctl;
1801         dev->open           = hdlcdev_open;
1802         dev->stop           = hdlcdev_close;
1803         dev->tx_timeout     = hdlcdev_tx_timeout;
1804         dev->watchdog_timeo = 10*HZ;
1805         dev->tx_queue_len   = 50;
1806
1807         /* generic HDLC layer callbacks and settings */
1808         hdlc         = dev_to_hdlc(dev);
1809         hdlc->attach = hdlcdev_attach;
1810         hdlc->xmit   = hdlcdev_xmit;
1811
1812         /* register objects with HDLC layer */
1813         if ((rc = register_hdlc_device(dev))) {
1814                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1815                 free_netdev(dev);
1816                 return rc;
1817         }
1818
1819         info->netdev = dev;
1820         return 0;
1821 }
1822
1823 /**
1824  * called by device driver when removing device instance
1825  * do generic HDLC cleanup
1826  *
1827  * info  pointer to device instance information
1828  */
1829 static void hdlcdev_exit(struct slgt_info *info)
1830 {
1831         unregister_hdlc_device(info->netdev);
1832         free_netdev(info->netdev);
1833         info->netdev = NULL;
1834 }
1835
1836 #endif /* ifdef CONFIG_HDLC */
1837
1838 /*
1839  * get async data from rx DMA buffers
1840  */
1841 static void rx_async(struct slgt_info *info)
1842 {
1843         struct tty_struct *tty = info->port.tty;
1844         struct mgsl_icount *icount = &info->icount;
1845         unsigned int start, end;
1846         unsigned char *p;
1847         unsigned char status;
1848         struct slgt_desc *bufs = info->rbufs;
1849         int i, count;
1850         int chars = 0;
1851         int stat;
1852         unsigned char ch;
1853
1854         start = end = info->rbuf_current;
1855
1856         while(desc_complete(bufs[end])) {
1857                 count = desc_count(bufs[end]) - info->rbuf_index;
1858                 p     = bufs[end].buf + info->rbuf_index;
1859
1860                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1861                 DBGDATA(info, p, count, "rx");
1862
1863                 for(i=0 ; i < count; i+=2, p+=2) {
1864                         ch = *p;
1865                         icount->rx++;
1866
1867                         stat = 0;
1868
1869                         if ((status = *(p+1) & (BIT1 + BIT0))) {
1870                                 if (status & BIT1)
1871                                         icount->parity++;
1872                                 else if (status & BIT0)
1873                                         icount->frame++;
1874                                 /* discard char if tty control flags say so */
1875                                 if (status & info->ignore_status_mask)
1876                                         continue;
1877                                 if (status & BIT1)
1878                                         stat = TTY_PARITY;
1879                                 else if (status & BIT0)
1880                                         stat = TTY_FRAME;
1881                         }
1882                         if (tty) {
1883                                 tty_insert_flip_char(tty, ch, stat);
1884                                 chars++;
1885                         }
1886                 }
1887
1888                 if (i < count) {
1889                         /* receive buffer not completed */
1890                         info->rbuf_index += i;
1891                         mod_timer(&info->rx_timer, jiffies + 1);
1892                         break;
1893                 }
1894
1895                 info->rbuf_index = 0;
1896                 free_rbufs(info, end, end);
1897
1898                 if (++end == info->rbuf_count)
1899                         end = 0;
1900
1901                 /* if entire list searched then no frame available */
1902                 if (end == start)
1903                         break;
1904         }
1905
1906         if (tty && chars)
1907                 tty_flip_buffer_push(tty);
1908 }
1909
1910 /*
1911  * return next bottom half action to perform
1912  */
1913 static int bh_action(struct slgt_info *info)
1914 {
1915         unsigned long flags;
1916         int rc;
1917
1918         spin_lock_irqsave(&info->lock,flags);
1919
1920         if (info->pending_bh & BH_RECEIVE) {
1921                 info->pending_bh &= ~BH_RECEIVE;
1922                 rc = BH_RECEIVE;
1923         } else if (info->pending_bh & BH_TRANSMIT) {
1924                 info->pending_bh &= ~BH_TRANSMIT;
1925                 rc = BH_TRANSMIT;
1926         } else if (info->pending_bh & BH_STATUS) {
1927                 info->pending_bh &= ~BH_STATUS;
1928                 rc = BH_STATUS;
1929         } else {
1930                 /* Mark BH routine as complete */
1931                 info->bh_running = false;
1932                 info->bh_requested = false;
1933                 rc = 0;
1934         }
1935
1936         spin_unlock_irqrestore(&info->lock,flags);
1937
1938         return rc;
1939 }
1940
1941 /*
1942  * perform bottom half processing
1943  */
1944 static void bh_handler(struct work_struct *work)
1945 {
1946         struct slgt_info *info = container_of(work, struct slgt_info, task);
1947         int action;
1948
1949         if (!info)
1950                 return;
1951         info->bh_running = true;
1952
1953         while((action = bh_action(info))) {
1954                 switch (action) {
1955                 case BH_RECEIVE:
1956                         DBGBH(("%s bh receive\n", info->device_name));
1957                         switch(info->params.mode) {
1958                         case MGSL_MODE_ASYNC:
1959                                 rx_async(info);
1960                                 break;
1961                         case MGSL_MODE_HDLC:
1962                                 while(rx_get_frame(info));
1963                                 break;
1964                         case MGSL_MODE_RAW:
1965                         case MGSL_MODE_MONOSYNC:
1966                         case MGSL_MODE_BISYNC:
1967                                 while(rx_get_buf(info));
1968                                 break;
1969                         }
1970                         /* restart receiver if rx DMA buffers exhausted */
1971                         if (info->rx_restart)
1972                                 rx_start(info);
1973                         break;
1974                 case BH_TRANSMIT:
1975                         bh_transmit(info);
1976                         break;
1977                 case BH_STATUS:
1978                         DBGBH(("%s bh status\n", info->device_name));
1979                         info->ri_chkcount = 0;
1980                         info->dsr_chkcount = 0;
1981                         info->dcd_chkcount = 0;
1982                         info->cts_chkcount = 0;
1983                         break;
1984                 default:
1985                         DBGBH(("%s unknown action\n", info->device_name));
1986                         break;
1987                 }
1988         }
1989         DBGBH(("%s bh_handler exit\n", info->device_name));
1990 }
1991
1992 static void bh_transmit(struct slgt_info *info)
1993 {
1994         struct tty_struct *tty = info->port.tty;
1995
1996         DBGBH(("%s bh_transmit\n", info->device_name));
1997         if (tty)
1998                 tty_wakeup(tty);
1999 }
2000
2001 static void dsr_change(struct slgt_info *info, unsigned short status)
2002 {
2003         if (status & BIT3) {
2004                 info->signals |= SerialSignal_DSR;
2005                 info->input_signal_events.dsr_up++;
2006         } else {
2007                 info->signals &= ~SerialSignal_DSR;
2008                 info->input_signal_events.dsr_down++;
2009         }
2010         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2011         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2012                 slgt_irq_off(info, IRQ_DSR);
2013                 return;
2014         }
2015         info->icount.dsr++;
2016         wake_up_interruptible(&info->status_event_wait_q);
2017         wake_up_interruptible(&info->event_wait_q);
2018         info->pending_bh |= BH_STATUS;
2019 }
2020
2021 static void cts_change(struct slgt_info *info, unsigned short status)
2022 {
2023         if (status & BIT2) {
2024                 info->signals |= SerialSignal_CTS;
2025                 info->input_signal_events.cts_up++;
2026         } else {
2027                 info->signals &= ~SerialSignal_CTS;
2028                 info->input_signal_events.cts_down++;
2029         }
2030         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2031         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2032                 slgt_irq_off(info, IRQ_CTS);
2033                 return;
2034         }
2035         info->icount.cts++;
2036         wake_up_interruptible(&info->status_event_wait_q);
2037         wake_up_interruptible(&info->event_wait_q);
2038         info->pending_bh |= BH_STATUS;
2039
2040         if (info->port.flags & ASYNC_CTS_FLOW) {
2041                 if (info->port.tty) {
2042                         if (info->port.tty->hw_stopped) {
2043                                 if (info->signals & SerialSignal_CTS) {
2044                                         info->port.tty->hw_stopped = 0;
2045                                         info->pending_bh |= BH_TRANSMIT;
2046                                         return;
2047                                 }
2048                         } else {
2049                                 if (!(info->signals & SerialSignal_CTS))
2050                                         info->port.tty->hw_stopped = 1;
2051                         }
2052                 }
2053         }
2054 }
2055
2056 static void dcd_change(struct slgt_info *info, unsigned short status)
2057 {
2058         if (status & BIT1) {
2059                 info->signals |= SerialSignal_DCD;
2060                 info->input_signal_events.dcd_up++;
2061         } else {
2062                 info->signals &= ~SerialSignal_DCD;
2063                 info->input_signal_events.dcd_down++;
2064         }
2065         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2066         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2067                 slgt_irq_off(info, IRQ_DCD);
2068                 return;
2069         }
2070         info->icount.dcd++;
2071 #if SYNCLINK_GENERIC_HDLC
2072         if (info->netcount) {
2073                 if (info->signals & SerialSignal_DCD)
2074                         netif_carrier_on(info->netdev);
2075                 else
2076                         netif_carrier_off(info->netdev);
2077         }
2078 #endif
2079         wake_up_interruptible(&info->status_event_wait_q);
2080         wake_up_interruptible(&info->event_wait_q);
2081         info->pending_bh |= BH_STATUS;
2082
2083         if (info->port.flags & ASYNC_CHECK_CD) {
2084                 if (info->signals & SerialSignal_DCD)
2085                         wake_up_interruptible(&info->port.open_wait);
2086                 else {
2087                         if (info->port.tty)
2088                                 tty_hangup(info->port.tty);
2089                 }
2090         }
2091 }
2092
2093 static void ri_change(struct slgt_info *info, unsigned short status)
2094 {
2095         if (status & BIT0) {
2096                 info->signals |= SerialSignal_RI;
2097                 info->input_signal_events.ri_up++;
2098         } else {
2099                 info->signals &= ~SerialSignal_RI;
2100                 info->input_signal_events.ri_down++;
2101         }
2102         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2103         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2104                 slgt_irq_off(info, IRQ_RI);
2105                 return;
2106         }
2107         info->icount.rng++;
2108         wake_up_interruptible(&info->status_event_wait_q);
2109         wake_up_interruptible(&info->event_wait_q);
2110         info->pending_bh |= BH_STATUS;
2111 }
2112
2113 static void isr_serial(struct slgt_info *info)
2114 {
2115         unsigned short status = rd_reg16(info, SSR);
2116
2117         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2118
2119         wr_reg16(info, SSR, status); /* clear pending */
2120
2121         info->irq_occurred = true;
2122
2123         if (info->params.mode == MGSL_MODE_ASYNC) {
2124                 if (status & IRQ_TXIDLE) {
2125                         if (info->tx_count)
2126                                 isr_txeom(info, status);
2127                 }
2128                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2129                         info->icount.brk++;
2130                         /* process break detection if tty control allows */
2131                         if (info->port.tty) {
2132                                 if (!(status & info->ignore_status_mask)) {
2133                                         if (info->read_status_mask & MASK_BREAK) {
2134                                                 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2135                                                 if (info->port.flags & ASYNC_SAK)
2136                                                         do_SAK(info->port.tty);
2137                                         }
2138                                 }
2139                         }
2140                 }
2141         } else {
2142                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2143                         isr_txeom(info, status);
2144
2145                 if (status & IRQ_RXIDLE) {
2146                         if (status & RXIDLE)
2147                                 info->icount.rxidle++;
2148                         else
2149                                 info->icount.exithunt++;
2150                         wake_up_interruptible(&info->event_wait_q);
2151                 }
2152
2153                 if (status & IRQ_RXOVER)
2154                         rx_start(info);
2155         }
2156
2157         if (status & IRQ_DSR)
2158                 dsr_change(info, status);
2159         if (status & IRQ_CTS)
2160                 cts_change(info, status);
2161         if (status & IRQ_DCD)
2162                 dcd_change(info, status);
2163         if (status & IRQ_RI)
2164                 ri_change(info, status);
2165 }
2166
2167 static void isr_rdma(struct slgt_info *info)
2168 {
2169         unsigned int status = rd_reg32(info, RDCSR);
2170
2171         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2172
2173         /* RDCSR (rx DMA control/status)
2174          *
2175          * 31..07  reserved
2176          * 06      save status byte to DMA buffer
2177          * 05      error
2178          * 04      eol (end of list)
2179          * 03      eob (end of buffer)
2180          * 02      IRQ enable
2181          * 01      reset
2182          * 00      enable
2183          */
2184         wr_reg32(info, RDCSR, status);  /* clear pending */
2185
2186         if (status & (BIT5 + BIT4)) {
2187                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2188                 info->rx_restart = true;
2189         }
2190         info->pending_bh |= BH_RECEIVE;
2191 }
2192
2193 static void isr_tdma(struct slgt_info *info)
2194 {
2195         unsigned int status = rd_reg32(info, TDCSR);
2196
2197         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2198
2199         /* TDCSR (tx DMA control/status)
2200          *
2201          * 31..06  reserved
2202          * 05      error
2203          * 04      eol (end of list)
2204          * 03      eob (end of buffer)
2205          * 02      IRQ enable
2206          * 01      reset
2207          * 00      enable
2208          */
2209         wr_reg32(info, TDCSR, status);  /* clear pending */
2210
2211         if (status & (BIT5 + BIT4 + BIT3)) {
2212                 // another transmit buffer has completed
2213                 // run bottom half to get more send data from user
2214                 info->pending_bh |= BH_TRANSMIT;
2215         }
2216 }
2217
2218 static void isr_txeom(struct slgt_info *info, unsigned short status)
2219 {
2220         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2221
2222         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2223         tdma_reset(info);
2224         reset_tbufs(info);
2225         if (status & IRQ_TXUNDER) {
2226                 unsigned short val = rd_reg16(info, TCR);
2227                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2228                 wr_reg16(info, TCR, val); /* clear reset bit */
2229         }
2230
2231         if (info->tx_active) {
2232                 if (info->params.mode != MGSL_MODE_ASYNC) {
2233                         if (status & IRQ_TXUNDER)
2234                                 info->icount.txunder++;
2235                         else if (status & IRQ_TXIDLE)
2236                                 info->icount.txok++;
2237                 }
2238
2239                 info->tx_active = false;
2240                 info->tx_count = 0;
2241
2242                 del_timer(&info->tx_timer);
2243
2244                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2245                         info->signals &= ~SerialSignal_RTS;
2246                         info->drop_rts_on_tx_done = false;
2247                         set_signals(info);
2248                 }
2249
2250 #if SYNCLINK_GENERIC_HDLC
2251                 if (info->netcount)
2252                         hdlcdev_tx_done(info);
2253                 else
2254 #endif
2255                 {
2256                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2257                                 tx_stop(info);
2258                                 return;
2259                         }
2260                         info->pending_bh |= BH_TRANSMIT;
2261                 }
2262         }
2263 }
2264
2265 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2266 {
2267         struct cond_wait *w, *prev;
2268
2269         /* wake processes waiting for specific transitions */
2270         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2271                 if (w->data & changed) {
2272                         w->data = state;
2273                         wake_up_interruptible(&w->q);
2274                         if (prev != NULL)
2275                                 prev->next = w->next;
2276                         else
2277                                 info->gpio_wait_q = w->next;
2278                 } else
2279                         prev = w;
2280         }
2281 }
2282
2283 /* interrupt service routine
2284  *
2285  *      irq     interrupt number
2286  *      dev_id  device ID supplied during interrupt registration
2287  */
2288 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2289 {
2290         struct slgt_info *info = dev_id;
2291         unsigned int gsr;
2292         unsigned int i;
2293
2294         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2295
2296         spin_lock(&info->lock);
2297
2298         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2299                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2300                 info->irq_occurred = true;
2301                 for(i=0; i < info->port_count ; i++) {
2302                         if (info->port_array[i] == NULL)
2303                                 continue;
2304                         if (gsr & (BIT8 << i))
2305                                 isr_serial(info->port_array[i]);
2306                         if (gsr & (BIT16 << (i*2)))
2307                                 isr_rdma(info->port_array[i]);
2308                         if (gsr & (BIT17 << (i*2)))
2309                                 isr_tdma(info->port_array[i]);
2310                 }
2311         }
2312
2313         if (info->gpio_present) {
2314                 unsigned int state;
2315                 unsigned int changed;
2316                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2317                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2318                         /* read latched state of GPIO signals */
2319                         state = rd_reg32(info, IOVR);
2320                         /* clear pending GPIO interrupt bits */
2321                         wr_reg32(info, IOSR, changed);
2322                         for (i=0 ; i < info->port_count ; i++) {
2323                                 if (info->port_array[i] != NULL)
2324                                         isr_gpio(info->port_array[i], changed, state);
2325                         }
2326                 }
2327         }
2328
2329         for(i=0; i < info->port_count ; i++) {
2330                 struct slgt_info *port = info->port_array[i];
2331
2332                 if (port && (port->port.count || port->netcount) &&
2333                     port->pending_bh && !port->bh_running &&
2334                     !port->bh_requested) {
2335                         DBGISR(("%s bh queued\n", port->device_name));
2336                         schedule_work(&port->task);
2337                         port->bh_requested = true;
2338                 }
2339         }
2340
2341         spin_unlock(&info->lock);
2342
2343         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2344         return IRQ_HANDLED;
2345 }
2346
2347 static int startup(struct slgt_info *info)
2348 {
2349         DBGINFO(("%s startup\n", info->device_name));
2350
2351         if (info->port.flags & ASYNC_INITIALIZED)
2352                 return 0;
2353
2354         if (!info->tx_buf) {
2355                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2356                 if (!info->tx_buf) {
2357                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2358                         return -ENOMEM;
2359                 }
2360         }
2361
2362         info->pending_bh = 0;
2363
2364         memset(&info->icount, 0, sizeof(info->icount));
2365
2366         /* program hardware for current parameters */
2367         change_params(info);
2368
2369         if (info->port.tty)
2370                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2371
2372         info->port.flags |= ASYNC_INITIALIZED;
2373
2374         return 0;
2375 }
2376
2377 /*
2378  *  called by close() and hangup() to shutdown hardware
2379  */
2380 static void shutdown(struct slgt_info *info)
2381 {
2382         unsigned long flags;
2383
2384         if (!(info->port.flags & ASYNC_INITIALIZED))
2385                 return;
2386
2387         DBGINFO(("%s shutdown\n", info->device_name));
2388
2389         /* clear status wait queue because status changes */
2390         /* can't happen after shutting down the hardware */
2391         wake_up_interruptible(&info->status_event_wait_q);
2392         wake_up_interruptible(&info->event_wait_q);
2393
2394         del_timer_sync(&info->tx_timer);
2395         del_timer_sync(&info->rx_timer);
2396
2397         kfree(info->tx_buf);
2398         info->tx_buf = NULL;
2399
2400         spin_lock_irqsave(&info->lock,flags);
2401
2402         tx_stop(info);
2403         rx_stop(info);
2404
2405         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2406
2407         if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2408                 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2409                 set_signals(info);
2410         }
2411
2412         flush_cond_wait(&info->gpio_wait_q);
2413
2414         spin_unlock_irqrestore(&info->lock,flags);
2415
2416         if (info->port.tty)
2417                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2418
2419         info->port.flags &= ~ASYNC_INITIALIZED;
2420 }
2421
2422 static void program_hw(struct slgt_info *info)
2423 {
2424         unsigned long flags;
2425
2426         spin_lock_irqsave(&info->lock,flags);
2427
2428         rx_stop(info);
2429         tx_stop(info);
2430
2431         if (info->params.mode != MGSL_MODE_ASYNC ||
2432             info->netcount)
2433                 sync_mode(info);
2434         else
2435                 async_mode(info);
2436
2437         set_signals(info);
2438
2439         info->dcd_chkcount = 0;
2440         info->cts_chkcount = 0;
2441         info->ri_chkcount = 0;
2442         info->dsr_chkcount = 0;
2443
2444         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2445         get_signals(info);
2446
2447         if (info->netcount ||
2448             (info->port.tty && info->port.tty->termios->c_cflag & CREAD))
2449                 rx_start(info);
2450
2451         spin_unlock_irqrestore(&info->lock,flags);
2452 }
2453
2454 /*
2455  * reconfigure adapter based on new parameters
2456  */
2457 static void change_params(struct slgt_info *info)
2458 {
2459         unsigned cflag;
2460         int bits_per_char;
2461
2462         if (!info->port.tty || !info->port.tty->termios)
2463                 return;
2464         DBGINFO(("%s change_params\n", info->device_name));
2465
2466         cflag = info->port.tty->termios->c_cflag;
2467
2468         /* if B0 rate (hangup) specified then negate DTR and RTS */
2469         /* otherwise assert DTR and RTS */
2470         if (cflag & CBAUD)
2471                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2472         else
2473                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2474
2475         /* byte size and parity */
2476
2477         switch (cflag & CSIZE) {
2478         case CS5: info->params.data_bits = 5; break;
2479         case CS6: info->params.data_bits = 6; break;
2480         case CS7: info->params.data_bits = 7; break;
2481         case CS8: info->params.data_bits = 8; break;
2482         default:  info->params.data_bits = 7; break;
2483         }
2484
2485         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2486
2487         if (cflag & PARENB)
2488                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2489         else
2490                 info->params.parity = ASYNC_PARITY_NONE;
2491
2492         /* calculate number of jiffies to transmit a full
2493          * FIFO (32 bytes) at specified data rate
2494          */
2495         bits_per_char = info->params.data_bits +
2496                         info->params.stop_bits + 1;
2497
2498         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2499
2500         if (info->params.data_rate) {
2501                 info->timeout = (32*HZ*bits_per_char) /
2502                                 info->params.data_rate;
2503         }
2504         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2505
2506         if (cflag & CRTSCTS)
2507                 info->port.flags |= ASYNC_CTS_FLOW;
2508         else
2509                 info->port.flags &= ~ASYNC_CTS_FLOW;
2510
2511         if (cflag & CLOCAL)
2512                 info->port.flags &= ~ASYNC_CHECK_CD;
2513         else
2514                 info->port.flags |= ASYNC_CHECK_CD;
2515
2516         /* process tty input control flags */
2517
2518         info->read_status_mask = IRQ_RXOVER;
2519         if (I_INPCK(info->port.tty))
2520                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2521         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2522                 info->read_status_mask |= MASK_BREAK;
2523         if (I_IGNPAR(info->port.tty))
2524                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2525         if (I_IGNBRK(info->port.tty)) {
2526                 info->ignore_status_mask |= MASK_BREAK;
2527                 /* If ignoring parity and break indicators, ignore
2528                  * overruns too.  (For real raw support).
2529                  */
2530                 if (I_IGNPAR(info->port.tty))
2531                         info->ignore_status_mask |= MASK_OVERRUN;
2532         }
2533
2534         program_hw(info);
2535 }
2536
2537 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2538 {
2539         DBGINFO(("%s get_stats\n",  info->device_name));
2540         if (!user_icount) {
2541                 memset(&info->icount, 0, sizeof(info->icount));
2542         } else {
2543                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2544                         return -EFAULT;
2545         }
2546         return 0;
2547 }
2548
2549 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2550 {
2551         DBGINFO(("%s get_params\n", info->device_name));
2552         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2553                 return -EFAULT;
2554         return 0;
2555 }
2556
2557 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2558 {
2559         unsigned long flags;
2560         MGSL_PARAMS tmp_params;
2561
2562         DBGINFO(("%s set_params\n", info->device_name));
2563         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2564                 return -EFAULT;
2565
2566         spin_lock_irqsave(&info->lock, flags);
2567         memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2568         spin_unlock_irqrestore(&info->lock, flags);
2569
2570         change_params(info);
2571
2572         return 0;
2573 }
2574
2575 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2576 {
2577         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2578         if (put_user(info->idle_mode, idle_mode))
2579                 return -EFAULT;
2580         return 0;
2581 }
2582
2583 static int set_txidle(struct slgt_info *info, int idle_mode)
2584 {
2585         unsigned long flags;
2586         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2587         spin_lock_irqsave(&info->lock,flags);
2588         info->idle_mode = idle_mode;
2589         if (info->params.mode != MGSL_MODE_ASYNC)
2590                 tx_set_idle(info);
2591         spin_unlock_irqrestore(&info->lock,flags);
2592         return 0;
2593 }
2594
2595 static int tx_enable(struct slgt_info *info, int enable)
2596 {
2597         unsigned long flags;
2598         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2599         spin_lock_irqsave(&info->lock,flags);
2600         if (enable) {
2601                 if (!info->tx_enabled)
2602                         tx_start(info);
2603         } else {
2604                 if (info->tx_enabled)
2605                         tx_stop(info);
2606         }
2607         spin_unlock_irqrestore(&info->lock,flags);
2608         return 0;
2609 }
2610
2611 /*
2612  * abort transmit HDLC frame
2613  */
2614 static int tx_abort(struct slgt_info *info)
2615 {
2616         unsigned long flags;
2617         DBGINFO(("%s tx_abort\n", info->device_name));
2618         spin_lock_irqsave(&info->lock,flags);
2619         tdma_reset(info);
2620         spin_unlock_irqrestore(&info->lock,flags);
2621         return 0;
2622 }
2623
2624 static int rx_enable(struct slgt_info *info, int enable)
2625 {
2626         unsigned long flags;
2627         unsigned int rbuf_fill_level;
2628         DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2629         spin_lock_irqsave(&info->lock,flags);
2630         /*
2631          * enable[31..16] = receive DMA buffer fill level
2632          * 0 = noop (leave fill level unchanged)
2633          * fill level must be multiple of 4 and <= buffer size
2634          */
2635         rbuf_fill_level = ((unsigned int)enable) >> 16;
2636         if (rbuf_fill_level) {
2637                 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2638                         spin_unlock_irqrestore(&info->lock, flags);
2639                         return -EINVAL;
2640                 }
2641                 info->rbuf_fill_level = rbuf_fill_level;
2642                 rx_stop(info); /* restart receiver to use new fill level */
2643         }
2644
2645         /*
2646          * enable[1..0] = receiver enable command
2647          * 0 = disable
2648          * 1 = enable
2649          * 2 = enable or force hunt mode if already enabled
2650          */
2651         enable &= 3;
2652         if (enable) {
2653                 if (!info->rx_enabled)
2654                         rx_start(info);
2655                 else if (enable == 2) {
2656                         /* force hunt mode (write 1 to RCR[3]) */
2657                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2658                 }
2659         } else {
2660                 if (info->rx_enabled)
2661                         rx_stop(info);
2662         }
2663         spin_unlock_irqrestore(&info->lock,flags);
2664         return 0;
2665 }
2666
2667 /*
2668  *  wait for specified event to occur
2669  */
2670 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2671 {
2672         unsigned long flags;
2673         int s;
2674         int rc=0;
2675         struct mgsl_icount cprev, cnow;
2676         int events;
2677         int mask;
2678         struct  _input_signal_events oldsigs, newsigs;
2679         DECLARE_WAITQUEUE(wait, current);
2680
2681         if (get_user(mask, mask_ptr))
2682                 return -EFAULT;
2683
2684         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2685
2686         spin_lock_irqsave(&info->lock,flags);
2687
2688         /* return immediately if state matches requested events */
2689         get_signals(info);
2690         s = info->signals;
2691
2692         events = mask &
2693                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2694                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2695                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2696                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2697         if (events) {
2698                 spin_unlock_irqrestore(&info->lock,flags);
2699                 goto exit;
2700         }
2701
2702         /* save current irq counts */
2703         cprev = info->icount;
2704         oldsigs = info->input_signal_events;
2705
2706         /* enable hunt and idle irqs if needed */
2707         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2708                 unsigned short val = rd_reg16(info, SCR);
2709                 if (!(val & IRQ_RXIDLE))
2710                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2711         }
2712
2713         set_current_state(TASK_INTERRUPTIBLE);
2714         add_wait_queue(&info->event_wait_q, &wait);
2715
2716         spin_unlock_irqrestore(&info->lock,flags);
2717
2718         for(;;) {
2719                 schedule();
2720                 if (signal_pending(current)) {
2721                         rc = -ERESTARTSYS;
2722                         break;
2723                 }
2724
2725                 /* get current irq counts */
2726                 spin_lock_irqsave(&info->lock,flags);
2727                 cnow = info->icount;
2728                 newsigs = info->input_signal_events;
2729                 set_current_state(TASK_INTERRUPTIBLE);
2730                 spin_unlock_irqrestore(&info->lock,flags);
2731
2732                 /* if no change, wait aborted for some reason */
2733                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2734                     newsigs.dsr_down == oldsigs.dsr_down &&
2735                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2736                     newsigs.dcd_down == oldsigs.dcd_down &&
2737                     newsigs.cts_up   == oldsigs.cts_up   &&
2738                     newsigs.cts_down == oldsigs.cts_down &&
2739                     newsigs.ri_up    == oldsigs.ri_up    &&
2740                     newsigs.ri_down  == oldsigs.ri_down  &&
2741                     cnow.exithunt    == cprev.exithunt   &&
2742                     cnow.rxidle      == cprev.rxidle) {
2743                         rc = -EIO;
2744                         break;
2745                 }
2746
2747                 events = mask &
2748                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2749                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2750                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2751                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2752                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2753                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2754                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2755                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2756                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2757                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2758                 if (events)
2759                         break;
2760
2761                 cprev = cnow;
2762                 oldsigs = newsigs;
2763         }
2764
2765         remove_wait_queue(&info->event_wait_q, &wait);
2766         set_current_state(TASK_RUNNING);
2767
2768
2769         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2770                 spin_lock_irqsave(&info->lock,flags);
2771                 if (!waitqueue_active(&info->event_wait_q)) {
2772                         /* disable enable exit hunt mode/idle rcvd IRQs */
2773                         wr_reg16(info, SCR,
2774                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2775                 }
2776                 spin_unlock_irqrestore(&info->lock,flags);
2777         }
2778 exit:
2779         if (rc == 0)
2780                 rc = put_user(events, mask_ptr);
2781         return rc;
2782 }
2783
2784 static int get_interface(struct slgt_info *info, int __user *if_mode)
2785 {
2786         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2787         if (put_user(info->if_mode, if_mode))
2788                 return -EFAULT;
2789         return 0;
2790 }
2791
2792 static int set_interface(struct slgt_info *info, int if_mode)
2793 {
2794         unsigned long flags;
2795         unsigned short val;
2796
2797         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2798         spin_lock_irqsave(&info->lock,flags);
2799         info->if_mode = if_mode;
2800
2801         msc_set_vcr(info);
2802
2803         /* TCR (tx control) 07  1=RTS driver control */
2804         val = rd_reg16(info, TCR);
2805         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2806                 val |= BIT7;
2807         else
2808                 val &= ~BIT7;
2809         wr_reg16(info, TCR, val);
2810
2811         spin_unlock_irqrestore(&info->lock,flags);
2812         return 0;
2813 }
2814
2815 /*
2816  * set general purpose IO pin state and direction
2817  *
2818  * user_gpio fields:
2819  * state   each bit indicates a pin state
2820  * smask   set bit indicates pin state to set
2821  * dir     each bit indicates a pin direction (0=input, 1=output)
2822  * dmask   set bit indicates pin direction to set
2823  */
2824 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2825 {
2826         unsigned long flags;
2827         struct gpio_desc gpio;
2828         __u32 data;
2829
2830         if (!info->gpio_present)
2831                 return -EINVAL;
2832         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2833                 return -EFAULT;
2834         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2835                  info->device_name, gpio.state, gpio.smask,
2836                  gpio.dir, gpio.dmask));
2837
2838         spin_lock_irqsave(&info->lock,flags);
2839         if (gpio.dmask) {
2840                 data = rd_reg32(info, IODR);
2841                 data |= gpio.dmask & gpio.dir;
2842                 data &= ~(gpio.dmask & ~gpio.dir);
2843                 wr_reg32(info, IODR, data);
2844         }
2845         if (gpio.smask) {
2846                 data = rd_reg32(info, IOVR);
2847                 data |= gpio.smask & gpio.state;
2848                 data &= ~(gpio.smask & ~gpio.state);
2849                 wr_reg32(info, IOVR, data);
2850         }
2851         spin_unlock_irqrestore(&info->lock,flags);
2852
2853         return 0;
2854 }
2855
2856 /*
2857  * get general purpose IO pin state and direction
2858  */
2859 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2860 {
2861         struct gpio_desc gpio;
2862         if (!info->gpio_present)
2863                 return -EINVAL;
2864         gpio.state = rd_reg32(info, IOVR);
2865         gpio.smask = 0xffffffff;
2866         gpio.dir   = rd_reg32(info, IODR);
2867         gpio.dmask = 0xffffffff;
2868         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2869                 return -EFAULT;
2870         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2871                  info->device_name, gpio.state, gpio.dir));
2872         return 0;
2873 }
2874
2875 /*
2876  * conditional wait facility
2877  */
2878 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2879 {
2880         init_waitqueue_head(&w->q);
2881         init_waitqueue_entry(&w->wait, current);
2882         w->data = data;
2883 }
2884
2885 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2886 {
2887         set_current_state(TASK_INTERRUPTIBLE);
2888         add_wait_queue(&w->q, &w->wait);
2889         w->next = *head;
2890         *head = w;
2891 }
2892
2893 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2894 {
2895         struct cond_wait *w, *prev;
2896         remove_wait_queue(&cw->q, &cw->wait);
2897         set_current_state(TASK_RUNNING);
2898         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2899                 if (w == cw) {
2900                         if (prev != NULL)
2901                                 prev->next = w->next;
2902                         else
2903                                 *head = w->next;
2904                         break;
2905                 }
2906         }
2907 }
2908
2909 static void flush_cond_wait(struct cond_wait **head)
2910 {
2911         while (*head != NULL) {
2912                 wake_up_interruptible(&(*head)->q);
2913                 *head = (*head)->next;
2914         }
2915 }
2916
2917 /*
2918  * wait for general purpose I/O pin(s) to enter specified state
2919  *
2920  * user_gpio fields:
2921  * state - bit indicates target pin state
2922  * smask - set bit indicates watched pin
2923  *
2924  * The wait ends when at least one watched pin enters the specified
2925  * state. When 0 (no error) is returned, user_gpio->state is set to the
2926  * state of all GPIO pins when the wait ends.
2927  *
2928  * Note: Each pin may be a dedicated input, dedicated output, or
2929  * configurable input/output. The number and configuration of pins
2930  * varies with the specific adapter model. Only input pins (dedicated
2931  * or configured) can be monitored with this function.
2932  */
2933 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2934 {
2935         unsigned long flags;
2936         int rc = 0;
2937         struct gpio_desc gpio;
2938         struct cond_wait wait;
2939         u32 state;
2940
2941         if (!info->gpio_present)
2942                 return -EINVAL;
2943         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2944                 return -EFAULT;
2945         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2946                  info->device_name, gpio.state, gpio.smask));
2947         /* ignore output pins identified by set IODR bit */
2948         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2949                 return -EINVAL;
2950         init_cond_wait(&wait, gpio.smask);
2951
2952         spin_lock_irqsave(&info->lock, flags);
2953         /* enable interrupts for watched pins */
2954         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2955         /* get current pin states */
2956         state = rd_reg32(info, IOVR);
2957
2958         if (gpio.smask & ~(state ^ gpio.state)) {
2959                 /* already in target state */
2960                 gpio.state = state;
2961         } else {
2962                 /* wait for target state */
2963                 add_cond_wait(&info->gpio_wait_q, &wait);
2964                 spin_unlock_irqrestore(&info->lock, flags);
2965                 schedule();
2966                 if (signal_pending(current))
2967                         rc = -ERESTARTSYS;
2968                 else
2969                         gpio.state = wait.data;
2970                 spin_lock_irqsave(&info->lock, flags);
2971                 remove_cond_wait(&info->gpio_wait_q, &wait);
2972         }
2973
2974         /* disable all GPIO interrupts if no waiting processes */
2975         if (info->gpio_wait_q == NULL)
2976                 wr_reg32(info, IOER, 0);
2977         spin_unlock_irqrestore(&info->lock,flags);
2978
2979         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2980                 rc = -EFAULT;
2981         return rc;
2982 }
2983
2984 static int modem_input_wait(struct slgt_info *info,int arg)
2985 {
2986         unsigned long flags;
2987         int rc;
2988         struct mgsl_icount cprev, cnow;
2989         DECLARE_WAITQUEUE(wait, current);
2990
2991         /* save current irq counts */
2992         spin_lock_irqsave(&info->lock,flags);
2993         cprev = info->icount;
2994         add_wait_queue(&info->status_event_wait_q, &wait);
2995         set_current_state(TASK_INTERRUPTIBLE);
2996         spin_unlock_irqrestore(&info->lock,flags);
2997
2998         for(;;) {
2999                 schedule();
3000                 if (signal_pending(current)) {
3001                         rc = -ERESTARTSYS;
3002                         break;
3003                 }
3004
3005                 /* get new irq counts */
3006                 spin_lock_irqsave(&info->lock,flags);
3007                 cnow = info->icount;
3008                 set_current_state(TASK_INTERRUPTIBLE);
3009                 spin_unlock_irqrestore(&info->lock,flags);
3010
3011                 /* if no change, wait aborted for some reason */
3012                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3013                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3014                         rc = -EIO;
3015                         break;
3016                 }
3017
3018                 /* check for change in caller specified modem input */
3019                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3020                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3021                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3022                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3023                         rc = 0;
3024                         break;
3025                 }
3026
3027                 cprev = cnow;
3028         }
3029         remove_wait_queue(&info->status_event_wait_q, &wait);
3030         set_current_state(TASK_RUNNING);
3031         return rc;
3032 }
3033
3034 /*
3035  *  return state of serial control and status signals
3036  */
3037 static int tiocmget(struct tty_struct *tty, struct file *file)
3038 {
3039         struct slgt_info *info = tty->driver_data;
3040         unsigned int result;
3041         unsigned long flags;
3042
3043         spin_lock_irqsave(&info->lock,flags);
3044         get_signals(info);
3045         spin_unlock_irqrestore(&info->lock,flags);
3046
3047         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3048                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3049                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3050                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3051                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3052                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3053
3054         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3055         return result;
3056 }
3057
3058 /*
3059  * set modem control signals (DTR/RTS)
3060  *
3061  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3062  *              TIOCMSET = set/clear signal values
3063  *      value   bit mask for command
3064  */
3065 static int tiocmset(struct tty_struct *tty, struct file *file,
3066                     unsigned int set, unsigned int clear)
3067 {
3068         struct slgt_info *info = tty->driver_data;
3069         unsigned long flags;
3070
3071         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3072
3073         if (set & TIOCM_RTS)
3074                 info->signals |= SerialSignal_RTS;
3075         if (set & TIOCM_DTR)
3076                 info->signals |= SerialSignal_DTR;
3077         if (clear & TIOCM_RTS)
3078                 info->signals &= ~SerialSignal_RTS;
3079         if (clear & TIOCM_DTR)
3080                 info->signals &= ~SerialSignal_DTR;
3081
3082         spin_lock_irqsave(&info->lock,flags);
3083         set_signals(info);
3084         spin_unlock_irqrestore(&info->lock,flags);
3085         return 0;
3086 }
3087
3088 static int carrier_raised(struct tty_port *port)
3089 {
3090         unsigned long flags;
3091         struct slgt_info *info = container_of(port, struct slgt_info, port);
3092
3093         spin_lock_irqsave(&info->lock,flags);
3094         get_signals(info);
3095         spin_unlock_irqrestore(&info->lock,flags);
3096         return (info->signals & SerialSignal_DCD) ? 1 : 0;
3097 }
3098
3099 static void raise_dtr_rts(struct tty_port *port)
3100 {
3101         unsigned long flags;
3102         struct slgt_info *info = container_of(port, struct slgt_info, port);
3103
3104         spin_lock_irqsave(&info->lock,flags);
3105         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3106         set_signals(info);
3107         spin_unlock_irqrestore(&info->lock,flags);
3108 }
3109
3110
3111 /*
3112  *  block current process until the device is ready to open
3113  */
3114 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3115                            struct slgt_info *info)
3116 {
3117         DECLARE_WAITQUEUE(wait, current);
3118         int             retval;
3119         bool            do_clocal = false;
3120         bool            extra_count = false;
3121         unsigned long   flags;
3122         int             cd;
3123         struct tty_port *port = &info->port;
3124
3125         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3126
3127         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3128                 /* nonblock mode is set or port is not enabled */
3129                 port->flags |= ASYNC_NORMAL_ACTIVE;
3130                 return 0;
3131         }
3132
3133         if (tty->termios->c_cflag & CLOCAL)
3134                 do_clocal = true;
3135
3136         /* Wait for carrier detect and the line to become
3137          * free (i.e., not in use by the callout).  While we are in
3138          * this loop, port->count is dropped by one, so that
3139          * close() knows when to free things.  We restore it upon
3140          * exit, either normal or abnormal.
3141          */
3142
3143         retval = 0;
3144         add_wait_queue(&port->open_wait, &wait);
3145
3146         spin_lock_irqsave(&info->lock, flags);
3147         if (!tty_hung_up_p(filp)) {
3148                 extra_count = true;
3149                 port->count--;
3150         }
3151         spin_unlock_irqrestore(&info->lock, flags);
3152         port->blocked_open++;
3153
3154         while (1) {
3155                 if ((tty->termios->c_cflag & CBAUD))
3156                         tty_port_raise_dtr_rts(port);
3157
3158                 set_current_state(TASK_INTERRUPTIBLE);
3159
3160                 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3161                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3162                                         -EAGAIN : -ERESTARTSYS;
3163                         break;
3164                 }
3165
3166                 cd = tty_port_carrier_raised(port);
3167
3168                 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd ))
3169                         break;
3170
3171                 if (signal_pending(current)) {
3172                         retval = -ERESTARTSYS;
3173                         break;
3174                 }
3175
3176                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3177                 schedule();
3178         }
3179
3180         set_current_state(TASK_RUNNING);
3181         remove_wait_queue(&port->open_wait, &wait);
3182
3183         if (extra_count)
3184                 port->count++;
3185         port->blocked_open--;
3186
3187         if (!retval)
3188                 port->flags |= ASYNC_NORMAL_ACTIVE;
3189
3190         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3191         return retval;
3192 }
3193
3194 static int alloc_tmp_rbuf(struct slgt_info *info)
3195 {
3196         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3197         if (info->tmp_rbuf == NULL)
3198                 return -ENOMEM;
3199         return 0;
3200 }
3201
3202 static void free_tmp_rbuf(struct slgt_info *info)
3203 {
3204         kfree(info->tmp_rbuf);
3205         info->tmp_rbuf = NULL;
3206 }
3207
3208 /*
3209  * allocate DMA descriptor lists.
3210  */
3211 static int alloc_desc(struct slgt_info *info)
3212 {
3213         unsigned int i;
3214         unsigned int pbufs;
3215
3216         /* allocate memory to hold descriptor lists */
3217         info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3218         if (info->bufs == NULL)
3219                 return -ENOMEM;
3220
3221         memset(info->bufs, 0, DESC_LIST_SIZE);
3222
3223         info->rbufs = (struct slgt_desc*)info->bufs;
3224         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3225
3226         pbufs = (unsigned int)info->bufs_dma_addr;
3227
3228         /*
3229          * Build circular lists of descriptors
3230          */
3231
3232         for (i=0; i < info->rbuf_count; i++) {
3233                 /* physical address of this descriptor */
3234                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3235
3236                 /* physical address of next descriptor */
3237                 if (i == info->rbuf_count - 1)
3238                         info->rbufs[i].next = cpu_to_le32(pbufs);
3239                 else
3240                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3241                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3242         }
3243
3244         for (i=0; i < info->tbuf_count; i++) {
3245                 /* physical address of this descriptor */
3246                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3247
3248                 /* physical address of next descriptor */
3249                 if (i == info->tbuf_count - 1)
3250                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3251                 else
3252                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3253         }
3254
3255         return 0;
3256 }
3257
3258 static void free_desc(struct slgt_info *info)
3259 {
3260         if (info->bufs != NULL) {
3261                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3262                 info->bufs  = NULL;
3263                 info->rbufs = NULL;
3264                 info->tbufs = NULL;
3265         }
3266 }
3267
3268 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3269 {
3270         int i;
3271         for (i=0; i < count; i++) {
3272                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3273                         return -ENOMEM;
3274                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3275         }
3276         return 0;
3277 }
3278
3279 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3280 {
3281         int i;
3282         for (i=0; i < count; i++) {
3283                 if (bufs[i].buf == NULL)
3284                         continue;
3285                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3286                 bufs[i].buf = NULL;
3287         }
3288 }
3289
3290 static int alloc_dma_bufs(struct slgt_info *info)
3291 {
3292         info->rbuf_count = 32;
3293         info->tbuf_count = 32;
3294
3295         if (alloc_desc(info) < 0 ||
3296             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3297             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3298             alloc_tmp_rbuf(info) < 0) {
3299                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3300                 return -ENOMEM;
3301         }
3302         reset_rbufs(info);
3303         return 0;
3304 }
3305
3306 static void free_dma_bufs(struct slgt_info *info)
3307 {
3308         if (info->bufs) {
3309                 free_bufs(info, info->rbufs, info->rbuf_count);
3310                 free_bufs(info, info->tbufs, info->tbuf_count);
3311                 free_desc(info);
3312         }
3313         free_tmp_rbuf(info);
3314 }
3315
3316 static int claim_resources(struct slgt_info *info)
3317 {
3318         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3319                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3320                         info->device_name, info->phys_reg_addr));
3321                 info->init_error = DiagStatus_AddressConflict;
3322                 goto errout;
3323         }
3324         else
3325                 info->reg_addr_requested = true;
3326
3327         info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3328         if (!info->reg_addr) {
3329                 DBGERR(("%s cant map device registers, addr=%08X\n",
3330                         info->device_name, info->phys_reg_addr));
3331                 info->init_error = DiagStatus_CantAssignPciResources;
3332                 goto errout;
3333         }
3334         return 0;
3335
3336 errout:
3337         release_resources(info);
3338         return -ENODEV;
3339 }
3340
3341 static void release_resources(struct slgt_info *info)
3342 {
3343         if (info->irq_requested) {
3344                 free_irq(info->irq_level, info);
3345                 info->irq_requested = false;
3346         }
3347
3348         if (info->reg_addr_requested) {
3349                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3350                 info->reg_addr_requested = false;
3351         }
3352
3353         if (info->reg_addr) {
3354                 iounmap(info->reg_addr);
3355                 info->reg_addr = NULL;
3356         }
3357 }
3358
3359 /* Add the specified device instance data structure to the
3360  * global linked list of devices and increment the device count.
3361  */
3362 static void add_device(struct slgt_info *info)
3363 {
3364         char *devstr;
3365
3366         info->next_device = NULL;
3367         info->line = slgt_device_count;
3368         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3369
3370         if (info->line < MAX_DEVICES) {
3371                 if (maxframe[info->line])
3372                         info->max_frame_size = maxframe[info->line];
3373         }
3374
3375         slgt_device_count++;
3376
3377         if (!slgt_device_list)
3378                 slgt_device_list = info;
3379         else {
3380                 struct slgt_info *current_dev = slgt_device_list;
3381                 while(current_dev->next_device)
3382                         current_dev = current_dev->next_device;
3383                 current_dev->next_device = info;
3384         }
3385
3386         if (info->max_frame_size < 4096)
3387                 info->max_frame_size = 4096;
3388         else if (info->max_frame_size > 65535)
3389                 info->max_frame_size = 65535;
3390
3391         switch(info->pdev->device) {
3392         case SYNCLINK_GT_DEVICE_ID:
3393                 devstr = "GT";
3394                 break;
3395         case SYNCLINK_GT2_DEVICE_ID:
3396                 devstr = "GT2";
3397                 break;
3398         case SYNCLINK_GT4_DEVICE_ID:
3399                 devstr = "GT4";
3400                 break;
3401         case SYNCLINK_AC_DEVICE_ID:
3402                 devstr = "AC";
3403                 info->params.mode = MGSL_MODE_ASYNC;
3404                 break;
3405         default:
3406                 devstr = "(unknown model)";
3407         }
3408         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3409                 devstr, info->device_name, info->phys_reg_addr,
3410                 info->irq_level, info->max_frame_size);
3411
3412 #if SYNCLINK_GENERIC_HDLC
3413         hdlcdev_init(info);
3414 #endif
3415 }
3416
3417 static const struct tty_port_operations slgt_port_ops = {
3418         .carrier_raised = carrier_raised,
3419         .raise_dtr_rts = raise_dtr_rts,
3420 };
3421
3422 /*
3423  *  allocate device instance structure, return NULL on failure
3424  */
3425 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3426 {
3427         struct slgt_info *info;
3428
3429         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3430
3431         if (!info) {
3432                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3433                         driver_name, adapter_num, port_num));
3434         } else {
3435                 tty_port_init(&info->port);
3436                 info->port.ops = &slgt_port_ops;
3437                 info->magic = MGSL_MAGIC;
3438                 INIT_WORK(&info->task, bh_handler);
3439                 info->max_frame_size = 4096;
3440                 info->rbuf_fill_level = DMABUFSIZE;
3441                 info->port.close_delay = 5*HZ/10;
3442                 info->port.closing_wait = 30*HZ;
3443                 init_waitqueue_head(&info->status_event_wait_q);
3444                 init_waitqueue_head(&info->event_wait_q);
3445                 spin_lock_init(&info->netlock);
3446                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3447                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3448                 info->adapter_num = adapter_num;
3449                 info->port_num = port_num;
3450
3451                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3452                 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3453
3454                 /* Copy configuration info to device instance data */
3455                 info->pdev = pdev;
3456                 info->irq_level = pdev->irq;
3457                 info->phys_reg_addr = pci_resource_start(pdev,0);
3458
3459                 info->bus_type = MGSL_BUS_TYPE_PCI;
3460                 info->irq_flags = IRQF_SHARED;
3461
3462                 info->init_error = -1; /* assume error, set to 0 on successful init */
3463         }
3464
3465         return info;
3466 }
3467
3468 static void device_init(int adapter_num, struct pci_dev *pdev)
3469 {
3470         struct slgt_info *port_array[SLGT_MAX_PORTS];
3471         int i;
3472         int port_count = 1;
3473
3474         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3475                 port_count = 2;
3476         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3477                 port_count = 4;
3478
3479         /* allocate device instances for all ports */
3480         for (i=0; i < port_count; ++i) {
3481                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3482                 if (port_array[i] == NULL) {
3483                         for (--i; i >= 0; --i)
3484                                 kfree(port_array[i]);
3485                         return;
3486                 }
3487         }
3488
3489         /* give copy of port_array to all ports and add to device list  */
3490         for (i=0; i < port_count; ++i) {
3491                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3492                 add_device(port_array[i]);
3493                 port_array[i]->port_count = port_count;
3494                 spin_lock_init(&port_array[i]->lock);
3495         }
3496
3497         /* Allocate and claim adapter resources */
3498         if (!claim_resources(port_array[0])) {
3499
3500                 alloc_dma_bufs(port_array[0]);
3501
3502                 /* copy resource information from first port to others */
3503                 for (i = 1; i < port_count; ++i) {
3504                         port_array[i]->lock      = port_array[0]->lock;
3505                         port_array[i]->irq_level = port_array[0]->irq_level;
3506                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3507                         alloc_dma_bufs(port_array[i]);
3508                 }
3509
3510                 if (request_irq(port_array[0]->irq_level,
3511                                         slgt_interrupt,
3512                                         port_array[0]->irq_flags,
3513                                         port_array[0]->device_name,
3514                                         port_array[0]) < 0) {
3515                         DBGERR(("%s request_irq failed IRQ=%d\n",
3516                                 port_array[0]->device_name,
3517                                 port_array[0]->irq_level));
3518                 } else {
3519                         port_array[0]->irq_requested = true;
3520                         adapter_test(port_array[0]);
3521                         for (i=1 ; i < port_count ; i++) {
3522                                 port_array[i]->init_error = port_array[0]->init_error;
3523                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3524                         }
3525                 }
3526         }
3527
3528         for (i=0; i < port_count; ++i)
3529                 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3530 }
3531
3532 static int __devinit init_one(struct pci_dev *dev,
3533                               const struct pci_device_id *ent)
3534 {
3535         if (pci_enable_device(dev)) {
3536                 printk("error enabling pci device %p\n", dev);
3537                 return -EIO;
3538         }
3539         pci_set_master(dev);
3540         device_init(slgt_device_count, dev);
3541         return 0;
3542 }
3543
3544 static void __devexit remove_one(struct pci_dev *dev)
3545 {
3546 }
3547
3548 static const struct tty_operations ops = {
3549         .open = open,
3550         .close = close,
3551         .write = write,
3552         .put_char = put_char,
3553         .flush_chars = flush_chars,
3554         .write_room = write_room,
3555         .chars_in_buffer = chars_in_buffer,
3556         .flush_buffer = flush_buffer,
3557         .ioctl = ioctl,
3558         .compat_ioctl = slgt_compat_ioctl,
3559         .throttle = throttle,
3560         .unthrottle = unthrottle,
3561         .send_xchar = send_xchar,
3562         .break_ctl = set_break,
3563         .wait_until_sent = wait_until_sent,
3564         .read_proc = read_proc,
3565         .set_termios = set_termios,
3566         .stop = tx_hold,
3567         .start = tx_release,
3568         .hangup = hangup,
3569         .tiocmget = tiocmget,
3570         .tiocmset = tiocmset,
3571 };
3572
3573 static void slgt_cleanup(void)
3574 {
3575         int rc;
3576         struct slgt_info *info;
3577         struct slgt_info *tmp;
3578
3579         printk("unload %s %s\n", driver_name, driver_version);
3580
3581         if (serial_driver) {
3582                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3583                         tty_unregister_device(serial_driver, info->line);
3584                 if ((rc = tty_unregister_driver(serial_driver)))
3585                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3586                 put_tty_driver(serial_driver);
3587         }
3588
3589         /* reset devices */
3590         info = slgt_device_list;
3591         while(info) {
3592                 reset_port(info);
3593                 info = info->next_device;
3594         }
3595
3596         /* release devices */
3597         info = slgt_device_list;
3598         while(info) {
3599 #if SYNCLINK_GENERIC_HDLC
3600                 hdlcdev_exit(info);
3601 #endif
3602                 free_dma_bufs(info);
3603                 free_tmp_rbuf(info);
3604                 if (info->port_num == 0)
3605                         release_resources(info);
3606                 tmp = info;
3607                 info = info->next_device;
3608                 kfree(tmp);
3609         }
3610
3611         if (pci_registered)
3612                 pci_unregister_driver(&pci_driver);
3613 }
3614
3615 /*
3616  *  Driver initialization entry point.
3617  */
3618 static int __init slgt_init(void)
3619 {
3620         int rc;
3621
3622         printk("%s %s\n", driver_name, driver_version);
3623
3624         serial_driver = alloc_tty_driver(MAX_DEVICES);
3625         if (!serial_driver) {
3626                 printk("%s can't allocate tty driver\n", driver_name);
3627                 return -ENOMEM;
3628         }
3629
3630         /* Initialize the tty_driver structure */
3631
3632         serial_driver->owner = THIS_MODULE;
3633         serial_driver->driver_name = tty_driver_name;
3634         serial_driver->name = tty_dev_prefix;
3635         serial_driver->major = ttymajor;
3636         serial_driver->minor_start = 64;
3637         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3638         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3639         serial_driver->init_termios = tty_std_termios;
3640         serial_driver->init_termios.c_cflag =
3641                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3642         serial_driver->init_termios.c_ispeed = 9600;
3643         serial_driver->init_termios.c_ospeed = 9600;
3644         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3645         tty_set_operations(serial_driver, &ops);
3646         if ((rc = tty_register_driver(serial_driver)) < 0) {
3647                 DBGERR(("%s can't register serial driver\n", driver_name));
3648                 put_tty_driver(serial_driver);
3649                 serial_driver = NULL;
3650                 goto error;
3651         }
3652
3653         printk("%s %s, tty major#%d\n",
3654                 driver_name, driver_version,
3655                 serial_driver->major);
3656
3657         slgt_device_count = 0;
3658         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3659                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3660                 goto error;
3661         }
3662         pci_registered = true;
3663
3664         if (!slgt_device_list)
3665                 printk("%s no devices found\n",driver_name);
3666
3667         return 0;
3668
3669 error:
3670         slgt_cleanup();
3671         return rc;
3672 }
3673
3674 static void __exit slgt_exit(void)
3675 {
3676         slgt_cleanup();
3677 }
3678
3679 module_init(slgt_init);
3680 module_exit(slgt_exit);
3681
3682 /*
3683  * register access routines
3684  */
3685
3686 #define CALC_REGADDR() \
3687         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3688         if (addr >= 0x80) \
3689                 reg_addr += (info->port_num) * 32;
3690
3691 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3692 {
3693         CALC_REGADDR();
3694         return readb((void __iomem *)reg_addr);
3695 }
3696
3697 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3698 {
3699         CALC_REGADDR();
3700         writeb(value, (void __iomem *)reg_addr);
3701 }
3702
3703 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3704 {
3705         CALC_REGADDR();
3706         return readw((void __iomem *)reg_addr);
3707 }
3708
3709 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3710 {
3711         CALC_REGADDR();
3712         writew(value, (void __iomem *)reg_addr);
3713 }
3714
3715 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3716 {
3717         CALC_REGADDR();
3718         return readl((void __iomem *)reg_addr);
3719 }
3720
3721 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3722 {
3723         CALC_REGADDR();
3724         writel(value, (void __iomem *)reg_addr);
3725 }
3726
3727 static void rdma_reset(struct slgt_info *info)
3728 {
3729         unsigned int i;
3730
3731         /* set reset bit */
3732         wr_reg32(info, RDCSR, BIT1);
3733
3734         /* wait for enable bit cleared */
3735         for(i=0 ; i < 1000 ; i++)
3736                 if (!(rd_reg32(info, RDCSR) & BIT0))
3737                         break;
3738 }
3739
3740 static void tdma_reset(struct slgt_info *info)
3741 {
3742         unsigned int i;
3743
3744         /* set reset bit */
3745         wr_reg32(info, TDCSR, BIT1);
3746
3747         /* wait for enable bit cleared */
3748         for(i=0 ; i < 1000 ; i++)
3749                 if (!(rd_reg32(info, TDCSR) & BIT0))
3750                         break;
3751 }
3752
3753 /*
3754  * enable internal loopback
3755  * TxCLK and RxCLK are generated from BRG
3756  * and TxD is looped back to RxD internally.
3757  */
3758 static void enable_loopback(struct slgt_info *info)
3759 {
3760         /* SCR (serial control) BIT2=looopback enable */
3761         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3762
3763         if (info->params.mode != MGSL_MODE_ASYNC) {
3764                 /* CCR (clock control)
3765                  * 07..05  tx clock source (010 = BRG)
3766                  * 04..02  rx clock source (010 = BRG)
3767                  * 01      auxclk enable   (0 = disable)
3768                  * 00      BRG enable      (1 = enable)
3769                  *
3770                  * 0100 1001
3771                  */
3772                 wr_reg8(info, CCR, 0x49);
3773
3774                 /* set speed if available, otherwise use default */
3775                 if (info->params.clock_speed)
3776                         set_rate(info, info->params.clock_speed);
3777                 else
3778                         set_rate(info, 3686400);
3779         }
3780 }
3781
3782 /*
3783  *  set baud rate generator to specified rate
3784  */
3785 static void set_rate(struct slgt_info *info, u32 rate)
3786 {
3787         unsigned int div;
3788         static unsigned int osc = 14745600;
3789
3790         /* div = osc/rate - 1
3791          *
3792          * Round div up if osc/rate is not integer to
3793          * force to next slowest rate.
3794          */
3795
3796         if (rate) {
3797                 div = osc/rate;
3798                 if (!(osc % rate) && div)
3799                         div--;
3800                 wr_reg16(info, BDR, (unsigned short)div);
3801         }
3802 }
3803
3804 static void rx_stop(struct slgt_info *info)
3805 {
3806         unsigned short val;
3807
3808         /* disable and reset receiver */
3809         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3810         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3811         wr_reg16(info, RCR, val);                  /* clear reset bit */
3812
3813         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3814
3815         /* clear pending rx interrupts */
3816         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3817
3818         rdma_reset(info);
3819
3820         info->rx_enabled = false;
3821         info->rx_restart = false;
3822 }
3823
3824 static void rx_start(struct slgt_info *info)
3825 {
3826         unsigned short val;
3827
3828         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3829
3830         /* clear pending rx overrun IRQ */
3831         wr_reg16(info, SSR, IRQ_RXOVER);
3832
3833         /* reset and disable receiver */
3834         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3835         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3836         wr_reg16(info, RCR, val);                  /* clear reset bit */
3837
3838         rdma_reset(info);
3839         reset_rbufs(info);
3840
3841         /* set 1st descriptor address */
3842         wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3843
3844         if (info->params.mode != MGSL_MODE_ASYNC) {
3845                 /* enable rx DMA and DMA interrupt */
3846                 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3847         } else {
3848                 /* enable saving of rx status, rx DMA and DMA interrupt */
3849                 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3850         }
3851
3852         slgt_irq_on(info, IRQ_RXOVER);
3853
3854         /* enable receiver */
3855         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3856
3857         info->rx_restart = false;
3858         info->rx_enabled = true;
3859 }
3860
3861 static void tx_start(struct slgt_info *info)
3862 {
3863         if (!info->tx_enabled) {
3864                 wr_reg16(info, TCR,
3865                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3866                 info->tx_enabled = true;
3867         }
3868
3869         if (info->tx_count) {
3870                 info->drop_rts_on_tx_done = false;
3871
3872                 if (info->params.mode != MGSL_MODE_ASYNC) {
3873                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3874                                 get_signals(info);
3875                                 if (!(info->signals & SerialSignal_RTS)) {
3876                                         info->signals |= SerialSignal_RTS;
3877                                         set_signals(info);
3878                                         info->drop_rts_on_tx_done = true;
3879                                 }
3880                         }
3881
3882                         slgt_irq_off(info, IRQ_TXDATA);
3883                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3884                         /* clear tx idle and underrun status bits */
3885                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3886                         if (info->params.mode == MGSL_MODE_HDLC)
3887                                 mod_timer(&info->tx_timer, jiffies +
3888                                                 msecs_to_jiffies(5000));
3889                 } else {
3890                         slgt_irq_off(info, IRQ_TXDATA);
3891                         slgt_irq_on(info, IRQ_TXIDLE);
3892                         /* clear tx idle status bit */
3893                         wr_reg16(info, SSR, IRQ_TXIDLE);
3894                 }
3895                 tdma_start(info);
3896                 info->tx_active = true;
3897         }
3898 }
3899
3900 /*
3901  * start transmit DMA if inactive and there are unsent buffers
3902  */
3903 static void tdma_start(struct slgt_info *info)
3904 {
3905         unsigned int i;
3906
3907         if (rd_reg32(info, TDCSR) & BIT0)
3908                 return;
3909
3910         /* transmit DMA inactive, check for unsent buffers */
3911         i = info->tbuf_start;
3912         while (!desc_count(info->tbufs[i])) {
3913                 if (++i == info->tbuf_count)
3914                         i = 0;
3915                 if (i == info->tbuf_current)
3916                         return;
3917         }
3918         info->tbuf_start = i;
3919
3920         /* there are unsent buffers, start transmit DMA */
3921
3922         /* reset needed if previous error condition */
3923         tdma_reset(info);
3924
3925         /* set 1st descriptor address */
3926         wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3927         wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3928 }
3929
3930 static void tx_stop(struct slgt_info *info)
3931 {
3932         unsigned short val;
3933
3934         del_timer(&info->tx_timer);
3935
3936         tdma_reset(info);
3937
3938         /* reset and disable transmitter */
3939         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
3940         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3941
3942         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3943
3944         /* clear tx idle and underrun status bit */
3945         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3946
3947         reset_tbufs(info);
3948
3949         info->tx_enabled = false;
3950         info->tx_active = false;
3951 }
3952
3953 static void reset_port(struct slgt_info *info)
3954 {
3955         if (!info->reg_addr)
3956                 return;
3957
3958         tx_stop(info);
3959         rx_stop(info);
3960
3961         info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3962         set_signals(info);
3963
3964         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3965 }
3966
3967 static void reset_adapter(struct slgt_info *info)
3968 {
3969         int i;
3970         for (i=0; i < info->port_count; ++i) {
3971                 if (info->port_array[i])
3972                         reset_port(info->port_array[i]);
3973         }
3974 }
3975
3976 static void async_mode(struct slgt_info *info)
3977 {
3978         unsigned short val;
3979
3980         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3981         tx_stop(info);
3982         rx_stop(info);
3983
3984         /* TCR (tx control)
3985          *
3986          * 15..13  mode, 010=async
3987          * 12..10  encoding, 000=NRZ
3988          * 09      parity enable
3989          * 08      1=odd parity, 0=even parity
3990          * 07      1=RTS driver control
3991          * 06      1=break enable
3992          * 05..04  character length
3993          *         00=5 bits
3994          *         01=6 bits
3995          *         10=7 bits
3996          *         11=8 bits
3997          * 03      0=1 stop bit, 1=2 stop bits
3998          * 02      reset
3999          * 01      enable
4000          * 00      auto-CTS enable
4001          */
4002         val = 0x4000;
4003
4004         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4005                 val |= BIT7;
4006
4007         if (info->params.parity != ASYNC_PARITY_NONE) {
4008                 val |= BIT9;
4009                 if (info->params.parity == ASYNC_PARITY_ODD)
4010                         val |= BIT8;
4011         }
4012
4013         switch (info->params.data_bits)
4014         {
4015         case 6: val |= BIT4; break;
4016         case 7: val |= BIT5; break;
4017         case 8: val |= BIT5 + BIT4; break;
4018         }
4019
4020         if (info->params.stop_bits != 1)
4021                 val |= BIT3;
4022
4023         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4024                 val |= BIT0;
4025
4026         wr_reg16(info, TCR, val);
4027
4028         /* RCR (rx control)
4029          *
4030          * 15..13  mode, 010=async
4031          * 12..10  encoding, 000=NRZ
4032          * 09      parity enable
4033          * 08      1=odd parity, 0=even parity
4034          * 07..06  reserved, must be 0
4035          * 05..04  character length
4036          *         00=5 bits
4037          *         01=6 bits
4038          *         10=7 bits
4039          *         11=8 bits
4040          * 03      reserved, must be zero
4041          * 02      reset
4042          * 01      enable
4043          * 00      auto-DCD enable
4044          */
4045         val = 0x4000;
4046
4047         if (info->params.parity != ASYNC_PARITY_NONE) {
4048                 val |= BIT9;
4049                 if (info->params.parity == ASYNC_PARITY_ODD)
4050                         val |= BIT8;
4051         }
4052
4053         switch (info->params.data_bits)
4054         {
4055         case 6: val |= BIT4; break;
4056         case 7: val |= BIT5; break;
4057         case 8: val |= BIT5 + BIT4; break;
4058         }
4059
4060         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4061                 val |= BIT0;
4062
4063         wr_reg16(info, RCR, val);
4064
4065         /* CCR (clock control)
4066          *
4067          * 07..05  011 = tx clock source is BRG/16
4068          * 04..02  010 = rx clock source is BRG
4069          * 01      0 = auxclk disabled
4070          * 00      1 = BRG enabled
4071          *
4072          * 0110 1001
4073          */
4074         wr_reg8(info, CCR, 0x69);
4075
4076         msc_set_vcr(info);
4077
4078         /* SCR (serial control)
4079          *
4080          * 15  1=tx req on FIFO half empty
4081          * 14  1=rx req on FIFO half full
4082          * 13  tx data  IRQ enable
4083          * 12  tx idle  IRQ enable
4084          * 11  rx break on IRQ enable
4085          * 10  rx data  IRQ enable
4086          * 09  rx break off IRQ enable
4087          * 08  overrun  IRQ enable
4088          * 07  DSR      IRQ enable
4089          * 06  CTS      IRQ enable
4090          * 05  DCD      IRQ enable
4091          * 04  RI       IRQ enable
4092          * 03  reserved, must be zero
4093          * 02  1=txd->rxd internal loopback enable
4094          * 01  reserved, must be zero
4095          * 00  1=master IRQ enable
4096          */
4097         val = BIT15 + BIT14 + BIT0;
4098         wr_reg16(info, SCR, val);
4099
4100         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4101
4102         set_rate(info, info->params.data_rate * 16);
4103
4104         if (info->params.loopback)
4105                 enable_loopback(info);
4106 }
4107
4108 static void sync_mode(struct slgt_info *info)
4109 {
4110         unsigned short val;
4111
4112         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4113         tx_stop(info);
4114         rx_stop(info);
4115
4116         /* TCR (tx control)
4117          *
4118          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4119          * 12..10  encoding
4120          * 09      CRC enable
4121          * 08      CRC32
4122          * 07      1=RTS driver control
4123          * 06      preamble enable
4124          * 05..04  preamble length
4125          * 03      share open/close flag
4126          * 02      reset
4127          * 01      enable
4128          * 00      auto-CTS enable
4129          */
4130         val = BIT2;
4131
4132         switch(info->params.mode) {
4133         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4134         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4135         case MGSL_MODE_RAW:      val |= BIT13; break;
4136         }
4137         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4138                 val |= BIT7;
4139
4140         switch(info->params.encoding)
4141         {
4142         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4143         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4144         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4145         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4146         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4147         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4148         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4149         }
4150
4151         switch (info->params.crc_type & HDLC_CRC_MASK)
4152         {
4153         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4154         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4155         }
4156
4157         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4158                 val |= BIT6;
4159
4160         switch (info->params.preamble_length)
4161         {
4162         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4163         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4164         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4165         }
4166
4167         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4168                 val |= BIT0;
4169
4170         wr_reg16(info, TCR, val);
4171
4172         /* TPR (transmit preamble) */
4173
4174         switch (info->params.preamble)
4175         {
4176         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4177         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4178         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4179         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4180         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4181         default:                          val = 0x7e; break;
4182         }
4183         wr_reg8(info, TPR, (unsigned char)val);
4184
4185         /* RCR (rx control)
4186          *
4187          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4188          * 12..10  encoding
4189          * 09      CRC enable
4190          * 08      CRC32
4191          * 07..03  reserved, must be 0
4192          * 02      reset
4193          * 01      enable
4194          * 00      auto-DCD enable
4195          */
4196         val = 0;
4197
4198         switch(info->params.mode) {
4199         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4200         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4201         case MGSL_MODE_RAW:      val |= BIT13; break;
4202         }
4203
4204         switch(info->params.encoding)
4205         {
4206         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4207         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4208         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4209         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4210         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4211         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4212         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4213         }
4214
4215         switch (info->params.crc_type & HDLC_CRC_MASK)
4216         {
4217         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4218         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4219         }
4220
4221         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4222                 val |= BIT0;
4223
4224         wr_reg16(info, RCR, val);
4225
4226         /* CCR (clock control)
4227          *
4228          * 07..05  tx clock source
4229          * 04..02  rx clock source
4230          * 01      auxclk enable
4231          * 00      BRG enable
4232          */
4233         val = 0;
4234
4235         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4236         {
4237                 // when RxC source is DPLL, BRG generates 16X DPLL
4238                 // reference clock, so take TxC from BRG/16 to get
4239                 // transmit clock at actual data rate
4240                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4241                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4242                 else
4243                         val |= BIT6;    /* 010, txclk = BRG */
4244         }
4245         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4246                 val |= BIT7;    /* 100, txclk = DPLL Input */
4247         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4248                 val |= BIT5;    /* 001, txclk = RXC Input */
4249
4250         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4251                 val |= BIT3;    /* 010, rxclk = BRG */
4252         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4253                 val |= BIT4;    /* 100, rxclk = DPLL */
4254         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4255                 val |= BIT2;    /* 001, rxclk = TXC Input */
4256
4257         if (info->params.clock_speed)
4258                 val |= BIT1 + BIT0;
4259
4260         wr_reg8(info, CCR, (unsigned char)val);
4261
4262         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4263         {
4264                 // program DPLL mode
4265                 switch(info->params.encoding)
4266                 {
4267                 case HDLC_ENCODING_BIPHASE_MARK:
4268                 case HDLC_ENCODING_BIPHASE_SPACE:
4269                         val = BIT7; break;
4270                 case HDLC_ENCODING_BIPHASE_LEVEL:
4271                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4272                         val = BIT7 + BIT6; break;
4273                 default: val = BIT6;    // NRZ encodings
4274                 }
4275                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4276
4277                 // DPLL requires a 16X reference clock from BRG
4278                 set_rate(info, info->params.clock_speed * 16);
4279         }
4280         else
4281                 set_rate(info, info->params.clock_speed);
4282
4283         tx_set_idle(info);
4284
4285         msc_set_vcr(info);
4286
4287         /* SCR (serial control)
4288          *
4289          * 15  1=tx req on FIFO half empty
4290          * 14  1=rx req on FIFO half full
4291          * 13  tx data  IRQ enable
4292          * 12  tx idle  IRQ enable
4293          * 11  underrun IRQ enable
4294          * 10  rx data  IRQ enable
4295          * 09  rx idle  IRQ enable
4296          * 08  overrun  IRQ enable
4297          * 07  DSR      IRQ enable
4298          * 06  CTS      IRQ enable
4299          * 05  DCD      IRQ enable
4300          * 04  RI       IRQ enable
4301          * 03  reserved, must be zero
4302          * 02  1=txd->rxd internal loopback enable
4303          * 01  reserved, must be zero
4304          * 00  1=master IRQ enable
4305          */
4306         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4307
4308         if (info->params.loopback)
4309                 enable_loopback(info);
4310 }
4311
4312 /*
4313  *  set transmit idle mode
4314  */
4315 static void tx_set_idle(struct slgt_info *info)
4316 {
4317         unsigned char val;
4318         unsigned short tcr;
4319
4320         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4321          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4322          */
4323         tcr = rd_reg16(info, TCR);
4324         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4325                 /* disable preamble, set idle size to 16 bits */
4326                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4327                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4328                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4329         } else if (!(tcr & BIT6)) {
4330                 /* preamble is disabled, set idle size to 8 bits */
4331                 tcr &= ~(BIT5 + BIT4);
4332         }
4333         wr_reg16(info, TCR, tcr);
4334
4335         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4336                 /* LSB of custom tx idle specified in tx idle register */
4337                 val = (unsigned char)(info->idle_mode & 0xff);
4338         } else {
4339                 /* standard 8 bit idle patterns */
4340                 switch(info->idle_mode)
4341                 {
4342                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4343                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4344                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4345                 case HDLC_TXIDLE_ZEROS:
4346                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4347                 default:                         val = 0xff;
4348                 }
4349         }
4350
4351         wr_reg8(info, TIR, val);
4352 }
4353
4354 /*
4355  * get state of V24 status (input) signals
4356  */
4357 static void get_signals(struct slgt_info *info)
4358 {
4359         unsigned short status = rd_reg16(info, SSR);
4360
4361         /* clear all serial signals except DTR and RTS */
4362         info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4363
4364         if (status & BIT3)
4365                 info->signals |= SerialSignal_DSR;
4366         if (status & BIT2)
4367                 info->signals |= SerialSignal_CTS;
4368         if (status & BIT1)
4369                 info->signals |= SerialSignal_DCD;
4370         if (status & BIT0)
4371                 info->signals |= SerialSignal_RI;
4372 }
4373
4374 /*
4375  * set V.24 Control Register based on current configuration
4376  */
4377 static void msc_set_vcr(struct slgt_info *info)
4378 {
4379         unsigned char val = 0;
4380
4381         /* VCR (V.24 control)
4382          *
4383          * 07..04  serial IF select
4384          * 03      DTR
4385          * 02      RTS
4386          * 01      LL
4387          * 00      RL
4388          */
4389
4390         switch(info->if_mode & MGSL_INTERFACE_MASK)
4391         {
4392         case MGSL_INTERFACE_RS232:
4393                 val |= BIT5; /* 0010 */
4394                 break;
4395         case MGSL_INTERFACE_V35:
4396                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4397                 break;
4398         case MGSL_INTERFACE_RS422:
4399                 val |= BIT6; /* 0100 */
4400                 break;
4401         }
4402
4403         if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4404                 val |= BIT4;
4405         if (info->signals & SerialSignal_DTR)
4406                 val |= BIT3;
4407         if (info->signals & SerialSignal_RTS)
4408                 val |= BIT2;
4409         if (info->if_mode & MGSL_INTERFACE_LL)
4410                 val |= BIT1;
4411         if (info->if_mode & MGSL_INTERFACE_RL)
4412                 val |= BIT0;
4413         wr_reg8(info, VCR, val);
4414 }
4415
4416 /*
4417  * set state of V24 control (output) signals
4418  */
4419 static void set_signals(struct slgt_info *info)
4420 {
4421         unsigned char val = rd_reg8(info, VCR);
4422         if (info->signals & SerialSignal_DTR)
4423                 val |= BIT3;
4424         else
4425                 val &= ~BIT3;
4426         if (info->signals & SerialSignal_RTS)
4427                 val |= BIT2;
4428         else
4429                 val &= ~BIT2;
4430         wr_reg8(info, VCR, val);
4431 }
4432
4433 /*
4434  * free range of receive DMA buffers (i to last)
4435  */
4436 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4437 {
4438         int done = 0;
4439
4440         while(!done) {
4441                 /* reset current buffer for reuse */
4442                 info->rbufs[i].status = 0;
4443                 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4444                 if (i == last)
4445                         done = 1;
4446                 if (++i == info->rbuf_count)
4447                         i = 0;
4448         }
4449         info->rbuf_current = i;
4450 }
4451
4452 /*
4453  * mark all receive DMA buffers as free
4454  */
4455 static void reset_rbufs(struct slgt_info *info)
4456 {
4457         free_rbufs(info, 0, info->rbuf_count - 1);
4458 }
4459
4460 /*
4461  * pass receive HDLC frame to upper layer
4462  *
4463  * return true if frame available, otherwise false
4464  */
4465 static bool rx_get_frame(struct slgt_info *info)
4466 {
4467         unsigned int start, end;
4468         unsigned short status;
4469         unsigned int framesize = 0;
4470         unsigned long flags;
4471         struct tty_struct *tty = info->port.tty;
4472         unsigned char addr_field = 0xff;
4473         unsigned int crc_size = 0;
4474
4475         switch (info->params.crc_type & HDLC_CRC_MASK) {
4476         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4477         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4478         }
4479
4480 check_again:
4481
4482         framesize = 0;
4483         addr_field = 0xff;
4484         start = end = info->rbuf_current;
4485
4486         for (;;) {
4487                 if (!desc_complete(info->rbufs[end]))
4488                         goto cleanup;
4489
4490                 if (framesize == 0 && info->params.addr_filter != 0xff)
4491                         addr_field = info->rbufs[end].buf[0];
4492
4493                 framesize += desc_count(info->rbufs[end]);
4494
4495                 if (desc_eof(info->rbufs[end]))
4496                         break;
4497
4498                 if (++end == info->rbuf_count)
4499                         end = 0;
4500
4501                 if (end == info->rbuf_current) {
4502                         if (info->rx_enabled){
4503                                 spin_lock_irqsave(&info->lock,flags);
4504                                 rx_start(info);
4505                                 spin_unlock_irqrestore(&info->lock,flags);
4506                         }
4507                         goto cleanup;
4508                 }
4509         }
4510
4511         /* status
4512          *
4513          * 15      buffer complete
4514          * 14..06  reserved
4515          * 05..04  residue
4516          * 02      eof (end of frame)
4517          * 01      CRC error
4518          * 00      abort
4519          */
4520         status = desc_status(info->rbufs[end]);
4521
4522         /* ignore CRC bit if not using CRC (bit is undefined) */
4523         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4524                 status &= ~BIT1;
4525
4526         if (framesize == 0 ||
4527                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4528                 free_rbufs(info, start, end);
4529                 goto check_again;
4530         }
4531
4532         if (framesize < (2 + crc_size) || status & BIT0) {
4533                 info->icount.rxshort++;
4534                 framesize = 0;
4535         } else if (status & BIT1) {
4536                 info->icount.rxcrc++;
4537                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4538                         framesize = 0;
4539         }
4540
4541 #if SYNCLINK_GENERIC_HDLC
4542         if (framesize == 0) {
4543                 info->netdev->stats.rx_errors++;
4544                 info->netdev->stats.rx_frame_errors++;
4545         }
4546 #endif
4547
4548         DBGBH(("%s rx frame status=%04X size=%d\n",
4549                 info->device_name, status, framesize));
4550         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4551
4552         if (framesize) {
4553                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4554                         framesize -= crc_size;
4555                         crc_size = 0;
4556                 }
4557
4558                 if (framesize > info->max_frame_size + crc_size)
4559                         info->icount.rxlong++;
4560                 else {
4561                         /* copy dma buffer(s) to contiguous temp buffer */
4562                         int copy_count = framesize;
4563                         int i = start;
4564                         unsigned char *p = info->tmp_rbuf;
4565                         info->tmp_rbuf_count = framesize;
4566
4567                         info->icount.rxok++;
4568
4569                         while(copy_count) {
4570                                 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4571                                 memcpy(p, info->rbufs[i].buf, partial_count);
4572                                 p += partial_count;
4573                                 copy_count -= partial_count;
4574                                 if (++i == info->rbuf_count)
4575                                         i = 0;
4576                         }
4577
4578                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4579                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4580                                 framesize++;
4581                         }
4582
4583 #if SYNCLINK_GENERIC_HDLC
4584                         if (info->netcount)
4585                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4586                         else
4587 #endif
4588                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4589                 }
4590         }
4591         free_rbufs(info, start, end);
4592         return true;
4593
4594 cleanup:
4595         return false;
4596 }
4597
4598 /*
4599  * pass receive buffer (RAW synchronous mode) to tty layer
4600  * return true if buffer available, otherwise false
4601  */
4602 static bool rx_get_buf(struct slgt_info *info)
4603 {
4604         unsigned int i = info->rbuf_current;
4605         unsigned int count;
4606
4607         if (!desc_complete(info->rbufs[i]))
4608                 return false;
4609         count = desc_count(info->rbufs[i]);
4610         switch(info->params.mode) {
4611         case MGSL_MODE_MONOSYNC:
4612         case MGSL_MODE_BISYNC:
4613                 /* ignore residue in byte synchronous modes */
4614                 if (desc_residue(info->rbufs[i]))
4615                         count--;
4616                 break;
4617         }
4618         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4619         DBGINFO(("rx_get_buf size=%d\n", count));
4620         if (count)
4621                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4622                                   info->flag_buf, count);
4623         free_rbufs(info, i, i);
4624         return true;
4625 }
4626
4627 static void reset_tbufs(struct slgt_info *info)
4628 {
4629         unsigned int i;
4630         info->tbuf_current = 0;
4631         for (i=0 ; i < info->tbuf_count ; i++) {
4632                 info->tbufs[i].status = 0;
4633                 info->tbufs[i].count  = 0;
4634         }
4635 }
4636
4637 /*
4638  * return number of free transmit DMA buffers
4639  */
4640 static unsigned int free_tbuf_count(struct slgt_info *info)
4641 {
4642         unsigned int count = 0;
4643         unsigned int i = info->tbuf_current;
4644
4645         do
4646         {
4647                 if (desc_count(info->tbufs[i]))
4648                         break; /* buffer in use */
4649                 ++count;
4650                 if (++i == info->tbuf_count)
4651                         i=0;
4652         } while (i != info->tbuf_current);
4653
4654         /* if tx DMA active, last zero count buffer is in use */
4655         if (count && (rd_reg32(info, TDCSR) & BIT0))
4656                 --count;
4657
4658         return count;
4659 }
4660
4661 /*
4662  * return number of bytes in unsent transmit DMA buffers
4663  * and the serial controller tx FIFO
4664  */
4665 static unsigned int tbuf_bytes(struct slgt_info *info)
4666 {
4667         unsigned int total_count = 0;
4668         unsigned int i = info->tbuf_current;
4669         unsigned int reg_value;
4670         unsigned int count;
4671         unsigned int active_buf_count = 0;
4672
4673         /*
4674          * Add descriptor counts for all tx DMA buffers.
4675          * If count is zero (cleared by DMA controller after read),
4676          * the buffer is complete or is actively being read from.
4677          *
4678          * Record buf_count of last buffer with zero count starting
4679          * from current ring position. buf_count is mirror
4680          * copy of count and is not cleared by serial controller.
4681          * If DMA controller is active, that buffer is actively
4682          * being read so add to total.
4683          */
4684         do {
4685                 count = desc_count(info->tbufs[i]);
4686                 if (count)
4687                         total_count += count;
4688                 else if (!total_count)
4689                         active_buf_count = info->tbufs[i].buf_count;
4690                 if (++i == info->tbuf_count)
4691                         i = 0;
4692         } while (i != info->tbuf_current);
4693
4694         /* read tx DMA status register */
4695         reg_value = rd_reg32(info, TDCSR);
4696
4697         /* if tx DMA active, last zero count buffer is in use */
4698         if (reg_value & BIT0)
4699                 total_count += active_buf_count;
4700
4701         /* add tx FIFO count = reg_value[15..8] */
4702         total_count += (reg_value >> 8) & 0xff;
4703
4704         /* if transmitter active add one byte for shift register */
4705         if (info->tx_active)
4706                 total_count++;
4707
4708         return total_count;
4709 }
4710
4711 /*
4712  * load transmit DMA buffer(s) with data
4713  */
4714 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4715 {
4716         unsigned short count;
4717         unsigned int i;
4718         struct slgt_desc *d;
4719
4720         if (size == 0)
4721                 return;
4722
4723         DBGDATA(info, buf, size, "tx");
4724
4725         info->tbuf_start = i = info->tbuf_current;
4726
4727         while (size) {
4728                 d = &info->tbufs[i];
4729                 if (++i == info->tbuf_count)
4730                         i = 0;
4731
4732                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4733                 memcpy(d->buf, buf, count);
4734
4735                 size -= count;
4736                 buf  += count;
4737
4738                 /*
4739                  * set EOF bit for last buffer of HDLC frame or
4740                  * for every buffer in raw mode
4741                  */
4742                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4743                     info->params.mode == MGSL_MODE_RAW)
4744                         set_desc_eof(*d, 1);
4745                 else
4746                         set_desc_eof(*d, 0);
4747
4748                 set_desc_count(*d, count);
4749                 d->buf_count = count;
4750         }
4751
4752         info->tbuf_current = i;
4753 }
4754
4755 static int register_test(struct slgt_info *info)
4756 {
4757         static unsigned short patterns[] =
4758                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4759         static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4760         unsigned int i;
4761         int rc = 0;
4762
4763         for (i=0 ; i < count ; i++) {
4764                 wr_reg16(info, TIR, patterns[i]);
4765                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4766                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4767                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4768                         rc = -ENODEV;
4769                         break;
4770                 }
4771         }
4772         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4773         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4774         return rc;
4775 }
4776
4777 static int irq_test(struct slgt_info *info)
4778 {
4779         unsigned long timeout;
4780         unsigned long flags;
4781         struct tty_struct *oldtty = info->port.tty;
4782         u32 speed = info->params.data_rate;
4783
4784         info->params.data_rate = 921600;
4785         info->port.tty = NULL;
4786
4787         spin_lock_irqsave(&info->lock, flags);
4788         async_mode(info);
4789         slgt_irq_on(info, IRQ_TXIDLE);
4790
4791         /* enable transmitter */
4792         wr_reg16(info, TCR,
4793                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4794
4795         /* write one byte and wait for tx idle */
4796         wr_reg16(info, TDR, 0);
4797
4798         /* assume failure */
4799         info->init_error = DiagStatus_IrqFailure;
4800         info->irq_occurred = false;
4801
4802         spin_unlock_irqrestore(&info->lock, flags);
4803
4804         timeout=100;
4805         while(timeout-- && !info->irq_occurred)
4806                 msleep_interruptible(10);
4807
4808         spin_lock_irqsave(&info->lock,flags);
4809         reset_port(info);
4810         spin_unlock_irqrestore(&info->lock,flags);
4811
4812         info->params.data_rate = speed;
4813         info->port.tty = oldtty;
4814
4815         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4816         return info->irq_occurred ? 0 : -ENODEV;
4817 }
4818
4819 static int loopback_test_rx(struct slgt_info *info)
4820 {
4821         unsigned char *src, *dest;
4822         int count;
4823
4824         if (desc_complete(info->rbufs[0])) {
4825                 count = desc_count(info->rbufs[0]);
4826                 src   = info->rbufs[0].buf;
4827                 dest  = info->tmp_rbuf;
4828
4829                 for( ; count ; count-=2, src+=2) {
4830                         /* src=data byte (src+1)=status byte */
4831                         if (!(*(src+1) & (BIT9 + BIT8))) {
4832                                 *dest = *src;
4833                                 dest++;
4834                                 info->tmp_rbuf_count++;
4835                         }
4836                 }
4837                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4838                 return 1;
4839         }
4840         return 0;
4841 }
4842
4843 static int loopback_test(struct slgt_info *info)
4844 {
4845 #define TESTFRAMESIZE 20
4846
4847         unsigned long timeout;
4848         u16 count = TESTFRAMESIZE;
4849         unsigned char buf[TESTFRAMESIZE];
4850         int rc = -ENODEV;
4851         unsigned long flags;
4852
4853         struct tty_struct *oldtty = info->port.tty;
4854         MGSL_PARAMS params;
4855
4856         memcpy(&params, &info->params, sizeof(params));
4857
4858         info->params.mode = MGSL_MODE_ASYNC;
4859         info->params.data_rate = 921600;
4860         info->params.loopback = 1;
4861         info->port.tty = NULL;
4862
4863         /* build and send transmit frame */
4864         for (count = 0; count < TESTFRAMESIZE; ++count)
4865                 buf[count] = (unsigned char)count;
4866
4867         info->tmp_rbuf_count = 0;
4868         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4869
4870         /* program hardware for HDLC and enabled receiver */
4871         spin_lock_irqsave(&info->lock,flags);
4872         async_mode(info);
4873         rx_start(info);
4874         info->tx_count = count;
4875         tx_load(info, buf, count);
4876         tx_start(info);
4877         spin_unlock_irqrestore(&info->lock, flags);
4878
4879         /* wait for receive complete */
4880         for (timeout = 100; timeout; --timeout) {
4881                 msleep_interruptible(10);
4882                 if (loopback_test_rx(info)) {
4883                         rc = 0;
4884                         break;
4885                 }
4886         }
4887
4888         /* verify received frame length and contents */
4889         if (!rc && (info->tmp_rbuf_count != count ||
4890                   memcmp(buf, info->tmp_rbuf, count))) {
4891                 rc = -ENODEV;
4892         }
4893
4894         spin_lock_irqsave(&info->lock,flags);
4895         reset_adapter(info);
4896         spin_unlock_irqrestore(&info->lock,flags);
4897
4898         memcpy(&info->params, &params, sizeof(info->params));
4899         info->port.tty = oldtty;
4900
4901         info->init_error = rc ? DiagStatus_DmaFailure : 0;
4902         return rc;
4903 }
4904
4905 static int adapter_test(struct slgt_info *info)
4906 {
4907         DBGINFO(("testing %s\n", info->device_name));
4908         if (register_test(info) < 0) {
4909                 printk("register test failure %s addr=%08X\n",
4910                         info->device_name, info->phys_reg_addr);
4911         } else if (irq_test(info) < 0) {
4912                 printk("IRQ test failure %s IRQ=%d\n",
4913                         info->device_name, info->irq_level);
4914         } else if (loopback_test(info) < 0) {
4915                 printk("loopback test failure %s\n", info->device_name);
4916         }
4917         return info->init_error;
4918 }
4919
4920 /*
4921  * transmit timeout handler
4922  */
4923 static void tx_timeout(unsigned long context)
4924 {
4925         struct slgt_info *info = (struct slgt_info*)context;
4926         unsigned long flags;
4927
4928         DBGINFO(("%s tx_timeout\n", info->device_name));
4929         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4930                 info->icount.txtimeout++;
4931         }
4932         spin_lock_irqsave(&info->lock,flags);
4933         info->tx_active = false;
4934         info->tx_count = 0;
4935         spin_unlock_irqrestore(&info->lock,flags);
4936
4937 #if SYNCLINK_GENERIC_HDLC
4938         if (info->netcount)
4939                 hdlcdev_tx_done(info);
4940         else
4941 #endif
4942                 bh_transmit(info);
4943 }
4944
4945 /*
4946  * receive buffer polling timer
4947  */
4948 static void rx_timeout(unsigned long context)
4949 {
4950         struct slgt_info *info = (struct slgt_info*)context;
4951         unsigned long flags;
4952
4953         DBGINFO(("%s rx_timeout\n", info->device_name));
4954         spin_lock_irqsave(&info->lock, flags);
4955         info->pending_bh |= BH_RECEIVE;
4956         spin_unlock_irqrestore(&info->lock, flags);
4957         bh_handler(&info->task);
4958 }
4959