arch/x86/kernel/pci-calgary_64.c

   1 /*
   2  * Derived from arch/powerpc/kernel/iommu.c
   3  *
   4  * Copyright IBM Corporation, 2006-2007
   5  * Copyright (C) 2006  Jon Mason <jdmason@kudzu.us>
   6  *
   7  * Author: Jon Mason <jdmason@kudzu.us>
   8  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
   9
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/mm.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/string.h>
  32 #include <linux/crash_dump.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/bitops.h>
  35 #include <linux/pci_ids.h>
  36 #include <linux/pci.h>
  37 #include <linux/delay.h>
  38 #include <linux/scatterlist.h>
  39 #include <linux/iommu-helper.h>
  40 #include <asm/iommu.h>
  41 #include <asm/calgary.h>
  42 #include <asm/tce.h>
  43 #include <asm/pci-direct.h>
  44 #include <asm/system.h>
  45 #include <asm/dma.h>
  46 #include <asm/rio.h>
  47 #include <asm/bios_ebda.h>
  48
  49 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
  50 int use_calgary __read_mostly = 1;
  51 #else
  52 int use_calgary __read_mostly = 0;
  53 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
  54
  55 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  56 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
  57
  58 /* register offsets inside the host bridge space */
  59 #define CALGARY_CONFIG_REG      0x0108
  60 #define PHB_CSR_OFFSET          0x0110 /* Channel Status */
  61 #define PHB_PLSSR_OFFSET        0x0120
  62 #define PHB_CONFIG_RW_OFFSET    0x0160
  63 #define PHB_IOBASE_BAR_LOW      0x0170
  64 #define PHB_IOBASE_BAR_HIGH     0x0180
  65 #define PHB_MEM_1_LOW           0x0190
  66 #define PHB_MEM_1_HIGH          0x01A0
  67 #define PHB_IO_ADDR_SIZE        0x01B0
  68 #define PHB_MEM_1_SIZE          0x01C0
  69 #define PHB_MEM_ST_OFFSET       0x01D0
  70 #define PHB_AER_OFFSET          0x0200
  71 #define PHB_CONFIG_0_HIGH       0x0220
  72 #define PHB_CONFIG_0_LOW        0x0230
  73 #define PHB_CONFIG_0_END        0x0240
  74 #define PHB_MEM_2_LOW           0x02B0
  75 #define PHB_MEM_2_HIGH          0x02C0
  76 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  77 #define PHB_MEM_2_SIZE_LOW      0x02E0
  78 #define PHB_DOSHOLE_OFFSET      0x08E0
  79
  80 /* CalIOC2 specific */
  81 #define PHB_SAVIOR_L2           0x0DB0
  82 #define PHB_PAGE_MIG_CTRL       0x0DA8
  83 #define PHB_PAGE_MIG_DEBUG      0x0DA0
  84 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
  85
  86 /* PHB_CONFIG_RW */
  87 #define PHB_TCE_ENABLE          0x20000000
  88 #define PHB_SLOT_DISABLE        0x1C000000
  89 #define PHB_DAC_DISABLE         0x01000000
  90 #define PHB_MEM2_ENABLE         0x00400000
  91 #define PHB_MCSR_ENABLE         0x00100000
  92 /* TAR (Table Address Register) */
  93 #define TAR_SW_BITS             0x0000ffffffff800fUL
  94 #define TAR_VALID               0x0000000000000008UL
  95 /* CSR (Channel/DMA Status Register) */
  96 #define CSR_AGENT_MASK          0xffe0ffff
  97 /* CCR (Calgary Configuration Register) */
  98 #define CCR_2SEC_TIMEOUT        0x000000000000000EUL
  99 /* PMCR/PMDR (Page Migration Control/Debug Registers */
 100 #define PMR_SOFTSTOP            0x80000000
 101 #define PMR_SOFTSTOPFAULT       0x40000000
 102 #define PMR_HARDSTOP            0x20000000
 103
 104 #define MAX_NUM_OF_PHBS         8 /* how many PHBs in total? */
 105 #define MAX_NUM_CHASSIS         8 /* max number of chassis */
 106 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
 107 #define MAX_PHB_BUS_NUM         (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
 108 #define PHBS_PER_CALGARY        4
 109
 110 /* register offsets in Calgary's internal register space */
 111 static const unsigned long tar_offsets[] = {
 112         0x0580 /* TAR0 */,
 113         0x0588 /* TAR1 */,
 114         0x0590 /* TAR2 */,
 115         0x0598 /* TAR3 */
 116 };
 117
 118 static const unsigned long split_queue_offsets[] = {
 119         0x4870 /* SPLIT QUEUE 0 */,
 120         0x5870 /* SPLIT QUEUE 1 */,
 121         0x6870 /* SPLIT QUEUE 2 */,
 122         0x7870 /* SPLIT QUEUE 3 */
 123 };
 124
 125 static const unsigned long phb_offsets[] = {
 126         0x8000 /* PHB0 */,
 127         0x9000 /* PHB1 */,
 128         0xA000 /* PHB2 */,
 129         0xB000 /* PHB3 */
 130 };
 131
 132 /* PHB debug registers */
 133
 134 static const unsigned long phb_debug_offsets[] = {
 135         0x4000  /* PHB 0 DEBUG */,
 136         0x5000  /* PHB 1 DEBUG */,
 137         0x6000  /* PHB 2 DEBUG */,
 138         0x7000  /* PHB 3 DEBUG */
 139 };
 140
 141 /*
 142  * STUFF register for each debug PHB,
 143  * byte 1 = start bus number, byte 2 = end bus number
 144  */
 145
 146 #define PHB_DEBUG_STUFF_OFFSET  0x0020
 147
 148 #define EMERGENCY_PAGES 32 /* = 128KB */
 149
 150 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 151 static int translate_empty_slots __read_mostly = 0;
 152 static int calgary_detected __read_mostly = 0;
 153
 154 static struct rio_table_hdr     *rio_table_hdr __initdata;
 155 static struct scal_detail       *scal_devs[MAX_NUMNODES] __initdata;
 156 static struct rio_detail        *rio_devs[MAX_NUMNODES * 4] __initdata;
 157
 158 struct calgary_bus_info {
 159         void *tce_space;
 160         unsigned char translation_disabled;
 161         signed char phbid;
 162         void __iomem *bbar;
 163 };
 164
 165 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 166 static void calgary_tce_cache_blast(struct iommu_table *tbl);
 167 static void calgary_dump_error_regs(struct iommu_table *tbl);
 168 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 169 static void calioc2_tce_cache_blast(struct iommu_table *tbl);
 170 static void calioc2_dump_error_regs(struct iommu_table *tbl);
 171 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl);
 172 static void get_tce_space_from_tar(void);
 173
 174 static struct cal_chipset_ops calgary_chip_ops = {
 175         .handle_quirks = calgary_handle_quirks,
 176         .tce_cache_blast = calgary_tce_cache_blast,
 177         .dump_error_regs = calgary_dump_error_regs
 178 };
 179
 180 static struct cal_chipset_ops calioc2_chip_ops = {
 181         .handle_quirks = calioc2_handle_quirks,
 182         .tce_cache_blast = calioc2_tce_cache_blast,
 183         .dump_error_regs = calioc2_dump_error_regs
 184 };
 185
 186 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
 187
 188 /* enable this to stress test the chip's TCE cache */
 189 #ifdef CONFIG_IOMMU_DEBUG
 190 static int debugging = 1;
 191
 192 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 193         int expected, unsigned long start, unsigned long end)
 194 {
 195         unsigned long idx = start;
 196
 197         BUG_ON(start >= end);
 198
 199         while (idx < end) {
 200                 if (!!test_bit(idx, bitmap) != expected)
 201                         return idx;
 202                 ++idx;
 203         }
 204
 205         /* all bits have the expected value */
 206         return ~0UL;
 207 }
 208 #else /* debugging is disabled */
 209 static int debugging;
 210
 211 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 212         int expected, unsigned long start, unsigned long end)
 213 {
 214         return ~0UL;
 215 }
 216
 217 #endif /* CONFIG_IOMMU_DEBUG */
 218
 219 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
 220 {
 221         unsigned int npages;
 222
 223         npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
 224         npages >>= PAGE_SHIFT;
 225
 226         return npages;
 227 }
 228
 229 static inline int translation_enabled(struct iommu_table *tbl)
 230 {
 231         /* only PHBs with translation enabled have an IOMMU table */
 232         return (tbl != NULL);
 233 }
 234
 235 static void iommu_range_reserve(struct iommu_table *tbl,
 236         unsigned long start_addr, unsigned int npages)
 237 {
 238         unsigned long index;
 239         unsigned long end;
 240         unsigned long badbit;
 241         unsigned long flags;
 242
 243         index = start_addr >> PAGE_SHIFT;
 244
 245         /* bail out if we're asked to reserve a region we don't cover */
 246         if (index >= tbl->it_size)
 247                 return;
 248
 249         end = index + npages;
 250         if (end > tbl->it_size) /* don't go off the table */
 251                 end = tbl->it_size;
 252
 253         spin_lock_irqsave(&tbl->it_lock, flags);
 254
 255         badbit = verify_bit_range(tbl->it_map, 0, index, end);
 256         if (badbit != ~0UL) {
 257                 if (printk_ratelimit())
 258                         printk(KERN_ERR "Calgary: entry already allocated at "
 259                                "0x%lx tbl %p dma 0x%lx npages %u\n",
 260                                badbit, tbl, start_addr, npages);
 261         }
 262
 263         set_bit_string(tbl->it_map, index, npages);
 264
 265         spin_unlock_irqrestore(&tbl->it_lock, flags);
 266 }
 267
 268 static unsigned long iommu_range_alloc(struct device *dev,
 269                                        struct iommu_table *tbl,
 270                                        unsigned int npages)
 271 {
 272         unsigned long flags;
 273         unsigned long offset;
 274         unsigned long boundary_size;
 275
 276         boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
 277                               PAGE_SIZE) >> PAGE_SHIFT;
 278
 279         BUG_ON(npages == 0);
 280
 281         spin_lock_irqsave(&tbl->it_lock, flags);
 282
 283         offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint,
 284                                   npages, 0, boundary_size, 0);
 285         if (offset == ~0UL) {
 286                 tbl->chip_ops->tce_cache_blast(tbl);
 287
 288                 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0,
 289                                           npages, 0, boundary_size, 0);
 290                 if (offset == ~0UL) {
 291                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
 292                         spin_unlock_irqrestore(&tbl->it_lock, flags);
 293                         if (panic_on_overflow)
 294                                 panic("Calgary: fix the allocator.\n");
 295                         else
 296                                 return bad_dma_address;
 297                 }
 298         }
 299
 300         tbl->it_hint = offset + npages;
 301         BUG_ON(tbl->it_hint > tbl->it_size);
 302
 303         spin_unlock_irqrestore(&tbl->it_lock, flags);
 304
 305         return offset;
 306 }
 307
 308 static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
 309                               void *vaddr, unsigned int npages, int direction)
 310 {
 311         unsigned long entry;
 312         dma_addr_t ret = bad_dma_address;
 313
 314         entry = iommu_range_alloc(dev, tbl, npages);
 315
 316         if (unlikely(entry == bad_dma_address))
 317                 goto error;
 318
 319         /* set the return dma address */
 320         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 321
 322         /* put the TCEs in the HW table */
 323         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 324                   direction);
 325
 326         return ret;
 327
 328 error:
 329         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
 330                "iommu %p\n", npages, tbl);
 331         return bad_dma_address;
 332 }
 333
 334 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 335         unsigned int npages)
 336 {
 337         unsigned long entry;
 338         unsigned long badbit;
 339         unsigned long badend;
 340         unsigned long flags;
 341
 342         /* were we called with bad_dma_address? */
 343         badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE);
 344         if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) {
 345                 printk(KERN_ERR "Calgary: driver tried unmapping bad DMA "
 346                        "address 0x%Lx\n", dma_addr);
 347                 WARN_ON(1);
 348                 return;
 349         }
 350
 351         entry = dma_addr >> PAGE_SHIFT;
 352
 353         BUG_ON(entry + npages > tbl->it_size);
 354
 355         tce_free(tbl, entry, npages);
 356
 357         spin_lock_irqsave(&tbl->it_lock, flags);
 358
 359         badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
 360         if (badbit != ~0UL) {
 361                 if (printk_ratelimit())
 362                         printk(KERN_ERR "Calgary: bit is off at 0x%lx "
 363                                "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
 364                                badbit, tbl, dma_addr, entry, npages);
 365         }
 366
 367         iommu_area_free(tbl->it_map, entry, npages);
 368
 369         spin_unlock_irqrestore(&tbl->it_lock, flags);
 370 }
 371
 372 static inline struct iommu_table *find_iommu_table(struct device *dev)
 373 {
 374         struct pci_dev *pdev;
 375         struct pci_bus *pbus;
 376         struct iommu_table *tbl;
 377
 378         pdev = to_pci_dev(dev);
 379
 380         pbus = pdev->bus;
 381
 382         /* is the device behind a bridge? Look for the root bus */
 383         while (pbus->parent)
 384                 pbus = pbus->parent;
 385
 386         tbl = pci_iommu(pbus);
 387
 388         BUG_ON(tbl && (tbl->it_busno != pbus->number));
 389
 390         return tbl;
 391 }
 392
 393 static void calgary_unmap_sg(struct device *dev,
 394         struct scatterlist *sglist, int nelems, int direction)
 395 {
 396         struct iommu_table *tbl = find_iommu_table(dev);
 397         struct scatterlist *s;
 398         int i;
 399
 400         if (!translation_enabled(tbl))
 401                 return;
 402
 403         for_each_sg(sglist, s, nelems, i) {
 404                 unsigned int npages;
 405                 dma_addr_t dma = s->dma_address;
 406                 unsigned int dmalen = s->dma_length;
 407
 408                 if (dmalen == 0)
 409                         break;
 410
 411                 npages = num_dma_pages(dma, dmalen);
 412                 iommu_free(tbl, dma, npages);
 413         }
 414 }
 415
 416 static int calgary_nontranslate_map_sg(struct device* dev,
 417         struct scatterlist *sg, int nelems, int direction)
 418 {
 419         struct scatterlist *s;
 420         int i;
 421
 422         for_each_sg(sg, s, nelems, i) {
 423                 struct page *p = sg_page(s);
 424
 425                 BUG_ON(!p);
 426                 s->dma_address = virt_to_bus(sg_virt(s));
 427                 s->dma_length = s->length;
 428         }
 429         return nelems;
 430 }
 431
 432 static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 433         int nelems, int direction)
 434 {
 435         struct iommu_table *tbl = find_iommu_table(dev);
 436         struct scatterlist *s;
 437         unsigned long vaddr;
 438         unsigned int npages;
 439         unsigned long entry;
 440         int i;
 441
 442         if (!translation_enabled(tbl))
 443                 return calgary_nontranslate_map_sg(dev, sg, nelems, direction);
 444
 445         for_each_sg(sg, s, nelems, i) {
 446                 BUG_ON(!sg_page(s));
 447
 448                 vaddr = (unsigned long) sg_virt(s);
 449                 npages = num_dma_pages(vaddr, s->length);
 450
 451                 entry = iommu_range_alloc(dev, tbl, npages);
 452                 if (entry == bad_dma_address) {
 453                         /* makes sure unmap knows to stop */
 454                         s->dma_length = 0;
 455                         goto error;
 456                 }
 457
 458                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 459
 460                 /* insert into HW table */
 461                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
 462                           direction);
 463
 464                 s->dma_length = s->length;
 465         }
 466
 467         return nelems;
 468 error:
 469         calgary_unmap_sg(dev, sg, nelems, direction);
 470         for_each_sg(sg, s, nelems, i) {
 471                 sg->dma_address = bad_dma_address;
 472                 sg->dma_length = 0;
 473         }
 474         return 0;
 475 }
 476
 477 static dma_addr_t calgary_map_single(struct device *dev, phys_addr_t paddr,
 478         size_t size, int direction)
 479 {
 480         dma_addr_t dma_handle = bad_dma_address;
 481         void *vaddr = phys_to_virt(paddr);
 482         unsigned long uaddr;
 483         unsigned int npages;
 484         struct iommu_table *tbl = find_iommu_table(dev);
 485
 486         uaddr = (unsigned long)vaddr;
 487         npages = num_dma_pages(uaddr, size);
 488
 489         if (translation_enabled(tbl))
 490                 dma_handle = iommu_alloc(dev, tbl, vaddr, npages, direction);
 491         else
 492                 dma_handle = virt_to_bus(vaddr);
 493
 494         return dma_handle;
 495 }
 496
 497 static void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
 498         size_t size, int direction)
 499 {
 500         struct iommu_table *tbl = find_iommu_table(dev);
 501         unsigned int npages;
 502
 503         if (!translation_enabled(tbl))
 504                 return;
 505
 506         npages = num_dma_pages(dma_handle, size);
 507         iommu_free(tbl, dma_handle, npages);
 508 }
 509
 510 static void* calgary_alloc_coherent(struct device *dev, size_t size,
 511         dma_addr_t *dma_handle, gfp_t flag)
 512 {
 513         void *ret = NULL;
 514         dma_addr_t mapping;
 515         unsigned int npages, order;
 516         struct iommu_table *tbl = find_iommu_table(dev);
 517
 518         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 519         npages = size >> PAGE_SHIFT;
 520         order = get_order(size);
 521
 522         /* alloc enough pages (and possibly more) */
 523         ret = (void *)__get_free_pages(flag, order);
 524         if (!ret)
 525                 goto error;
 526         memset(ret, 0, size);
 527
 528         if (translation_enabled(tbl)) {
 529                 /* set up tces to cover the allocated range */
 530                 mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL);
 531                 if (mapping == bad_dma_address)
 532                         goto free;
 533
 534                 *dma_handle = mapping;
 535         } else /* non translated slot */
 536                 *dma_handle = virt_to_bus(ret);
 537
 538         return ret;
 539
 540 free:
 541         free_pages((unsigned long)ret, get_order(size));
 542         ret = NULL;
 543 error:
 544         return ret;
 545 }
 546
 547 static struct dma_mapping_ops calgary_dma_ops = {
 548         .alloc_coherent = calgary_alloc_coherent,
 549         .map_single = calgary_map_single,
 550         .unmap_single = calgary_unmap_single,
 551         .map_sg = calgary_map_sg,
 552         .unmap_sg = calgary_unmap_sg,
 553 };
 554
 555 static inline void __iomem * busno_to_bbar(unsigned char num)
 556 {
 557         return bus_info[num].bbar;
 558 }
 559
 560 static inline int busno_to_phbid(unsigned char num)
 561 {
 562         return bus_info[num].phbid;
 563 }
 564
 565 static inline unsigned long split_queue_offset(unsigned char num)
 566 {
 567         size_t idx = busno_to_phbid(num);
 568
 569         return split_queue_offsets[idx];
 570 }
 571
 572 static inline unsigned long tar_offset(unsigned char num)
 573 {
 574         size_t idx = busno_to_phbid(num);
 575
 576         return tar_offsets[idx];
 577 }
 578
 579 static inline unsigned long phb_offset(unsigned char num)
 580 {
 581         size_t idx = busno_to_phbid(num);
 582
 583         return phb_offsets[idx];
 584 }
 585
 586 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 587 {
 588         unsigned long target = ((unsigned long)bar) | offset;
 589         return (void __iomem*)target;
 590 }
 591
 592 static inline int is_calioc2(unsigned short device)
 593 {
 594         return (device == PCI_DEVICE_ID_IBM_CALIOC2);
 595 }
 596
 597 static inline int is_calgary(unsigned short device)
 598 {
 599         return (device == PCI_DEVICE_ID_IBM_CALGARY);
 600 }
 601
 602 static inline int is_cal_pci_dev(unsigned short device)
 603 {
 604         return (is_calgary(device) || is_calioc2(device));
 605 }
 606
 607 static void calgary_tce_cache_blast(struct iommu_table *tbl)
 608 {
 609         u64 val;
 610         u32 aer;
 611         int i = 0;
 612         void __iomem *bbar = tbl->bbar;
 613         void __iomem *target;
 614
 615         /* disable arbitration on the bus */
 616         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 617         aer = readl(target);
 618         writel(0, target);
 619
 620         /* read plssr to ensure it got there */
 621         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 622         val = readl(target);
 623
 624         /* poll split queues until all DMA activity is done */
 625         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 626         do {
 627                 val = readq(target);
 628                 i++;
 629         } while ((val & 0xff) != 0xff && i < 100);
 630         if (i == 100)
 631                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
 632                        "continuing anyway\n");
 633
 634         /* invalidate TCE cache */
 635         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 636         writeq(tbl->tar_val, target);
 637
 638         /* enable arbitration */
 639         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 640         writel(aer, target);
 641         (void)readl(target); /* flush */
 642 }
 643
 644 static void calioc2_tce_cache_blast(struct iommu_table *tbl)
 645 {
 646         void __iomem *bbar = tbl->bbar;
 647         void __iomem *target;
 648         u64 val64;
 649         u32 val;
 650         int i = 0;
 651         int count = 1;
 652         unsigned char bus = tbl->it_busno;
 653
 654 begin:
 655         printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
 656                "sequence - count %d\n", bus, count);
 657
 658         /* 1. using the Page Migration Control reg set SoftStop */
 659         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 660         val = be32_to_cpu(readl(target));
 661         printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
 662         val |= PMR_SOFTSTOP;
 663         printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
 664         writel(cpu_to_be32(val), target);
 665
 666         /* 2. poll split queues until all DMA activity is done */
 667         printk(KERN_DEBUG "2a. starting to poll split queues\n");
 668         target = calgary_reg(bbar, split_queue_offset(bus));
 669         do {
 670                 val64 = readq(target);
 671                 i++;
 672         } while ((val64 & 0xff) != 0xff && i < 100);
 673         if (i == 100)
 674                 printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, "
 675                        "continuing anyway\n");
 676
 677         /* 3. poll Page Migration DEBUG for SoftStopFault */
 678         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 679         val = be32_to_cpu(readl(target));
 680         printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
 681
 682         /* 4. if SoftStopFault - goto (1) */
 683         if (val & PMR_SOFTSTOPFAULT) {
 684                 if (++count < 100)
 685                         goto begin;
 686                 else {
 687                         printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, "
 688                                "aborting TCE cache flush sequence!\n");
 689                         return; /* pray for the best */
 690                 }
 691         }
 692
 693         /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
 694         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 695         printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
 696         val = be32_to_cpu(readl(target));
 697         printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
 698         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 699         val = be32_to_cpu(readl(target));
 700         printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
 701
 702         /* 6. invalidate TCE cache */
 703         printk(KERN_DEBUG "6. invalidating TCE cache\n");
 704         target = calgary_reg(bbar, tar_offset(bus));
 705         writeq(tbl->tar_val, target);
 706
 707         /* 7. Re-read PMCR */
 708         printk(KERN_DEBUG "7a. Re-reading PMCR\n");
 709         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 710         val = be32_to_cpu(readl(target));
 711         printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
 712
 713         /* 8. Remove HardStop */
 714         printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
 715         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 716         val = 0;
 717         printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
 718         writel(cpu_to_be32(val), target);
 719         val = be32_to_cpu(readl(target));
 720         printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
 721 }
 722
 723 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 724         u64 limit)
 725 {
 726         unsigned int numpages;
 727
 728         limit = limit | 0xfffff;
 729         limit++;
 730
 731         numpages = ((limit - start) >> PAGE_SHIFT);
 732         iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
 733 }
 734
 735 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 736 {
 737         void __iomem *target;
 738         u64 low, high, sizelow;
 739         u64 start, limit;
 740         struct iommu_table *tbl = pci_iommu(dev->bus);
 741         unsigned char busnum = dev->bus->number;
 742         void __iomem *bbar = tbl->bbar;
 743
 744         /* peripheral MEM_1 region */
 745         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 746         low = be32_to_cpu(readl(target));
 747         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 748         high = be32_to_cpu(readl(target));
 749         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 750         sizelow = be32_to_cpu(readl(target));
 751
 752         start = (high << 32) | low;
 753         limit = sizelow;
 754
 755         calgary_reserve_mem_region(dev, start, limit);
 756 }
 757
 758 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 759 {
 760         void __iomem *target;
 761         u32 val32;
 762         u64 low, high, sizelow, sizehigh;
 763         u64 start, limit;
 764         struct iommu_table *tbl = pci_iommu(dev->bus);
 765         unsigned char busnum = dev->bus->number;
 766         void __iomem *bbar = tbl->bbar;
 767
 768         /* is it enabled? */
 769         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 770         val32 = be32_to_cpu(readl(target));
 771         if (!(val32 & PHB_MEM2_ENABLE))
 772                 return;
 773
 774         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 775         low = be32_to_cpu(readl(target));
 776         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 777         high = be32_to_cpu(readl(target));
 778         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 779         sizelow = be32_to_cpu(readl(target));
 780         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 781         sizehigh = be32_to_cpu(readl(target));
 782
 783         start = (high << 32) | low;
 784         limit = (sizehigh << 32) | sizelow;
 785
 786         calgary_reserve_mem_region(dev, start, limit);
 787 }
 788
 789 /*
 790  * some regions of the IO address space do not get translated, so we
 791  * must not give devices IO addresses in those regions. The regions
 792  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 793  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 794  * later.
 795  */
 796 static void __init calgary_reserve_regions(struct pci_dev *dev)
 797 {
 798         unsigned int npages;
 799         u64 start;
 800         struct iommu_table *tbl = pci_iommu(dev->bus);
 801
 802         /* reserve EMERGENCY_PAGES from bad_dma_address and up */
 803         iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES);
 804
 805         /* avoid the BIOS/VGA first 640KB-1MB region */
 806         /* for CalIOC2 - avoid the entire first MB */
 807         if (is_calgary(dev->device)) {
 808                 start = (640 * 1024);
 809                 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 810         } else { /* calioc2 */
 811                 start = 0;
 812                 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
 813         }
 814         iommu_range_reserve(tbl, start, npages);
 815
 816         /* reserve the two PCI peripheral memory regions in IO space */
 817         calgary_reserve_peripheral_mem_1(dev);
 818         calgary_reserve_peripheral_mem_2(dev);
 819 }
 820
 821 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 822 {
 823         u64 val64;
 824         u64 table_phys;
 825         void __iomem *target;
 826         int ret;
 827         struct iommu_table *tbl;
 828
 829         /* build TCE tables for each PHB */
 830         ret = build_tce_table(dev, bbar);
 831         if (ret)
 832                 return ret;
 833
 834         tbl = pci_iommu(dev->bus);
 835         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
 836
 837         if (is_kdump_kernel())
 838                 calgary_init_bitmap_from_tce_table(tbl);
 839         else
 840                 tce_free(tbl, 0, tbl->it_size);
 841
 842         if (is_calgary(dev->device))
 843                 tbl->chip_ops = &calgary_chip_ops;
 844         else if (is_calioc2(dev->device))
 845                 tbl->chip_ops = &calioc2_chip_ops;
 846         else
 847                 BUG();
 848
 849         calgary_reserve_regions(dev);
 850
 851         /* set TARs for each PHB */
 852         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 853         val64 = be64_to_cpu(readq(target));
 854
 855         /* zero out all TAR bits under sw control */
 856         val64 &= ~TAR_SW_BITS;
 857         table_phys = (u64)__pa(tbl->it_base);
 858
 859         val64 |= table_phys;
 860
 861         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 862         val64 |= (u64) specified_table_size;
 863
 864         tbl->tar_val = cpu_to_be64(val64);
 865
 866         writeq(tbl->tar_val, target);
 867         readq(target); /* flush */
 868
 869         return 0;
 870 }
 871
 872 static void __init calgary_free_bus(struct pci_dev *dev)
 873 {
 874         u64 val64;
 875         struct iommu_table *tbl = pci_iommu(dev->bus);
 876         void __iomem *target;
 877         unsigned int bitmapsz;
 878
 879         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 880         val64 = be64_to_cpu(readq(target));
 881         val64 &= ~TAR_SW_BITS;
 882         writeq(cpu_to_be64(val64), target);
 883         readq(target); /* flush */
 884
 885         bitmapsz = tbl->it_size / BITS_PER_BYTE;
 886         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
 887         tbl->it_map = NULL;
 888
 889         kfree(tbl);
 890
 891         set_pci_iommu(dev->bus, NULL);
 892
 893         /* Can't free bootmem allocated memory after system is up :-( */
 894         bus_info[dev->bus->number].tce_space = NULL;
 895 }
 896
 897 static void calgary_dump_error_regs(struct iommu_table *tbl)
 898 {
 899         void __iomem *bbar = tbl->bbar;
 900         void __iomem *target;
 901         u32 csr, plssr;
 902
 903         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 904         csr = be32_to_cpu(readl(target));
 905
 906         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 907         plssr = be32_to_cpu(readl(target));
 908
 909         /* If no error, the agent ID in the CSR is not valid */
 910         printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
 911                "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr);
 912 }
 913
 914 static void calioc2_dump_error_regs(struct iommu_table *tbl)
 915 {
 916         void __iomem *bbar = tbl->bbar;
 917         u32 csr, csmr, plssr, mck, rcstat;
 918         void __iomem *target;
 919         unsigned long phboff = phb_offset(tbl->it_busno);
 920         unsigned long erroff;
 921         u32 errregs[7];
 922         int i;
 923
 924         /* dump CSR */
 925         target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
 926         csr = be32_to_cpu(readl(target));
 927         /* dump PLSSR */
 928         target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
 929         plssr = be32_to_cpu(readl(target));
 930         /* dump CSMR */
 931         target = calgary_reg(bbar, phboff | 0x290);
 932         csmr = be32_to_cpu(readl(target));
 933         /* dump mck */
 934         target = calgary_reg(bbar, phboff | 0x800);
 935         mck = be32_to_cpu(readl(target));
 936
 937         printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
 938                tbl->it_busno);
 939
 940         printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
 941                csr, plssr, csmr, mck);
 942
 943         /* dump rest of error regs */
 944         printk(KERN_EMERG "Calgary: ");
 945         for (i = 0; i < ARRAY_SIZE(errregs); i++) {
 946                 /* err regs are at 0x810 - 0x870 */
 947                 erroff = (0x810 + (i * 0x10));
 948                 target = calgary_reg(bbar, phboff | erroff);
 949                 errregs[i] = be32_to_cpu(readl(target));
 950                 printk("0x%08x@0x%lx ", errregs[i], erroff);
 951         }
 952         printk("\n");
 953
 954         /* root complex status */
 955         target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
 956         rcstat = be32_to_cpu(readl(target));
 957         printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
 958                PHB_ROOT_COMPLEX_STATUS);
 959 }
 960
 961 static void calgary_watchdog(unsigned long data)
 962 {
 963         struct pci_dev *dev = (struct pci_dev *)data;
 964         struct iommu_table *tbl = pci_iommu(dev->bus);
 965         void __iomem *bbar = tbl->bbar;
 966         u32 val32;
 967         void __iomem *target;
 968
 969         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 970         val32 = be32_to_cpu(readl(target));
 971
 972         /* If no error, the agent ID in the CSR is not valid */
 973         if (val32 & CSR_AGENT_MASK) {
 974                 tbl->chip_ops->dump_error_regs(tbl);
 975
 976                 /* reset error */
 977                 writel(0, target);
 978
 979                 /* Disable bus that caused the error */
 980                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 981                                      PHB_CONFIG_RW_OFFSET);
 982                 val32 = be32_to_cpu(readl(target));
 983                 val32 |= PHB_SLOT_DISABLE;
 984                 writel(cpu_to_be32(val32), target);
 985                 readl(target); /* flush */
 986         } else {
 987                 /* Reset the timer */
 988                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 989         }
 990 }
 991
 992 static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
 993         unsigned char busnum, unsigned long timeout)
 994 {
 995         u64 val64;
 996         void __iomem *target;
 997         unsigned int phb_shift = ~0; /* silence gcc */
 998         u64 mask;
 999
1000         switch (busno_to_phbid(busnum)) {
1001         case 0: phb_shift = (63 - 19);
1002                 break;
1003         case 1: phb_shift = (63 - 23);
1004                 break;
1005         case 2: phb_shift = (63 - 27);
1006                 break;
1007         case 3: phb_shift = (63 - 35);
1008                 break;
1009         default:
1010                 BUG_ON(busno_to_phbid(busnum));
1011         }
1012
1013         target = calgary_reg(bbar, CALGARY_CONFIG_REG);
1014         val64 = be64_to_cpu(readq(target));
1015
1016         /* zero out this PHB's timer bits */
1017         mask = ~(0xFUL << phb_shift);
1018         val64 &= mask;
1019         val64 |= (timeout << phb_shift);
1020         writeq(cpu_to_be64(val64), target);
1021         readq(target); /* flush */
1022 }
1023
1024 static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1025 {
1026         unsigned char busnum = dev->bus->number;
1027         void __iomem *bbar = tbl->bbar;
1028         void __iomem *target;
1029         u32 val;
1030
1031         /*
1032          * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
1033          */
1034         target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
1035         val = cpu_to_be32(readl(target));
1036         val |= 0x00800000;
1037         writel(cpu_to_be32(val), target);
1038 }
1039
1040 static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1041 {
1042         unsigned char busnum = dev->bus->number;
1043
1044         /*
1045          * Give split completion a longer timeout on bus 1 for aic94xx
1046          * http://bugzilla.kernel.org/show_bug.cgi?id=7180
1047          */
1048         if (is_calgary(dev->device) && (busnum == 1))
1049                 calgary_set_split_completion_timeout(tbl->bbar, busnum,
1050                                                      CCR_2SEC_TIMEOUT);
1051 }
1052
1053 static void __init calgary_enable_translation(struct pci_dev *dev)
1054 {
1055         u32 val32;
1056         unsigned char busnum;
1057         void __iomem *target;
1058         void __iomem *bbar;
1059         struct iommu_table *tbl;
1060
1061         busnum = dev->bus->number;
1062         tbl = pci_iommu(dev->bus);
1063         bbar = tbl->bbar;
1064
1065         /* enable TCE in PHB Config Register */
1066         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1067         val32 = be32_to_cpu(readl(target));
1068         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
1069
1070         printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
1071                (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
1072                "Calgary" : "CalIOC2", busnum);
1073         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1074                "bus.\n");
1075
1076         writel(cpu_to_be32(val32), target);
1077         readl(target); /* flush */
1078
1079         init_timer(&tbl->watchdog_timer);
1080         tbl->watchdog_timer.function = &calgary_watchdog;
1081         tbl->watchdog_timer.data = (unsigned long)dev;
1082         mod_timer(&tbl->watchdog_timer, jiffies);
1083 }
1084
1085 static void __init calgary_disable_translation(struct pci_dev *dev)
1086 {
1087         u32 val32;
1088         unsigned char busnum;
1089         void __iomem *target;
1090         void __iomem *bbar;
1091         struct iommu_table *tbl;
1092
1093         busnum = dev->bus->number;
1094         tbl = pci_iommu(dev->bus);
1095         bbar = tbl->bbar;
1096
1097         /* disable TCE in PHB Config Register */
1098         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1099         val32 = be32_to_cpu(readl(target));
1100         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1101
1102         printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1103         writel(cpu_to_be32(val32), target);
1104         readl(target); /* flush */
1105
1106         del_timer_sync(&tbl->watchdog_timer);
1107 }
1108
1109 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1110 {
1111         pci_dev_get(dev);
1112         set_pci_iommu(dev->bus, NULL);
1113
1114         /* is the device behind a bridge? */
1115         if (dev->bus->parent)
1116                 dev->bus->parent->self = dev;
1117         else
1118                 dev->bus->self = dev;
1119 }
1120
1121 static int __init calgary_init_one(struct pci_dev *dev)
1122 {
1123         void __iomem *bbar;
1124         struct iommu_table *tbl;
1125         int ret;
1126
1127         BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
1128
1129         bbar = busno_to_bbar(dev->bus->number);
1130         ret = calgary_setup_tar(dev, bbar);
1131         if (ret)
1132                 goto done;
1133
1134         pci_dev_get(dev);
1135
1136         if (dev->bus->parent) {
1137                 if (dev->bus->parent->self)
1138                         printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1139                                "bus->parent->self!\n", dev);
1140                 dev->bus->parent->self = dev;
1141         } else
1142                 dev->bus->self = dev;
1143
1144         tbl = pci_iommu(dev->bus);
1145         tbl->chip_ops->handle_quirks(tbl, dev);
1146
1147         calgary_enable_translation(dev);
1148
1149         return 0;
1150
1151 done:
1152         return ret;
1153 }
1154
1155 static int __init calgary_locate_bbars(void)
1156 {
1157         int ret;
1158         int rioidx, phb, bus;
1159         void __iomem *bbar;
1160         void __iomem *target;
1161         unsigned long offset;
1162         u8 start_bus, end_bus;
1163         u32 val;
1164
1165         ret = -ENODATA;
1166         for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1167                 struct rio_detail *rio = rio_devs[rioidx];
1168
1169                 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1170                         continue;
1171
1172                 /* map entire 1MB of Calgary config space */
1173                 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1174                 if (!bbar)
1175                         goto error;
1176
1177                 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1178                         offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1179                         target = calgary_reg(bbar, offset);
1180
1181                         val = be32_to_cpu(readl(target));
1182
1183                         start_bus = (u8)((val & 0x00FF0000) >> 16);
1184                         end_bus = (u8)((val & 0x0000FF00) >> 8);
1185
1186                         if (end_bus) {
1187                                 for (bus = start_bus; bus <= end_bus; bus++) {
1188                                         bus_info[bus].bbar = bbar;
1189                                         bus_info[bus].phbid = phb;
1190                                 }
1191                         } else {
1192                                 bus_info[start_bus].bbar = bbar;
1193                                 bus_info[start_bus].phbid = phb;
1194                         }
1195                 }
1196         }
1197
1198         return 0;
1199
1200 error:
1201         /* scan bus_info and iounmap any bbars we previously ioremap'd */
1202         for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1203                 if (bus_info[bus].bbar)
1204                         iounmap(bus_info[bus].bbar);
1205
1206         return ret;
1207 }
1208
1209 static int __init calgary_init(void)
1210 {
1211         int ret;
1212         struct pci_dev *dev = NULL;
1213         struct calgary_bus_info *info;
1214
1215         ret = calgary_locate_bbars();
1216         if (ret)
1217                 return ret;
1218
1219         /* Purely for kdump kernel case */
1220         if (is_kdump_kernel())
1221                 get_tce_space_from_tar();
1222
1223         do {
1224                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1225                 if (!dev)
1226                         break;
1227                 if (!is_cal_pci_dev(dev->device))
1228                         continue;
1229
1230                 info = &bus_info[dev->bus->number];
1231                 if (info->translation_disabled) {
1232                         calgary_init_one_nontraslated(dev);
1233                         continue;
1234                 }
1235
1236                 if (!info->tce_space && !translate_empty_slots)
1237                         continue;
1238
1239                 ret = calgary_init_one(dev);
1240                 if (ret)
1241                         goto error;
1242         } while (1);
1243
1244         return ret;
1245
1246 error:
1247         do {
1248                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1249                 if (!dev)
1250                         break;
1251                 if (!is_cal_pci_dev(dev->device))
1252                         continue;
1253
1254                 info = &bus_info[dev->bus->number];
1255                 if (info->translation_disabled) {
1256                         pci_dev_put(dev);
1257                         continue;
1258                 }
1259                 if (!info->tce_space && !translate_empty_slots)
1260                         continue;
1261
1262                 calgary_disable_translation(dev);
1263                 calgary_free_bus(dev);
1264                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1265         } while (1);
1266
1267         return ret;
1268 }
1269
1270 static inline int __init determine_tce_table_size(u64 ram)
1271 {
1272         int ret;
1273
1274         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1275                 return specified_table_size;
1276
1277         /*
1278          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1279          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1280          * larger table size has twice as many entries, so shift the
1281          * max ram address by 13 to divide by 8K and then look at the
1282          * order of the result to choose between 0-7.
1283          */
1284         ret = get_order(ram >> 13);
1285         if (ret > TCE_TABLE_SIZE_8M)
1286                 ret = TCE_TABLE_SIZE_8M;
1287
1288         return ret;
1289 }
1290
1291 static int __init build_detail_arrays(void)
1292 {
1293         unsigned long ptr;
1294         int i, scal_detail_size, rio_detail_size;
1295
1296         if (rio_table_hdr->num_scal_dev > MAX_NUMNODES){
1297                 printk(KERN_WARNING
1298                         "Calgary: MAX_NUMNODES too low! Defined as %d, "
1299                         "but system has %d nodes.\n",
1300                         MAX_NUMNODES, rio_table_hdr->num_scal_dev);
1301                 return -ENODEV;
1302         }
1303
1304         switch (rio_table_hdr->version){
1305         case 2:
1306                 scal_detail_size = 11;
1307                 rio_detail_size = 13;
1308                 break;
1309         case 3:
1310                 scal_detail_size = 12;
1311                 rio_detail_size = 15;
1312                 break;
1313         default:
1314                 printk(KERN_WARNING
1315                        "Calgary: Invalid Rio Grande Table Version: %d\n",
1316                        rio_table_hdr->version);
1317                 return -EPROTO;
1318         }
1319
1320         ptr = ((unsigned long)rio_table_hdr) + 3;
1321         for (i = 0; i < rio_table_hdr->num_scal_dev;
1322                     i++, ptr += scal_detail_size)
1323                 scal_devs[i] = (struct scal_detail *)ptr;
1324
1325         for (i = 0; i < rio_table_hdr->num_rio_dev;
1326                     i++, ptr += rio_detail_size)
1327                 rio_devs[i] = (struct rio_detail *)ptr;
1328
1329         return 0;
1330 }
1331
1332 static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1333 {
1334         int dev;
1335         u32 val;
1336
1337         if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1338                 /*
1339                  * FIXME: properly scan for devices accross the
1340                  * PCI-to-PCI bridge on every CalIOC2 port.
1341                  */
1342                 return 1;
1343         }
1344
1345         for (dev = 1; dev < 8; dev++) {
1346                 val = read_pci_config(bus, dev, 0, 0);
1347                 if (val != 0xffffffff)
1348                         break;
1349         }
1350         return (val != 0xffffffff);
1351 }
1352
1353 /*
1354  * calgary_init_bitmap_from_tce_table():
1355  * Funtion for kdump case. In the second/kdump kernel initialize
1356  * the bitmap based on the tce table entries obtained from first kernel
1357  */
1358 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl)
1359 {
1360         u64 *tp;
1361         unsigned int index;
1362         tp = ((u64 *)tbl->it_base);
1363         for (index = 0 ; index < tbl->it_size; index++) {
1364                 if (*tp != 0x0)
1365                         set_bit(index, tbl->it_map);
1366                 tp++;
1367         }
1368 }
1369
1370 /*
1371  * get_tce_space_from_tar():
1372  * Function for kdump case. Get the tce tables from first kernel
1373  * by reading the contents of the base adress register of calgary iommu
1374  */
1375 static void get_tce_space_from_tar()
1376 {
1377         int bus;
1378         void __iomem *target;
1379         unsigned long tce_space;
1380
1381         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1382                 struct calgary_bus_info *info = &bus_info[bus];
1383                 unsigned short pci_device;
1384                 u32 val;
1385
1386                 val = read_pci_config(bus, 0, 0, 0);
1387                 pci_device = (val & 0xFFFF0000) >> 16;
1388
1389                 if (!is_cal_pci_dev(pci_device))
1390                         continue;
1391                 if (info->translation_disabled)
1392                         continue;
1393
1394                 if (calgary_bus_has_devices(bus, pci_device) ||
1395                                                 translate_empty_slots) {
1396                         target = calgary_reg(bus_info[bus].bbar,
1397                                                 tar_offset(bus));
1398                         tce_space = be64_to_cpu(readq(target));
1399                         tce_space = tce_space & TAR_SW_BITS;
1400
1401                         tce_space = tce_space & (~specified_table_size);
1402                         info->tce_space = (u64 *)__va(tce_space);
1403                 }
1404         }
1405         return;
1406 }
1407
1408 void __init detect_calgary(void)
1409 {
1410         int bus;
1411         void *tbl;
1412         int calgary_found = 0;
1413         unsigned long ptr;
1414         unsigned int offset, prev_offset;
1415         int ret;
1416
1417         /*
1418          * if the user specified iommu=off or iommu=soft or we found
1419          * another HW IOMMU already, bail out.
1420          */
1421         if (swiotlb || no_iommu || iommu_detected)
1422                 return;
1423
1424         if (!use_calgary)
1425                 return;
1426
1427         if (!early_pci_allowed())
1428                 return;
1429
1430         printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1431
1432         ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1433
1434         rio_table_hdr = NULL;
1435         prev_offset = 0;
1436         offset = 0x180;
1437         /*
1438          * The next offset is stored in the 1st word.
1439          * Only parse up until the offset increases:
1440          */
1441         while (offset > prev_offset) {
1442                 /* The block id is stored in the 2nd word */
1443                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1444                         /* set the pointer past the offset & block id */
1445                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1446                         break;
1447                 }
1448                 prev_offset = offset;
1449                 offset = *((unsigned short *)(ptr + offset));
1450         }
1451         if (!rio_table_hdr) {
1452                 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1453                        "in EBDA - bailing!\n");
1454                 return;
1455         }
1456
1457         ret = build_detail_arrays();
1458         if (ret) {
1459                 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1460                 return;
1461         }
1462
1463         specified_table_size = determine_tce_table_size((is_kdump_kernel() ?
1464                                         saved_max_pfn : max_pfn) * PAGE_SIZE);
1465
1466         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1467                 struct calgary_bus_info *info = &bus_info[bus];
1468                 unsigned short pci_device;
1469                 u32 val;
1470
1471                 val = read_pci_config(bus, 0, 0, 0);
1472                 pci_device = (val & 0xFFFF0000) >> 16;
1473
1474                 if (!is_cal_pci_dev(pci_device))
1475                         continue;
1476
1477                 if (info->translation_disabled)
1478                         continue;
1479
1480                 if (calgary_bus_has_devices(bus, pci_device) ||
1481                     translate_empty_slots) {
1482                         /*
1483                          * If it is kdump kernel, find and use tce tables
1484                          * from first kernel, else allocate tce tables here
1485                          */
1486                         if (!is_kdump_kernel()) {
1487                                 tbl = alloc_tce_table();
1488                                 if (!tbl)
1489                                         goto cleanup;
1490                                 info->tce_space = tbl;
1491                         }
1492                         calgary_found = 1;
1493                 }
1494         }
1495
1496         printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1497                calgary_found ? "found" : "not found");
1498
1499         if (calgary_found) {
1500                 iommu_detected = 1;
1501                 calgary_detected = 1;
1502                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1503                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
1504                        "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
1505                        debugging ? "enabled" : "disabled");
1506         }
1507         return;
1508
1509 cleanup:
1510         for (--bus; bus >= 0; --bus) {
1511                 struct calgary_bus_info *info = &bus_info[bus];
1512
1513                 if (info->tce_space)
1514                         free_tce_table(info->tce_space);
1515         }
1516 }
1517
1518 int __init calgary_iommu_init(void)
1519 {
1520         int ret;
1521
1522         if (no_iommu || swiotlb)
1523                 return -ENODEV;
1524
1525         if (!calgary_detected)
1526                 return -ENODEV;
1527
1528         /* ok, we're trying to use Calgary - let's roll */
1529         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1530
1531         ret = calgary_init();
1532         if (ret) {
1533                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1534                        "falling back to no_iommu\n", ret);
1535                 if (max_pfn > MAX_DMA32_PFN)
1536                         printk(KERN_ERR "WARNING more than 4GB of memory, "
1537                                         "32bit PCI may malfunction.\n");
1538                 return ret;
1539         }
1540
1541         force_iommu = 1;
1542         bad_dma_address = 0x0;
1543         dma_ops = &calgary_dma_ops;
1544
1545         return 0;
1546 }
1547
1548 static int __init calgary_parse_options(char *p)
1549 {
1550         unsigned int bridge;
1551         size_t len;
1552         char* endp;
1553
1554         while (*p) {
1555                 if (!strncmp(p, "64k", 3))
1556                         specified_table_size = TCE_TABLE_SIZE_64K;
1557                 else if (!strncmp(p, "128k", 4))
1558                         specified_table_size = TCE_TABLE_SIZE_128K;
1559                 else if (!strncmp(p, "256k", 4))
1560                         specified_table_size = TCE_TABLE_SIZE_256K;
1561                 else if (!strncmp(p, "512k", 4))
1562                         specified_table_size = TCE_TABLE_SIZE_512K;
1563                 else if (!strncmp(p, "1M", 2))
1564                         specified_table_size = TCE_TABLE_SIZE_1M;
1565                 else if (!strncmp(p, "2M", 2))
1566                         specified_table_size = TCE_TABLE_SIZE_2M;
1567                 else if (!strncmp(p, "4M", 2))
1568                         specified_table_size = TCE_TABLE_SIZE_4M;
1569                 else if (!strncmp(p, "8M", 2))
1570                         specified_table_size = TCE_TABLE_SIZE_8M;
1571
1572                 len = strlen("translate_empty_slots");
1573                 if (!strncmp(p, "translate_empty_slots", len))
1574                         translate_empty_slots = 1;
1575
1576                 len = strlen("disable");
1577                 if (!strncmp(p, "disable", len)) {
1578                         p += len;
1579                         if (*p == '=')
1580                                 ++p;
1581                         if (*p == '\0')
1582                                 break;
1583                         bridge = simple_strtol(p, &endp, 0);
1584                         if (p == endp)
1585                                 break;
1586
1587                         if (bridge < MAX_PHB_BUS_NUM) {
1588                                 printk(KERN_INFO "Calgary: disabling "
1589                                        "translation for PHB %#x\n", bridge);
1590                                 bus_info[bridge].translation_disabled = 1;
1591                         }
1592                 }
1593
1594                 p = strpbrk(p, ",");
1595                 if (!p)
1596                         break;
1597
1598                 p++; /* skip ',' */
1599         }
1600         return 1;
1601 }
1602 __setup("calgary=", calgary_parse_options);
1603
1604 static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1605 {
1606         struct iommu_table *tbl;
1607         unsigned int npages;
1608         int i;
1609
1610         tbl = pci_iommu(dev->bus);
1611
1612         for (i = 0; i < 4; i++) {
1613                 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1614
1615                 /* Don't give out TCEs that map MEM resources */
1616                 if (!(r->flags & IORESOURCE_MEM))
1617                         continue;
1618
1619                 /* 0-based? we reserve the whole 1st MB anyway */
1620                 if (!r->start)
1621                         continue;
1622
1623                 /* cover the whole region */
1624                 npages = (r->end - r->start) >> PAGE_SHIFT;
1625                 npages++;
1626
1627                 iommu_range_reserve(tbl, r->start, npages);
1628         }
1629 }
1630
1631 static int __init calgary_fixup_tce_spaces(void)
1632 {
1633         struct pci_dev *dev = NULL;
1634         struct calgary_bus_info *info;
1635
1636         if (no_iommu || swiotlb || !calgary_detected)
1637                 return -ENODEV;
1638
1639         printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1640
1641         do {
1642                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1643                 if (!dev)
1644                         break;
1645                 if (!is_cal_pci_dev(dev->device))
1646                         continue;
1647
1648                 info = &bus_info[dev->bus->number];
1649                 if (info->translation_disabled)
1650                         continue;
1651
1652                 if (!info->tce_space)
1653                         continue;
1654
1655                 calgary_fixup_one_tce_space(dev);
1656
1657         } while (1);
1658
1659         return 0;
1660 }
1661
1662 /*
1663  * We need to be call after pcibios_assign_resources (fs_initcall level)
1664  * and before device_initcall.
1665  */
1666 rootfs_initcall(calgary_fixup_tce_spaces);