arch/mips/mm/c-r4k.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
   7  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  */
  10 #include <linux/config.h>
  11 #include <linux/init.h>
  12 #include <linux/kernel.h>
  13 #include <linux/sched.h>
  14 #include <linux/mm.h>
  15 #include <linux/bitops.h>
  16
  17 #include <asm/bcache.h>
  18 #include <asm/bootinfo.h>
  19 #include <asm/cache.h>
  20 #include <asm/cacheops.h>
  21 #include <asm/cpu.h>
  22 #include <asm/cpu-features.h>
  23 #include <asm/io.h>
  24 #include <asm/page.h>
  25 #include <asm/pgtable.h>
  26 #include <asm/r4kcache.h>
  27 #include <asm/system.h>
  28 #include <asm/mmu_context.h>
  29 #include <asm/war.h>
  30 #include <asm/cacheflush.h> /* for run_uncached() */
  31
  32 /*
  33  * Must die.
  34  */
  35 static unsigned long icache_size __read_mostly;
  36 static unsigned long dcache_size __read_mostly;
  37 static unsigned long scache_size __read_mostly;
  38
  39 /*
  40  * Dummy cache handling routines for machines without boardcaches
  41  */
  42 static void no_sc_noop(void) {}
  43
  44 static struct bcache_ops no_sc_ops = {
  45         .bc_enable = (void *)no_sc_noop,
  46         .bc_disable = (void *)no_sc_noop,
  47         .bc_wback_inv = (void *)no_sc_noop,
  48         .bc_inv = (void *)no_sc_noop
  49 };
  50
  51 struct bcache_ops *bcops = &no_sc_ops;
  52
  53 #define cpu_is_r4600_v1_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002010)
  54 #define cpu_is_r4600_v2_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002020)
  55
  56 #define R4600_HIT_CACHEOP_WAR_IMPL                                      \
  57 do {                                                                    \
  58         if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())            \
  59                 *(volatile unsigned long *)CKSEG1;                      \
  60         if (R4600_V1_HIT_CACHEOP_WAR)                                   \
  61                 __asm__ __volatile__("nop;nop;nop;nop");                \
  62 } while (0)
  63
  64 static void (*r4k_blast_dcache_page)(unsigned long addr);
  65
  66 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
  67 {
  68         R4600_HIT_CACHEOP_WAR_IMPL;
  69         blast_dcache32_page(addr);
  70 }
  71
  72 static inline void r4k_blast_dcache_page_setup(void)
  73 {
  74         unsigned long  dc_lsize = cpu_dcache_line_size();
  75
  76         if (dc_lsize == 16)
  77                 r4k_blast_dcache_page = blast_dcache16_page;
  78         else if (dc_lsize == 32)
  79                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
  80 }
  81
  82 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
  83
  84 static inline void r4k_blast_dcache_page_indexed_setup(void)
  85 {
  86         unsigned long dc_lsize = cpu_dcache_line_size();
  87
  88         if (dc_lsize == 16)
  89                 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
  90         else if (dc_lsize == 32)
  91                 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
  92 }
  93
  94 static void (* r4k_blast_dcache)(void);
  95
  96 static inline void r4k_blast_dcache_setup(void)
  97 {
  98         unsigned long dc_lsize = cpu_dcache_line_size();
  99
 100         if (dc_lsize == 16)
 101                 r4k_blast_dcache = blast_dcache16;
 102         else if (dc_lsize == 32)
 103                 r4k_blast_dcache = blast_dcache32;
 104 }
 105
 106 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
 107 #define JUMP_TO_ALIGN(order) \
 108         __asm__ __volatile__( \
 109                 "b\t1f\n\t" \
 110                 ".align\t" #order "\n\t" \
 111                 "1:\n\t" \
 112                 )
 113 #define CACHE32_UNROLL32_ALIGN  JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
 114 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
 115
 116 static inline void blast_r4600_v1_icache32(void)
 117 {
 118         unsigned long flags;
 119
 120         local_irq_save(flags);
 121         blast_icache32();
 122         local_irq_restore(flags);
 123 }
 124
 125 static inline void tx49_blast_icache32(void)
 126 {
 127         unsigned long start = INDEX_BASE;
 128         unsigned long end = start + current_cpu_data.icache.waysize;
 129         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 130         unsigned long ws_end = current_cpu_data.icache.ways <<
 131                                current_cpu_data.icache.waybit;
 132         unsigned long ws, addr;
 133
 134         CACHE32_UNROLL32_ALIGN2;
 135         /* I'm in even chunk.  blast odd chunks */
 136         for (ws = 0; ws < ws_end; ws += ws_inc)
 137                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 138                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 139         CACHE32_UNROLL32_ALIGN;
 140         /* I'm in odd chunk.  blast even chunks */
 141         for (ws = 0; ws < ws_end; ws += ws_inc)
 142                 for (addr = start; addr < end; addr += 0x400 * 2)
 143                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 144 }
 145
 146 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
 147 {
 148         unsigned long flags;
 149
 150         local_irq_save(flags);
 151         blast_icache32_page_indexed(page);
 152         local_irq_restore(flags);
 153 }
 154
 155 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
 156 {
 157         unsigned long start = page;
 158         unsigned long end = start + PAGE_SIZE;
 159         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 160         unsigned long ws_end = current_cpu_data.icache.ways <<
 161                                current_cpu_data.icache.waybit;
 162         unsigned long ws, addr;
 163
 164         CACHE32_UNROLL32_ALIGN2;
 165         /* I'm in even chunk.  blast odd chunks */
 166         for (ws = 0; ws < ws_end; ws += ws_inc)
 167                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 168                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 169         CACHE32_UNROLL32_ALIGN;
 170         /* I'm in odd chunk.  blast even chunks */
 171         for (ws = 0; ws < ws_end; ws += ws_inc)
 172                 for (addr = start; addr < end; addr += 0x400 * 2)
 173                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 174 }
 175
 176 static void (* r4k_blast_icache_page)(unsigned long addr);
 177
 178 static inline void r4k_blast_icache_page_setup(void)
 179 {
 180         unsigned long ic_lsize = cpu_icache_line_size();
 181
 182         if (ic_lsize == 16)
 183                 r4k_blast_icache_page = blast_icache16_page;
 184         else if (ic_lsize == 32)
 185                 r4k_blast_icache_page = blast_icache32_page;
 186         else if (ic_lsize == 64)
 187                 r4k_blast_icache_page = blast_icache64_page;
 188 }
 189
 190
 191 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
 192
 193 static inline void r4k_blast_icache_page_indexed_setup(void)
 194 {
 195         unsigned long ic_lsize = cpu_icache_line_size();
 196
 197         if (ic_lsize == 16)
 198                 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
 199         else if (ic_lsize == 32) {
 200                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 201                         r4k_blast_icache_page_indexed =
 202                                 blast_icache32_r4600_v1_page_indexed;
 203                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 204                         r4k_blast_icache_page_indexed =
 205                                 tx49_blast_icache32_page_indexed;
 206                 else
 207                         r4k_blast_icache_page_indexed =
 208                                 blast_icache32_page_indexed;
 209         } else if (ic_lsize == 64)
 210                 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
 211 }
 212
 213 static void (* r4k_blast_icache)(void);
 214
 215 static inline void r4k_blast_icache_setup(void)
 216 {
 217         unsigned long ic_lsize = cpu_icache_line_size();
 218
 219         if (ic_lsize == 16)
 220                 r4k_blast_icache = blast_icache16;
 221         else if (ic_lsize == 32) {
 222                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 223                         r4k_blast_icache = blast_r4600_v1_icache32;
 224                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 225                         r4k_blast_icache = tx49_blast_icache32;
 226                 else
 227                         r4k_blast_icache = blast_icache32;
 228         } else if (ic_lsize == 64)
 229                 r4k_blast_icache = blast_icache64;
 230 }
 231
 232 static void (* r4k_blast_scache_page)(unsigned long addr);
 233
 234 static inline void r4k_blast_scache_page_setup(void)
 235 {
 236         unsigned long sc_lsize = cpu_scache_line_size();
 237
 238         if (scache_size == 0)
 239                 r4k_blast_scache_page = (void *)no_sc_noop;
 240         else if (sc_lsize == 16)
 241                 r4k_blast_scache_page = blast_scache16_page;
 242         else if (sc_lsize == 32)
 243                 r4k_blast_scache_page = blast_scache32_page;
 244         else if (sc_lsize == 64)
 245                 r4k_blast_scache_page = blast_scache64_page;
 246         else if (sc_lsize == 128)
 247                 r4k_blast_scache_page = blast_scache128_page;
 248 }
 249
 250 static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
 251
 252 static inline void r4k_blast_scache_page_indexed_setup(void)
 253 {
 254         unsigned long sc_lsize = cpu_scache_line_size();
 255
 256         if (scache_size == 0)
 257                 r4k_blast_scache_page_indexed = (void *)no_sc_noop;
 258         else if (sc_lsize == 16)
 259                 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
 260         else if (sc_lsize == 32)
 261                 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
 262         else if (sc_lsize == 64)
 263                 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
 264         else if (sc_lsize == 128)
 265                 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
 266 }
 267
 268 static void (* r4k_blast_scache)(void);
 269
 270 static inline void r4k_blast_scache_setup(void)
 271 {
 272         unsigned long sc_lsize = cpu_scache_line_size();
 273
 274         if (scache_size == 0)
 275                 r4k_blast_scache = (void *)no_sc_noop;
 276         else if (sc_lsize == 16)
 277                 r4k_blast_scache = blast_scache16;
 278         else if (sc_lsize == 32)
 279                 r4k_blast_scache = blast_scache32;
 280         else if (sc_lsize == 64)
 281                 r4k_blast_scache = blast_scache64;
 282         else if (sc_lsize == 128)
 283                 r4k_blast_scache = blast_scache128;
 284 }
 285
 286 /*
 287  * This is former mm's flush_cache_all() which really should be
 288  * flush_cache_vunmap these days ...
 289  */
 290 static inline void local_r4k_flush_cache_all(void * args)
 291 {
 292         r4k_blast_dcache();
 293         r4k_blast_icache();
 294 }
 295
 296 static void r4k_flush_cache_all(void)
 297 {
 298         if (!cpu_has_dc_aliases)
 299                 return;
 300
 301         on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1);
 302 }
 303
 304 static inline void local_r4k___flush_cache_all(void * args)
 305 {
 306         r4k_blast_dcache();
 307         r4k_blast_icache();
 308
 309         switch (current_cpu_data.cputype) {
 310         case CPU_R4000SC:
 311         case CPU_R4000MC:
 312         case CPU_R4400SC:
 313         case CPU_R4400MC:
 314         case CPU_R10000:
 315         case CPU_R12000:
 316                 r4k_blast_scache();
 317         }
 318 }
 319
 320 static void r4k___flush_cache_all(void)
 321 {
 322         on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1);
 323 }
 324
 325 static inline void local_r4k_flush_cache_range(void * args)
 326 {
 327         struct vm_area_struct *vma = args;
 328         int exec;
 329
 330         if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
 331                 return;
 332
 333         exec = vma->vm_flags & VM_EXEC;
 334         if (cpu_has_dc_aliases || exec)
 335                 r4k_blast_dcache();
 336         if (exec)
 337                 r4k_blast_icache();
 338 }
 339
 340 static void r4k_flush_cache_range(struct vm_area_struct *vma,
 341         unsigned long start, unsigned long end)
 342 {
 343         on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
 344 }
 345
 346 static inline void local_r4k_flush_cache_mm(void * args)
 347 {
 348         struct mm_struct *mm = args;
 349
 350         if (!cpu_context(smp_processor_id(), mm))
 351                 return;
 352
 353         r4k_blast_dcache();
 354         r4k_blast_icache();
 355
 356         /*
 357          * Kludge alert.  For obscure reasons R4000SC and R4400SC go nuts if we
 358          * only flush the primary caches but R10000 and R12000 behave sane ...
 359          */
 360         if (current_cpu_data.cputype == CPU_R4000SC ||
 361             current_cpu_data.cputype == CPU_R4000MC ||
 362             current_cpu_data.cputype == CPU_R4400SC ||
 363             current_cpu_data.cputype == CPU_R4400MC)
 364                 r4k_blast_scache();
 365 }
 366
 367 static void r4k_flush_cache_mm(struct mm_struct *mm)
 368 {
 369         if (!cpu_has_dc_aliases)
 370                 return;
 371
 372         on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1);
 373 }
 374
 375 struct flush_cache_page_args {
 376         struct vm_area_struct *vma;
 377         unsigned long addr;
 378 };
 379
 380 static inline void local_r4k_flush_cache_page(void *args)
 381 {
 382         struct flush_cache_page_args *fcp_args = args;
 383         struct vm_area_struct *vma = fcp_args->vma;
 384         unsigned long addr = fcp_args->addr;
 385         int exec = vma->vm_flags & VM_EXEC;
 386         struct mm_struct *mm = vma->vm_mm;
 387         pgd_t *pgdp;
 388         pud_t *pudp;
 389         pmd_t *pmdp;
 390         pte_t *ptep;
 391
 392         /*
 393          * If ownes no valid ASID yet, cannot possibly have gotten
 394          * this page into the cache.
 395          */
 396         if (cpu_context(smp_processor_id(), mm) == 0)
 397                 return;
 398
 399         addr &= PAGE_MASK;
 400         pgdp = pgd_offset(mm, addr);
 401         pudp = pud_offset(pgdp, addr);
 402         pmdp = pmd_offset(pudp, addr);
 403         ptep = pte_offset(pmdp, addr);
 404
 405         /*
 406          * If the page isn't marked valid, the page cannot possibly be
 407          * in the cache.
 408          */
 409         if (!(pte_val(*ptep) & _PAGE_PRESENT))
 410                 return;
 411
 412         /*
 413          * Doing flushes for another ASID than the current one is
 414          * too difficult since stupid R4k caches do a TLB translation
 415          * for every cache flush operation.  So we do indexed flushes
 416          * in that case, which doesn't overly flush the cache too much.
 417          */
 418         if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
 419                 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
 420                         r4k_blast_dcache_page(addr);
 421                         if (exec && !cpu_icache_snoops_remote_store)
 422                                 r4k_blast_scache_page(addr);
 423                 }
 424                 if (exec)
 425                         r4k_blast_icache_page(addr);
 426
 427                 return;
 428         }
 429
 430         /*
 431          * Do indexed flush, too much work to get the (possible) TLB refills
 432          * to work correctly.
 433          */
 434         addr = INDEX_BASE + (addr & (dcache_size - 1));
 435         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
 436                 r4k_blast_dcache_page_indexed(addr);
 437                 if (exec && !cpu_icache_snoops_remote_store)
 438                         r4k_blast_scache_page_indexed(addr);
 439         }
 440         if (exec) {
 441                 if (cpu_has_vtag_icache) {
 442                         int cpu = smp_processor_id();
 443
 444                         if (cpu_context(cpu, mm) != 0)
 445                                 drop_mmu_context(mm, cpu);
 446                 } else
 447                         r4k_blast_icache_page_indexed(addr);
 448         }
 449 }
 450
 451 static void r4k_flush_cache_page(struct vm_area_struct *vma,
 452         unsigned long addr, unsigned long pfn)
 453 {
 454         struct flush_cache_page_args args;
 455
 456         args.vma = vma;
 457         args.addr = addr;
 458
 459         on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1);
 460 }
 461
 462 static inline void local_r4k_flush_data_cache_page(void * addr)
 463 {
 464         r4k_blast_dcache_page((unsigned long) addr);
 465 }
 466
 467 static void r4k_flush_data_cache_page(unsigned long addr)
 468 {
 469         on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1);
 470 }
 471
 472 struct flush_icache_range_args {
 473         unsigned long start;
 474         unsigned long end;
 475 };
 476
 477 static inline void local_r4k_flush_icache_range(void *args)
 478 {
 479         struct flush_icache_range_args *fir_args = args;
 480         unsigned long start = fir_args->start;
 481         unsigned long end = fir_args->end;
 482
 483         if (!cpu_has_ic_fills_f_dc) {
 484                 if (end - start > dcache_size) {
 485                         r4k_blast_dcache();
 486                 } else {
 487                         R4600_HIT_CACHEOP_WAR_IMPL;
 488                         protected_blast_dcache_range(start, end);
 489                 }
 490
 491                 if (!cpu_icache_snoops_remote_store && scache_size) {
 492                         if (end - start > scache_size)
 493                                 r4k_blast_scache();
 494                         else
 495                                 protected_blast_scache_range(start, end);
 496                 }
 497         }
 498
 499         if (end - start > icache_size)
 500                 r4k_blast_icache();
 501         else
 502                 protected_blast_icache_range(start, end);
 503 }
 504
 505 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
 506 {
 507         struct flush_icache_range_args args;
 508
 509         args.start = start;
 510         args.end = end;
 511
 512         on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
 513         instruction_hazard();
 514 }
 515
 516 /*
 517  * Ok, this seriously sucks.  We use them to flush a user page but don't
 518  * know the virtual address, so we have to blast away the whole icache
 519  * which is significantly more expensive than the real thing.  Otoh we at
 520  * least know the kernel address of the page so we can flush it
 521  * selectivly.
 522  */
 523
 524 struct flush_icache_page_args {
 525         struct vm_area_struct *vma;
 526         struct page *page;
 527 };
 528
 529 static inline void local_r4k_flush_icache_page(void *args)
 530 {
 531         struct flush_icache_page_args *fip_args = args;
 532         struct vm_area_struct *vma = fip_args->vma;
 533         struct page *page = fip_args->page;
 534
 535         /*
 536          * Tricky ...  Because we don't know the virtual address we've got the
 537          * choice of either invalidating the entire primary and secondary
 538          * caches or invalidating the secondary caches also.  With the subset
 539          * enforcment on R4000SC, R4400SC, R10000 and R12000 invalidating the
 540          * secondary cache will result in any entries in the primary caches
 541          * also getting invalidated which hopefully is a bit more economical.
 542          */
 543         if (cpu_has_subset_pcaches) {
 544                 unsigned long addr = (unsigned long) page_address(page);
 545
 546                 r4k_blast_scache_page(addr);
 547                 ClearPageDcacheDirty(page);
 548
 549                 return;
 550         }
 551
 552         if (!cpu_has_ic_fills_f_dc) {
 553                 unsigned long addr = (unsigned long) page_address(page);
 554                 r4k_blast_dcache_page(addr);
 555                 if (!cpu_icache_snoops_remote_store)
 556                         r4k_blast_scache_page(addr);
 557                 ClearPageDcacheDirty(page);
 558         }
 559
 560         /*
 561          * We're not sure of the virtual address(es) involved here, so
 562          * we have to flush the entire I-cache.
 563          */
 564         if (cpu_has_vtag_icache) {
 565                 int cpu = smp_processor_id();
 566
 567                 if (cpu_context(cpu, vma->vm_mm) != 0)
 568                         drop_mmu_context(vma->vm_mm, cpu);
 569         } else
 570                 r4k_blast_icache();
 571 }
 572
 573 static void r4k_flush_icache_page(struct vm_area_struct *vma,
 574         struct page *page)
 575 {
 576         struct flush_icache_page_args args;
 577
 578         /*
 579          * If there's no context yet, or the page isn't executable, no I-cache
 580          * flush is needed.
 581          */
 582         if (!(vma->vm_flags & VM_EXEC))
 583                 return;
 584
 585         args.vma = vma;
 586         args.page = page;
 587
 588         on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1);
 589 }
 590
 591
 592 #ifdef CONFIG_DMA_NONCOHERENT
 593
 594 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 595 {
 596         /* Catch bad driver code */
 597         BUG_ON(size == 0);
 598
 599         if (cpu_has_subset_pcaches) {
 600                 if (size >= scache_size)
 601                         r4k_blast_scache();
 602                 else
 603                         blast_scache_range(addr, addr + size);
 604                 return;
 605         }
 606
 607         /*
 608          * Either no secondary cache or the available caches don't have the
 609          * subset property so we have to flush the primary caches
 610          * explicitly
 611          */
 612         if (size >= dcache_size) {
 613                 r4k_blast_dcache();
 614         } else {
 615                 R4600_HIT_CACHEOP_WAR_IMPL;
 616                 blast_dcache_range(addr, addr + size);
 617         }
 618
 619         bc_wback_inv(addr, size);
 620 }
 621
 622 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 623 {
 624         /* Catch bad driver code */
 625         BUG_ON(size == 0);
 626
 627         if (cpu_has_subset_pcaches) {
 628                 if (size >= scache_size)
 629                         r4k_blast_scache();
 630                 else
 631                         blast_scache_range(addr, addr + size);
 632                 return;
 633         }
 634
 635         if (size >= dcache_size) {
 636                 r4k_blast_dcache();
 637         } else {
 638                 R4600_HIT_CACHEOP_WAR_IMPL;
 639                 blast_dcache_range(addr, addr + size);
 640         }
 641
 642         bc_inv(addr, size);
 643 }
 644 #endif /* CONFIG_DMA_NONCOHERENT */
 645
 646 /*
 647  * While we're protected against bad userland addresses we don't care
 648  * very much about what happens in that case.  Usually a segmentation
 649  * fault will dump the process later on anyway ...
 650  */
 651 static void local_r4k_flush_cache_sigtramp(void * arg)
 652 {
 653         unsigned long ic_lsize = cpu_icache_line_size();
 654         unsigned long dc_lsize = cpu_dcache_line_size();
 655         unsigned long sc_lsize = cpu_scache_line_size();
 656         unsigned long addr = (unsigned long) arg;
 657
 658         R4600_HIT_CACHEOP_WAR_IMPL;
 659         protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
 660         if (!cpu_icache_snoops_remote_store && scache_size)
 661                 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
 662         protected_flush_icache_line(addr & ~(ic_lsize - 1));
 663         if (MIPS4K_ICACHE_REFILL_WAR) {
 664                 __asm__ __volatile__ (
 665                         ".set push\n\t"
 666                         ".set noat\n\t"
 667                         ".set mips3\n\t"
 668 #ifdef CONFIG_32BIT
 669                         "la     $at,1f\n\t"
 670 #endif
 671 #ifdef CONFIG_64BIT
 672                         "dla    $at,1f\n\t"
 673 #endif
 674                         "cache  %0,($at)\n\t"
 675                         "nop; nop; nop\n"
 676                         "1:\n\t"
 677                         ".set pop"
 678                         :
 679                         : "i" (Hit_Invalidate_I));
 680         }
 681         if (MIPS_CACHE_SYNC_WAR)
 682                 __asm__ __volatile__ ("sync");
 683 }
 684
 685 static void r4k_flush_cache_sigtramp(unsigned long addr)
 686 {
 687         on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1);
 688 }
 689
 690 static void r4k_flush_icache_all(void)
 691 {
 692         if (cpu_has_vtag_icache)
 693                 r4k_blast_icache();
 694 }
 695
 696 static inline void rm7k_erratum31(void)
 697 {
 698         const unsigned long ic_lsize = 32;
 699         unsigned long addr;
 700
 701         /* RM7000 erratum #31. The icache is screwed at startup. */
 702         write_c0_taglo(0);
 703         write_c0_taghi(0);
 704
 705         for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
 706                 __asm__ __volatile__ (
 707                         ".set push\n\t"
 708                         ".set noreorder\n\t"
 709                         ".set mips3\n\t"
 710                         "cache\t%1, 0(%0)\n\t"
 711                         "cache\t%1, 0x1000(%0)\n\t"
 712                         "cache\t%1, 0x2000(%0)\n\t"
 713                         "cache\t%1, 0x3000(%0)\n\t"
 714                         "cache\t%2, 0(%0)\n\t"
 715                         "cache\t%2, 0x1000(%0)\n\t"
 716                         "cache\t%2, 0x2000(%0)\n\t"
 717                         "cache\t%2, 0x3000(%0)\n\t"
 718                         "cache\t%1, 0(%0)\n\t"
 719                         "cache\t%1, 0x1000(%0)\n\t"
 720                         "cache\t%1, 0x2000(%0)\n\t"
 721                         "cache\t%1, 0x3000(%0)\n\t"
 722                         ".set pop\n"
 723                         :
 724                         : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
 725         }
 726 }
 727
 728 static char *way_string[] __initdata = { NULL, "direct mapped", "2-way",
 729         "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
 730 };
 731
 732 static void __init probe_pcache(void)
 733 {
 734         struct cpuinfo_mips *c = &current_cpu_data;
 735         unsigned int config = read_c0_config();
 736         unsigned int prid = read_c0_prid();
 737         unsigned long config1;
 738         unsigned int lsize;
 739
 740         switch (c->cputype) {
 741         case CPU_R4600:                 /* QED style two way caches? */
 742         case CPU_R4700:
 743         case CPU_R5000:
 744         case CPU_NEVADA:
 745                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 746                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 747                 c->icache.ways = 2;
 748                 c->icache.waybit = ffs(icache_size/2) - 1;
 749
 750                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 751                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 752                 c->dcache.ways = 2;
 753                 c->dcache.waybit= ffs(dcache_size/2) - 1;
 754
 755                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 756                 break;
 757
 758         case CPU_R5432:
 759         case CPU_R5500:
 760                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 761                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 762                 c->icache.ways = 2;
 763                 c->icache.waybit= 0;
 764
 765                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 766                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 767                 c->dcache.ways = 2;
 768                 c->dcache.waybit = 0;
 769
 770                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 771                 break;
 772
 773         case CPU_TX49XX:
 774                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 775                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 776                 c->icache.ways = 4;
 777                 c->icache.waybit= 0;
 778
 779                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 780                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 781                 c->dcache.ways = 4;
 782                 c->dcache.waybit = 0;
 783
 784                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 785                 break;
 786
 787         case CPU_R4000PC:
 788         case CPU_R4000SC:
 789         case CPU_R4000MC:
 790         case CPU_R4400PC:
 791         case CPU_R4400SC:
 792         case CPU_R4400MC:
 793         case CPU_R4300:
 794                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 795                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 796                 c->icache.ways = 1;
 797                 c->icache.waybit = 0;   /* doesn't matter */
 798
 799                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 800                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 801                 c->dcache.ways = 1;
 802                 c->dcache.waybit = 0;   /* does not matter */
 803
 804                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 805                 break;
 806
 807         case CPU_R10000:
 808         case CPU_R12000:
 809                 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
 810                 c->icache.linesz = 64;
 811                 c->icache.ways = 2;
 812                 c->icache.waybit = 0;
 813
 814                 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
 815                 c->dcache.linesz = 32;
 816                 c->dcache.ways = 2;
 817                 c->dcache.waybit = 0;
 818
 819                 c->options |= MIPS_CPU_PREFETCH;
 820                 break;
 821
 822         case CPU_VR4133:
 823                 write_c0_config(config & ~CONF_EB);
 824         case CPU_VR4131:
 825                 /* Workaround for cache instruction bug of VR4131 */
 826                 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
 827                     c->processor_id == 0x0c82U) {
 828                         config &= ~0x00000030U;
 829                         config |= 0x00410000U;
 830                         write_c0_config(config);
 831                 }
 832                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
 833                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 834                 c->icache.ways = 2;
 835                 c->icache.waybit = ffs(icache_size/2) - 1;
 836
 837                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
 838                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 839                 c->dcache.ways = 2;
 840                 c->dcache.waybit = ffs(dcache_size/2) - 1;
 841
 842                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 843                 break;
 844
 845         case CPU_VR41XX:
 846         case CPU_VR4111:
 847         case CPU_VR4121:
 848         case CPU_VR4122:
 849         case CPU_VR4181:
 850         case CPU_VR4181A:
 851                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
 852                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 853                 c->icache.ways = 1;
 854                 c->icache.waybit = 0;   /* doesn't matter */
 855
 856                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
 857                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 858                 c->dcache.ways = 1;
 859                 c->dcache.waybit = 0;   /* does not matter */
 860
 861                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 862                 break;
 863
 864         case CPU_RM7000:
 865                 rm7k_erratum31();
 866
 867         case CPU_RM9000:
 868                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 869                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 870                 c->icache.ways = 4;
 871                 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
 872
 873                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 874                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 875                 c->dcache.ways = 4;
 876                 c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;
 877
 878 #if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
 879                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 880 #endif
 881                 c->options |= MIPS_CPU_PREFETCH;
 882                 break;
 883
 884         default:
 885                 if (!(config & MIPS_CONF_M))
 886                         panic("Don't know how to probe P-caches on this cpu.");
 887
 888                 /*
 889                  * So we seem to be a MIPS32 or MIPS64 CPU
 890                  * So let's probe the I-cache ...
 891                  */
 892                 config1 = read_c0_config1();
 893
 894                 if ((lsize = ((config1 >> 19) & 7)))
 895                         c->icache.linesz = 2 << lsize;
 896                 else
 897                         c->icache.linesz = lsize;
 898                 c->icache.sets = 64 << ((config1 >> 22) & 7);
 899                 c->icache.ways = 1 + ((config1 >> 16) & 7);
 900
 901                 icache_size = c->icache.sets *
 902                               c->icache.ways *
 903                               c->icache.linesz;
 904                 c->icache.waybit = ffs(icache_size/c->icache.ways) - 1;
 905
 906                 if (config & 0x8)               /* VI bit */
 907                         c->icache.flags |= MIPS_CACHE_VTAG;
 908
 909                 /*
 910                  * Now probe the MIPS32 / MIPS64 data cache.
 911                  */
 912                 c->dcache.flags = 0;
 913
 914                 if ((lsize = ((config1 >> 10) & 7)))
 915                         c->dcache.linesz = 2 << lsize;
 916                 else
 917                         c->dcache.linesz= lsize;
 918                 c->dcache.sets = 64 << ((config1 >> 13) & 7);
 919                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
 920
 921                 dcache_size = c->dcache.sets *
 922                               c->dcache.ways *
 923                               c->dcache.linesz;
 924                 c->dcache.waybit = ffs(dcache_size/c->dcache.ways) - 1;
 925
 926                 c->options |= MIPS_CPU_PREFETCH;
 927                 break;
 928         }
 929
 930         /*
 931          * Processor configuration sanity check for the R4000SC erratum
 932          * #5.  With page sizes larger than 32kB there is no possibility
 933          * to get a VCE exception anymore so we don't care about this
 934          * misconfiguration.  The case is rather theoretical anyway;
 935          * presumably no vendor is shipping his hardware in the "bad"
 936          * configuration.
 937          */
 938         if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 &&
 939             !(config & CONF_SC) && c->icache.linesz != 16 &&
 940             PAGE_SIZE <= 0x8000)
 941                 panic("Improper R4000SC processor configuration detected");
 942
 943         /* compute a couple of other cache variables */
 944         c->icache.waysize = icache_size / c->icache.ways;
 945         c->dcache.waysize = dcache_size / c->dcache.ways;
 946
 947         c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);
 948         c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
 949
 950         /*
 951          * R10000 and R12000 P-caches are odd in a positive way.  They're 32kB
 952          * 2-way virtually indexed so normally would suffer from aliases.  So
 953          * normally they'd suffer from aliases but magic in the hardware deals
 954          * with that for us so we don't need to take care ourselves.
 955          */
 956         switch (c->cputype) {
 957         case CPU_20KC:
 958         case CPU_25KF:
 959         case CPU_R10000:
 960         case CPU_R12000:
 961         case CPU_SB1:
 962                 break;
 963         case CPU_24K:
 964                 if (!(read_c0_config7() & (1 << 16)))
 965         default:
 966                         if (c->dcache.waysize > PAGE_SIZE)
 967                                 c->dcache.flags |= MIPS_CACHE_ALIASES;
 968         }
 969
 970         switch (c->cputype) {
 971         case CPU_20KC:
 972                 /*
 973                  * Some older 20Kc chips doesn't have the 'VI' bit in
 974                  * the config register.
 975                  */
 976                 c->icache.flags |= MIPS_CACHE_VTAG;
 977                 break;
 978
 979         case CPU_AU1000:
 980         case CPU_AU1500:
 981         case CPU_AU1100:
 982         case CPU_AU1550:
 983         case CPU_AU1200:
 984                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
 985                 break;
 986         }
 987
 988         printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
 989                icache_size >> 10,
 990                cpu_has_vtag_icache ? "virtually tagged" : "physically tagged",
 991                way_string[c->icache.ways], c->icache.linesz);
 992
 993         printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",
 994                dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz);
 995 }
 996
 997 /*
 998  * If you even _breathe_ on this function, look at the gcc output and make sure
 999  * it does not pop things on and off the stack for the cache sizing loop that
1000  * executes in KSEG1 space or else you will crash and burn badly.  You have
1001  * been warned.
1002  */
1003 static int __init probe_scache(void)
1004 {
1005         extern unsigned long stext;
1006         unsigned long flags, addr, begin, end, pow2;
1007         unsigned int config = read_c0_config();
1008         struct cpuinfo_mips *c = &current_cpu_data;
1009         int tmp;
1010
1011         if (config & CONF_SC)
1012                 return 0;
1013
1014         begin = (unsigned long) &stext;
1015         begin &= ~((4 * 1024 * 1024) - 1);
1016         end = begin + (4 * 1024 * 1024);
1017
1018         /*
1019          * This is such a bitch, you'd think they would make it easy to do
1020          * this.  Away you daemons of stupidity!
1021          */
1022         local_irq_save(flags);
1023
1024         /* Fill each size-multiple cache line with a valid tag. */
1025         pow2 = (64 * 1024);
1026         for (addr = begin; addr < end; addr = (begin + pow2)) {
1027                 unsigned long *p = (unsigned long *) addr;
1028                 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1029                 pow2 <<= 1;
1030         }
1031
1032         /* Load first line with zero (therefore invalid) tag. */
1033         write_c0_taglo(0);
1034         write_c0_taghi(0);
1035         __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1036         cache_op(Index_Store_Tag_I, begin);
1037         cache_op(Index_Store_Tag_D, begin);
1038         cache_op(Index_Store_Tag_SD, begin);
1039
1040         /* Now search for the wrap around point. */
1041         pow2 = (128 * 1024);
1042         tmp = 0;
1043         for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1044                 cache_op(Index_Load_Tag_SD, addr);
1045                 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1046                 if (!read_c0_taglo())
1047                         break;
1048                 pow2 <<= 1;
1049         }
1050         local_irq_restore(flags);
1051         addr -= begin;
1052
1053         scache_size = addr;
1054         c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1055         c->scache.ways = 1;
1056         c->dcache.waybit = 0;           /* does not matter */
1057
1058         return 1;
1059 }
1060
1061 extern int r5k_sc_init(void);
1062 extern int rm7k_sc_init(void);
1063
1064 static void __init setup_scache(void)
1065 {
1066         struct cpuinfo_mips *c = &current_cpu_data;
1067         unsigned int config = read_c0_config();
1068         int sc_present = 0;
1069
1070         /*
1071          * Do the probing thing on R4000SC and R4400SC processors.  Other
1072          * processors don't have a S-cache that would be relevant to the
1073          * Linux memory managment.
1074          */
1075         switch (c->cputype) {
1076         case CPU_R4000SC:
1077         case CPU_R4000MC:
1078         case CPU_R4400SC:
1079         case CPU_R4400MC:
1080                 sc_present = run_uncached(probe_scache);
1081                 if (sc_present)
1082                         c->options |= MIPS_CPU_CACHE_CDEX_S;
1083                 break;
1084
1085         case CPU_R10000:
1086         case CPU_R12000:
1087                 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1088                 c->scache.linesz = 64 << ((config >> 13) & 1);
1089                 c->scache.ways = 2;
1090                 c->scache.waybit= 0;
1091                 sc_present = 1;
1092                 break;
1093
1094         case CPU_R5000:
1095         case CPU_NEVADA:
1096 #ifdef CONFIG_R5000_CPU_SCACHE
1097                 r5k_sc_init();
1098 #endif
1099                 return;
1100
1101         case CPU_RM7000:
1102         case CPU_RM9000:
1103 #ifdef CONFIG_RM7000_CPU_SCACHE
1104                 rm7k_sc_init();
1105 #endif
1106                 return;
1107
1108         default:
1109                 sc_present = 0;
1110         }
1111
1112         if (!sc_present)
1113                 return;
1114
1115         if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
1116              c->isa_level == MIPS_CPU_ISA_M64R1) &&
1117             !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1118                 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1119
1120         /* compute a couple of other cache variables */
1121         c->scache.waysize = scache_size / c->scache.ways;
1122
1123         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1124
1125         printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1126                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1127
1128         c->options |= MIPS_CPU_SUBSET_CACHES;
1129 }
1130
1131 static inline void coherency_setup(void)
1132 {
1133         change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
1134
1135         /*
1136          * c0_status.cu=0 specifies that updates by the sc instruction use
1137          * the coherency mode specified by the TLB; 1 means cachable
1138          * coherent update on write will be used.  Not all processors have
1139          * this bit and; some wire it to zero, others like Toshiba had the
1140          * silly idea of putting something else there ...
1141          */
1142         switch (current_cpu_data.cputype) {
1143         case CPU_R4000PC:
1144         case CPU_R4000SC:
1145         case CPU_R4000MC:
1146         case CPU_R4400PC:
1147         case CPU_R4400SC:
1148         case CPU_R4400MC:
1149                 clear_c0_config(CONF_CU);
1150                 break;
1151         }
1152 }
1153
1154 void __init r4k_cache_init(void)
1155 {
1156         extern void build_clear_page(void);
1157         extern void build_copy_page(void);
1158         extern char except_vec2_generic;
1159         struct cpuinfo_mips *c = &current_cpu_data;
1160
1161         /* Default cache error handler for R4000 and R5000 family */
1162         set_uncached_handler (0x100, &except_vec2_generic, 0x80);
1163
1164         probe_pcache();
1165         setup_scache();
1166
1167         r4k_blast_dcache_page_setup();
1168         r4k_blast_dcache_page_indexed_setup();
1169         r4k_blast_dcache_setup();
1170         r4k_blast_icache_page_setup();
1171         r4k_blast_icache_page_indexed_setup();
1172         r4k_blast_icache_setup();
1173         r4k_blast_scache_page_setup();
1174         r4k_blast_scache_page_indexed_setup();
1175         r4k_blast_scache_setup();
1176
1177         /*
1178          * Some MIPS32 and MIPS64 processors have physically indexed caches.
1179          * This code supports virtually indexed processors and will be
1180          * unnecessarily inefficient on physically indexed processors.
1181          */
1182         shm_align_mask = max_t( unsigned long,
1183                                 c->dcache.sets * c->dcache.linesz - 1,
1184                                 PAGE_SIZE - 1);
1185
1186         flush_cache_all         = r4k_flush_cache_all;
1187         __flush_cache_all       = r4k___flush_cache_all;
1188         flush_cache_mm          = r4k_flush_cache_mm;
1189         flush_cache_page        = r4k_flush_cache_page;
1190         flush_icache_page       = r4k_flush_icache_page;
1191         flush_cache_range       = r4k_flush_cache_range;
1192
1193         flush_cache_sigtramp    = r4k_flush_cache_sigtramp;
1194         flush_icache_all        = r4k_flush_icache_all;
1195         flush_data_cache_page   = r4k_flush_data_cache_page;
1196         flush_icache_range      = r4k_flush_icache_range;
1197
1198 #ifdef CONFIG_DMA_NONCOHERENT
1199         _dma_cache_wback_inv    = r4k_dma_cache_wback_inv;
1200         _dma_cache_wback        = r4k_dma_cache_wback_inv;
1201         _dma_cache_inv          = r4k_dma_cache_inv;
1202 #endif
1203
1204         build_clear_page();
1205         build_copy_page();
1206         local_r4k___flush_cache_all(NULL);
1207         coherency_setup();
1208 }