2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/sysdev.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
21 #include <asm/hardware.h>
23 #include <asm/arch/irqs.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/mach/irq.h>
30 * OMAP1510 GPIO registers
32 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
33 #define OMAP1510_GPIO_DATA_INPUT 0x00
34 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
35 #define OMAP1510_GPIO_DIR_CONTROL 0x08
36 #define OMAP1510_GPIO_INT_CONTROL 0x0c
37 #define OMAP1510_GPIO_INT_MASK 0x10
38 #define OMAP1510_GPIO_INT_STATUS 0x14
39 #define OMAP1510_GPIO_PIN_CONTROL 0x18
41 #define OMAP1510_IH_GPIO_BASE 64
44 * OMAP1610 specific GPIO registers
46 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
47 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
48 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
49 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
50 #define OMAP1610_GPIO_REVISION 0x0000
51 #define OMAP1610_GPIO_SYSCONFIG 0x0010
52 #define OMAP1610_GPIO_SYSSTATUS 0x0014
53 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
54 #define OMAP1610_GPIO_IRQENABLE1 0x001c
55 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
56 #define OMAP1610_GPIO_DATAIN 0x002c
57 #define OMAP1610_GPIO_DATAOUT 0x0030
58 #define OMAP1610_GPIO_DIRECTION 0x0034
59 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
60 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
61 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
62 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
63 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
64 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
65 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
66 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
69 * OMAP730 specific GPIO registers
71 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
72 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
73 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
74 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
75 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
76 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
77 #define OMAP730_GPIO_DATA_INPUT 0x00
78 #define OMAP730_GPIO_DATA_OUTPUT 0x04
79 #define OMAP730_GPIO_DIR_CONTROL 0x08
80 #define OMAP730_GPIO_INT_CONTROL 0x0c
81 #define OMAP730_GPIO_INT_MASK 0x10
82 #define OMAP730_GPIO_INT_STATUS 0x14
85 * omap24xx specific GPIO registers
87 #define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000
88 #define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000
89 #define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000
90 #define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000
92 #define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000
93 #define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000
94 #define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000
95 #define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000
96 #define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000
98 #define OMAP24XX_GPIO_REVISION 0x0000
99 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
100 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
101 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
102 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
103 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
104 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
105 #define OMAP24XX_GPIO_CTRL 0x0030
106 #define OMAP24XX_GPIO_OE 0x0034
107 #define OMAP24XX_GPIO_DATAIN 0x0038
108 #define OMAP24XX_GPIO_DATAOUT 0x003c
109 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
110 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
111 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
112 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
113 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
114 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
115 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
116 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
117 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
118 #define OMAP24XX_GPIO_SETWKUENA 0x0084
119 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
120 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
123 * omap34xx specific GPIO registers
126 #define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000
127 #define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000
128 #define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000
129 #define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000
130 #define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000
131 #define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000
137 u16 virtual_irq_start;
140 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
144 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
145 u32 non_wakeup_gpios;
146 u32 enabled_non_wakeup_gpios;
149 u32 saved_fallingdetect;
150 u32 saved_risingdetect;
155 #define METHOD_MPUIO 0
156 #define METHOD_GPIO_1510 1
157 #define METHOD_GPIO_1610 2
158 #define METHOD_GPIO_730 3
159 #define METHOD_GPIO_24XX 4
161 #ifdef CONFIG_ARCH_OMAP16XX
162 static struct gpio_bank gpio_bank_1610[5] = {
163 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
164 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
165 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
166 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
167 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
171 #ifdef CONFIG_ARCH_OMAP15XX
172 static struct gpio_bank gpio_bank_1510[2] = {
173 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
174 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
178 #ifdef CONFIG_ARCH_OMAP730
179 static struct gpio_bank gpio_bank_730[7] = {
180 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
181 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
182 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
183 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
184 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
185 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
186 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
190 #ifdef CONFIG_ARCH_OMAP24XX
192 static struct gpio_bank gpio_bank_242x[4] = {
193 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
194 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
195 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
196 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
199 static struct gpio_bank gpio_bank_243x[5] = {
200 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
201 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
202 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
203 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
204 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
209 #ifdef CONFIG_ARCH_OMAP34XX
210 static struct gpio_bank gpio_bank_34xx[6] = {
211 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
212 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
213 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
214 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
221 static struct gpio_bank *gpio_bank;
222 static int gpio_bank_count;
224 static inline struct gpio_bank *get_gpio_bank(int gpio)
226 if (cpu_is_omap15xx()) {
227 if (OMAP_GPIO_IS_MPUIO(gpio))
228 return &gpio_bank[0];
229 return &gpio_bank[1];
231 if (cpu_is_omap16xx()) {
232 if (OMAP_GPIO_IS_MPUIO(gpio))
233 return &gpio_bank[0];
234 return &gpio_bank[1 + (gpio >> 4)];
236 if (cpu_is_omap730()) {
237 if (OMAP_GPIO_IS_MPUIO(gpio))
238 return &gpio_bank[0];
239 return &gpio_bank[1 + (gpio >> 5)];
241 if (cpu_is_omap24xx())
242 return &gpio_bank[gpio >> 5];
243 if (cpu_is_omap34xx())
244 return &gpio_bank[gpio >> 5];
247 static inline int get_gpio_index(int gpio)
249 if (cpu_is_omap730())
251 if (cpu_is_omap24xx())
253 if (cpu_is_omap34xx())
258 static inline int gpio_valid(int gpio)
262 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
263 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
267 if (cpu_is_omap15xx() && gpio < 16)
269 if ((cpu_is_omap16xx()) && gpio < 64)
271 if (cpu_is_omap730() && gpio < 192)
273 if (cpu_is_omap24xx() && gpio < 128)
275 if (cpu_is_omap34xx() && gpio < 160)
280 static int check_gpio(int gpio)
282 if (unlikely(gpio_valid(gpio)) < 0) {
283 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
290 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
292 void __iomem *reg = bank->base;
295 switch (bank->method) {
296 #ifdef CONFIG_ARCH_OMAP1
298 reg += OMAP_MPUIO_IO_CNTL;
301 #ifdef CONFIG_ARCH_OMAP15XX
302 case METHOD_GPIO_1510:
303 reg += OMAP1510_GPIO_DIR_CONTROL;
306 #ifdef CONFIG_ARCH_OMAP16XX
307 case METHOD_GPIO_1610:
308 reg += OMAP1610_GPIO_DIRECTION;
311 #ifdef CONFIG_ARCH_OMAP730
312 case METHOD_GPIO_730:
313 reg += OMAP730_GPIO_DIR_CONTROL;
316 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
317 case METHOD_GPIO_24XX:
318 reg += OMAP24XX_GPIO_OE;
325 l = __raw_readl(reg);
330 __raw_writel(l, reg);
333 void omap_set_gpio_direction(int gpio, int is_input)
335 struct gpio_bank *bank;
337 if (check_gpio(gpio) < 0)
339 bank = get_gpio_bank(gpio);
340 spin_lock(&bank->lock);
341 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
342 spin_unlock(&bank->lock);
345 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
347 void __iomem *reg = bank->base;
350 switch (bank->method) {
351 #ifdef CONFIG_ARCH_OMAP1
353 reg += OMAP_MPUIO_OUTPUT;
354 l = __raw_readl(reg);
361 #ifdef CONFIG_ARCH_OMAP15XX
362 case METHOD_GPIO_1510:
363 reg += OMAP1510_GPIO_DATA_OUTPUT;
364 l = __raw_readl(reg);
371 #ifdef CONFIG_ARCH_OMAP16XX
372 case METHOD_GPIO_1610:
374 reg += OMAP1610_GPIO_SET_DATAOUT;
376 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
380 #ifdef CONFIG_ARCH_OMAP730
381 case METHOD_GPIO_730:
382 reg += OMAP730_GPIO_DATA_OUTPUT;
383 l = __raw_readl(reg);
390 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
391 case METHOD_GPIO_24XX:
393 reg += OMAP24XX_GPIO_SETDATAOUT;
395 reg += OMAP24XX_GPIO_CLEARDATAOUT;
403 __raw_writel(l, reg);
406 void omap_set_gpio_dataout(int gpio, int enable)
408 struct gpio_bank *bank;
410 if (check_gpio(gpio) < 0)
412 bank = get_gpio_bank(gpio);
413 spin_lock(&bank->lock);
414 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
415 spin_unlock(&bank->lock);
418 int omap_get_gpio_datain(int gpio)
420 struct gpio_bank *bank;
423 if (check_gpio(gpio) < 0)
425 bank = get_gpio_bank(gpio);
427 switch (bank->method) {
428 #ifdef CONFIG_ARCH_OMAP1
430 reg += OMAP_MPUIO_INPUT_LATCH;
433 #ifdef CONFIG_ARCH_OMAP15XX
434 case METHOD_GPIO_1510:
435 reg += OMAP1510_GPIO_DATA_INPUT;
438 #ifdef CONFIG_ARCH_OMAP16XX
439 case METHOD_GPIO_1610:
440 reg += OMAP1610_GPIO_DATAIN;
443 #ifdef CONFIG_ARCH_OMAP730
444 case METHOD_GPIO_730:
445 reg += OMAP730_GPIO_DATA_INPUT;
448 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
449 case METHOD_GPIO_24XX:
450 reg += OMAP24XX_GPIO_DATAIN;
456 return (__raw_readl(reg)
457 & (1 << get_gpio_index(gpio))) != 0;
460 #define MOD_REG_BIT(reg, bit_mask, set) \
462 int l = __raw_readl(base + reg); \
463 if (set) l |= bit_mask; \
464 else l &= ~bit_mask; \
465 __raw_writel(l, base + reg); \
468 void omap_set_gpio_debounce(int gpio, int enable)
470 struct gpio_bank *bank;
472 u32 val, l = 1 << get_gpio_index(gpio);
474 if (cpu_class_is_omap1())
477 bank = get_gpio_bank(gpio);
480 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
481 val = __raw_readl(reg);
488 __raw_writel(val, reg);
490 EXPORT_SYMBOL(omap_set_gpio_debounce);
492 void omap_set_gpio_debounce_time(int gpio, int enc_time)
494 struct gpio_bank *bank;
497 if (cpu_class_is_omap1())
500 bank = get_gpio_bank(gpio);
504 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
505 __raw_writel(enc_time, reg);
507 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
509 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
510 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
513 void __iomem *base = bank->base;
514 u32 gpio_bit = 1 << gpio;
516 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
517 trigger & __IRQT_LOWLVL);
518 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
519 trigger & __IRQT_HIGHLVL);
520 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
521 trigger & __IRQT_RISEDGE);
522 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
523 trigger & __IRQT_FALEDGE);
525 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
527 __raw_writel(1 << gpio, bank->base
528 + OMAP24XX_GPIO_SETWKUENA);
530 __raw_writel(1 << gpio, bank->base
531 + OMAP24XX_GPIO_CLEARWKUENA);
534 bank->enabled_non_wakeup_gpios |= gpio_bit;
536 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
540 * FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only
541 * level triggering requested.
546 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
548 void __iomem *reg = bank->base;
551 switch (bank->method) {
552 #ifdef CONFIG_ARCH_OMAP1
554 reg += OMAP_MPUIO_GPIO_INT_EDGE;
555 l = __raw_readl(reg);
556 if (trigger & __IRQT_RISEDGE)
558 else if (trigger & __IRQT_FALEDGE)
564 #ifdef CONFIG_ARCH_OMAP15XX
565 case METHOD_GPIO_1510:
566 reg += OMAP1510_GPIO_INT_CONTROL;
567 l = __raw_readl(reg);
568 if (trigger & __IRQT_RISEDGE)
570 else if (trigger & __IRQT_FALEDGE)
576 #ifdef CONFIG_ARCH_OMAP16XX
577 case METHOD_GPIO_1610:
579 reg += OMAP1610_GPIO_EDGE_CTRL2;
581 reg += OMAP1610_GPIO_EDGE_CTRL1;
583 l = __raw_readl(reg);
584 l &= ~(3 << (gpio << 1));
585 if (trigger & __IRQT_RISEDGE)
586 l |= 2 << (gpio << 1);
587 if (trigger & __IRQT_FALEDGE)
588 l |= 1 << (gpio << 1);
590 /* Enable wake-up during idle for dynamic tick */
591 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
593 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
596 #ifdef CONFIG_ARCH_OMAP730
597 case METHOD_GPIO_730:
598 reg += OMAP730_GPIO_INT_CONTROL;
599 l = __raw_readl(reg);
600 if (trigger & __IRQT_RISEDGE)
602 else if (trigger & __IRQT_FALEDGE)
608 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
609 case METHOD_GPIO_24XX:
610 set_24xx_gpio_triggering(bank, gpio, trigger);
616 __raw_writel(l, reg);
622 static int gpio_irq_type(unsigned irq, unsigned type)
624 struct gpio_bank *bank;
628 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
629 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
631 gpio = irq - IH_GPIO_BASE;
633 if (check_gpio(gpio) < 0)
636 if (type & ~IRQ_TYPE_SENSE_MASK)
639 /* OMAP1 allows only only edge triggering */
640 if (!cpu_class_is_omap2()
641 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
644 bank = get_irq_chip_data(irq);
645 spin_lock(&bank->lock);
646 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
648 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
649 irq_desc[irq].status |= type;
651 spin_unlock(&bank->lock);
655 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
657 void __iomem *reg = bank->base;
659 switch (bank->method) {
660 #ifdef CONFIG_ARCH_OMAP1
662 /* MPUIO irqstatus is reset by reading the status register,
663 * so do nothing here */
666 #ifdef CONFIG_ARCH_OMAP15XX
667 case METHOD_GPIO_1510:
668 reg += OMAP1510_GPIO_INT_STATUS;
671 #ifdef CONFIG_ARCH_OMAP16XX
672 case METHOD_GPIO_1610:
673 reg += OMAP1610_GPIO_IRQSTATUS1;
676 #ifdef CONFIG_ARCH_OMAP730
677 case METHOD_GPIO_730:
678 reg += OMAP730_GPIO_INT_STATUS;
681 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
682 case METHOD_GPIO_24XX:
683 reg += OMAP24XX_GPIO_IRQSTATUS1;
690 __raw_writel(gpio_mask, reg);
692 /* Workaround for clearing DSP GPIO interrupts to allow retention */
693 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
694 if (cpu_is_omap24xx() || cpu_is_omap34xx())
695 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
699 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
701 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
704 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
706 void __iomem *reg = bank->base;
711 switch (bank->method) {
712 #ifdef CONFIG_ARCH_OMAP1
714 reg += OMAP_MPUIO_GPIO_MASKIT;
719 #ifdef CONFIG_ARCH_OMAP15XX
720 case METHOD_GPIO_1510:
721 reg += OMAP1510_GPIO_INT_MASK;
726 #ifdef CONFIG_ARCH_OMAP16XX
727 case METHOD_GPIO_1610:
728 reg += OMAP1610_GPIO_IRQENABLE1;
732 #ifdef CONFIG_ARCH_OMAP730
733 case METHOD_GPIO_730:
734 reg += OMAP730_GPIO_INT_MASK;
739 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
740 case METHOD_GPIO_24XX:
741 reg += OMAP24XX_GPIO_IRQENABLE1;
750 l = __raw_readl(reg);
757 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
759 void __iomem *reg = bank->base;
762 switch (bank->method) {
763 #ifdef CONFIG_ARCH_OMAP1
765 reg += OMAP_MPUIO_GPIO_MASKIT;
766 l = __raw_readl(reg);
773 #ifdef CONFIG_ARCH_OMAP15XX
774 case METHOD_GPIO_1510:
775 reg += OMAP1510_GPIO_INT_MASK;
776 l = __raw_readl(reg);
783 #ifdef CONFIG_ARCH_OMAP16XX
784 case METHOD_GPIO_1610:
786 reg += OMAP1610_GPIO_SET_IRQENABLE1;
788 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
792 #ifdef CONFIG_ARCH_OMAP730
793 case METHOD_GPIO_730:
794 reg += OMAP730_GPIO_INT_MASK;
795 l = __raw_readl(reg);
802 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
803 case METHOD_GPIO_24XX:
805 reg += OMAP24XX_GPIO_SETIRQENABLE1;
807 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
815 __raw_writel(l, reg);
818 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
820 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
824 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
825 * 1510 does not seem to have a wake-up register. If JTAG is connected
826 * to the target, system will wake up always on GPIO events. While
827 * system is running all registered GPIO interrupts need to have wake-up
828 * enabled. When system is suspended, only selected GPIO interrupts need
829 * to have wake-up enabled.
831 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
833 switch (bank->method) {
834 #ifdef CONFIG_ARCH_OMAP16XX
836 case METHOD_GPIO_1610:
837 spin_lock(&bank->lock);
839 bank->suspend_wakeup |= (1 << gpio);
840 enable_irq_wake(bank->irq);
842 disable_irq_wake(bank->irq);
843 bank->suspend_wakeup &= ~(1 << gpio);
845 spin_unlock(&bank->lock);
848 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
849 case METHOD_GPIO_24XX:
850 if (bank->non_wakeup_gpios & (1 << gpio)) {
851 printk(KERN_ERR "Unable to modify wakeup on "
852 "non-wakeup GPIO%d\n",
853 (bank - gpio_bank) * 32 + gpio);
856 spin_lock(&bank->lock);
858 bank->suspend_wakeup |= (1 << gpio);
859 enable_irq_wake(bank->irq);
861 disable_irq_wake(bank->irq);
862 bank->suspend_wakeup &= ~(1 << gpio);
864 spin_unlock(&bank->lock);
868 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
874 static void _reset_gpio(struct gpio_bank *bank, int gpio)
876 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
877 _set_gpio_irqenable(bank, gpio, 0);
878 _clear_gpio_irqstatus(bank, gpio);
879 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
882 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
883 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
885 unsigned int gpio = irq - IH_GPIO_BASE;
886 struct gpio_bank *bank;
889 if (check_gpio(gpio) < 0)
891 bank = get_irq_chip_data(irq);
892 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
897 int omap_request_gpio(int gpio)
899 struct gpio_bank *bank;
901 if (check_gpio(gpio) < 0)
904 bank = get_gpio_bank(gpio);
905 spin_lock(&bank->lock);
906 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
907 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
909 spin_unlock(&bank->lock);
912 bank->reserved_map |= (1 << get_gpio_index(gpio));
914 /* Set trigger to none. You need to enable the desired trigger with
915 * request_irq() or set_irq_type().
917 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
919 #ifdef CONFIG_ARCH_OMAP15XX
920 if (bank->method == METHOD_GPIO_1510) {
923 /* Claim the pin for MPU */
924 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
925 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
928 spin_unlock(&bank->lock);
933 void omap_free_gpio(int gpio)
935 struct gpio_bank *bank;
937 if (check_gpio(gpio) < 0)
939 bank = get_gpio_bank(gpio);
940 spin_lock(&bank->lock);
941 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
942 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
944 spin_unlock(&bank->lock);
947 #ifdef CONFIG_ARCH_OMAP16XX
948 if (bank->method == METHOD_GPIO_1610) {
949 /* Disable wake-up during idle for dynamic tick */
950 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
951 __raw_writel(1 << get_gpio_index(gpio), reg);
954 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
955 if (bank->method == METHOD_GPIO_24XX) {
956 /* Disable wake-up during idle for dynamic tick */
957 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
958 __raw_writel(1 << get_gpio_index(gpio), reg);
961 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
962 _reset_gpio(bank, gpio);
963 spin_unlock(&bank->lock);
967 * We need to unmask the GPIO bank interrupt as soon as possible to
968 * avoid missing GPIO interrupts for other lines in the bank.
969 * Then we need to mask-read-clear-unmask the triggered GPIO lines
970 * in the bank to avoid missing nested interrupts for a GPIO line.
971 * If we wait to unmask individual GPIO lines in the bank after the
972 * line's interrupt handler has been run, we may miss some nested
975 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
977 void __iomem *isr_reg = NULL;
979 unsigned int gpio_irq;
980 struct gpio_bank *bank;
984 desc->chip->ack(irq);
986 bank = get_irq_data(irq);
987 #ifdef CONFIG_ARCH_OMAP1
988 if (bank->method == METHOD_MPUIO)
989 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
991 #ifdef CONFIG_ARCH_OMAP15XX
992 if (bank->method == METHOD_GPIO_1510)
993 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
995 #if defined(CONFIG_ARCH_OMAP16XX)
996 if (bank->method == METHOD_GPIO_1610)
997 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
999 #ifdef CONFIG_ARCH_OMAP730
1000 if (bank->method == METHOD_GPIO_730)
1001 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1003 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1004 if (bank->method == METHOD_GPIO_24XX)
1005 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1008 u32 isr_saved, level_mask = 0;
1011 enabled = _get_gpio_irqbank_mask(bank);
1012 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1014 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1017 if (cpu_class_is_omap2()) {
1019 __raw_readl(bank->base +
1020 OMAP24XX_GPIO_LEVELDETECT0) |
1021 __raw_readl(bank->base +
1022 OMAP24XX_GPIO_LEVELDETECT1);
1023 level_mask &= enabled;
1026 /* clear edge sensitive interrupts before handler(s) are
1027 called so that we don't miss any interrupt occurred while
1029 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1030 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1031 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1033 /* if there is only edge sensitive GPIO pin interrupts
1034 configured, we could unmask GPIO bank interrupt immediately */
1035 if (!level_mask && !unmasked) {
1037 desc->chip->unmask(irq);
1045 gpio_irq = bank->virtual_irq_start;
1046 for (; isr != 0; isr >>= 1, gpio_irq++) {
1051 d = irq_desc + gpio_irq;
1052 /* Don't run the handler if it's already running
1053 * or was disabled lazely.
1055 if (unlikely((d->depth ||
1056 (d->status & IRQ_INPROGRESS)))) {
1058 (gpio_irq - bank->virtual_irq_start);
1059 /* The unmasking will be done by
1060 * enable_irq in case it is disabled or
1061 * after returning from the handler if
1062 * it's already running.
1064 _enable_gpio_irqbank(bank, irq_mask, 0);
1066 /* Level triggered interrupts
1067 * won't ever be reentered
1069 BUG_ON(level_mask & irq_mask);
1070 d->status |= IRQ_PENDING;
1075 desc_handle_irq(gpio_irq, d);
1077 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
1079 (gpio_irq - bank->virtual_irq_start);
1080 d->status &= ~IRQ_PENDING;
1081 _enable_gpio_irqbank(bank, irq_mask, 1);
1082 retrigger |= irq_mask;
1086 if (cpu_class_is_omap2()) {
1087 /* clear level sensitive interrupts after handler(s) */
1088 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
1089 _clear_gpio_irqbank(bank, isr_saved & level_mask);
1090 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
1094 /* if bank has any level sensitive GPIO pin interrupt
1095 configured, we must unmask the bank interrupt only after
1096 handler(s) are executed in order to avoid spurious bank
1099 desc->chip->unmask(irq);
1103 static void gpio_irq_shutdown(unsigned int irq)
1105 unsigned int gpio = irq - IH_GPIO_BASE;
1106 struct gpio_bank *bank = get_irq_chip_data(irq);
1108 _reset_gpio(bank, gpio);
1111 static void gpio_ack_irq(unsigned int irq)
1113 unsigned int gpio = irq - IH_GPIO_BASE;
1114 struct gpio_bank *bank = get_irq_chip_data(irq);
1116 _clear_gpio_irqstatus(bank, gpio);
1119 static void gpio_mask_irq(unsigned int irq)
1121 unsigned int gpio = irq - IH_GPIO_BASE;
1122 struct gpio_bank *bank = get_irq_chip_data(irq);
1124 _set_gpio_irqenable(bank, gpio, 0);
1127 static void gpio_unmask_irq(unsigned int irq)
1129 unsigned int gpio = irq - IH_GPIO_BASE;
1130 struct gpio_bank *bank = get_irq_chip_data(irq);
1132 _set_gpio_irqenable(bank, gpio, 1);
1135 static struct irq_chip gpio_irq_chip = {
1137 .shutdown = gpio_irq_shutdown,
1138 .ack = gpio_ack_irq,
1139 .mask = gpio_mask_irq,
1140 .unmask = gpio_unmask_irq,
1141 .set_type = gpio_irq_type,
1142 .set_wake = gpio_wake_enable,
1145 /*---------------------------------------------------------------------*/
1147 #ifdef CONFIG_ARCH_OMAP1
1149 /* MPUIO uses the always-on 32k clock */
1151 static void mpuio_ack_irq(unsigned int irq)
1153 /* The ISR is reset automatically, so do nothing here. */
1156 static void mpuio_mask_irq(unsigned int irq)
1158 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1159 struct gpio_bank *bank = get_irq_chip_data(irq);
1161 _set_gpio_irqenable(bank, gpio, 0);
1164 static void mpuio_unmask_irq(unsigned int irq)
1166 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1167 struct gpio_bank *bank = get_irq_chip_data(irq);
1169 _set_gpio_irqenable(bank, gpio, 1);
1172 static struct irq_chip mpuio_irq_chip = {
1174 .ack = mpuio_ack_irq,
1175 .mask = mpuio_mask_irq,
1176 .unmask = mpuio_unmask_irq,
1177 .set_type = gpio_irq_type,
1178 #ifdef CONFIG_ARCH_OMAP16XX
1179 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1180 .set_wake = gpio_wake_enable,
1185 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1188 #ifdef CONFIG_ARCH_OMAP16XX
1190 #include <linux/platform_device.h>
1192 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1194 struct gpio_bank *bank = platform_get_drvdata(pdev);
1195 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1197 spin_lock(&bank->lock);
1198 bank->saved_wakeup = __raw_readl(mask_reg);
1199 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1200 spin_unlock(&bank->lock);
1205 static int omap_mpuio_resume_early(struct platform_device *pdev)
1207 struct gpio_bank *bank = platform_get_drvdata(pdev);
1208 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1210 spin_lock(&bank->lock);
1211 __raw_writel(bank->saved_wakeup, mask_reg);
1212 spin_unlock(&bank->lock);
1217 /* use platform_driver for this, now that there's no longer any
1218 * point to sys_device (other than not disturbing old code).
1220 static struct platform_driver omap_mpuio_driver = {
1221 .suspend_late = omap_mpuio_suspend_late,
1222 .resume_early = omap_mpuio_resume_early,
1228 static struct platform_device omap_mpuio_device = {
1232 .driver = &omap_mpuio_driver.driver,
1234 /* could list the /proc/iomem resources */
1237 static inline void mpuio_init(void)
1239 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1241 if (platform_driver_register(&omap_mpuio_driver) == 0)
1242 (void) platform_device_register(&omap_mpuio_device);
1246 static inline void mpuio_init(void) {}
1251 extern struct irq_chip mpuio_irq_chip;
1253 #define bank_is_mpuio(bank) 0
1254 static inline void mpuio_init(void) {}
1258 /*---------------------------------------------------------------------*/
1260 static int initialized;
1261 #if !defined(CONFIG_ARCH_OMAP3)
1262 static struct clk * gpio_ick;
1265 #if defined(CONFIG_ARCH_OMAP2)
1266 static struct clk * gpio_fck;
1269 #if defined(CONFIG_ARCH_OMAP2430)
1270 static struct clk * gpio5_ick;
1271 static struct clk * gpio5_fck;
1274 #if defined(CONFIG_ARCH_OMAP3)
1275 static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
1276 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1279 static int __init _omap_gpio_init(void)
1282 struct gpio_bank *bank;
1283 #if defined(CONFIG_ARCH_OMAP3)
1289 #if defined(CONFIG_ARCH_OMAP1)
1290 if (cpu_is_omap15xx()) {
1291 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1292 if (IS_ERR(gpio_ick))
1293 printk("Could not get arm_gpio_ck\n");
1295 clk_enable(gpio_ick);
1298 #if defined(CONFIG_ARCH_OMAP2)
1299 if (cpu_class_is_omap2()) {
1300 gpio_ick = clk_get(NULL, "gpios_ick");
1301 if (IS_ERR(gpio_ick))
1302 printk("Could not get gpios_ick\n");
1304 clk_enable(gpio_ick);
1305 gpio_fck = clk_get(NULL, "gpios_fck");
1306 if (IS_ERR(gpio_fck))
1307 printk("Could not get gpios_fck\n");
1309 clk_enable(gpio_fck);
1312 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1314 #if defined(CONFIG_ARCH_OMAP2430)
1315 if (cpu_is_omap2430()) {
1316 gpio5_ick = clk_get(NULL, "gpio5_ick");
1317 if (IS_ERR(gpio5_ick))
1318 printk("Could not get gpio5_ick\n");
1320 clk_enable(gpio5_ick);
1321 gpio5_fck = clk_get(NULL, "gpio5_fck");
1322 if (IS_ERR(gpio5_fck))
1323 printk("Could not get gpio5_fck\n");
1325 clk_enable(gpio5_fck);
1331 #if defined(CONFIG_ARCH_OMAP3)
1332 if (cpu_is_omap34xx()) {
1333 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1334 sprintf(clk_name, "gpio%d_ick", i + 1);
1335 gpio_iclks[i] = clk_get(NULL, clk_name);
1336 if (IS_ERR(gpio_iclks[i]))
1337 printk(KERN_ERR "Could not get %s\n", clk_name);
1339 clk_enable(gpio_iclks[i]);
1340 sprintf(clk_name, "gpio%d_fck", i + 1);
1341 gpio_fclks[i] = clk_get(NULL, clk_name);
1342 if (IS_ERR(gpio_fclks[i]))
1343 printk(KERN_ERR "Could not get %s\n", clk_name);
1345 clk_enable(gpio_fclks[i]);
1351 #ifdef CONFIG_ARCH_OMAP15XX
1352 if (cpu_is_omap15xx()) {
1353 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1354 gpio_bank_count = 2;
1355 gpio_bank = gpio_bank_1510;
1358 #if defined(CONFIG_ARCH_OMAP16XX)
1359 if (cpu_is_omap16xx()) {
1362 gpio_bank_count = 5;
1363 gpio_bank = gpio_bank_1610;
1364 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1365 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1366 (rev >> 4) & 0x0f, rev & 0x0f);
1369 #ifdef CONFIG_ARCH_OMAP730
1370 if (cpu_is_omap730()) {
1371 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1372 gpio_bank_count = 7;
1373 gpio_bank = gpio_bank_730;
1377 #ifdef CONFIG_ARCH_OMAP24XX
1378 if (cpu_is_omap242x()) {
1381 gpio_bank_count = 4;
1382 gpio_bank = gpio_bank_242x;
1383 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1384 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1385 (rev >> 4) & 0x0f, rev & 0x0f);
1387 if (cpu_is_omap243x()) {
1390 gpio_bank_count = 5;
1391 gpio_bank = gpio_bank_243x;
1392 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1393 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1394 (rev >> 4) & 0x0f, rev & 0x0f);
1397 #ifdef CONFIG_ARCH_OMAP34XX
1398 if (cpu_is_omap34xx()) {
1401 gpio_bank_count = OMAP34XX_NR_GPIOS;
1402 gpio_bank = gpio_bank_34xx;
1403 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1404 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1405 (rev >> 4) & 0x0f, rev & 0x0f);
1408 for (i = 0; i < gpio_bank_count; i++) {
1409 int j, gpio_count = 16;
1411 bank = &gpio_bank[i];
1412 bank->reserved_map = 0;
1413 bank->base = IO_ADDRESS(bank->base);
1414 spin_lock_init(&bank->lock);
1415 if (bank_is_mpuio(bank))
1416 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1417 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1418 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1419 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1421 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1422 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1423 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1424 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1426 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
1427 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1428 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1430 gpio_count = 32; /* 730 has 32-bit GPIOs */
1433 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1434 if (bank->method == METHOD_GPIO_24XX) {
1435 static const u32 non_wakeup_gpios[] = {
1436 0xe203ffc0, 0x08700040
1439 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1440 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1441 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1443 /* Initialize interface clock ungated, module enabled */
1444 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1445 if (i < ARRAY_SIZE(non_wakeup_gpios))
1446 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1450 for (j = bank->virtual_irq_start;
1451 j < bank->virtual_irq_start + gpio_count; j++) {
1452 set_irq_chip_data(j, bank);
1453 if (bank_is_mpuio(bank))
1454 set_irq_chip(j, &mpuio_irq_chip);
1456 set_irq_chip(j, &gpio_irq_chip);
1457 set_irq_handler(j, handle_simple_irq);
1458 set_irq_flags(j, IRQF_VALID);
1460 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1461 set_irq_data(bank->irq, bank);
1464 /* Enable system clock for GPIO module.
1465 * The CAM_CLK_CTRL *is* really the right place. */
1466 if (cpu_is_omap16xx())
1467 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1469 /* Enable autoidle for the OCP interface */
1470 if (cpu_is_omap24xx())
1471 omap_writel(1 << 0, 0x48019010);
1472 if (cpu_is_omap34xx())
1473 omap_writel(1 << 0, 0x48306814);
1478 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1479 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1483 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1486 for (i = 0; i < gpio_bank_count; i++) {
1487 struct gpio_bank *bank = &gpio_bank[i];
1488 void __iomem *wake_status;
1489 void __iomem *wake_clear;
1490 void __iomem *wake_set;
1492 switch (bank->method) {
1493 #ifdef CONFIG_ARCH_OMAP16XX
1494 case METHOD_GPIO_1610:
1495 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1496 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1497 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1500 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1501 case METHOD_GPIO_24XX:
1502 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1503 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1504 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1511 spin_lock(&bank->lock);
1512 bank->saved_wakeup = __raw_readl(wake_status);
1513 __raw_writel(0xffffffff, wake_clear);
1514 __raw_writel(bank->suspend_wakeup, wake_set);
1515 spin_unlock(&bank->lock);
1521 static int omap_gpio_resume(struct sys_device *dev)
1525 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1528 for (i = 0; i < gpio_bank_count; i++) {
1529 struct gpio_bank *bank = &gpio_bank[i];
1530 void __iomem *wake_clear;
1531 void __iomem *wake_set;
1533 switch (bank->method) {
1534 #ifdef CONFIG_ARCH_OMAP16XX
1535 case METHOD_GPIO_1610:
1536 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1537 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1540 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1541 case METHOD_GPIO_24XX:
1542 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1543 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1550 spin_lock(&bank->lock);
1551 __raw_writel(0xffffffff, wake_clear);
1552 __raw_writel(bank->saved_wakeup, wake_set);
1553 spin_unlock(&bank->lock);
1559 static struct sysdev_class omap_gpio_sysclass = {
1560 set_kset_name("gpio"),
1561 .suspend = omap_gpio_suspend,
1562 .resume = omap_gpio_resume,
1565 static struct sys_device omap_gpio_device = {
1567 .cls = &omap_gpio_sysclass,
1572 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1574 static int workaround_enabled;
1576 void omap2_gpio_prepare_for_retention(void)
1580 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1581 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1582 for (i = 0; i < gpio_bank_count; i++) {
1583 struct gpio_bank *bank = &gpio_bank[i];
1586 if (!(bank->enabled_non_wakeup_gpios))
1588 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1589 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1590 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1591 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1593 bank->saved_fallingdetect = l1;
1594 bank->saved_risingdetect = l2;
1595 l1 &= ~bank->enabled_non_wakeup_gpios;
1596 l2 &= ~bank->enabled_non_wakeup_gpios;
1597 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1598 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1599 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1604 workaround_enabled = 0;
1607 workaround_enabled = 1;
1610 void omap2_gpio_resume_after_retention(void)
1614 if (!workaround_enabled)
1616 for (i = 0; i < gpio_bank_count; i++) {
1617 struct gpio_bank *bank = &gpio_bank[i];
1620 if (!(bank->enabled_non_wakeup_gpios))
1622 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1623 __raw_writel(bank->saved_fallingdetect,
1624 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1625 __raw_writel(bank->saved_risingdetect,
1626 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1628 /* Check if any of the non-wakeup interrupt GPIOs have changed
1629 * state. If so, generate an IRQ by software. This is
1630 * horribly racy, but it's the best we can do to work around
1631 * this silicon bug. */
1632 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1633 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1635 l ^= bank->saved_datain;
1636 l &= bank->non_wakeup_gpios;
1639 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1640 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1641 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1642 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1643 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1644 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1645 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1655 * This may get called early from board specific init
1656 * for boards that have interrupts routed via FPGA.
1658 int __init omap_gpio_init(void)
1661 return _omap_gpio_init();
1666 static int __init omap_gpio_sysinit(void)
1671 ret = _omap_gpio_init();
1675 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1676 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1678 ret = sysdev_class_register(&omap_gpio_sysclass);
1680 ret = sysdev_register(&omap_gpio_device);
1688 EXPORT_SYMBOL(omap_request_gpio);
1689 EXPORT_SYMBOL(omap_free_gpio);
1690 EXPORT_SYMBOL(omap_set_gpio_direction);
1691 EXPORT_SYMBOL(omap_set_gpio_dataout);
1692 EXPORT_SYMBOL(omap_get_gpio_datain);
1694 arch_initcall(omap_gpio_sysinit);
1697 #ifdef CONFIG_DEBUG_FS
1699 #include <linux/debugfs.h>
1700 #include <linux/seq_file.h>
1702 static int gpio_is_input(struct gpio_bank *bank, int mask)
1704 void __iomem *reg = bank->base;
1706 switch (bank->method) {
1708 reg += OMAP_MPUIO_IO_CNTL;
1710 case METHOD_GPIO_1510:
1711 reg += OMAP1510_GPIO_DIR_CONTROL;
1713 case METHOD_GPIO_1610:
1714 reg += OMAP1610_GPIO_DIRECTION;
1716 case METHOD_GPIO_730:
1717 reg += OMAP730_GPIO_DIR_CONTROL;
1719 case METHOD_GPIO_24XX:
1720 reg += OMAP24XX_GPIO_OE;
1723 return __raw_readl(reg) & mask;
1727 static int dbg_gpio_show(struct seq_file *s, void *unused)
1729 unsigned i, j, gpio;
1731 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1732 struct gpio_bank *bank = gpio_bank + i;
1733 unsigned bankwidth = 16;
1736 if (bank_is_mpuio(bank))
1737 gpio = OMAP_MPUIO(0);
1738 else if (cpu_class_is_omap2() || cpu_is_omap730())
1741 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1742 unsigned irq, value, is_in, irqstat;
1744 if (!(bank->reserved_map & mask))
1747 irq = bank->virtual_irq_start + j;
1748 value = omap_get_gpio_datain(gpio);
1749 is_in = gpio_is_input(bank, mask);
1751 if (bank_is_mpuio(bank))
1752 seq_printf(s, "MPUIO %2d: ", j);
1754 seq_printf(s, "GPIO %3d: ", gpio);
1755 seq_printf(s, "%s %s",
1756 is_in ? "in " : "out",
1757 value ? "hi" : "lo");
1759 irqstat = irq_desc[irq].status;
1760 if (is_in && ((bank->suspend_wakeup & mask)
1761 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1762 char *trigger = NULL;
1764 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1765 case IRQ_TYPE_EDGE_FALLING:
1766 trigger = "falling";
1768 case IRQ_TYPE_EDGE_RISING:
1771 case IRQ_TYPE_EDGE_BOTH:
1772 trigger = "bothedge";
1774 case IRQ_TYPE_LEVEL_LOW:
1777 case IRQ_TYPE_LEVEL_HIGH:
1781 trigger = "(unspecified)";
1784 seq_printf(s, ", irq-%d %s%s",
1786 (bank->suspend_wakeup & mask)
1789 seq_printf(s, "\n");
1792 if (bank_is_mpuio(bank)) {
1793 seq_printf(s, "\n");
1800 static int dbg_gpio_open(struct inode *inode, struct file *file)
1802 return single_open(file, dbg_gpio_show, &inode->i_private);
1805 static const struct file_operations debug_fops = {
1806 .open = dbg_gpio_open,
1808 .llseek = seq_lseek,
1809 .release = single_release,
1812 static int __init omap_gpio_debuginit(void)
1814 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1815 NULL, NULL, &debug_fops);
1818 late_initcall(omap_gpio_debuginit);