2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/sysdev.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
21 #include <asm/hardware.h>
23 #include <asm/arch/irqs.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/mach/irq.h>
30 * OMAP1510 GPIO registers
32 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
33 #define OMAP1510_GPIO_DATA_INPUT 0x00
34 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
35 #define OMAP1510_GPIO_DIR_CONTROL 0x08
36 #define OMAP1510_GPIO_INT_CONTROL 0x0c
37 #define OMAP1510_GPIO_INT_MASK 0x10
38 #define OMAP1510_GPIO_INT_STATUS 0x14
39 #define OMAP1510_GPIO_PIN_CONTROL 0x18
41 #define OMAP1510_IH_GPIO_BASE 64
44 * OMAP1610 specific GPIO registers
46 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
47 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
48 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
49 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
50 #define OMAP1610_GPIO_REVISION 0x0000
51 #define OMAP1610_GPIO_SYSCONFIG 0x0010
52 #define OMAP1610_GPIO_SYSSTATUS 0x0014
53 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
54 #define OMAP1610_GPIO_IRQENABLE1 0x001c
55 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
56 #define OMAP1610_GPIO_DATAIN 0x002c
57 #define OMAP1610_GPIO_DATAOUT 0x0030
58 #define OMAP1610_GPIO_DIRECTION 0x0034
59 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
60 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
61 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
62 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
63 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
64 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
65 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
66 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
69 * OMAP730 specific GPIO registers
71 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
72 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
73 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
74 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
75 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
76 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
77 #define OMAP730_GPIO_DATA_INPUT 0x00
78 #define OMAP730_GPIO_DATA_OUTPUT 0x04
79 #define OMAP730_GPIO_DIR_CONTROL 0x08
80 #define OMAP730_GPIO_INT_CONTROL 0x0c
81 #define OMAP730_GPIO_INT_MASK 0x10
82 #define OMAP730_GPIO_INT_STATUS 0x14
85 * omap24xx specific GPIO registers
87 #define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000
88 #define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000
89 #define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000
90 #define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000
92 #define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000
93 #define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000
94 #define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000
95 #define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000
96 #define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000
98 #define OMAP24XX_GPIO_REVISION 0x0000
99 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
100 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
101 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
102 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
103 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
104 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
105 #define OMAP24XX_GPIO_CTRL 0x0030
106 #define OMAP24XX_GPIO_OE 0x0034
107 #define OMAP24XX_GPIO_DATAIN 0x0038
108 #define OMAP24XX_GPIO_DATAOUT 0x003c
109 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
110 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
111 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
112 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
113 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
114 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
115 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
116 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
117 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
118 #define OMAP24XX_GPIO_SETWKUENA 0x0084
119 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
120 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
123 * omap34xx specific GPIO registers
126 #define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000
127 #define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000
128 #define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000
129 #define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000
130 #define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000
131 #define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000
137 u16 virtual_irq_start;
140 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
144 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
145 u32 non_wakeup_gpios;
146 u32 enabled_non_wakeup_gpios;
149 u32 saved_fallingdetect;
150 u32 saved_risingdetect;
156 #define METHOD_MPUIO 0
157 #define METHOD_GPIO_1510 1
158 #define METHOD_GPIO_1610 2
159 #define METHOD_GPIO_730 3
160 #define METHOD_GPIO_24XX 4
162 #ifdef CONFIG_ARCH_OMAP16XX
163 static struct gpio_bank gpio_bank_1610[5] = {
164 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
165 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
166 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
167 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
168 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
172 #ifdef CONFIG_ARCH_OMAP15XX
173 static struct gpio_bank gpio_bank_1510[2] = {
174 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
175 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
179 #ifdef CONFIG_ARCH_OMAP730
180 static struct gpio_bank gpio_bank_730[7] = {
181 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
182 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
183 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
184 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
185 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
186 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
187 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
191 #ifdef CONFIG_ARCH_OMAP24XX
193 static struct gpio_bank gpio_bank_242x[4] = {
194 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
195 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
196 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
197 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
200 static struct gpio_bank gpio_bank_243x[5] = {
201 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
202 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
203 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
204 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
205 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
210 #ifdef CONFIG_ARCH_OMAP34XX
211 static struct gpio_bank gpio_bank_34xx[6] = {
212 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
213 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
214 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
217 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
222 static struct gpio_bank *gpio_bank;
223 static int gpio_bank_count;
225 static inline struct gpio_bank *get_gpio_bank(int gpio)
227 if (cpu_is_omap15xx()) {
228 if (OMAP_GPIO_IS_MPUIO(gpio))
229 return &gpio_bank[0];
230 return &gpio_bank[1];
232 if (cpu_is_omap16xx()) {
233 if (OMAP_GPIO_IS_MPUIO(gpio))
234 return &gpio_bank[0];
235 return &gpio_bank[1 + (gpio >> 4)];
237 if (cpu_is_omap730()) {
238 if (OMAP_GPIO_IS_MPUIO(gpio))
239 return &gpio_bank[0];
240 return &gpio_bank[1 + (gpio >> 5)];
242 if (cpu_is_omap24xx())
243 return &gpio_bank[gpio >> 5];
244 if (cpu_is_omap34xx())
245 return &gpio_bank[gpio >> 5];
248 static inline int get_gpio_index(int gpio)
250 if (cpu_is_omap730())
252 if (cpu_is_omap24xx())
254 if (cpu_is_omap34xx())
259 static inline int gpio_valid(int gpio)
263 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
264 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
268 if (cpu_is_omap15xx() && gpio < 16)
270 if ((cpu_is_omap16xx()) && gpio < 64)
272 if (cpu_is_omap730() && gpio < 192)
274 if (cpu_is_omap24xx() && gpio < 128)
276 if (cpu_is_omap34xx() && gpio < 160)
281 static int check_gpio(int gpio)
283 if (unlikely(gpio_valid(gpio)) < 0) {
284 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
291 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
293 void __iomem *reg = bank->base;
296 switch (bank->method) {
297 #ifdef CONFIG_ARCH_OMAP1
299 reg += OMAP_MPUIO_IO_CNTL;
302 #ifdef CONFIG_ARCH_OMAP15XX
303 case METHOD_GPIO_1510:
304 reg += OMAP1510_GPIO_DIR_CONTROL;
307 #ifdef CONFIG_ARCH_OMAP16XX
308 case METHOD_GPIO_1610:
309 reg += OMAP1610_GPIO_DIRECTION;
312 #ifdef CONFIG_ARCH_OMAP730
313 case METHOD_GPIO_730:
314 reg += OMAP730_GPIO_DIR_CONTROL;
317 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
318 case METHOD_GPIO_24XX:
319 reg += OMAP24XX_GPIO_OE;
326 l = __raw_readl(reg);
331 __raw_writel(l, reg);
334 void omap_set_gpio_direction(int gpio, int is_input)
336 struct gpio_bank *bank;
338 if (check_gpio(gpio) < 0)
340 bank = get_gpio_bank(gpio);
341 spin_lock(&bank->lock);
342 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
343 spin_unlock(&bank->lock);
346 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
348 void __iomem *reg = bank->base;
351 switch (bank->method) {
352 #ifdef CONFIG_ARCH_OMAP1
354 reg += OMAP_MPUIO_OUTPUT;
355 l = __raw_readl(reg);
362 #ifdef CONFIG_ARCH_OMAP15XX
363 case METHOD_GPIO_1510:
364 reg += OMAP1510_GPIO_DATA_OUTPUT;
365 l = __raw_readl(reg);
372 #ifdef CONFIG_ARCH_OMAP16XX
373 case METHOD_GPIO_1610:
375 reg += OMAP1610_GPIO_SET_DATAOUT;
377 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
381 #ifdef CONFIG_ARCH_OMAP730
382 case METHOD_GPIO_730:
383 reg += OMAP730_GPIO_DATA_OUTPUT;
384 l = __raw_readl(reg);
391 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
392 case METHOD_GPIO_24XX:
394 reg += OMAP24XX_GPIO_SETDATAOUT;
396 reg += OMAP24XX_GPIO_CLEARDATAOUT;
404 __raw_writel(l, reg);
407 void omap_set_gpio_dataout(int gpio, int enable)
409 struct gpio_bank *bank;
411 if (check_gpio(gpio) < 0)
413 bank = get_gpio_bank(gpio);
414 spin_lock(&bank->lock);
415 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
416 spin_unlock(&bank->lock);
419 int omap_get_gpio_datain(int gpio)
421 struct gpio_bank *bank;
424 if (check_gpio(gpio) < 0)
426 bank = get_gpio_bank(gpio);
428 switch (bank->method) {
429 #ifdef CONFIG_ARCH_OMAP1
431 reg += OMAP_MPUIO_INPUT_LATCH;
434 #ifdef CONFIG_ARCH_OMAP15XX
435 case METHOD_GPIO_1510:
436 reg += OMAP1510_GPIO_DATA_INPUT;
439 #ifdef CONFIG_ARCH_OMAP16XX
440 case METHOD_GPIO_1610:
441 reg += OMAP1610_GPIO_DATAIN;
444 #ifdef CONFIG_ARCH_OMAP730
445 case METHOD_GPIO_730:
446 reg += OMAP730_GPIO_DATA_INPUT;
449 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
450 case METHOD_GPIO_24XX:
451 reg += OMAP24XX_GPIO_DATAIN;
457 return (__raw_readl(reg)
458 & (1 << get_gpio_index(gpio))) != 0;
461 #define MOD_REG_BIT(reg, bit_mask, set) \
463 int l = __raw_readl(base + reg); \
464 if (set) l |= bit_mask; \
465 else l &= ~bit_mask; \
466 __raw_writel(l, base + reg); \
469 void omap_set_gpio_debounce(int gpio, int enable)
471 struct gpio_bank *bank;
473 u32 val, l = 1 << get_gpio_index(gpio);
475 if (cpu_class_is_omap1())
478 bank = get_gpio_bank(gpio);
481 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
482 val = __raw_readl(reg);
489 __raw_writel(val, reg);
491 EXPORT_SYMBOL(omap_set_gpio_debounce);
493 void omap_set_gpio_debounce_time(int gpio, int enc_time)
495 struct gpio_bank *bank;
498 if (cpu_class_is_omap1())
501 bank = get_gpio_bank(gpio);
505 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
506 __raw_writel(enc_time, reg);
508 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
510 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
511 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
514 void __iomem *base = bank->base;
515 u32 gpio_bit = 1 << gpio;
517 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
518 trigger & __IRQT_LOWLVL);
519 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
520 trigger & __IRQT_HIGHLVL);
521 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
522 trigger & __IRQT_RISEDGE);
523 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
524 trigger & __IRQT_FALEDGE);
526 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
528 __raw_writel(1 << gpio, bank->base
529 + OMAP24XX_GPIO_SETWKUENA);
531 __raw_writel(1 << gpio, bank->base
532 + OMAP24XX_GPIO_CLEARWKUENA);
535 bank->enabled_non_wakeup_gpios |= gpio_bit;
537 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
541 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
542 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
544 * FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only
545 * level triggering requested.
550 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
552 void __iomem *reg = bank->base;
555 switch (bank->method) {
556 #ifdef CONFIG_ARCH_OMAP1
558 reg += OMAP_MPUIO_GPIO_INT_EDGE;
559 l = __raw_readl(reg);
560 if (trigger & __IRQT_RISEDGE)
562 else if (trigger & __IRQT_FALEDGE)
568 #ifdef CONFIG_ARCH_OMAP15XX
569 case METHOD_GPIO_1510:
570 reg += OMAP1510_GPIO_INT_CONTROL;
571 l = __raw_readl(reg);
572 if (trigger & __IRQT_RISEDGE)
574 else if (trigger & __IRQT_FALEDGE)
580 #ifdef CONFIG_ARCH_OMAP16XX
581 case METHOD_GPIO_1610:
583 reg += OMAP1610_GPIO_EDGE_CTRL2;
585 reg += OMAP1610_GPIO_EDGE_CTRL1;
587 l = __raw_readl(reg);
588 l &= ~(3 << (gpio << 1));
589 if (trigger & __IRQT_RISEDGE)
590 l |= 2 << (gpio << 1);
591 if (trigger & __IRQT_FALEDGE)
592 l |= 1 << (gpio << 1);
594 /* Enable wake-up during idle for dynamic tick */
595 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
597 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
600 #ifdef CONFIG_ARCH_OMAP730
601 case METHOD_GPIO_730:
602 reg += OMAP730_GPIO_INT_CONTROL;
603 l = __raw_readl(reg);
604 if (trigger & __IRQT_RISEDGE)
606 else if (trigger & __IRQT_FALEDGE)
612 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
613 case METHOD_GPIO_24XX:
614 set_24xx_gpio_triggering(bank, gpio, trigger);
620 __raw_writel(l, reg);
626 static int gpio_irq_type(unsigned irq, unsigned type)
628 struct gpio_bank *bank;
632 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
633 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
635 gpio = irq - IH_GPIO_BASE;
637 if (check_gpio(gpio) < 0)
640 if (type & ~IRQ_TYPE_SENSE_MASK)
643 /* OMAP1 allows only only edge triggering */
644 if (!cpu_class_is_omap2()
645 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
648 bank = get_irq_chip_data(irq);
649 spin_lock(&bank->lock);
650 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
652 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
653 irq_desc[irq].status |= type;
655 spin_unlock(&bank->lock);
659 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
661 void __iomem *reg = bank->base;
663 switch (bank->method) {
664 #ifdef CONFIG_ARCH_OMAP1
666 /* MPUIO irqstatus is reset by reading the status register,
667 * so do nothing here */
670 #ifdef CONFIG_ARCH_OMAP15XX
671 case METHOD_GPIO_1510:
672 reg += OMAP1510_GPIO_INT_STATUS;
675 #ifdef CONFIG_ARCH_OMAP16XX
676 case METHOD_GPIO_1610:
677 reg += OMAP1610_GPIO_IRQSTATUS1;
680 #ifdef CONFIG_ARCH_OMAP730
681 case METHOD_GPIO_730:
682 reg += OMAP730_GPIO_INT_STATUS;
685 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
686 case METHOD_GPIO_24XX:
687 reg += OMAP24XX_GPIO_IRQSTATUS1;
694 __raw_writel(gpio_mask, reg);
696 /* Workaround for clearing DSP GPIO interrupts to allow retention */
697 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
698 if (cpu_is_omap24xx() || cpu_is_omap34xx())
699 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
703 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
705 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
708 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
710 void __iomem *reg = bank->base;
715 switch (bank->method) {
716 #ifdef CONFIG_ARCH_OMAP1
718 reg += OMAP_MPUIO_GPIO_MASKIT;
723 #ifdef CONFIG_ARCH_OMAP15XX
724 case METHOD_GPIO_1510:
725 reg += OMAP1510_GPIO_INT_MASK;
730 #ifdef CONFIG_ARCH_OMAP16XX
731 case METHOD_GPIO_1610:
732 reg += OMAP1610_GPIO_IRQENABLE1;
736 #ifdef CONFIG_ARCH_OMAP730
737 case METHOD_GPIO_730:
738 reg += OMAP730_GPIO_INT_MASK;
743 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
744 case METHOD_GPIO_24XX:
745 reg += OMAP24XX_GPIO_IRQENABLE1;
754 l = __raw_readl(reg);
761 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
763 void __iomem *reg = bank->base;
766 switch (bank->method) {
767 #ifdef CONFIG_ARCH_OMAP1
769 reg += OMAP_MPUIO_GPIO_MASKIT;
770 l = __raw_readl(reg);
777 #ifdef CONFIG_ARCH_OMAP15XX
778 case METHOD_GPIO_1510:
779 reg += OMAP1510_GPIO_INT_MASK;
780 l = __raw_readl(reg);
787 #ifdef CONFIG_ARCH_OMAP16XX
788 case METHOD_GPIO_1610:
790 reg += OMAP1610_GPIO_SET_IRQENABLE1;
792 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
796 #ifdef CONFIG_ARCH_OMAP730
797 case METHOD_GPIO_730:
798 reg += OMAP730_GPIO_INT_MASK;
799 l = __raw_readl(reg);
806 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
807 case METHOD_GPIO_24XX:
809 reg += OMAP24XX_GPIO_SETIRQENABLE1;
811 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
819 __raw_writel(l, reg);
822 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
824 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
828 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
829 * 1510 does not seem to have a wake-up register. If JTAG is connected
830 * to the target, system will wake up always on GPIO events. While
831 * system is running all registered GPIO interrupts need to have wake-up
832 * enabled. When system is suspended, only selected GPIO interrupts need
833 * to have wake-up enabled.
835 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
837 switch (bank->method) {
838 #ifdef CONFIG_ARCH_OMAP16XX
840 case METHOD_GPIO_1610:
841 spin_lock(&bank->lock);
843 bank->suspend_wakeup |= (1 << gpio);
844 enable_irq_wake(bank->irq);
846 disable_irq_wake(bank->irq);
847 bank->suspend_wakeup &= ~(1 << gpio);
849 spin_unlock(&bank->lock);
852 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
853 case METHOD_GPIO_24XX:
854 if (bank->non_wakeup_gpios & (1 << gpio)) {
855 printk(KERN_ERR "Unable to modify wakeup on "
856 "non-wakeup GPIO%d\n",
857 (bank - gpio_bank) * 32 + gpio);
860 spin_lock(&bank->lock);
862 bank->suspend_wakeup |= (1 << gpio);
863 enable_irq_wake(bank->irq);
865 disable_irq_wake(bank->irq);
866 bank->suspend_wakeup &= ~(1 << gpio);
868 spin_unlock(&bank->lock);
872 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
878 static void _reset_gpio(struct gpio_bank *bank, int gpio)
880 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
881 _set_gpio_irqenable(bank, gpio, 0);
882 _clear_gpio_irqstatus(bank, gpio);
883 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
886 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
887 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
889 unsigned int gpio = irq - IH_GPIO_BASE;
890 struct gpio_bank *bank;
893 if (check_gpio(gpio) < 0)
895 bank = get_irq_chip_data(irq);
896 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
901 int omap_request_gpio(int gpio)
903 struct gpio_bank *bank;
905 if (check_gpio(gpio) < 0)
908 bank = get_gpio_bank(gpio);
909 spin_lock(&bank->lock);
910 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
911 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
913 spin_unlock(&bank->lock);
916 bank->reserved_map |= (1 << get_gpio_index(gpio));
918 /* Set trigger to none. You need to enable the desired trigger with
919 * request_irq() or set_irq_type().
921 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
923 #ifdef CONFIG_ARCH_OMAP15XX
924 if (bank->method == METHOD_GPIO_1510) {
927 /* Claim the pin for MPU */
928 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
929 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
932 spin_unlock(&bank->lock);
937 void omap_free_gpio(int gpio)
939 struct gpio_bank *bank;
941 if (check_gpio(gpio) < 0)
943 bank = get_gpio_bank(gpio);
944 spin_lock(&bank->lock);
945 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
946 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
948 spin_unlock(&bank->lock);
951 #ifdef CONFIG_ARCH_OMAP16XX
952 if (bank->method == METHOD_GPIO_1610) {
953 /* Disable wake-up during idle for dynamic tick */
954 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
955 __raw_writel(1 << get_gpio_index(gpio), reg);
958 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
959 if (bank->method == METHOD_GPIO_24XX) {
960 /* Disable wake-up during idle for dynamic tick */
961 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
962 __raw_writel(1 << get_gpio_index(gpio), reg);
965 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
966 _reset_gpio(bank, gpio);
967 spin_unlock(&bank->lock);
971 * We need to unmask the GPIO bank interrupt as soon as possible to
972 * avoid missing GPIO interrupts for other lines in the bank.
973 * Then we need to mask-read-clear-unmask the triggered GPIO lines
974 * in the bank to avoid missing nested interrupts for a GPIO line.
975 * If we wait to unmask individual GPIO lines in the bank after the
976 * line's interrupt handler has been run, we may miss some nested
979 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
981 void __iomem *isr_reg = NULL;
983 unsigned int gpio_irq;
984 struct gpio_bank *bank;
988 desc->chip->ack(irq);
990 bank = get_irq_data(irq);
991 #ifdef CONFIG_ARCH_OMAP1
992 if (bank->method == METHOD_MPUIO)
993 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
995 #ifdef CONFIG_ARCH_OMAP15XX
996 if (bank->method == METHOD_GPIO_1510)
997 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
999 #if defined(CONFIG_ARCH_OMAP16XX)
1000 if (bank->method == METHOD_GPIO_1610)
1001 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1003 #ifdef CONFIG_ARCH_OMAP730
1004 if (bank->method == METHOD_GPIO_730)
1005 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1007 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1008 if (bank->method == METHOD_GPIO_24XX)
1009 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1012 u32 isr_saved, level_mask = 0;
1015 enabled = _get_gpio_irqbank_mask(bank);
1016 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1018 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1021 if (cpu_class_is_omap2()) {
1022 level_mask = bank->level_mask & enabled;
1025 /* clear edge sensitive interrupts before handler(s) are
1026 called so that we don't miss any interrupt occurred while
1028 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1029 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1030 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1032 /* if there is only edge sensitive GPIO pin interrupts
1033 configured, we could unmask GPIO bank interrupt immediately */
1034 if (!level_mask && !unmasked) {
1036 desc->chip->unmask(irq);
1044 gpio_irq = bank->virtual_irq_start;
1045 for (; isr != 0; isr >>= 1, gpio_irq++) {
1050 d = irq_desc + gpio_irq;
1051 /* Don't run the handler if it's already running
1052 * or was disabled lazely.
1054 if (unlikely((d->depth ||
1055 (d->status & IRQ_INPROGRESS)))) {
1057 (gpio_irq - bank->virtual_irq_start);
1058 /* The unmasking will be done by
1059 * enable_irq in case it is disabled or
1060 * after returning from the handler if
1061 * it's already running.
1063 _enable_gpio_irqbank(bank, irq_mask, 0);
1065 /* Level triggered interrupts
1066 * won't ever be reentered
1068 BUG_ON(level_mask & irq_mask);
1069 d->status |= IRQ_PENDING;
1074 desc_handle_irq(gpio_irq, d);
1076 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
1078 (gpio_irq - bank->virtual_irq_start);
1079 d->status &= ~IRQ_PENDING;
1080 _enable_gpio_irqbank(bank, irq_mask, 1);
1081 retrigger |= irq_mask;
1085 /* if bank has any level sensitive GPIO pin interrupt
1086 configured, we must unmask the bank interrupt only after
1087 handler(s) are executed in order to avoid spurious bank
1090 desc->chip->unmask(irq);
1094 static void gpio_irq_shutdown(unsigned int irq)
1096 unsigned int gpio = irq - IH_GPIO_BASE;
1097 struct gpio_bank *bank = get_irq_chip_data(irq);
1099 _reset_gpio(bank, gpio);
1102 static void gpio_ack_irq(unsigned int irq)
1104 unsigned int gpio = irq - IH_GPIO_BASE;
1105 struct gpio_bank *bank = get_irq_chip_data(irq);
1107 _clear_gpio_irqstatus(bank, gpio);
1110 static void gpio_mask_irq(unsigned int irq)
1112 unsigned int gpio = irq - IH_GPIO_BASE;
1113 struct gpio_bank *bank = get_irq_chip_data(irq);
1115 _set_gpio_irqenable(bank, gpio, 0);
1118 static void gpio_unmask_irq(unsigned int irq)
1120 unsigned int gpio = irq - IH_GPIO_BASE;
1121 struct gpio_bank *bank = get_irq_chip_data(irq);
1122 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1124 /* For level-triggered GPIOs, the clearing must be done after
1125 * the HW source is cleared, thus after the handler has run */
1126 if (bank->level_mask & irq_mask) {
1127 _set_gpio_irqenable(bank, gpio, 0);
1128 _clear_gpio_irqstatus(bank, gpio);
1131 _set_gpio_irqenable(bank, gpio, 1);
1134 static struct irq_chip gpio_irq_chip = {
1136 .shutdown = gpio_irq_shutdown,
1137 .ack = gpio_ack_irq,
1138 .mask = gpio_mask_irq,
1139 .unmask = gpio_unmask_irq,
1140 .set_type = gpio_irq_type,
1141 .set_wake = gpio_wake_enable,
1144 /*---------------------------------------------------------------------*/
1146 #ifdef CONFIG_ARCH_OMAP1
1148 /* MPUIO uses the always-on 32k clock */
1150 static void mpuio_ack_irq(unsigned int irq)
1152 /* The ISR is reset automatically, so do nothing here. */
1155 static void mpuio_mask_irq(unsigned int irq)
1157 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1158 struct gpio_bank *bank = get_irq_chip_data(irq);
1160 _set_gpio_irqenable(bank, gpio, 0);
1163 static void mpuio_unmask_irq(unsigned int irq)
1165 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1166 struct gpio_bank *bank = get_irq_chip_data(irq);
1168 _set_gpio_irqenable(bank, gpio, 1);
1171 static struct irq_chip mpuio_irq_chip = {
1173 .ack = mpuio_ack_irq,
1174 .mask = mpuio_mask_irq,
1175 .unmask = mpuio_unmask_irq,
1176 .set_type = gpio_irq_type,
1177 #ifdef CONFIG_ARCH_OMAP16XX
1178 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1179 .set_wake = gpio_wake_enable,
1184 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1187 #ifdef CONFIG_ARCH_OMAP16XX
1189 #include <linux/platform_device.h>
1191 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1193 struct gpio_bank *bank = platform_get_drvdata(pdev);
1194 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1196 spin_lock(&bank->lock);
1197 bank->saved_wakeup = __raw_readl(mask_reg);
1198 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1199 spin_unlock(&bank->lock);
1204 static int omap_mpuio_resume_early(struct platform_device *pdev)
1206 struct gpio_bank *bank = platform_get_drvdata(pdev);
1207 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1209 spin_lock(&bank->lock);
1210 __raw_writel(bank->saved_wakeup, mask_reg);
1211 spin_unlock(&bank->lock);
1216 /* use platform_driver for this, now that there's no longer any
1217 * point to sys_device (other than not disturbing old code).
1219 static struct platform_driver omap_mpuio_driver = {
1220 .suspend_late = omap_mpuio_suspend_late,
1221 .resume_early = omap_mpuio_resume_early,
1227 static struct platform_device omap_mpuio_device = {
1231 .driver = &omap_mpuio_driver.driver,
1233 /* could list the /proc/iomem resources */
1236 static inline void mpuio_init(void)
1238 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1240 if (platform_driver_register(&omap_mpuio_driver) == 0)
1241 (void) platform_device_register(&omap_mpuio_device);
1245 static inline void mpuio_init(void) {}
1250 extern struct irq_chip mpuio_irq_chip;
1252 #define bank_is_mpuio(bank) 0
1253 static inline void mpuio_init(void) {}
1257 /*---------------------------------------------------------------------*/
1259 static int initialized;
1260 #if !defined(CONFIG_ARCH_OMAP3)
1261 static struct clk * gpio_ick;
1264 #if defined(CONFIG_ARCH_OMAP2)
1265 static struct clk * gpio_fck;
1268 #if defined(CONFIG_ARCH_OMAP2430)
1269 static struct clk * gpio5_ick;
1270 static struct clk * gpio5_fck;
1273 #if defined(CONFIG_ARCH_OMAP3)
1274 static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
1275 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1278 static int __init _omap_gpio_init(void)
1281 struct gpio_bank *bank;
1282 #if defined(CONFIG_ARCH_OMAP3)
1288 #if defined(CONFIG_ARCH_OMAP1)
1289 if (cpu_is_omap15xx()) {
1290 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1291 if (IS_ERR(gpio_ick))
1292 printk("Could not get arm_gpio_ck\n");
1294 clk_enable(gpio_ick);
1297 #if defined(CONFIG_ARCH_OMAP2)
1298 if (cpu_class_is_omap2()) {
1299 gpio_ick = clk_get(NULL, "gpios_ick");
1300 if (IS_ERR(gpio_ick))
1301 printk("Could not get gpios_ick\n");
1303 clk_enable(gpio_ick);
1304 gpio_fck = clk_get(NULL, "gpios_fck");
1305 if (IS_ERR(gpio_fck))
1306 printk("Could not get gpios_fck\n");
1308 clk_enable(gpio_fck);
1311 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1313 #if defined(CONFIG_ARCH_OMAP2430)
1314 if (cpu_is_omap2430()) {
1315 gpio5_ick = clk_get(NULL, "gpio5_ick");
1316 if (IS_ERR(gpio5_ick))
1317 printk("Could not get gpio5_ick\n");
1319 clk_enable(gpio5_ick);
1320 gpio5_fck = clk_get(NULL, "gpio5_fck");
1321 if (IS_ERR(gpio5_fck))
1322 printk("Could not get gpio5_fck\n");
1324 clk_enable(gpio5_fck);
1330 #if defined(CONFIG_ARCH_OMAP3)
1331 if (cpu_is_omap34xx()) {
1332 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1333 sprintf(clk_name, "gpio%d_ick", i + 1);
1334 gpio_iclks[i] = clk_get(NULL, clk_name);
1335 if (IS_ERR(gpio_iclks[i]))
1336 printk(KERN_ERR "Could not get %s\n", clk_name);
1338 clk_enable(gpio_iclks[i]);
1339 sprintf(clk_name, "gpio%d_fck", i + 1);
1340 gpio_fclks[i] = clk_get(NULL, clk_name);
1341 if (IS_ERR(gpio_fclks[i]))
1342 printk(KERN_ERR "Could not get %s\n", clk_name);
1344 clk_enable(gpio_fclks[i]);
1350 #ifdef CONFIG_ARCH_OMAP15XX
1351 if (cpu_is_omap15xx()) {
1352 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1353 gpio_bank_count = 2;
1354 gpio_bank = gpio_bank_1510;
1357 #if defined(CONFIG_ARCH_OMAP16XX)
1358 if (cpu_is_omap16xx()) {
1361 gpio_bank_count = 5;
1362 gpio_bank = gpio_bank_1610;
1363 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1364 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1365 (rev >> 4) & 0x0f, rev & 0x0f);
1368 #ifdef CONFIG_ARCH_OMAP730
1369 if (cpu_is_omap730()) {
1370 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1371 gpio_bank_count = 7;
1372 gpio_bank = gpio_bank_730;
1376 #ifdef CONFIG_ARCH_OMAP24XX
1377 if (cpu_is_omap242x()) {
1380 gpio_bank_count = 4;
1381 gpio_bank = gpio_bank_242x;
1382 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1383 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1384 (rev >> 4) & 0x0f, rev & 0x0f);
1386 if (cpu_is_omap243x()) {
1389 gpio_bank_count = 5;
1390 gpio_bank = gpio_bank_243x;
1391 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1392 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1393 (rev >> 4) & 0x0f, rev & 0x0f);
1396 #ifdef CONFIG_ARCH_OMAP34XX
1397 if (cpu_is_omap34xx()) {
1400 gpio_bank_count = OMAP34XX_NR_GPIOS;
1401 gpio_bank = gpio_bank_34xx;
1402 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1403 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1404 (rev >> 4) & 0x0f, rev & 0x0f);
1407 for (i = 0; i < gpio_bank_count; i++) {
1408 int j, gpio_count = 16;
1410 bank = &gpio_bank[i];
1411 bank->reserved_map = 0;
1412 bank->base = IO_ADDRESS(bank->base);
1413 spin_lock_init(&bank->lock);
1414 if (bank_is_mpuio(bank))
1415 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1416 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1417 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1418 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1420 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1421 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1422 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1423 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1425 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
1426 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1427 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1429 gpio_count = 32; /* 730 has 32-bit GPIOs */
1432 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1433 if (bank->method == METHOD_GPIO_24XX) {
1434 static const u32 non_wakeup_gpios[] = {
1435 0xe203ffc0, 0x08700040
1438 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1439 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1440 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1442 /* Initialize interface clock ungated, module enabled */
1443 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1444 if (i < ARRAY_SIZE(non_wakeup_gpios))
1445 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1449 for (j = bank->virtual_irq_start;
1450 j < bank->virtual_irq_start + gpio_count; j++) {
1451 set_irq_chip_data(j, bank);
1452 if (bank_is_mpuio(bank))
1453 set_irq_chip(j, &mpuio_irq_chip);
1455 set_irq_chip(j, &gpio_irq_chip);
1456 set_irq_handler(j, handle_simple_irq);
1457 set_irq_flags(j, IRQF_VALID);
1459 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1460 set_irq_data(bank->irq, bank);
1463 /* Enable system clock for GPIO module.
1464 * The CAM_CLK_CTRL *is* really the right place. */
1465 if (cpu_is_omap16xx())
1466 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1468 /* Enable autoidle for the OCP interface */
1469 if (cpu_is_omap24xx())
1470 omap_writel(1 << 0, 0x48019010);
1471 if (cpu_is_omap34xx())
1472 omap_writel(1 << 0, 0x48306814);
1477 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1478 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1482 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1485 for (i = 0; i < gpio_bank_count; i++) {
1486 struct gpio_bank *bank = &gpio_bank[i];
1487 void __iomem *wake_status;
1488 void __iomem *wake_clear;
1489 void __iomem *wake_set;
1491 switch (bank->method) {
1492 #ifdef CONFIG_ARCH_OMAP16XX
1493 case METHOD_GPIO_1610:
1494 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1495 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1496 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1499 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1500 case METHOD_GPIO_24XX:
1501 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1502 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1503 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1510 spin_lock(&bank->lock);
1511 bank->saved_wakeup = __raw_readl(wake_status);
1512 __raw_writel(0xffffffff, wake_clear);
1513 __raw_writel(bank->suspend_wakeup, wake_set);
1514 spin_unlock(&bank->lock);
1520 static int omap_gpio_resume(struct sys_device *dev)
1524 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1527 for (i = 0; i < gpio_bank_count; i++) {
1528 struct gpio_bank *bank = &gpio_bank[i];
1529 void __iomem *wake_clear;
1530 void __iomem *wake_set;
1532 switch (bank->method) {
1533 #ifdef CONFIG_ARCH_OMAP16XX
1534 case METHOD_GPIO_1610:
1535 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1536 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1539 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1540 case METHOD_GPIO_24XX:
1541 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1542 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1549 spin_lock(&bank->lock);
1550 __raw_writel(0xffffffff, wake_clear);
1551 __raw_writel(bank->saved_wakeup, wake_set);
1552 spin_unlock(&bank->lock);
1558 static struct sysdev_class omap_gpio_sysclass = {
1559 set_kset_name("gpio"),
1560 .suspend = omap_gpio_suspend,
1561 .resume = omap_gpio_resume,
1564 static struct sys_device omap_gpio_device = {
1566 .cls = &omap_gpio_sysclass,
1571 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1573 static int workaround_enabled;
1575 void omap2_gpio_prepare_for_retention(void)
1579 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1580 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1581 for (i = 0; i < gpio_bank_count; i++) {
1582 struct gpio_bank *bank = &gpio_bank[i];
1585 if (!(bank->enabled_non_wakeup_gpios))
1587 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1588 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1589 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1590 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1592 bank->saved_fallingdetect = l1;
1593 bank->saved_risingdetect = l2;
1594 l1 &= ~bank->enabled_non_wakeup_gpios;
1595 l2 &= ~bank->enabled_non_wakeup_gpios;
1596 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1597 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1598 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1603 workaround_enabled = 0;
1606 workaround_enabled = 1;
1609 void omap2_gpio_resume_after_retention(void)
1613 if (!workaround_enabled)
1615 for (i = 0; i < gpio_bank_count; i++) {
1616 struct gpio_bank *bank = &gpio_bank[i];
1619 if (!(bank->enabled_non_wakeup_gpios))
1621 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1622 __raw_writel(bank->saved_fallingdetect,
1623 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1624 __raw_writel(bank->saved_risingdetect,
1625 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1627 /* Check if any of the non-wakeup interrupt GPIOs have changed
1628 * state. If so, generate an IRQ by software. This is
1629 * horribly racy, but it's the best we can do to work around
1630 * this silicon bug. */
1631 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1632 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1634 l ^= bank->saved_datain;
1635 l &= bank->non_wakeup_gpios;
1638 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1639 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1640 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1641 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1642 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1643 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1644 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1654 * This may get called early from board specific init
1655 * for boards that have interrupts routed via FPGA.
1657 int __init omap_gpio_init(void)
1660 return _omap_gpio_init();
1665 static int __init omap_gpio_sysinit(void)
1670 ret = _omap_gpio_init();
1674 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1675 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1677 ret = sysdev_class_register(&omap_gpio_sysclass);
1679 ret = sysdev_register(&omap_gpio_device);
1687 EXPORT_SYMBOL(omap_request_gpio);
1688 EXPORT_SYMBOL(omap_free_gpio);
1689 EXPORT_SYMBOL(omap_set_gpio_direction);
1690 EXPORT_SYMBOL(omap_set_gpio_dataout);
1691 EXPORT_SYMBOL(omap_get_gpio_datain);
1693 arch_initcall(omap_gpio_sysinit);
1696 #ifdef CONFIG_DEBUG_FS
1698 #include <linux/debugfs.h>
1699 #include <linux/seq_file.h>
1701 static int gpio_is_input(struct gpio_bank *bank, int mask)
1703 void __iomem *reg = bank->base;
1705 switch (bank->method) {
1707 reg += OMAP_MPUIO_IO_CNTL;
1709 case METHOD_GPIO_1510:
1710 reg += OMAP1510_GPIO_DIR_CONTROL;
1712 case METHOD_GPIO_1610:
1713 reg += OMAP1610_GPIO_DIRECTION;
1715 case METHOD_GPIO_730:
1716 reg += OMAP730_GPIO_DIR_CONTROL;
1718 case METHOD_GPIO_24XX:
1719 reg += OMAP24XX_GPIO_OE;
1722 return __raw_readl(reg) & mask;
1726 static int dbg_gpio_show(struct seq_file *s, void *unused)
1728 unsigned i, j, gpio;
1730 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1731 struct gpio_bank *bank = gpio_bank + i;
1732 unsigned bankwidth = 16;
1735 if (bank_is_mpuio(bank))
1736 gpio = OMAP_MPUIO(0);
1737 else if (cpu_class_is_omap2() || cpu_is_omap730())
1740 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1741 unsigned irq, value, is_in, irqstat;
1743 if (!(bank->reserved_map & mask))
1746 irq = bank->virtual_irq_start + j;
1747 value = omap_get_gpio_datain(gpio);
1748 is_in = gpio_is_input(bank, mask);
1750 if (bank_is_mpuio(bank))
1751 seq_printf(s, "MPUIO %2d: ", j);
1753 seq_printf(s, "GPIO %3d: ", gpio);
1754 seq_printf(s, "%s %s",
1755 is_in ? "in " : "out",
1756 value ? "hi" : "lo");
1758 irqstat = irq_desc[irq].status;
1759 if (is_in && ((bank->suspend_wakeup & mask)
1760 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1761 char *trigger = NULL;
1763 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1764 case IRQ_TYPE_EDGE_FALLING:
1765 trigger = "falling";
1767 case IRQ_TYPE_EDGE_RISING:
1770 case IRQ_TYPE_EDGE_BOTH:
1771 trigger = "bothedge";
1773 case IRQ_TYPE_LEVEL_LOW:
1776 case IRQ_TYPE_LEVEL_HIGH:
1780 trigger = "(unspecified)";
1783 seq_printf(s, ", irq-%d %s%s",
1785 (bank->suspend_wakeup & mask)
1788 seq_printf(s, "\n");
1791 if (bank_is_mpuio(bank)) {
1792 seq_printf(s, "\n");
1799 static int dbg_gpio_open(struct inode *inode, struct file *file)
1801 return single_open(file, dbg_gpio_show, &inode->i_private);
1804 static const struct file_operations debug_fops = {
1805 .open = dbg_gpio_open,
1807 .llseek = seq_lseek,
1808 .release = single_release,
1811 static int __init omap_gpio_debuginit(void)
1813 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1814 NULL, NULL, &debug_fops);
1817 late_initcall(omap_gpio_debuginit);