2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/sched.h>
17 #include <linux/interrupt.h>
18 #include <linux/sysdev.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <asm/hardware.h>
24 #include <asm/arch/irqs.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/mach/irq.h>
31 * OMAP1510 GPIO registers
33 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
34 #define OMAP1510_GPIO_DATA_INPUT 0x00
35 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
36 #define OMAP1510_GPIO_DIR_CONTROL 0x08
37 #define OMAP1510_GPIO_INT_CONTROL 0x0c
38 #define OMAP1510_GPIO_INT_MASK 0x10
39 #define OMAP1510_GPIO_INT_STATUS 0x14
40 #define OMAP1510_GPIO_PIN_CONTROL 0x18
42 #define OMAP1510_IH_GPIO_BASE 64
45 * OMAP1610 specific GPIO registers
47 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
48 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
49 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
50 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
51 #define OMAP1610_GPIO_REVISION 0x0000
52 #define OMAP1610_GPIO_SYSCONFIG 0x0010
53 #define OMAP1610_GPIO_SYSSTATUS 0x0014
54 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
55 #define OMAP1610_GPIO_IRQENABLE1 0x001c
56 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
57 #define OMAP1610_GPIO_DATAIN 0x002c
58 #define OMAP1610_GPIO_DATAOUT 0x0030
59 #define OMAP1610_GPIO_DIRECTION 0x0034
60 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
61 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
62 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
63 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
64 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
65 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
66 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
67 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
70 * OMAP730 specific GPIO registers
72 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
73 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
74 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
75 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
76 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
77 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
78 #define OMAP730_GPIO_DATA_INPUT 0x00
79 #define OMAP730_GPIO_DATA_OUTPUT 0x04
80 #define OMAP730_GPIO_DIR_CONTROL 0x08
81 #define OMAP730_GPIO_INT_CONTROL 0x0c
82 #define OMAP730_GPIO_INT_MASK 0x10
83 #define OMAP730_GPIO_INT_STATUS 0x14
86 * omap24xx specific GPIO registers
88 #define OMAP24XX_GPIO1_BASE (void __iomem *)0x48018000
89 #define OMAP24XX_GPIO2_BASE (void __iomem *)0x4801a000
90 #define OMAP24XX_GPIO3_BASE (void __iomem *)0x4801c000
91 #define OMAP24XX_GPIO4_BASE (void __iomem *)0x4801e000
92 #define OMAP24XX_GPIO_REVISION 0x0000
93 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
94 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
95 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
96 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
97 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
98 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
99 #define OMAP24XX_GPIO_CTRL 0x0030
100 #define OMAP24XX_GPIO_OE 0x0034
101 #define OMAP24XX_GPIO_DATAIN 0x0038
102 #define OMAP24XX_GPIO_DATAOUT 0x003c
103 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
104 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
105 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
106 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
107 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
108 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
109 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
110 #define OMAP24XX_GPIO_SETWKUENA 0x0084
111 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
112 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
117 u16 virtual_irq_start;
125 #define METHOD_MPUIO 0
126 #define METHOD_GPIO_1510 1
127 #define METHOD_GPIO_1610 2
128 #define METHOD_GPIO_730 3
129 #define METHOD_GPIO_24XX 4
131 #ifdef CONFIG_ARCH_OMAP16XX
132 static struct gpio_bank gpio_bank_1610[5] = {
133 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
134 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
135 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
136 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
137 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
141 #ifdef CONFIG_ARCH_OMAP15XX
142 static struct gpio_bank gpio_bank_1510[2] = {
143 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
144 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
148 #ifdef CONFIG_ARCH_OMAP730
149 static struct gpio_bank gpio_bank_730[7] = {
150 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
151 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
152 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
153 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
154 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
155 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
156 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
160 #ifdef CONFIG_ARCH_OMAP24XX
161 static struct gpio_bank gpio_bank_24xx[4] = {
162 { OMAP24XX_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
163 { OMAP24XX_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
164 { OMAP24XX_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
165 { OMAP24XX_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
169 static struct gpio_bank *gpio_bank;
170 static int gpio_bank_count;
172 static inline struct gpio_bank *get_gpio_bank(int gpio)
174 #ifdef CONFIG_ARCH_OMAP15XX
175 if (cpu_is_omap15xx()) {
176 if (OMAP_GPIO_IS_MPUIO(gpio))
177 return &gpio_bank[0];
178 return &gpio_bank[1];
181 #if defined(CONFIG_ARCH_OMAP16XX)
182 if (cpu_is_omap16xx()) {
183 if (OMAP_GPIO_IS_MPUIO(gpio))
184 return &gpio_bank[0];
185 return &gpio_bank[1 + (gpio >> 4)];
188 #ifdef CONFIG_ARCH_OMAP730
189 if (cpu_is_omap730()) {
190 if (OMAP_GPIO_IS_MPUIO(gpio))
191 return &gpio_bank[0];
192 return &gpio_bank[1 + (gpio >> 5)];
195 #ifdef CONFIG_ARCH_OMAP24XX
196 if (cpu_is_omap24xx())
197 return &gpio_bank[gpio >> 5];
201 static inline int get_gpio_index(int gpio)
203 #ifdef CONFIG_ARCH_OMAP730
204 if (cpu_is_omap730())
207 #ifdef CONFIG_ARCH_OMAP24XX
208 if (cpu_is_omap24xx())
214 static inline int gpio_valid(int gpio)
218 #ifndef CONFIG_ARCH_OMAP24XX
219 if (OMAP_GPIO_IS_MPUIO(gpio)) {
220 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
225 #ifdef CONFIG_ARCH_OMAP15XX
226 if (cpu_is_omap15xx() && gpio < 16)
229 #if defined(CONFIG_ARCH_OMAP16XX)
230 if ((cpu_is_omap16xx()) && gpio < 64)
233 #ifdef CONFIG_ARCH_OMAP730
234 if (cpu_is_omap730() && gpio < 192)
237 #ifdef CONFIG_ARCH_OMAP24XX
238 if (cpu_is_omap24xx() && gpio < 128)
244 static int check_gpio(int gpio)
246 if (unlikely(gpio_valid(gpio)) < 0) {
247 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
254 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
256 void __iomem *reg = bank->base;
259 switch (bank->method) {
261 reg += OMAP_MPUIO_IO_CNTL;
263 case METHOD_GPIO_1510:
264 reg += OMAP1510_GPIO_DIR_CONTROL;
266 case METHOD_GPIO_1610:
267 reg += OMAP1610_GPIO_DIRECTION;
269 case METHOD_GPIO_730:
270 reg += OMAP730_GPIO_DIR_CONTROL;
272 case METHOD_GPIO_24XX:
273 reg += OMAP24XX_GPIO_OE;
276 l = __raw_readl(reg);
281 __raw_writel(l, reg);
284 void omap_set_gpio_direction(int gpio, int is_input)
286 struct gpio_bank *bank;
288 if (check_gpio(gpio) < 0)
290 bank = get_gpio_bank(gpio);
291 spin_lock(&bank->lock);
292 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
293 spin_unlock(&bank->lock);
296 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
298 void __iomem *reg = bank->base;
301 switch (bank->method) {
303 reg += OMAP_MPUIO_OUTPUT;
304 l = __raw_readl(reg);
310 case METHOD_GPIO_1510:
311 reg += OMAP1510_GPIO_DATA_OUTPUT;
312 l = __raw_readl(reg);
318 case METHOD_GPIO_1610:
320 reg += OMAP1610_GPIO_SET_DATAOUT;
322 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
325 case METHOD_GPIO_730:
326 reg += OMAP730_GPIO_DATA_OUTPUT;
327 l = __raw_readl(reg);
333 case METHOD_GPIO_24XX:
335 reg += OMAP24XX_GPIO_SETDATAOUT;
337 reg += OMAP24XX_GPIO_CLEARDATAOUT;
344 __raw_writel(l, reg);
347 void omap_set_gpio_dataout(int gpio, int enable)
349 struct gpio_bank *bank;
351 if (check_gpio(gpio) < 0)
353 bank = get_gpio_bank(gpio);
354 spin_lock(&bank->lock);
355 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
356 spin_unlock(&bank->lock);
359 int omap_get_gpio_datain(int gpio)
361 struct gpio_bank *bank;
364 if (check_gpio(gpio) < 0)
366 bank = get_gpio_bank(gpio);
368 switch (bank->method) {
370 reg += OMAP_MPUIO_INPUT_LATCH;
372 case METHOD_GPIO_1510:
373 reg += OMAP1510_GPIO_DATA_INPUT;
375 case METHOD_GPIO_1610:
376 reg += OMAP1610_GPIO_DATAIN;
378 case METHOD_GPIO_730:
379 reg += OMAP730_GPIO_DATA_INPUT;
381 case METHOD_GPIO_24XX:
382 reg += OMAP24XX_GPIO_DATAIN;
388 return (__raw_readl(reg)
389 & (1 << get_gpio_index(gpio))) != 0;
392 #define MOD_REG_BIT(reg, bit_mask, set) \
394 int l = __raw_readl(base + reg); \
395 if (set) l |= bit_mask; \
396 else l &= ~bit_mask; \
397 __raw_writel(l, base + reg); \
400 static inline void set_24xx_gpio_triggering(void __iomem *base, int gpio, int trigger)
402 u32 gpio_bit = 1 << gpio;
404 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
405 trigger & __IRQT_LOWLVL);
406 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
407 trigger & __IRQT_HIGHLVL);
408 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
409 trigger & __IRQT_RISEDGE);
410 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
411 trigger & __IRQT_FALEDGE);
412 /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level
413 * triggering requested. */
416 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
418 void __iomem *reg = bank->base;
421 switch (bank->method) {
423 reg += OMAP_MPUIO_GPIO_INT_EDGE;
424 l = __raw_readl(reg);
425 if (trigger & __IRQT_RISEDGE)
427 else if (trigger & __IRQT_FALEDGE)
432 case METHOD_GPIO_1510:
433 reg += OMAP1510_GPIO_INT_CONTROL;
434 l = __raw_readl(reg);
435 if (trigger & __IRQT_RISEDGE)
437 else if (trigger & __IRQT_FALEDGE)
442 case METHOD_GPIO_1610:
444 reg += OMAP1610_GPIO_EDGE_CTRL2;
446 reg += OMAP1610_GPIO_EDGE_CTRL1;
448 /* We allow only edge triggering, i.e. two lowest bits */
449 if (trigger & (__IRQT_LOWLVL | __IRQT_HIGHLVL))
451 l = __raw_readl(reg);
452 l &= ~(3 << (gpio << 1));
453 if (trigger & __IRQT_RISEDGE)
454 l |= 2 << (gpio << 1);
455 if (trigger & __IRQT_FALEDGE)
456 l |= 1 << (gpio << 1);
458 case METHOD_GPIO_730:
459 reg += OMAP730_GPIO_INT_CONTROL;
460 l = __raw_readl(reg);
461 if (trigger & __IRQT_RISEDGE)
463 else if (trigger & __IRQT_FALEDGE)
468 case METHOD_GPIO_24XX:
469 set_24xx_gpio_triggering(reg, gpio, trigger);
475 __raw_writel(l, reg);
481 static int gpio_irq_type(unsigned irq, unsigned type)
483 struct gpio_bank *bank;
487 if (irq > IH_MPUIO_BASE)
488 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
490 gpio = irq - IH_GPIO_BASE;
492 if (check_gpio(gpio) < 0)
495 if (type & IRQT_PROBE)
497 if (!cpu_is_omap24xx() && (type & (__IRQT_LOWLVL|__IRQT_HIGHLVL)))
500 bank = get_gpio_bank(gpio);
501 spin_lock(&bank->lock);
502 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
503 spin_unlock(&bank->lock);
507 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
509 void __iomem *reg = bank->base;
511 switch (bank->method) {
513 /* MPUIO irqstatus is reset by reading the status register,
514 * so do nothing here */
516 case METHOD_GPIO_1510:
517 reg += OMAP1510_GPIO_INT_STATUS;
519 case METHOD_GPIO_1610:
520 reg += OMAP1610_GPIO_IRQSTATUS1;
522 case METHOD_GPIO_730:
523 reg += OMAP730_GPIO_INT_STATUS;
525 case METHOD_GPIO_24XX:
526 reg += OMAP24XX_GPIO_IRQSTATUS1;
532 __raw_writel(gpio_mask, reg);
534 /* Workaround for clearing DSP GPIO interrupts to allow retention */
535 if (cpu_is_omap2420())
536 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
539 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
541 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
544 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
546 void __iomem *reg = bank->base;
551 switch (bank->method) {
553 reg += OMAP_MPUIO_GPIO_MASKIT;
557 case METHOD_GPIO_1510:
558 reg += OMAP1510_GPIO_INT_MASK;
562 case METHOD_GPIO_1610:
563 reg += OMAP1610_GPIO_IRQENABLE1;
566 case METHOD_GPIO_730:
567 reg += OMAP730_GPIO_INT_MASK;
571 case METHOD_GPIO_24XX:
572 reg += OMAP24XX_GPIO_IRQENABLE1;
580 l = __raw_readl(reg);
587 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
589 void __iomem *reg = bank->base;
592 switch (bank->method) {
594 reg += OMAP_MPUIO_GPIO_MASKIT;
595 l = __raw_readl(reg);
601 case METHOD_GPIO_1510:
602 reg += OMAP1510_GPIO_INT_MASK;
603 l = __raw_readl(reg);
609 case METHOD_GPIO_1610:
611 reg += OMAP1610_GPIO_SET_IRQENABLE1;
613 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
616 case METHOD_GPIO_730:
617 reg += OMAP730_GPIO_INT_MASK;
618 l = __raw_readl(reg);
624 case METHOD_GPIO_24XX:
626 reg += OMAP24XX_GPIO_SETIRQENABLE1;
628 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
635 __raw_writel(l, reg);
638 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
640 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
644 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
645 * 1510 does not seem to have a wake-up register. If JTAG is connected
646 * to the target, system will wake up always on GPIO events. While
647 * system is running all registered GPIO interrupts need to have wake-up
648 * enabled. When system is suspended, only selected GPIO interrupts need
649 * to have wake-up enabled.
651 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
653 switch (bank->method) {
654 case METHOD_GPIO_1610:
655 case METHOD_GPIO_24XX:
656 spin_lock(&bank->lock);
658 bank->suspend_wakeup |= (1 << gpio);
660 bank->suspend_wakeup &= ~(1 << gpio);
661 spin_unlock(&bank->lock);
664 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
670 static void _reset_gpio(struct gpio_bank *bank, int gpio)
672 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
673 _set_gpio_irqenable(bank, gpio, 0);
674 _clear_gpio_irqstatus(bank, gpio);
675 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
678 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
679 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
681 unsigned int gpio = irq - IH_GPIO_BASE;
682 struct gpio_bank *bank;
685 if (check_gpio(gpio) < 0)
687 bank = get_gpio_bank(gpio);
688 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
693 int omap_request_gpio(int gpio)
695 struct gpio_bank *bank;
697 if (check_gpio(gpio) < 0)
700 bank = get_gpio_bank(gpio);
701 spin_lock(&bank->lock);
702 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
703 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
705 spin_unlock(&bank->lock);
708 bank->reserved_map |= (1 << get_gpio_index(gpio));
710 /* Set trigger to none. You need to enable the desired trigger with
711 * request_irq() or set_irq_type().
713 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
715 #ifdef CONFIG_ARCH_OMAP15XX
716 if (bank->method == METHOD_GPIO_1510) {
719 /* Claim the pin for MPU */
720 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
721 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
724 #ifdef CONFIG_ARCH_OMAP16XX
725 if (bank->method == METHOD_GPIO_1610) {
726 /* Enable wake-up during idle for dynamic tick */
727 void __iomem *reg = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
728 __raw_writel(1 << get_gpio_index(gpio), reg);
731 #ifdef CONFIG_ARCH_OMAP24XX
732 if (bank->method == METHOD_GPIO_24XX) {
733 /* Enable wake-up during idle for dynamic tick */
734 void __iomem *reg = bank->base + OMAP24XX_GPIO_SETWKUENA;
735 __raw_writel(1 << get_gpio_index(gpio), reg);
738 spin_unlock(&bank->lock);
743 void omap_free_gpio(int gpio)
745 struct gpio_bank *bank;
747 if (check_gpio(gpio) < 0)
749 bank = get_gpio_bank(gpio);
750 spin_lock(&bank->lock);
751 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
752 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
754 spin_unlock(&bank->lock);
757 #ifdef CONFIG_ARCH_OMAP16XX
758 if (bank->method == METHOD_GPIO_1610) {
759 /* Disable wake-up during idle for dynamic tick */
760 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
761 __raw_writel(1 << get_gpio_index(gpio), reg);
764 #ifdef CONFIG_ARCH_OMAP24XX
765 if (bank->method == METHOD_GPIO_24XX) {
766 /* Disable wake-up during idle for dynamic tick */
767 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
768 __raw_writel(1 << get_gpio_index(gpio), reg);
771 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
772 _reset_gpio(bank, gpio);
773 spin_unlock(&bank->lock);
777 * We need to unmask the GPIO bank interrupt as soon as possible to
778 * avoid missing GPIO interrupts for other lines in the bank.
779 * Then we need to mask-read-clear-unmask the triggered GPIO lines
780 * in the bank to avoid missing nested interrupts for a GPIO line.
781 * If we wait to unmask individual GPIO lines in the bank after the
782 * line's interrupt handler has been run, we may miss some nested
785 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
787 void __iomem *isr_reg = NULL;
789 unsigned int gpio_irq;
790 struct gpio_bank *bank;
794 desc->chip->ack(irq);
796 bank = get_irq_data(irq);
797 if (bank->method == METHOD_MPUIO)
798 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
799 #ifdef CONFIG_ARCH_OMAP15XX
800 if (bank->method == METHOD_GPIO_1510)
801 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
803 #if defined(CONFIG_ARCH_OMAP16XX)
804 if (bank->method == METHOD_GPIO_1610)
805 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
807 #ifdef CONFIG_ARCH_OMAP730
808 if (bank->method == METHOD_GPIO_730)
809 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
811 #ifdef CONFIG_ARCH_OMAP24XX
812 if (bank->method == METHOD_GPIO_24XX)
813 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
816 u32 isr_saved, level_mask = 0;
819 enabled = _get_gpio_irqbank_mask(bank);
820 isr_saved = isr = __raw_readl(isr_reg) & enabled;
822 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
825 if (cpu_is_omap24xx()) {
827 __raw_readl(bank->base +
828 OMAP24XX_GPIO_LEVELDETECT0) |
829 __raw_readl(bank->base +
830 OMAP24XX_GPIO_LEVELDETECT1);
831 level_mask &= enabled;
834 /* clear edge sensitive interrupts before handler(s) are
835 called so that we don't miss any interrupt occurred while
837 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
838 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
839 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
841 /* if there is only edge sensitive GPIO pin interrupts
842 configured, we could unmask GPIO bank interrupt immediately */
843 if (!level_mask && !unmasked) {
845 desc->chip->unmask(irq);
853 gpio_irq = bank->virtual_irq_start;
854 for (; isr != 0; isr >>= 1, gpio_irq++) {
859 d = irq_desc + gpio_irq;
860 /* Don't run the handler if it's already running
861 * or was disabled lazely.
863 if (unlikely((d->depth ||
864 (d->status & IRQ_INPROGRESS)))) {
866 (gpio_irq - bank->virtual_irq_start);
867 /* The unmasking will be done by
868 * enable_irq in case it is disabled or
869 * after returning from the handler if
870 * it's already running.
872 _enable_gpio_irqbank(bank, irq_mask, 0);
874 /* Level triggered interrupts
875 * won't ever be reentered
877 BUG_ON(level_mask & irq_mask);
878 d->status |= IRQ_PENDING;
883 desc_handle_irq(gpio_irq, d);
885 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
887 (gpio_irq - bank->virtual_irq_start);
888 d->status &= ~IRQ_PENDING;
889 _enable_gpio_irqbank(bank, irq_mask, 1);
890 retrigger |= irq_mask;
894 if (cpu_is_omap24xx()) {
895 /* clear level sensitive interrupts after handler(s) */
896 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
897 _clear_gpio_irqbank(bank, isr_saved & level_mask);
898 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
902 /* if bank has any level sensitive GPIO pin interrupt
903 configured, we must unmask the bank interrupt only after
904 handler(s) are executed in order to avoid spurious bank
907 desc->chip->unmask(irq);
911 static void gpio_irq_shutdown(unsigned int irq)
913 unsigned int gpio = irq - IH_GPIO_BASE;
914 struct gpio_bank *bank = get_gpio_bank(gpio);
916 _reset_gpio(bank, gpio);
919 static void gpio_ack_irq(unsigned int irq)
921 unsigned int gpio = irq - IH_GPIO_BASE;
922 struct gpio_bank *bank = get_gpio_bank(gpio);
924 _clear_gpio_irqstatus(bank, gpio);
927 static void gpio_mask_irq(unsigned int irq)
929 unsigned int gpio = irq - IH_GPIO_BASE;
930 struct gpio_bank *bank = get_gpio_bank(gpio);
932 _set_gpio_irqenable(bank, gpio, 0);
935 static void gpio_unmask_irq(unsigned int irq)
937 unsigned int gpio = irq - IH_GPIO_BASE;
938 unsigned int gpio_idx = get_gpio_index(gpio);
939 struct gpio_bank *bank = get_gpio_bank(gpio);
941 _set_gpio_irqenable(bank, gpio_idx, 1);
944 static void mpuio_ack_irq(unsigned int irq)
946 /* The ISR is reset automatically, so do nothing here. */
949 static void mpuio_mask_irq(unsigned int irq)
951 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
952 struct gpio_bank *bank = get_gpio_bank(gpio);
954 _set_gpio_irqenable(bank, gpio, 0);
957 static void mpuio_unmask_irq(unsigned int irq)
959 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
960 struct gpio_bank *bank = get_gpio_bank(gpio);
962 _set_gpio_irqenable(bank, gpio, 1);
965 static struct irq_chip gpio_irq_chip = {
967 .shutdown = gpio_irq_shutdown,
969 .mask = gpio_mask_irq,
970 .unmask = gpio_unmask_irq,
971 .set_type = gpio_irq_type,
972 .set_wake = gpio_wake_enable,
975 static struct irq_chip mpuio_irq_chip = {
977 .ack = mpuio_ack_irq,
978 .mask = mpuio_mask_irq,
979 .unmask = mpuio_unmask_irq,
980 .set_type = gpio_irq_type,
983 static int initialized;
984 static struct clk * gpio_ick;
985 static struct clk * gpio_fck;
987 static int __init _omap_gpio_init(void)
990 struct gpio_bank *bank;
994 if (cpu_is_omap15xx()) {
995 gpio_ick = clk_get(NULL, "arm_gpio_ck");
996 if (IS_ERR(gpio_ick))
997 printk("Could not get arm_gpio_ck\n");
999 clk_enable(gpio_ick);
1001 if (cpu_is_omap24xx()) {
1002 gpio_ick = clk_get(NULL, "gpios_ick");
1003 if (IS_ERR(gpio_ick))
1004 printk("Could not get gpios_ick\n");
1006 clk_enable(gpio_ick);
1007 gpio_fck = clk_get(NULL, "gpios_fck");
1008 if (IS_ERR(gpio_fck))
1009 printk("Could not get gpios_fck\n");
1011 clk_enable(gpio_fck);
1014 #ifdef CONFIG_ARCH_OMAP15XX
1015 if (cpu_is_omap15xx()) {
1016 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1017 gpio_bank_count = 2;
1018 gpio_bank = gpio_bank_1510;
1021 #if defined(CONFIG_ARCH_OMAP16XX)
1022 if (cpu_is_omap16xx()) {
1025 gpio_bank_count = 5;
1026 gpio_bank = gpio_bank_1610;
1027 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1028 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1029 (rev >> 4) & 0x0f, rev & 0x0f);
1032 #ifdef CONFIG_ARCH_OMAP730
1033 if (cpu_is_omap730()) {
1034 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1035 gpio_bank_count = 7;
1036 gpio_bank = gpio_bank_730;
1039 #ifdef CONFIG_ARCH_OMAP24XX
1040 if (cpu_is_omap24xx()) {
1043 gpio_bank_count = 4;
1044 gpio_bank = gpio_bank_24xx;
1045 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1046 printk(KERN_INFO "OMAP24xx GPIO hardware version %d.%d\n",
1047 (rev >> 4) & 0x0f, rev & 0x0f);
1050 for (i = 0; i < gpio_bank_count; i++) {
1051 int j, gpio_count = 16;
1053 bank = &gpio_bank[i];
1054 bank->reserved_map = 0;
1055 bank->base = IO_ADDRESS(bank->base);
1056 spin_lock_init(&bank->lock);
1057 if (bank->method == METHOD_MPUIO) {
1058 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1060 #ifdef CONFIG_ARCH_OMAP15XX
1061 if (bank->method == METHOD_GPIO_1510) {
1062 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1063 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1066 #if defined(CONFIG_ARCH_OMAP16XX)
1067 if (bank->method == METHOD_GPIO_1610) {
1068 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1069 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1070 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1073 #ifdef CONFIG_ARCH_OMAP730
1074 if (bank->method == METHOD_GPIO_730) {
1075 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1076 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1078 gpio_count = 32; /* 730 has 32-bit GPIOs */
1081 #ifdef CONFIG_ARCH_OMAP24XX
1082 if (bank->method == METHOD_GPIO_24XX) {
1083 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1084 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1089 for (j = bank->virtual_irq_start;
1090 j < bank->virtual_irq_start + gpio_count; j++) {
1091 if (bank->method == METHOD_MPUIO)
1092 set_irq_chip(j, &mpuio_irq_chip);
1094 set_irq_chip(j, &gpio_irq_chip);
1095 set_irq_handler(j, handle_simple_irq);
1096 set_irq_flags(j, IRQF_VALID);
1098 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1099 set_irq_data(bank->irq, bank);
1102 /* Enable system clock for GPIO module.
1103 * The CAM_CLK_CTRL *is* really the right place. */
1104 if (cpu_is_omap16xx())
1105 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1110 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
1111 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1115 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1118 for (i = 0; i < gpio_bank_count; i++) {
1119 struct gpio_bank *bank = &gpio_bank[i];
1120 void __iomem *wake_status;
1121 void __iomem *wake_clear;
1122 void __iomem *wake_set;
1124 switch (bank->method) {
1125 case METHOD_GPIO_1610:
1126 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1127 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1128 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1130 case METHOD_GPIO_24XX:
1131 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1132 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1133 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1139 spin_lock(&bank->lock);
1140 bank->saved_wakeup = __raw_readl(wake_status);
1141 __raw_writel(0xffffffff, wake_clear);
1142 __raw_writel(bank->suspend_wakeup, wake_set);
1143 spin_unlock(&bank->lock);
1149 static int omap_gpio_resume(struct sys_device *dev)
1153 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1156 for (i = 0; i < gpio_bank_count; i++) {
1157 struct gpio_bank *bank = &gpio_bank[i];
1158 void __iomem *wake_clear;
1159 void __iomem *wake_set;
1161 switch (bank->method) {
1162 case METHOD_GPIO_1610:
1163 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1164 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1166 case METHOD_GPIO_24XX:
1167 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1168 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1174 spin_lock(&bank->lock);
1175 __raw_writel(0xffffffff, wake_clear);
1176 __raw_writel(bank->saved_wakeup, wake_set);
1177 spin_unlock(&bank->lock);
1183 static struct sysdev_class omap_gpio_sysclass = {
1184 set_kset_name("gpio"),
1185 .suspend = omap_gpio_suspend,
1186 .resume = omap_gpio_resume,
1189 static struct sys_device omap_gpio_device = {
1191 .cls = &omap_gpio_sysclass,
1196 * This may get called early from board specific init
1197 * for boards that have interrupts routed via FPGA.
1199 int omap_gpio_init(void)
1202 return _omap_gpio_init();
1207 static int __init omap_gpio_sysinit(void)
1212 ret = _omap_gpio_init();
1214 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX)
1215 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
1217 ret = sysdev_class_register(&omap_gpio_sysclass);
1219 ret = sysdev_register(&omap_gpio_device);
1227 EXPORT_SYMBOL(omap_request_gpio);
1228 EXPORT_SYMBOL(omap_free_gpio);
1229 EXPORT_SYMBOL(omap_set_gpio_direction);
1230 EXPORT_SYMBOL(omap_set_gpio_dataout);
1231 EXPORT_SYMBOL(omap_get_gpio_datain);
1233 arch_initcall(omap_gpio_sysinit);