2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/sysdev.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
22 #include <mach/hardware.h>
24 #include <mach/irqs.h>
25 #include <mach/gpio.h>
26 #include <asm/mach/irq.h>
29 * OMAP1510 GPIO registers
31 #define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
32 #define OMAP1510_GPIO_DATA_INPUT 0x00
33 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
34 #define OMAP1510_GPIO_DIR_CONTROL 0x08
35 #define OMAP1510_GPIO_INT_CONTROL 0x0c
36 #define OMAP1510_GPIO_INT_MASK 0x10
37 #define OMAP1510_GPIO_INT_STATUS 0x14
38 #define OMAP1510_GPIO_PIN_CONTROL 0x18
40 #define OMAP1510_IH_GPIO_BASE 64
43 * OMAP1610 specific GPIO registers
45 #define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
46 #define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
47 #define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
48 #define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
49 #define OMAP1610_GPIO_REVISION 0x0000
50 #define OMAP1610_GPIO_SYSCONFIG 0x0010
51 #define OMAP1610_GPIO_SYSSTATUS 0x0014
52 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
53 #define OMAP1610_GPIO_IRQENABLE1 0x001c
54 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
55 #define OMAP1610_GPIO_DATAIN 0x002c
56 #define OMAP1610_GPIO_DATAOUT 0x0030
57 #define OMAP1610_GPIO_DIRECTION 0x0034
58 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
59 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
60 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
61 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
62 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
63 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
64 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
65 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
68 * OMAP730 specific GPIO registers
70 #define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
71 #define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
72 #define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
73 #define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
74 #define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
75 #define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
76 #define OMAP730_GPIO_DATA_INPUT 0x00
77 #define OMAP730_GPIO_DATA_OUTPUT 0x04
78 #define OMAP730_GPIO_DIR_CONTROL 0x08
79 #define OMAP730_GPIO_INT_CONTROL 0x0c
80 #define OMAP730_GPIO_INT_MASK 0x10
81 #define OMAP730_GPIO_INT_STATUS 0x14
84 * omap24xx specific GPIO registers
86 #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
87 #define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
88 #define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
89 #define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
91 #define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
92 #define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
93 #define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
94 #define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
95 #define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
97 #define OMAP24XX_GPIO_REVISION 0x0000
98 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
99 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
100 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
101 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
102 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
103 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
104 #define OMAP24XX_GPIO_WAKE_EN 0x0020
105 #define OMAP24XX_GPIO_CTRL 0x0030
106 #define OMAP24XX_GPIO_OE 0x0034
107 #define OMAP24XX_GPIO_DATAIN 0x0038
108 #define OMAP24XX_GPIO_DATAOUT 0x003c
109 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
110 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
111 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
112 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
113 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
114 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
115 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
116 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
117 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
118 #define OMAP24XX_GPIO_SETWKUENA 0x0084
119 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
120 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
123 * omap34xx specific GPIO registers
126 #define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
127 #define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
128 #define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
129 #define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
130 #define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
131 #define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
133 #define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
138 u16 virtual_irq_start;
140 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
144 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
145 u32 non_wakeup_gpios;
146 u32 enabled_non_wakeup_gpios;
149 u32 saved_fallingdetect;
150 u32 saved_risingdetect;
154 struct gpio_chip chip;
158 #define METHOD_MPUIO 0
159 #define METHOD_GPIO_1510 1
160 #define METHOD_GPIO_1610 2
161 #define METHOD_GPIO_730 3
162 #define METHOD_GPIO_24XX 4
164 #ifdef CONFIG_ARCH_OMAP16XX
165 static struct gpio_bank gpio_bank_1610[5] = {
166 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
167 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
168 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
169 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
170 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
174 #ifdef CONFIG_ARCH_OMAP15XX
175 static struct gpio_bank gpio_bank_1510[2] = {
176 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
177 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
181 #ifdef CONFIG_ARCH_OMAP730
182 static struct gpio_bank gpio_bank_730[7] = {
183 { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
184 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
185 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
186 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
187 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
188 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
189 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
193 #ifdef CONFIG_ARCH_OMAP24XX
195 static struct gpio_bank gpio_bank_242x[4] = {
196 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
197 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
198 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
199 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
202 static struct gpio_bank gpio_bank_243x[5] = {
203 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
204 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
205 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
206 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
207 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
212 #ifdef CONFIG_ARCH_OMAP34XX
213 static struct gpio_bank gpio_bank_34xx[6] = {
214 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
217 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
218 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
219 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
224 static struct gpio_bank *gpio_bank;
225 static int gpio_bank_count;
227 static inline struct gpio_bank *get_gpio_bank(int gpio)
229 if (cpu_is_omap15xx()) {
230 if (OMAP_GPIO_IS_MPUIO(gpio))
231 return &gpio_bank[0];
232 return &gpio_bank[1];
234 if (cpu_is_omap16xx()) {
235 if (OMAP_GPIO_IS_MPUIO(gpio))
236 return &gpio_bank[0];
237 return &gpio_bank[1 + (gpio >> 4)];
239 if (cpu_is_omap730()) {
240 if (OMAP_GPIO_IS_MPUIO(gpio))
241 return &gpio_bank[0];
242 return &gpio_bank[1 + (gpio >> 5)];
244 if (cpu_is_omap24xx())
245 return &gpio_bank[gpio >> 5];
246 if (cpu_is_omap34xx())
247 return &gpio_bank[gpio >> 5];
252 static inline int get_gpio_index(int gpio)
254 if (cpu_is_omap730())
256 if (cpu_is_omap24xx())
258 if (cpu_is_omap34xx())
263 static inline int gpio_valid(int gpio)
267 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
268 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
272 if (cpu_is_omap15xx() && gpio < 16)
274 if ((cpu_is_omap16xx()) && gpio < 64)
276 if (cpu_is_omap730() && gpio < 192)
278 if (cpu_is_omap24xx() && gpio < 128)
280 if (cpu_is_omap34xx() && gpio < 160)
285 static int check_gpio(int gpio)
287 if (unlikely(gpio_valid(gpio)) < 0) {
288 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
295 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
297 void __iomem *reg = bank->base;
300 switch (bank->method) {
301 #ifdef CONFIG_ARCH_OMAP1
303 reg += OMAP_MPUIO_IO_CNTL;
306 #ifdef CONFIG_ARCH_OMAP15XX
307 case METHOD_GPIO_1510:
308 reg += OMAP1510_GPIO_DIR_CONTROL;
311 #ifdef CONFIG_ARCH_OMAP16XX
312 case METHOD_GPIO_1610:
313 reg += OMAP1610_GPIO_DIRECTION;
316 #ifdef CONFIG_ARCH_OMAP730
317 case METHOD_GPIO_730:
318 reg += OMAP730_GPIO_DIR_CONTROL;
321 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
322 case METHOD_GPIO_24XX:
323 reg += OMAP24XX_GPIO_OE;
330 l = __raw_readl(reg);
335 __raw_writel(l, reg);
338 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
340 void __iomem *reg = bank->base;
343 switch (bank->method) {
344 #ifdef CONFIG_ARCH_OMAP1
346 reg += OMAP_MPUIO_OUTPUT;
347 l = __raw_readl(reg);
354 #ifdef CONFIG_ARCH_OMAP15XX
355 case METHOD_GPIO_1510:
356 reg += OMAP1510_GPIO_DATA_OUTPUT;
357 l = __raw_readl(reg);
364 #ifdef CONFIG_ARCH_OMAP16XX
365 case METHOD_GPIO_1610:
367 reg += OMAP1610_GPIO_SET_DATAOUT;
369 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
373 #ifdef CONFIG_ARCH_OMAP730
374 case METHOD_GPIO_730:
375 reg += OMAP730_GPIO_DATA_OUTPUT;
376 l = __raw_readl(reg);
383 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
384 case METHOD_GPIO_24XX:
386 reg += OMAP24XX_GPIO_SETDATAOUT;
388 reg += OMAP24XX_GPIO_CLEARDATAOUT;
396 __raw_writel(l, reg);
399 static int __omap_get_gpio_datain(int gpio)
401 struct gpio_bank *bank;
404 if (check_gpio(gpio) < 0)
406 bank = get_gpio_bank(gpio);
408 switch (bank->method) {
409 #ifdef CONFIG_ARCH_OMAP1
411 reg += OMAP_MPUIO_INPUT_LATCH;
414 #ifdef CONFIG_ARCH_OMAP15XX
415 case METHOD_GPIO_1510:
416 reg += OMAP1510_GPIO_DATA_INPUT;
419 #ifdef CONFIG_ARCH_OMAP16XX
420 case METHOD_GPIO_1610:
421 reg += OMAP1610_GPIO_DATAIN;
424 #ifdef CONFIG_ARCH_OMAP730
425 case METHOD_GPIO_730:
426 reg += OMAP730_GPIO_DATA_INPUT;
429 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
430 case METHOD_GPIO_24XX:
431 reg += OMAP24XX_GPIO_DATAIN;
437 return (__raw_readl(reg)
438 & (1 << get_gpio_index(gpio))) != 0;
441 #define MOD_REG_BIT(reg, bit_mask, set) \
443 int l = __raw_readl(base + reg); \
444 if (set) l |= bit_mask; \
445 else l &= ~bit_mask; \
446 __raw_writel(l, base + reg); \
449 void omap_set_gpio_debounce(int gpio, int enable)
451 struct gpio_bank *bank;
454 u32 val, l = 1 << get_gpio_index(gpio);
456 if (cpu_class_is_omap1())
459 bank = get_gpio_bank(gpio);
461 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
463 spin_lock_irqsave(&bank->lock, flags);
464 val = __raw_readl(reg);
466 if (enable && !(val & l))
468 else if (!enable && (val & l))
473 if (cpu_is_omap34xx()) {
475 clk_enable(bank->dbck);
477 clk_disable(bank->dbck);
480 __raw_writel(val, reg);
482 spin_unlock_irqrestore(&bank->lock, flags);
484 EXPORT_SYMBOL(omap_set_gpio_debounce);
486 void omap_set_gpio_debounce_time(int gpio, int enc_time)
488 struct gpio_bank *bank;
491 if (cpu_class_is_omap1())
494 bank = get_gpio_bank(gpio);
498 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
499 __raw_writel(enc_time, reg);
501 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
503 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
504 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
507 void __iomem *base = bank->base;
508 u32 gpio_bit = 1 << gpio;
510 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
511 trigger & IRQ_TYPE_LEVEL_LOW);
512 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
513 trigger & IRQ_TYPE_LEVEL_HIGH);
514 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
515 trigger & IRQ_TYPE_EDGE_RISING);
516 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
517 trigger & IRQ_TYPE_EDGE_FALLING);
519 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
521 __raw_writel(1 << gpio, bank->base
522 + OMAP24XX_GPIO_SETWKUENA);
524 __raw_writel(1 << gpio, bank->base
525 + OMAP24XX_GPIO_CLEARWKUENA);
528 bank->enabled_non_wakeup_gpios |= gpio_bit;
530 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
534 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
535 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
539 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
541 void __iomem *reg = bank->base;
544 switch (bank->method) {
545 #ifdef CONFIG_ARCH_OMAP1
547 reg += OMAP_MPUIO_GPIO_INT_EDGE;
548 l = __raw_readl(reg);
549 if (trigger & IRQ_TYPE_EDGE_RISING)
551 else if (trigger & IRQ_TYPE_EDGE_FALLING)
557 #ifdef CONFIG_ARCH_OMAP15XX
558 case METHOD_GPIO_1510:
559 reg += OMAP1510_GPIO_INT_CONTROL;
560 l = __raw_readl(reg);
561 if (trigger & IRQ_TYPE_EDGE_RISING)
563 else if (trigger & IRQ_TYPE_EDGE_FALLING)
569 #ifdef CONFIG_ARCH_OMAP16XX
570 case METHOD_GPIO_1610:
572 reg += OMAP1610_GPIO_EDGE_CTRL2;
574 reg += OMAP1610_GPIO_EDGE_CTRL1;
576 l = __raw_readl(reg);
577 l &= ~(3 << (gpio << 1));
578 if (trigger & IRQ_TYPE_EDGE_RISING)
579 l |= 2 << (gpio << 1);
580 if (trigger & IRQ_TYPE_EDGE_FALLING)
581 l |= 1 << (gpio << 1);
583 /* Enable wake-up during idle for dynamic tick */
584 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
586 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
589 #ifdef CONFIG_ARCH_OMAP730
590 case METHOD_GPIO_730:
591 reg += OMAP730_GPIO_INT_CONTROL;
592 l = __raw_readl(reg);
593 if (trigger & IRQ_TYPE_EDGE_RISING)
595 else if (trigger & IRQ_TYPE_EDGE_FALLING)
601 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
602 case METHOD_GPIO_24XX:
603 set_24xx_gpio_triggering(bank, gpio, trigger);
609 __raw_writel(l, reg);
615 static int gpio_irq_type(unsigned irq, unsigned type)
617 struct gpio_bank *bank;
622 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
623 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
625 gpio = irq - IH_GPIO_BASE;
627 if (check_gpio(gpio) < 0)
630 if (type & ~IRQ_TYPE_SENSE_MASK)
633 /* OMAP1 allows only only edge triggering */
634 if (!cpu_class_is_omap2()
635 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
638 bank = get_irq_chip_data(irq);
639 spin_lock_irqsave(&bank->lock, flags);
640 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
642 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
643 irq_desc[irq].status |= type;
645 spin_unlock_irqrestore(&bank->lock, flags);
647 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
648 __set_irq_handler_unlocked(irq, handle_level_irq);
649 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
650 __set_irq_handler_unlocked(irq, handle_edge_irq);
655 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
657 void __iomem *reg = bank->base;
659 switch (bank->method) {
660 #ifdef CONFIG_ARCH_OMAP1
662 /* MPUIO irqstatus is reset by reading the status register,
663 * so do nothing here */
666 #ifdef CONFIG_ARCH_OMAP15XX
667 case METHOD_GPIO_1510:
668 reg += OMAP1510_GPIO_INT_STATUS;
671 #ifdef CONFIG_ARCH_OMAP16XX
672 case METHOD_GPIO_1610:
673 reg += OMAP1610_GPIO_IRQSTATUS1;
676 #ifdef CONFIG_ARCH_OMAP730
677 case METHOD_GPIO_730:
678 reg += OMAP730_GPIO_INT_STATUS;
681 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
682 case METHOD_GPIO_24XX:
683 reg += OMAP24XX_GPIO_IRQSTATUS1;
690 __raw_writel(gpio_mask, reg);
692 /* Workaround for clearing DSP GPIO interrupts to allow retention */
693 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
694 if (cpu_is_omap24xx() || cpu_is_omap34xx())
695 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
699 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
701 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
704 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
706 void __iomem *reg = bank->base;
711 switch (bank->method) {
712 #ifdef CONFIG_ARCH_OMAP1
714 reg += OMAP_MPUIO_GPIO_MASKIT;
719 #ifdef CONFIG_ARCH_OMAP15XX
720 case METHOD_GPIO_1510:
721 reg += OMAP1510_GPIO_INT_MASK;
726 #ifdef CONFIG_ARCH_OMAP16XX
727 case METHOD_GPIO_1610:
728 reg += OMAP1610_GPIO_IRQENABLE1;
732 #ifdef CONFIG_ARCH_OMAP730
733 case METHOD_GPIO_730:
734 reg += OMAP730_GPIO_INT_MASK;
739 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
740 case METHOD_GPIO_24XX:
741 reg += OMAP24XX_GPIO_IRQENABLE1;
750 l = __raw_readl(reg);
757 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
759 void __iomem *reg = bank->base;
762 switch (bank->method) {
763 #ifdef CONFIG_ARCH_OMAP1
765 reg += OMAP_MPUIO_GPIO_MASKIT;
766 l = __raw_readl(reg);
773 #ifdef CONFIG_ARCH_OMAP15XX
774 case METHOD_GPIO_1510:
775 reg += OMAP1510_GPIO_INT_MASK;
776 l = __raw_readl(reg);
783 #ifdef CONFIG_ARCH_OMAP16XX
784 case METHOD_GPIO_1610:
786 reg += OMAP1610_GPIO_SET_IRQENABLE1;
788 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
792 #ifdef CONFIG_ARCH_OMAP730
793 case METHOD_GPIO_730:
794 reg += OMAP730_GPIO_INT_MASK;
795 l = __raw_readl(reg);
802 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
803 case METHOD_GPIO_24XX:
805 reg += OMAP24XX_GPIO_SETIRQENABLE1;
807 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
815 __raw_writel(l, reg);
818 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
820 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
824 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
825 * 1510 does not seem to have a wake-up register. If JTAG is connected
826 * to the target, system will wake up always on GPIO events. While
827 * system is running all registered GPIO interrupts need to have wake-up
828 * enabled. When system is suspended, only selected GPIO interrupts need
829 * to have wake-up enabled.
831 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
835 switch (bank->method) {
836 #ifdef CONFIG_ARCH_OMAP16XX
838 case METHOD_GPIO_1610:
839 spin_lock_irqsave(&bank->lock, flags);
841 bank->suspend_wakeup |= (1 << gpio);
843 bank->suspend_wakeup &= ~(1 << gpio);
844 spin_unlock_irqrestore(&bank->lock, flags);
847 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
848 case METHOD_GPIO_24XX:
849 if (bank->non_wakeup_gpios & (1 << gpio)) {
850 printk(KERN_ERR "Unable to modify wakeup on "
851 "non-wakeup GPIO%d\n",
852 (bank - gpio_bank) * 32 + gpio);
855 spin_lock_irqsave(&bank->lock, flags);
857 bank->suspend_wakeup |= (1 << gpio);
859 bank->suspend_wakeup &= ~(1 << gpio);
860 spin_unlock_irqrestore(&bank->lock, flags);
864 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
870 static void _reset_gpio(struct gpio_bank *bank, int gpio)
872 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
873 _set_gpio_irqenable(bank, gpio, 0);
874 _clear_gpio_irqstatus(bank, gpio);
875 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
878 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
879 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
881 unsigned int gpio = irq - IH_GPIO_BASE;
882 struct gpio_bank *bank;
885 if (check_gpio(gpio) < 0)
887 bank = get_irq_chip_data(irq);
888 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
893 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
895 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
898 spin_lock_irqsave(&bank->lock, flags);
900 /* Set trigger to none. You need to enable the desired trigger with
901 * request_irq() or set_irq_type().
903 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
905 #ifdef CONFIG_ARCH_OMAP15XX
906 if (bank->method == METHOD_GPIO_1510) {
909 /* Claim the pin for MPU */
910 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
911 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
914 spin_unlock_irqrestore(&bank->lock, flags);
919 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
921 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
924 spin_lock_irqsave(&bank->lock, flags);
925 #ifdef CONFIG_ARCH_OMAP16XX
926 if (bank->method == METHOD_GPIO_1610) {
927 /* Disable wake-up during idle for dynamic tick */
928 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
929 __raw_writel(1 << offset, reg);
932 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
933 if (bank->method == METHOD_GPIO_24XX) {
934 /* Disable wake-up during idle for dynamic tick */
935 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
936 __raw_writel(1 << offset, reg);
939 _reset_gpio(bank, bank->chip.base + offset);
940 spin_unlock_irqrestore(&bank->lock, flags);
944 * We need to unmask the GPIO bank interrupt as soon as possible to
945 * avoid missing GPIO interrupts for other lines in the bank.
946 * Then we need to mask-read-clear-unmask the triggered GPIO lines
947 * in the bank to avoid missing nested interrupts for a GPIO line.
948 * If we wait to unmask individual GPIO lines in the bank after the
949 * line's interrupt handler has been run, we may miss some nested
952 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
954 void __iomem *isr_reg = NULL;
956 unsigned int gpio_irq;
957 struct gpio_bank *bank;
961 desc->chip->ack(irq);
963 bank = get_irq_data(irq);
964 #ifdef CONFIG_ARCH_OMAP1
965 if (bank->method == METHOD_MPUIO)
966 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
968 #ifdef CONFIG_ARCH_OMAP15XX
969 if (bank->method == METHOD_GPIO_1510)
970 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
972 #if defined(CONFIG_ARCH_OMAP16XX)
973 if (bank->method == METHOD_GPIO_1610)
974 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
976 #ifdef CONFIG_ARCH_OMAP730
977 if (bank->method == METHOD_GPIO_730)
978 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
980 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
981 if (bank->method == METHOD_GPIO_24XX)
982 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
985 u32 isr_saved, level_mask = 0;
988 enabled = _get_gpio_irqbank_mask(bank);
989 isr_saved = isr = __raw_readl(isr_reg) & enabled;
991 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
994 if (cpu_class_is_omap2()) {
995 level_mask = bank->level_mask & enabled;
998 /* clear edge sensitive interrupts before handler(s) are
999 called so that we don't miss any interrupt occurred while
1001 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1002 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1003 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1005 /* if there is only edge sensitive GPIO pin interrupts
1006 configured, we could unmask GPIO bank interrupt immediately */
1007 if (!level_mask && !unmasked) {
1009 desc->chip->unmask(irq);
1017 gpio_irq = bank->virtual_irq_start;
1018 for (; isr != 0; isr >>= 1, gpio_irq++) {
1022 generic_handle_irq(gpio_irq);
1025 /* if bank has any level sensitive GPIO pin interrupt
1026 configured, we must unmask the bank interrupt only after
1027 handler(s) are executed in order to avoid spurious bank
1030 desc->chip->unmask(irq);
1034 static void gpio_irq_shutdown(unsigned int irq)
1036 unsigned int gpio = irq - IH_GPIO_BASE;
1037 struct gpio_bank *bank = get_irq_chip_data(irq);
1039 _reset_gpio(bank, gpio);
1042 static void gpio_ack_irq(unsigned int irq)
1044 unsigned int gpio = irq - IH_GPIO_BASE;
1045 struct gpio_bank *bank = get_irq_chip_data(irq);
1047 _clear_gpio_irqstatus(bank, gpio);
1050 static void gpio_mask_irq(unsigned int irq)
1052 unsigned int gpio = irq - IH_GPIO_BASE;
1053 struct gpio_bank *bank = get_irq_chip_data(irq);
1055 _set_gpio_irqenable(bank, gpio, 0);
1058 static void gpio_unmask_irq(unsigned int irq)
1060 unsigned int gpio = irq - IH_GPIO_BASE;
1061 struct gpio_bank *bank = get_irq_chip_data(irq);
1062 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1064 /* For level-triggered GPIOs, the clearing must be done after
1065 * the HW source is cleared, thus after the handler has run */
1066 if (bank->level_mask & irq_mask) {
1067 _set_gpio_irqenable(bank, gpio, 0);
1068 _clear_gpio_irqstatus(bank, gpio);
1071 _set_gpio_irqenable(bank, gpio, 1);
1074 static struct irq_chip gpio_irq_chip = {
1076 .shutdown = gpio_irq_shutdown,
1077 .ack = gpio_ack_irq,
1078 .mask = gpio_mask_irq,
1079 .unmask = gpio_unmask_irq,
1080 .set_type = gpio_irq_type,
1081 .set_wake = gpio_wake_enable,
1084 /*---------------------------------------------------------------------*/
1086 #ifdef CONFIG_ARCH_OMAP1
1088 /* MPUIO uses the always-on 32k clock */
1090 static void mpuio_ack_irq(unsigned int irq)
1092 /* The ISR is reset automatically, so do nothing here. */
1095 static void mpuio_mask_irq(unsigned int irq)
1097 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1098 struct gpio_bank *bank = get_irq_chip_data(irq);
1100 _set_gpio_irqenable(bank, gpio, 0);
1103 static void mpuio_unmask_irq(unsigned int irq)
1105 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1106 struct gpio_bank *bank = get_irq_chip_data(irq);
1108 _set_gpio_irqenable(bank, gpio, 1);
1111 static struct irq_chip mpuio_irq_chip = {
1113 .ack = mpuio_ack_irq,
1114 .mask = mpuio_mask_irq,
1115 .unmask = mpuio_unmask_irq,
1116 .set_type = gpio_irq_type,
1117 #ifdef CONFIG_ARCH_OMAP16XX
1118 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1119 .set_wake = gpio_wake_enable,
1124 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1127 #ifdef CONFIG_ARCH_OMAP16XX
1129 #include <linux/platform_device.h>
1131 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1133 struct gpio_bank *bank = platform_get_drvdata(pdev);
1134 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1135 unsigned long flags;
1137 spin_lock_irqsave(&bank->lock, flags);
1138 bank->saved_wakeup = __raw_readl(mask_reg);
1139 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1140 spin_unlock_irqrestore(&bank->lock, flags);
1145 static int omap_mpuio_resume_early(struct platform_device *pdev)
1147 struct gpio_bank *bank = platform_get_drvdata(pdev);
1148 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1149 unsigned long flags;
1151 spin_lock_irqsave(&bank->lock, flags);
1152 __raw_writel(bank->saved_wakeup, mask_reg);
1153 spin_unlock_irqrestore(&bank->lock, flags);
1158 /* use platform_driver for this, now that there's no longer any
1159 * point to sys_device (other than not disturbing old code).
1161 static struct platform_driver omap_mpuio_driver = {
1162 .suspend_late = omap_mpuio_suspend_late,
1163 .resume_early = omap_mpuio_resume_early,
1169 static struct platform_device omap_mpuio_device = {
1173 .driver = &omap_mpuio_driver.driver,
1175 /* could list the /proc/iomem resources */
1178 static inline void mpuio_init(void)
1180 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1182 if (platform_driver_register(&omap_mpuio_driver) == 0)
1183 (void) platform_device_register(&omap_mpuio_device);
1187 static inline void mpuio_init(void) {}
1192 extern struct irq_chip mpuio_irq_chip;
1194 #define bank_is_mpuio(bank) 0
1195 static inline void mpuio_init(void) {}
1199 /*---------------------------------------------------------------------*/
1201 /* REVISIT these are stupid implementations! replace by ones that
1202 * don't switch on METHOD_* and which mostly avoid spinlocks
1205 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1207 struct gpio_bank *bank;
1208 unsigned long flags;
1210 bank = container_of(chip, struct gpio_bank, chip);
1211 spin_lock_irqsave(&bank->lock, flags);
1212 _set_gpio_direction(bank, offset, 1);
1213 spin_unlock_irqrestore(&bank->lock, flags);
1217 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1219 return __omap_get_gpio_datain(chip->base + offset);
1222 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1224 struct gpio_bank *bank;
1225 unsigned long flags;
1227 bank = container_of(chip, struct gpio_bank, chip);
1228 spin_lock_irqsave(&bank->lock, flags);
1229 _set_gpio_dataout(bank, offset, value);
1230 _set_gpio_direction(bank, offset, 0);
1231 spin_unlock_irqrestore(&bank->lock, flags);
1235 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1237 struct gpio_bank *bank;
1238 unsigned long flags;
1240 bank = container_of(chip, struct gpio_bank, chip);
1241 spin_lock_irqsave(&bank->lock, flags);
1242 _set_gpio_dataout(bank, offset, value);
1243 spin_unlock_irqrestore(&bank->lock, flags);
1246 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1248 struct gpio_bank *bank;
1250 bank = container_of(chip, struct gpio_bank, chip);
1251 return bank->virtual_irq_start + offset;
1254 /*---------------------------------------------------------------------*/
1256 static int initialized;
1257 #if !defined(CONFIG_ARCH_OMAP3)
1258 static struct clk * gpio_ick;
1261 #if defined(CONFIG_ARCH_OMAP2)
1262 static struct clk * gpio_fck;
1265 #if defined(CONFIG_ARCH_OMAP2430)
1266 static struct clk * gpio5_ick;
1267 static struct clk * gpio5_fck;
1270 #if defined(CONFIG_ARCH_OMAP3)
1271 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1274 /* This lock class tells lockdep that GPIO irqs are in a different
1275 * category than their parents, so it won't report false recursion.
1277 static struct lock_class_key gpio_lock_class;
1279 static int __init _omap_gpio_init(void)
1283 struct gpio_bank *bank;
1288 #if defined(CONFIG_ARCH_OMAP1)
1289 if (cpu_is_omap15xx()) {
1290 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1291 if (IS_ERR(gpio_ick))
1292 printk("Could not get arm_gpio_ck\n");
1294 clk_enable(gpio_ick);
1297 #if defined(CONFIG_ARCH_OMAP2)
1298 if (cpu_class_is_omap2()) {
1299 gpio_ick = clk_get(NULL, "gpios_ick");
1300 if (IS_ERR(gpio_ick))
1301 printk("Could not get gpios_ick\n");
1303 clk_enable(gpio_ick);
1304 gpio_fck = clk_get(NULL, "gpios_fck");
1305 if (IS_ERR(gpio_fck))
1306 printk("Could not get gpios_fck\n");
1308 clk_enable(gpio_fck);
1311 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1313 #if defined(CONFIG_ARCH_OMAP2430)
1314 if (cpu_is_omap2430()) {
1315 gpio5_ick = clk_get(NULL, "gpio5_ick");
1316 if (IS_ERR(gpio5_ick))
1317 printk("Could not get gpio5_ick\n");
1319 clk_enable(gpio5_ick);
1320 gpio5_fck = clk_get(NULL, "gpio5_fck");
1321 if (IS_ERR(gpio5_fck))
1322 printk("Could not get gpio5_fck\n");
1324 clk_enable(gpio5_fck);
1330 #if defined(CONFIG_ARCH_OMAP3)
1331 if (cpu_is_omap34xx()) {
1332 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1333 sprintf(clk_name, "gpio%d_ick", i + 1);
1334 gpio_iclks[i] = clk_get(NULL, clk_name);
1335 if (IS_ERR(gpio_iclks[i]))
1336 printk(KERN_ERR "Could not get %s\n", clk_name);
1338 clk_enable(gpio_iclks[i]);
1344 #ifdef CONFIG_ARCH_OMAP15XX
1345 if (cpu_is_omap15xx()) {
1346 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1347 gpio_bank_count = 2;
1348 gpio_bank = gpio_bank_1510;
1351 #if defined(CONFIG_ARCH_OMAP16XX)
1352 if (cpu_is_omap16xx()) {
1355 gpio_bank_count = 5;
1356 gpio_bank = gpio_bank_1610;
1357 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1358 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1359 (rev >> 4) & 0x0f, rev & 0x0f);
1362 #ifdef CONFIG_ARCH_OMAP730
1363 if (cpu_is_omap730()) {
1364 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1365 gpio_bank_count = 7;
1366 gpio_bank = gpio_bank_730;
1370 #ifdef CONFIG_ARCH_OMAP24XX
1371 if (cpu_is_omap242x()) {
1374 gpio_bank_count = 4;
1375 gpio_bank = gpio_bank_242x;
1376 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1377 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1378 (rev >> 4) & 0x0f, rev & 0x0f);
1380 if (cpu_is_omap243x()) {
1383 gpio_bank_count = 5;
1384 gpio_bank = gpio_bank_243x;
1385 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1386 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1387 (rev >> 4) & 0x0f, rev & 0x0f);
1390 #ifdef CONFIG_ARCH_OMAP34XX
1391 if (cpu_is_omap34xx()) {
1394 gpio_bank_count = OMAP34XX_NR_GPIOS;
1395 gpio_bank = gpio_bank_34xx;
1396 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1397 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1398 (rev >> 4) & 0x0f, rev & 0x0f);
1401 for (i = 0; i < gpio_bank_count; i++) {
1402 int j, gpio_count = 16;
1404 bank = &gpio_bank[i];
1405 spin_lock_init(&bank->lock);
1406 if (bank_is_mpuio(bank))
1407 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1408 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1409 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1410 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1412 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1413 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1414 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1415 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1417 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
1418 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1419 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1421 gpio_count = 32; /* 730 has 32-bit GPIOs */
1424 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1425 if (bank->method == METHOD_GPIO_24XX) {
1426 static const u32 non_wakeup_gpios[] = {
1427 0xe203ffc0, 0x08700040
1430 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1431 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1432 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1434 /* Initialize interface clock ungated, module enabled */
1435 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1436 if (i < ARRAY_SIZE(non_wakeup_gpios))
1437 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1442 /* REVISIT eventually switch from OMAP-specific gpio structs
1443 * over to the generic ones
1445 bank->chip.request = omap_gpio_request;
1446 bank->chip.free = omap_gpio_free;
1447 bank->chip.direction_input = gpio_input;
1448 bank->chip.get = gpio_get;
1449 bank->chip.direction_output = gpio_output;
1450 bank->chip.set = gpio_set;
1451 bank->chip.to_irq = gpio_2irq;
1452 if (bank_is_mpuio(bank)) {
1453 bank->chip.label = "mpuio";
1454 #ifdef CONFIG_ARCH_OMAP16XX
1455 bank->chip.dev = &omap_mpuio_device.dev;
1457 bank->chip.base = OMAP_MPUIO(0);
1459 bank->chip.label = "gpio";
1460 bank->chip.base = gpio;
1463 bank->chip.ngpio = gpio_count;
1465 gpiochip_add(&bank->chip);
1467 for (j = bank->virtual_irq_start;
1468 j < bank->virtual_irq_start + gpio_count; j++) {
1469 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1470 set_irq_chip_data(j, bank);
1471 if (bank_is_mpuio(bank))
1472 set_irq_chip(j, &mpuio_irq_chip);
1474 set_irq_chip(j, &gpio_irq_chip);
1475 set_irq_handler(j, handle_simple_irq);
1476 set_irq_flags(j, IRQF_VALID);
1478 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1479 set_irq_data(bank->irq, bank);
1481 if (cpu_is_omap34xx()) {
1482 sprintf(clk_name, "gpio%d_dbck", i + 1);
1483 bank->dbck = clk_get(NULL, clk_name);
1484 if (IS_ERR(bank->dbck))
1485 printk(KERN_ERR "Could not get %s\n", clk_name);
1489 /* Enable system clock for GPIO module.
1490 * The CAM_CLK_CTRL *is* really the right place. */
1491 if (cpu_is_omap16xx())
1492 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1494 /* Enable autoidle for the OCP interface */
1495 if (cpu_is_omap24xx())
1496 omap_writel(1 << 0, 0x48019010);
1497 if (cpu_is_omap34xx())
1498 omap_writel(1 << 0, 0x48306814);
1503 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1504 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1508 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1511 for (i = 0; i < gpio_bank_count; i++) {
1512 struct gpio_bank *bank = &gpio_bank[i];
1513 void __iomem *wake_status;
1514 void __iomem *wake_clear;
1515 void __iomem *wake_set;
1516 unsigned long flags;
1518 switch (bank->method) {
1519 #ifdef CONFIG_ARCH_OMAP16XX
1520 case METHOD_GPIO_1610:
1521 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1522 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1523 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1526 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1527 case METHOD_GPIO_24XX:
1528 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1529 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1530 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1537 spin_lock_irqsave(&bank->lock, flags);
1538 bank->saved_wakeup = __raw_readl(wake_status);
1539 __raw_writel(0xffffffff, wake_clear);
1540 __raw_writel(bank->suspend_wakeup, wake_set);
1541 spin_unlock_irqrestore(&bank->lock, flags);
1547 static int omap_gpio_resume(struct sys_device *dev)
1551 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1554 for (i = 0; i < gpio_bank_count; i++) {
1555 struct gpio_bank *bank = &gpio_bank[i];
1556 void __iomem *wake_clear;
1557 void __iomem *wake_set;
1558 unsigned long flags;
1560 switch (bank->method) {
1561 #ifdef CONFIG_ARCH_OMAP16XX
1562 case METHOD_GPIO_1610:
1563 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1564 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1567 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1568 case METHOD_GPIO_24XX:
1569 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1570 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1577 spin_lock_irqsave(&bank->lock, flags);
1578 __raw_writel(0xffffffff, wake_clear);
1579 __raw_writel(bank->saved_wakeup, wake_set);
1580 spin_unlock_irqrestore(&bank->lock, flags);
1586 static struct sysdev_class omap_gpio_sysclass = {
1588 .suspend = omap_gpio_suspend,
1589 .resume = omap_gpio_resume,
1592 static struct sys_device omap_gpio_device = {
1594 .cls = &omap_gpio_sysclass,
1599 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1601 static int workaround_enabled;
1603 void omap2_gpio_prepare_for_retention(void)
1607 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1608 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1609 for (i = 0; i < gpio_bank_count; i++) {
1610 struct gpio_bank *bank = &gpio_bank[i];
1613 if (!(bank->enabled_non_wakeup_gpios))
1615 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1616 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1617 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1618 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1620 bank->saved_fallingdetect = l1;
1621 bank->saved_risingdetect = l2;
1622 l1 &= ~bank->enabled_non_wakeup_gpios;
1623 l2 &= ~bank->enabled_non_wakeup_gpios;
1624 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1625 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1626 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1631 workaround_enabled = 0;
1634 workaround_enabled = 1;
1637 void omap2_gpio_resume_after_retention(void)
1641 if (!workaround_enabled)
1643 for (i = 0; i < gpio_bank_count; i++) {
1644 struct gpio_bank *bank = &gpio_bank[i];
1647 if (!(bank->enabled_non_wakeup_gpios))
1649 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1650 __raw_writel(bank->saved_fallingdetect,
1651 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1652 __raw_writel(bank->saved_risingdetect,
1653 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1655 /* Check if any of the non-wakeup interrupt GPIOs have changed
1656 * state. If so, generate an IRQ by software. This is
1657 * horribly racy, but it's the best we can do to work around
1658 * this silicon bug. */
1659 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1660 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1662 l ^= bank->saved_datain;
1663 l &= bank->non_wakeup_gpios;
1666 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1667 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1668 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1669 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1670 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1671 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1672 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1682 * This may get called early from board specific init
1683 * for boards that have interrupts routed via FPGA.
1685 int __init omap_gpio_init(void)
1688 return _omap_gpio_init();
1693 static int __init omap_gpio_sysinit(void)
1698 ret = _omap_gpio_init();
1702 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1703 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1705 ret = sysdev_class_register(&omap_gpio_sysclass);
1707 ret = sysdev_register(&omap_gpio_device);
1715 arch_initcall(omap_gpio_sysinit);
1718 #ifdef CONFIG_DEBUG_FS
1720 #include <linux/debugfs.h>
1721 #include <linux/seq_file.h>
1723 static int gpio_is_input(struct gpio_bank *bank, int mask)
1725 void __iomem *reg = bank->base;
1727 switch (bank->method) {
1729 reg += OMAP_MPUIO_IO_CNTL;
1731 case METHOD_GPIO_1510:
1732 reg += OMAP1510_GPIO_DIR_CONTROL;
1734 case METHOD_GPIO_1610:
1735 reg += OMAP1610_GPIO_DIRECTION;
1737 case METHOD_GPIO_730:
1738 reg += OMAP730_GPIO_DIR_CONTROL;
1740 case METHOD_GPIO_24XX:
1741 reg += OMAP24XX_GPIO_OE;
1744 return __raw_readl(reg) & mask;
1748 static int dbg_gpio_show(struct seq_file *s, void *unused)
1750 unsigned i, j, gpio;
1752 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1753 struct gpio_bank *bank = gpio_bank + i;
1754 unsigned bankwidth = 16;
1757 if (bank_is_mpuio(bank))
1758 gpio = OMAP_MPUIO(0);
1759 else if (cpu_class_is_omap2() || cpu_is_omap730())
1762 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1763 unsigned irq, value, is_in, irqstat;
1766 label = gpiochip_is_requested(&bank->chip, j);
1770 irq = bank->virtual_irq_start + j;
1771 value = gpio_get_value(gpio);
1772 is_in = gpio_is_input(bank, mask);
1774 if (bank_is_mpuio(bank))
1775 seq_printf(s, "MPUIO %2d ", j);
1777 seq_printf(s, "GPIO %3d ", gpio);
1778 seq_printf(s, "(%-20.20s): %s %s",
1780 is_in ? "in " : "out",
1781 value ? "hi" : "lo");
1783 /* FIXME for at least omap2, show pullup/pulldown state */
1785 irqstat = irq_desc[irq].status;
1786 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1787 defined(CONFIG_ARCH_OMAP34XX)
1788 if (is_in && ((bank->suspend_wakeup & mask)
1789 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1790 char *trigger = NULL;
1792 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1793 case IRQ_TYPE_EDGE_FALLING:
1794 trigger = "falling";
1796 case IRQ_TYPE_EDGE_RISING:
1799 case IRQ_TYPE_EDGE_BOTH:
1800 trigger = "bothedge";
1802 case IRQ_TYPE_LEVEL_LOW:
1805 case IRQ_TYPE_LEVEL_HIGH:
1812 seq_printf(s, ", irq-%d %-8s%s",
1814 (bank->suspend_wakeup & mask)
1818 seq_printf(s, "\n");
1821 if (bank_is_mpuio(bank)) {
1822 seq_printf(s, "\n");
1829 static int dbg_gpio_open(struct inode *inode, struct file *file)
1831 return single_open(file, dbg_gpio_show, &inode->i_private);
1834 static const struct file_operations debug_fops = {
1835 .open = dbg_gpio_open,
1837 .llseek = seq_lseek,
1838 .release = single_release,
1841 static int __init omap_gpio_debuginit(void)
1843 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1844 NULL, NULL, &debug_fops);
1847 late_initcall(omap_gpio_debuginit);