2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/ptrace.h>
18 #include <linux/sysdev.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <asm/hardware.h>
24 #include <asm/arch/irqs.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/mach/irq.h>
31 * OMAP1510 GPIO registers
33 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
34 #define OMAP1510_GPIO_DATA_INPUT 0x00
35 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
36 #define OMAP1510_GPIO_DIR_CONTROL 0x08
37 #define OMAP1510_GPIO_INT_CONTROL 0x0c
38 #define OMAP1510_GPIO_INT_MASK 0x10
39 #define OMAP1510_GPIO_INT_STATUS 0x14
40 #define OMAP1510_GPIO_PIN_CONTROL 0x18
42 #define OMAP1510_IH_GPIO_BASE 64
45 * OMAP1610 specific GPIO registers
47 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
48 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
49 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
50 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
51 #define OMAP1610_GPIO_REVISION 0x0000
52 #define OMAP1610_GPIO_SYSCONFIG 0x0010
53 #define OMAP1610_GPIO_SYSSTATUS 0x0014
54 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
55 #define OMAP1610_GPIO_IRQENABLE1 0x001c
56 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
57 #define OMAP1610_GPIO_DATAIN 0x002c
58 #define OMAP1610_GPIO_DATAOUT 0x0030
59 #define OMAP1610_GPIO_DIRECTION 0x0034
60 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
61 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
62 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
63 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
64 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
65 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
66 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
67 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
70 * OMAP730 specific GPIO registers
72 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
73 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
74 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
75 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
76 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
77 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
78 #define OMAP730_GPIO_DATA_INPUT 0x00
79 #define OMAP730_GPIO_DATA_OUTPUT 0x04
80 #define OMAP730_GPIO_DIR_CONTROL 0x08
81 #define OMAP730_GPIO_INT_CONTROL 0x0c
82 #define OMAP730_GPIO_INT_MASK 0x10
83 #define OMAP730_GPIO_INT_STATUS 0x14
86 * omap24xx specific GPIO registers
88 #define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000
89 #define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000
90 #define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000
91 #define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000
93 #define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000
94 #define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000
95 #define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000
96 #define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000
97 #define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000
99 #define OMAP24XX_GPIO_REVISION 0x0000
100 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
101 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
102 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
103 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
104 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
105 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
106 #define OMAP24XX_GPIO_CTRL 0x0030
107 #define OMAP24XX_GPIO_OE 0x0034
108 #define OMAP24XX_GPIO_DATAIN 0x0038
109 #define OMAP24XX_GPIO_DATAOUT 0x003c
110 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
111 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
112 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
113 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
114 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
115 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
116 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
117 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
118 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
119 #define OMAP24XX_GPIO_SETWKUENA 0x0084
120 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
121 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
124 * omap34xx specific GPIO registers
127 #define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000
128 #define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000
129 #define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000
130 #define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000
131 #define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000
132 #define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000
138 u16 virtual_irq_start;
141 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
145 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
146 u32 non_wakeup_gpios;
147 u32 enabled_non_wakeup_gpios;
150 u32 saved_fallingdetect;
151 u32 saved_risingdetect;
156 #define METHOD_MPUIO 0
157 #define METHOD_GPIO_1510 1
158 #define METHOD_GPIO_1610 2
159 #define METHOD_GPIO_730 3
160 #define METHOD_GPIO_24XX 4
162 #ifdef CONFIG_ARCH_OMAP16XX
163 static struct gpio_bank gpio_bank_1610[5] = {
164 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
165 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
166 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
167 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
168 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
172 #ifdef CONFIG_ARCH_OMAP15XX
173 static struct gpio_bank gpio_bank_1510[2] = {
174 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
175 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
179 #ifdef CONFIG_ARCH_OMAP730
180 static struct gpio_bank gpio_bank_730[7] = {
181 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
182 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
183 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
184 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
185 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
186 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
187 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
191 #ifdef CONFIG_ARCH_OMAP24XX
193 static struct gpio_bank gpio_bank_242x[4] = {
194 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
195 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
196 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
197 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
200 static struct gpio_bank gpio_bank_243x[5] = {
201 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
202 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
203 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
204 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
205 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
210 #ifdef CONFIG_ARCH_OMAP34XX
211 static struct gpio_bank gpio_bank_34xx[6] = {
212 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
213 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
214 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
217 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
222 static struct gpio_bank *gpio_bank;
223 static int gpio_bank_count;
225 static inline struct gpio_bank *get_gpio_bank(int gpio)
227 #ifdef CONFIG_ARCH_OMAP15XX
228 if (cpu_is_omap15xx()) {
229 if (OMAP_GPIO_IS_MPUIO(gpio))
230 return &gpio_bank[0];
231 return &gpio_bank[1];
234 #if defined(CONFIG_ARCH_OMAP16XX)
235 if (cpu_is_omap16xx()) {
236 if (OMAP_GPIO_IS_MPUIO(gpio))
237 return &gpio_bank[0];
238 return &gpio_bank[1 + (gpio >> 4)];
241 #ifdef CONFIG_ARCH_OMAP730
242 if (cpu_is_omap730()) {
243 if (OMAP_GPIO_IS_MPUIO(gpio))
244 return &gpio_bank[0];
245 return &gpio_bank[1 + (gpio >> 5)];
248 #ifdef CONFIG_ARCH_OMAP24XX
249 if (cpu_is_omap24xx())
250 return &gpio_bank[gpio >> 5];
252 #ifdef CONFIG_ARCH_OMAP34XX
253 if (cpu_is_omap34xx())
254 return &gpio_bank[gpio >> 5];
258 static inline int get_gpio_index(int gpio)
260 #ifdef CONFIG_ARCH_OMAP730
261 if (cpu_is_omap730())
264 #ifdef CONFIG_ARCH_OMAP24XX
265 if (cpu_is_omap24xx())
268 #ifdef CONFIG_ARCH_OMAP34XX
269 if (cpu_is_omap34xx())
275 static inline int gpio_valid(int gpio)
279 #ifndef CONFIG_ARCH_OMAP24XX
280 if (OMAP_GPIO_IS_MPUIO(gpio)) {
281 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
286 #ifdef CONFIG_ARCH_OMAP15XX
287 if (cpu_is_omap15xx() && gpio < 16)
290 #if defined(CONFIG_ARCH_OMAP16XX)
291 if ((cpu_is_omap16xx()) && gpio < 64)
294 #ifdef CONFIG_ARCH_OMAP730
295 if (cpu_is_omap730() && gpio < 192)
298 #ifdef CONFIG_ARCH_OMAP24XX
299 if (cpu_is_omap24xx() && gpio < 128)
302 #ifdef CONFIG_ARCH_OMAP34XX
303 if (cpu_is_omap34xx() && gpio < 160)
309 static int check_gpio(int gpio)
311 if (unlikely(gpio_valid(gpio)) < 0) {
312 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
319 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
321 void __iomem *reg = bank->base;
324 switch (bank->method) {
325 #ifdef CONFIG_ARCH_OMAP1
327 reg += OMAP_MPUIO_IO_CNTL;
330 #ifdef CONFIG_ARCH_OMAP15XX
331 case METHOD_GPIO_1510:
332 reg += OMAP1510_GPIO_DIR_CONTROL;
335 #ifdef CONFIG_ARCH_OMAP16XX
336 case METHOD_GPIO_1610:
337 reg += OMAP1610_GPIO_DIRECTION;
340 #ifdef CONFIG_ARCH_OMAP730
341 case METHOD_GPIO_730:
342 reg += OMAP730_GPIO_DIR_CONTROL;
345 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
346 case METHOD_GPIO_24XX:
347 reg += OMAP24XX_GPIO_OE;
354 l = __raw_readl(reg);
359 __raw_writel(l, reg);
362 void omap_set_gpio_direction(int gpio, int is_input)
364 struct gpio_bank *bank;
366 if (check_gpio(gpio) < 0)
368 bank = get_gpio_bank(gpio);
369 spin_lock(&bank->lock);
370 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
371 spin_unlock(&bank->lock);
374 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
376 void __iomem *reg = bank->base;
379 switch (bank->method) {
380 #ifdef CONFIG_ARCH_OMAP1
382 reg += OMAP_MPUIO_OUTPUT;
383 l = __raw_readl(reg);
390 #ifdef CONFIG_ARCH_OMAP15XX
391 case METHOD_GPIO_1510:
392 reg += OMAP1510_GPIO_DATA_OUTPUT;
393 l = __raw_readl(reg);
400 #ifdef CONFIG_ARCH_OMAP16XX
401 case METHOD_GPIO_1610:
403 reg += OMAP1610_GPIO_SET_DATAOUT;
405 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
409 #ifdef CONFIG_ARCH_OMAP730
410 case METHOD_GPIO_730:
411 reg += OMAP730_GPIO_DATA_OUTPUT;
412 l = __raw_readl(reg);
419 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
420 case METHOD_GPIO_24XX:
422 reg += OMAP24XX_GPIO_SETDATAOUT;
424 reg += OMAP24XX_GPIO_CLEARDATAOUT;
432 __raw_writel(l, reg);
435 void omap_set_gpio_dataout(int gpio, int enable)
437 struct gpio_bank *bank;
439 if (check_gpio(gpio) < 0)
441 bank = get_gpio_bank(gpio);
442 spin_lock(&bank->lock);
443 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
444 spin_unlock(&bank->lock);
447 int omap_get_gpio_datain(int gpio)
449 struct gpio_bank *bank;
452 if (check_gpio(gpio) < 0)
454 bank = get_gpio_bank(gpio);
456 switch (bank->method) {
457 #ifdef CONFIG_ARCH_OMAP1
459 reg += OMAP_MPUIO_INPUT_LATCH;
462 #ifdef CONFIG_ARCH_OMAP15XX
463 case METHOD_GPIO_1510:
464 reg += OMAP1510_GPIO_DATA_INPUT;
467 #ifdef CONFIG_ARCH_OMAP16XX
468 case METHOD_GPIO_1610:
469 reg += OMAP1610_GPIO_DATAIN;
472 #ifdef CONFIG_ARCH_OMAP730
473 case METHOD_GPIO_730:
474 reg += OMAP730_GPIO_DATA_INPUT;
477 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
478 case METHOD_GPIO_24XX:
479 reg += OMAP24XX_GPIO_DATAIN;
485 return (__raw_readl(reg)
486 & (1 << get_gpio_index(gpio))) != 0;
489 #define MOD_REG_BIT(reg, bit_mask, set) \
491 int l = __raw_readl(base + reg); \
492 if (set) l |= bit_mask; \
493 else l &= ~bit_mask; \
494 __raw_writel(l, base + reg); \
497 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
498 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
500 void __iomem *base = bank->base;
501 u32 gpio_bit = 1 << gpio;
503 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
504 trigger & __IRQT_LOWLVL);
505 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
506 trigger & __IRQT_HIGHLVL);
507 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
508 trigger & __IRQT_RISEDGE);
509 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
510 trigger & __IRQT_FALEDGE);
511 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
513 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_SETWKUENA);
515 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_CLEARWKUENA);
518 bank->enabled_non_wakeup_gpios |= gpio_bit;
520 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
522 /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level
523 * triggering requested. */
527 omap_set_gpio_debounce(int gpio, int enable)
529 struct gpio_bank *bank;
531 u32 val, l = 1 << get_gpio_index(gpio);
533 bank = get_gpio_bank(gpio);
536 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
537 val = __raw_readl(reg);
544 __raw_writel(val, reg);
546 EXPORT_SYMBOL(omap_set_gpio_debounce);
549 omap_set_gpio_debounce_time(int gpio, int enc_time)
551 struct gpio_bank *bank;
554 bank = get_gpio_bank(gpio);
558 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
559 __raw_writel(enc_time, reg);
561 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
564 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
566 void __iomem *reg = bank->base;
569 switch (bank->method) {
570 #ifdef CONFIG_ARCH_OMAP1
572 reg += OMAP_MPUIO_GPIO_INT_EDGE;
573 l = __raw_readl(reg);
574 if (trigger & __IRQT_RISEDGE)
576 else if (trigger & __IRQT_FALEDGE)
582 #ifdef CONFIG_ARCH_OMAP15XX
583 case METHOD_GPIO_1510:
584 reg += OMAP1510_GPIO_INT_CONTROL;
585 l = __raw_readl(reg);
586 if (trigger & __IRQT_RISEDGE)
588 else if (trigger & __IRQT_FALEDGE)
594 #ifdef CONFIG_ARCH_OMAP16XX
595 case METHOD_GPIO_1610:
597 reg += OMAP1610_GPIO_EDGE_CTRL2;
599 reg += OMAP1610_GPIO_EDGE_CTRL1;
601 l = __raw_readl(reg);
602 l &= ~(3 << (gpio << 1));
603 if (trigger & __IRQT_RISEDGE)
604 l |= 2 << (gpio << 1);
605 if (trigger & __IRQT_FALEDGE)
606 l |= 1 << (gpio << 1);
608 /* Enable wake-up during idle for dynamic tick */
609 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
611 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
614 #ifdef CONFIG_ARCH_OMAP730
615 case METHOD_GPIO_730:
616 reg += OMAP730_GPIO_INT_CONTROL;
617 l = __raw_readl(reg);
618 if (trigger & __IRQT_RISEDGE)
620 else if (trigger & __IRQT_FALEDGE)
626 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
627 case METHOD_GPIO_24XX:
628 set_24xx_gpio_triggering(bank, gpio, trigger);
634 __raw_writel(l, reg);
640 static int gpio_irq_type(unsigned irq, unsigned type)
642 struct gpio_bank *bank;
646 if (!(cpu_class_is_omap2()) && irq > IH_MPUIO_BASE)
647 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
649 gpio = irq - IH_GPIO_BASE;
651 if (check_gpio(gpio) < 0)
654 if (type & ~IRQ_TYPE_SENSE_MASK)
657 /* OMAP1 allows only only edge triggering */
658 if (!(cpu_class_is_omap2())
659 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
662 bank = get_irq_chip_data(irq);
663 spin_lock(&bank->lock);
664 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
666 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
667 irq_desc[irq].status |= type;
669 spin_unlock(&bank->lock);
673 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
675 void __iomem *reg = bank->base;
677 switch (bank->method) {
678 #ifdef CONFIG_ARCH_OMAP1
680 /* MPUIO irqstatus is reset by reading the status register,
681 * so do nothing here */
684 #ifdef CONFIG_ARCH_OMAP15XX
685 case METHOD_GPIO_1510:
686 reg += OMAP1510_GPIO_INT_STATUS;
689 #ifdef CONFIG_ARCH_OMAP16XX
690 case METHOD_GPIO_1610:
691 reg += OMAP1610_GPIO_IRQSTATUS1;
694 #ifdef CONFIG_ARCH_OMAP730
695 case METHOD_GPIO_730:
696 reg += OMAP730_GPIO_INT_STATUS;
699 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
700 case METHOD_GPIO_24XX:
701 reg += OMAP24XX_GPIO_IRQSTATUS1;
708 __raw_writel(gpio_mask, reg);
710 /* Workaround for clearing DSP GPIO interrupts to allow retention */
711 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
712 if (cpu_is_omap24xx() || cpu_is_omap34xx())
713 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
717 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
719 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
722 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
724 void __iomem *reg = bank->base;
729 switch (bank->method) {
730 #ifdef CONFIG_ARCH_OMAP1
732 reg += OMAP_MPUIO_GPIO_MASKIT;
737 #ifdef CONFIG_ARCH_OMAP15XX
738 case METHOD_GPIO_1510:
739 reg += OMAP1510_GPIO_INT_MASK;
744 #ifdef CONFIG_ARCH_OMAP16XX
745 case METHOD_GPIO_1610:
746 reg += OMAP1610_GPIO_IRQENABLE1;
750 #ifdef CONFIG_ARCH_OMAP730
751 case METHOD_GPIO_730:
752 reg += OMAP730_GPIO_INT_MASK;
757 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
758 case METHOD_GPIO_24XX:
759 reg += OMAP24XX_GPIO_IRQENABLE1;
768 l = __raw_readl(reg);
775 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
777 void __iomem *reg = bank->base;
780 switch (bank->method) {
781 #ifdef CONFIG_ARCH_OMAP1
783 reg += OMAP_MPUIO_GPIO_MASKIT;
784 l = __raw_readl(reg);
791 #ifdef CONFIG_ARCH_OMAP15XX
792 case METHOD_GPIO_1510:
793 reg += OMAP1510_GPIO_INT_MASK;
794 l = __raw_readl(reg);
801 #ifdef CONFIG_ARCH_OMAP16XX
802 case METHOD_GPIO_1610:
804 reg += OMAP1610_GPIO_SET_IRQENABLE1;
806 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
810 #ifdef CONFIG_ARCH_OMAP730
811 case METHOD_GPIO_730:
812 reg += OMAP730_GPIO_INT_MASK;
813 l = __raw_readl(reg);
820 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
821 case METHOD_GPIO_24XX:
823 reg += OMAP24XX_GPIO_SETIRQENABLE1;
825 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
833 __raw_writel(l, reg);
836 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
838 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
842 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
843 * 1510 does not seem to have a wake-up register. If JTAG is connected
844 * to the target, system will wake up always on GPIO events. While
845 * system is running all registered GPIO interrupts need to have wake-up
846 * enabled. When system is suspended, only selected GPIO interrupts need
847 * to have wake-up enabled.
849 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
851 switch (bank->method) {
852 #ifdef CONFIG_ARCH_OMAP16XX
854 case METHOD_GPIO_1610:
855 spin_lock(&bank->lock);
857 bank->suspend_wakeup |= (1 << gpio);
858 enable_irq_wake(bank->irq);
860 disable_irq_wake(bank->irq);
861 bank->suspend_wakeup &= ~(1 << gpio);
863 spin_unlock(&bank->lock);
866 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
867 case METHOD_GPIO_24XX:
868 if (bank->non_wakeup_gpios & (1 << gpio)) {
869 printk(KERN_ERR "Unable to modify wakeup on "
870 "non-wakeup GPIO%d\n",
871 (bank - gpio_bank) * 32 + gpio);
874 spin_lock(&bank->lock);
876 bank->suspend_wakeup |= (1 << gpio);
877 enable_irq_wake(bank->irq);
879 disable_irq_wake(bank->irq);
880 bank->suspend_wakeup &= ~(1 << gpio);
882 spin_unlock(&bank->lock);
886 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
892 static void _reset_gpio(struct gpio_bank *bank, int gpio)
894 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
895 _set_gpio_irqenable(bank, gpio, 0);
896 _clear_gpio_irqstatus(bank, gpio);
897 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
900 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
901 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
903 unsigned int gpio = irq - IH_GPIO_BASE;
904 struct gpio_bank *bank;
907 if (check_gpio(gpio) < 0)
909 bank = get_irq_chip_data(irq);
910 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
915 int omap_request_gpio(int gpio)
917 struct gpio_bank *bank;
919 if (check_gpio(gpio) < 0)
922 bank = get_gpio_bank(gpio);
923 spin_lock(&bank->lock);
924 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
925 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
927 spin_unlock(&bank->lock);
930 bank->reserved_map |= (1 << get_gpio_index(gpio));
932 /* Set trigger to none. You need to enable the desired trigger with
933 * request_irq() or set_irq_type().
935 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
937 #ifdef CONFIG_ARCH_OMAP15XX
938 if (bank->method == METHOD_GPIO_1510) {
941 /* Claim the pin for MPU */
942 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
943 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
946 spin_unlock(&bank->lock);
951 void omap_free_gpio(int gpio)
953 struct gpio_bank *bank;
955 if (check_gpio(gpio) < 0)
957 bank = get_gpio_bank(gpio);
958 spin_lock(&bank->lock);
959 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
960 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
962 spin_unlock(&bank->lock);
965 #ifdef CONFIG_ARCH_OMAP16XX
966 if (bank->method == METHOD_GPIO_1610) {
967 /* Disable wake-up during idle for dynamic tick */
968 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
969 __raw_writel(1 << get_gpio_index(gpio), reg);
972 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
973 if (bank->method == METHOD_GPIO_24XX) {
974 /* Disable wake-up during idle for dynamic tick */
975 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
976 __raw_writel(1 << get_gpio_index(gpio), reg);
979 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
980 _reset_gpio(bank, gpio);
981 spin_unlock(&bank->lock);
985 * We need to unmask the GPIO bank interrupt as soon as possible to
986 * avoid missing GPIO interrupts for other lines in the bank.
987 * Then we need to mask-read-clear-unmask the triggered GPIO lines
988 * in the bank to avoid missing nested interrupts for a GPIO line.
989 * If we wait to unmask individual GPIO lines in the bank after the
990 * line's interrupt handler has been run, we may miss some nested
993 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
995 void __iomem *isr_reg = NULL;
997 unsigned int gpio_irq;
998 struct gpio_bank *bank;
1002 desc->chip->ack(irq);
1004 bank = get_irq_data(irq);
1005 #ifdef CONFIG_ARCH_OMAP1
1006 if (bank->method == METHOD_MPUIO)
1007 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1009 #ifdef CONFIG_ARCH_OMAP15XX
1010 if (bank->method == METHOD_GPIO_1510)
1011 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1013 #if defined(CONFIG_ARCH_OMAP16XX)
1014 if (bank->method == METHOD_GPIO_1610)
1015 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1017 #ifdef CONFIG_ARCH_OMAP730
1018 if (bank->method == METHOD_GPIO_730)
1019 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1021 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1022 if (bank->method == METHOD_GPIO_24XX)
1023 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1026 u32 isr_saved, level_mask = 0;
1029 enabled = _get_gpio_irqbank_mask(bank);
1030 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1032 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1035 if (cpu_class_is_omap2()) {
1037 __raw_readl(bank->base +
1038 OMAP24XX_GPIO_LEVELDETECT0) |
1039 __raw_readl(bank->base +
1040 OMAP24XX_GPIO_LEVELDETECT1);
1041 level_mask &= enabled;
1044 /* clear edge sensitive interrupts before handler(s) are
1045 called so that we don't miss any interrupt occurred while
1047 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1048 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1049 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1051 /* if there is only edge sensitive GPIO pin interrupts
1052 configured, we could unmask GPIO bank interrupt immediately */
1053 if (!level_mask && !unmasked) {
1055 desc->chip->unmask(irq);
1063 gpio_irq = bank->virtual_irq_start;
1064 for (; isr != 0; isr >>= 1, gpio_irq++) {
1069 d = irq_desc + gpio_irq;
1070 /* Don't run the handler if it's already running
1071 * or was disabled lazely.
1073 if (unlikely((d->depth ||
1074 (d->status & IRQ_INPROGRESS)))) {
1076 (gpio_irq - bank->virtual_irq_start);
1077 /* The unmasking will be done by
1078 * enable_irq in case it is disabled or
1079 * after returning from the handler if
1080 * it's already running.
1082 _enable_gpio_irqbank(bank, irq_mask, 0);
1084 /* Level triggered interrupts
1085 * won't ever be reentered
1087 BUG_ON(level_mask & irq_mask);
1088 d->status |= IRQ_PENDING;
1093 desc_handle_irq(gpio_irq, d);
1095 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
1097 (gpio_irq - bank->virtual_irq_start);
1098 d->status &= ~IRQ_PENDING;
1099 _enable_gpio_irqbank(bank, irq_mask, 1);
1100 retrigger |= irq_mask;
1104 if (cpu_class_is_omap2()) {
1105 /* clear level sensitive interrupts after handler(s) */
1106 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
1107 _clear_gpio_irqbank(bank, isr_saved & level_mask);
1108 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
1112 /* if bank has any level sensitive GPIO pin interrupt
1113 configured, we must unmask the bank interrupt only after
1114 handler(s) are executed in order to avoid spurious bank
1117 desc->chip->unmask(irq);
1121 static void gpio_irq_shutdown(unsigned int irq)
1123 unsigned int gpio = irq - IH_GPIO_BASE;
1124 struct gpio_bank *bank = get_irq_chip_data(irq);
1126 _reset_gpio(bank, gpio);
1129 static void gpio_ack_irq(unsigned int irq)
1131 unsigned int gpio = irq - IH_GPIO_BASE;
1132 struct gpio_bank *bank = get_irq_chip_data(irq);
1134 _clear_gpio_irqstatus(bank, gpio);
1137 static void gpio_mask_irq(unsigned int irq)
1139 unsigned int gpio = irq - IH_GPIO_BASE;
1140 struct gpio_bank *bank = get_irq_chip_data(irq);
1142 _set_gpio_irqenable(bank, gpio, 0);
1145 static void gpio_unmask_irq(unsigned int irq)
1147 unsigned int gpio = irq - IH_GPIO_BASE;
1148 unsigned int gpio_idx = get_gpio_index(gpio);
1149 struct gpio_bank *bank = get_irq_chip_data(irq);
1151 _set_gpio_irqenable(bank, gpio_idx, 1);
1154 static struct irq_chip gpio_irq_chip = {
1156 .shutdown = gpio_irq_shutdown,
1157 .ack = gpio_ack_irq,
1158 .mask = gpio_mask_irq,
1159 .unmask = gpio_unmask_irq,
1160 .set_type = gpio_irq_type,
1161 .set_wake = gpio_wake_enable,
1164 /*---------------------------------------------------------------------*/
1166 #ifdef CONFIG_ARCH_OMAP1
1168 /* MPUIO uses the always-on 32k clock */
1170 static void mpuio_ack_irq(unsigned int irq)
1172 /* The ISR is reset automatically, so do nothing here. */
1175 static void mpuio_mask_irq(unsigned int irq)
1177 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1178 struct gpio_bank *bank = get_irq_chip_data(irq);
1180 _set_gpio_irqenable(bank, gpio, 0);
1183 static void mpuio_unmask_irq(unsigned int irq)
1185 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1186 struct gpio_bank *bank = get_irq_chip_data(irq);
1188 _set_gpio_irqenable(bank, gpio, 1);
1191 static struct irq_chip mpuio_irq_chip = {
1193 .ack = mpuio_ack_irq,
1194 .mask = mpuio_mask_irq,
1195 .unmask = mpuio_unmask_irq,
1196 .set_type = gpio_irq_type,
1197 #ifdef CONFIG_ARCH_OMAP16XX
1198 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1199 .set_wake = gpio_wake_enable,
1204 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1207 #ifdef CONFIG_ARCH_OMAP16XX
1209 #include <linux/platform_device.h>
1211 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1213 struct gpio_bank *bank = platform_get_drvdata(pdev);
1214 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1216 spin_lock(&bank->lock);
1217 bank->saved_wakeup = __raw_readl(mask_reg);
1218 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1219 spin_unlock(&bank->lock);
1224 static int omap_mpuio_resume_early(struct platform_device *pdev)
1226 struct gpio_bank *bank = platform_get_drvdata(pdev);
1227 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1229 spin_lock(&bank->lock);
1230 __raw_writel(bank->saved_wakeup, mask_reg);
1231 spin_unlock(&bank->lock);
1236 /* use platform_driver for this, now that there's no longer any
1237 * point to sys_device (other than not disturbing old code).
1239 static struct platform_driver omap_mpuio_driver = {
1240 .suspend_late = omap_mpuio_suspend_late,
1241 .resume_early = omap_mpuio_resume_early,
1247 static struct platform_device omap_mpuio_device = {
1251 .driver = &omap_mpuio_driver.driver,
1253 /* could list the /proc/iomem resources */
1256 static inline void mpuio_init(void)
1258 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1260 if (platform_driver_register(&omap_mpuio_driver) == 0)
1261 (void) platform_device_register(&omap_mpuio_device);
1265 static inline void mpuio_init(void) {}
1270 extern struct irq_chip mpuio_irq_chip;
1272 #define bank_is_mpuio(bank) 0
1273 static inline void mpuio_init(void) {}
1277 /*---------------------------------------------------------------------*/
1279 static int initialized;
1280 #if !defined(CONFIG_ARCH_OMAP3)
1281 static struct clk * gpio_ick;
1284 #if defined(CONFIG_ARCH_OMAP2)
1285 static struct clk * gpio_fck;
1288 #if defined(CONFIG_ARCH_OMAP2430)
1289 static struct clk * gpio5_ick;
1290 static struct clk * gpio5_fck;
1293 #if defined(CONFIG_ARCH_OMAP3)
1294 static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
1295 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1298 static int __init _omap_gpio_init(void)
1301 struct gpio_bank *bank;
1302 #if defined(CONFIG_ARCH_OMAP3)
1308 #if defined(CONFIG_ARCH_OMAP1)
1309 if (cpu_is_omap15xx()) {
1310 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1311 if (IS_ERR(gpio_ick))
1312 printk("Could not get arm_gpio_ck\n");
1314 clk_enable(gpio_ick);
1317 #if defined(CONFIG_ARCH_OMAP2)
1318 if (cpu_class_is_omap2()) {
1319 gpio_ick = clk_get(NULL, "gpios_ick");
1320 if (IS_ERR(gpio_ick))
1321 printk("Could not get gpios_ick\n");
1323 clk_enable(gpio_ick);
1324 gpio_fck = clk_get(NULL, "gpios_fck");
1325 if (IS_ERR(gpio_fck))
1326 printk("Could not get gpios_fck\n");
1328 clk_enable(gpio_fck);
1331 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1333 #if defined(CONFIG_ARCH_OMAP2430)
1334 if (cpu_is_omap2430()) {
1335 gpio5_ick = clk_get(NULL, "gpio5_ick");
1336 if (IS_ERR(gpio5_ick))
1337 printk("Could not get gpio5_ick\n");
1339 clk_enable(gpio5_ick);
1340 gpio5_fck = clk_get(NULL, "gpio5_fck");
1341 if (IS_ERR(gpio5_fck))
1342 printk("Could not get gpio5_fck\n");
1344 clk_enable(gpio5_fck);
1350 #if defined(CONFIG_ARCH_OMAP3)
1351 if (cpu_is_omap34xx()) {
1352 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1353 sprintf(clk_name, "gpio%d_ick", i + 1);
1354 gpio_iclks[i] = clk_get(NULL, clk_name);
1355 if (IS_ERR(gpio_iclks[i]))
1356 printk(KERN_ERR "Could not get %s\n", clk_name);
1358 clk_enable(gpio_iclks[i]);
1359 sprintf(clk_name, "gpio%d_fck", i + 1);
1360 gpio_fclks[i] = clk_get(NULL, clk_name);
1361 if (IS_ERR(gpio_fclks[i]))
1362 printk(KERN_ERR "Could not get %s\n", clk_name);
1364 clk_enable(gpio_fclks[i]);
1370 #ifdef CONFIG_ARCH_OMAP15XX
1371 if (cpu_is_omap15xx()) {
1372 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1373 gpio_bank_count = 2;
1374 gpio_bank = gpio_bank_1510;
1377 #if defined(CONFIG_ARCH_OMAP16XX)
1378 if (cpu_is_omap16xx()) {
1381 gpio_bank_count = 5;
1382 gpio_bank = gpio_bank_1610;
1383 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1384 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1385 (rev >> 4) & 0x0f, rev & 0x0f);
1388 #ifdef CONFIG_ARCH_OMAP730
1389 if (cpu_is_omap730()) {
1390 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1391 gpio_bank_count = 7;
1392 gpio_bank = gpio_bank_730;
1396 #ifdef CONFIG_ARCH_OMAP24XX
1397 if (cpu_is_omap242x()) {
1400 gpio_bank_count = 4;
1401 gpio_bank = gpio_bank_242x;
1402 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1403 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1404 (rev >> 4) & 0x0f, rev & 0x0f);
1406 if (cpu_is_omap243x()) {
1409 gpio_bank_count = 5;
1410 gpio_bank = gpio_bank_243x;
1411 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1412 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1413 (rev >> 4) & 0x0f, rev & 0x0f);
1416 #ifdef CONFIG_ARCH_OMAP34XX
1417 if (cpu_is_omap34xx()) {
1420 gpio_bank_count = OMAP34XX_NR_GPIOS;
1421 gpio_bank = gpio_bank_34xx;
1422 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1423 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1424 (rev >> 4) & 0x0f, rev & 0x0f);
1427 for (i = 0; i < gpio_bank_count; i++) {
1428 int j, gpio_count = 16;
1430 bank = &gpio_bank[i];
1431 bank->reserved_map = 0;
1432 bank->base = IO_ADDRESS(bank->base);
1433 spin_lock_init(&bank->lock);
1434 if (bank_is_mpuio(bank))
1435 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1436 #ifdef CONFIG_ARCH_OMAP15XX
1437 if (bank->method == METHOD_GPIO_1510) {
1438 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1439 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1442 #if defined(CONFIG_ARCH_OMAP16XX)
1443 if (bank->method == METHOD_GPIO_1610) {
1444 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1445 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1446 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1449 #ifdef CONFIG_ARCH_OMAP730
1450 if (bank->method == METHOD_GPIO_730) {
1451 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1452 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1454 gpio_count = 32; /* 730 has 32-bit GPIOs */
1457 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1458 if (bank->method == METHOD_GPIO_24XX) {
1459 static const u32 non_wakeup_gpios[] = {
1460 0xe203ffc0, 0x08700040
1463 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1464 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1465 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1467 /* Initialize interface clock ungated, module enabled */
1468 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1469 if (i < ARRAY_SIZE(non_wakeup_gpios))
1470 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1474 for (j = bank->virtual_irq_start;
1475 j < bank->virtual_irq_start + gpio_count; j++) {
1476 set_irq_chip_data(j, bank);
1477 if (bank_is_mpuio(bank))
1478 set_irq_chip(j, &mpuio_irq_chip);
1480 set_irq_chip(j, &gpio_irq_chip);
1481 set_irq_handler(j, handle_simple_irq);
1482 set_irq_flags(j, IRQF_VALID);
1484 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1485 set_irq_data(bank->irq, bank);
1488 /* Enable system clock for GPIO module.
1489 * The CAM_CLK_CTRL *is* really the right place. */
1490 if (cpu_is_omap16xx())
1491 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1493 #if defined(CONFIG_ARCH_OMAP24XX)
1494 /* Enable autoidle for the OCP interface */
1495 if (cpu_is_omap24xx())
1496 omap_writel(1 << 0, 0x48019010);
1497 #elif defined(CONFIG_ARCH_OMAP34XX)
1498 if (cpu_is_omap34xx())
1499 omap_writel(1 << 0, 0x48306814);
1504 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX) || defined (CONFIG_ARCH_OMAP34XX)
1505 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1509 if ((!cpu_class_is_omap2()) && (!cpu_is_omap16xx()))
1512 for (i = 0; i < gpio_bank_count; i++) {
1513 struct gpio_bank *bank = &gpio_bank[i];
1514 void __iomem *wake_status;
1515 void __iomem *wake_clear;
1516 void __iomem *wake_set;
1518 switch (bank->method) {
1519 #ifdef CONFIG_ARCH_OMAP16XX
1520 case METHOD_GPIO_1610:
1521 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1522 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1523 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1526 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1527 case METHOD_GPIO_24XX:
1528 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1529 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1530 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1537 spin_lock(&bank->lock);
1538 bank->saved_wakeup = __raw_readl(wake_status);
1539 __raw_writel(0xffffffff, wake_clear);
1540 __raw_writel(bank->suspend_wakeup, wake_set);
1541 spin_unlock(&bank->lock);
1547 static int omap_gpio_resume(struct sys_device *dev)
1551 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1554 for (i = 0; i < gpio_bank_count; i++) {
1555 struct gpio_bank *bank = &gpio_bank[i];
1556 void __iomem *wake_clear;
1557 void __iomem *wake_set;
1559 switch (bank->method) {
1560 #ifdef CONFIG_ARCH_OMAP16XX
1561 case METHOD_GPIO_1610:
1562 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1563 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1566 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1567 case METHOD_GPIO_24XX:
1568 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1569 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1576 spin_lock(&bank->lock);
1577 __raw_writel(0xffffffff, wake_clear);
1578 __raw_writel(bank->saved_wakeup, wake_set);
1579 spin_unlock(&bank->lock);
1585 static struct sysdev_class omap_gpio_sysclass = {
1586 set_kset_name("gpio"),
1587 .suspend = omap_gpio_suspend,
1588 .resume = omap_gpio_resume,
1591 static struct sys_device omap_gpio_device = {
1593 .cls = &omap_gpio_sysclass,
1598 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1600 static int workaround_enabled;
1602 void omap2_gpio_prepare_for_retention(void)
1606 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1607 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1608 for (i = 0; i < gpio_bank_count; i++) {
1609 struct gpio_bank *bank = &gpio_bank[i];
1612 if (!(bank->enabled_non_wakeup_gpios))
1614 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1615 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1616 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1617 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1619 bank->saved_fallingdetect = l1;
1620 bank->saved_risingdetect = l2;
1621 l1 &= ~bank->enabled_non_wakeup_gpios;
1622 l2 &= ~bank->enabled_non_wakeup_gpios;
1623 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1624 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1625 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1630 workaround_enabled = 0;
1633 workaround_enabled = 1;
1636 void omap2_gpio_resume_after_retention(void)
1640 if (!workaround_enabled)
1642 for (i = 0; i < gpio_bank_count; i++) {
1643 struct gpio_bank *bank = &gpio_bank[i];
1646 if (!(bank->enabled_non_wakeup_gpios))
1648 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1649 __raw_writel(bank->saved_fallingdetect,
1650 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1651 __raw_writel(bank->saved_risingdetect,
1652 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1654 /* Check if any of the non-wakeup interrupt GPIOs have changed
1655 * state. If so, generate an IRQ by software. This is
1656 * horribly racy, but it's the best we can do to work around
1657 * this silicon bug. */
1658 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1659 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1661 l ^= bank->saved_datain;
1662 l &= bank->non_wakeup_gpios;
1665 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1666 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1667 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1668 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1669 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1670 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1671 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1681 * This may get called early from board specific init
1682 * for boards that have interrupts routed via FPGA.
1684 int __init omap_gpio_init(void)
1687 return _omap_gpio_init();
1692 static int __init omap_gpio_sysinit(void)
1697 ret = _omap_gpio_init();
1701 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1702 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1704 ret = sysdev_class_register(&omap_gpio_sysclass);
1706 ret = sysdev_register(&omap_gpio_device);
1714 EXPORT_SYMBOL(omap_request_gpio);
1715 EXPORT_SYMBOL(omap_free_gpio);
1716 EXPORT_SYMBOL(omap_set_gpio_direction);
1717 EXPORT_SYMBOL(omap_set_gpio_dataout);
1718 EXPORT_SYMBOL(omap_get_gpio_datain);
1720 arch_initcall(omap_gpio_sysinit);
1723 #ifdef CONFIG_DEBUG_FS
1725 #include <linux/debugfs.h>
1726 #include <linux/seq_file.h>
1728 static int gpio_is_input(struct gpio_bank *bank, int mask)
1730 void __iomem *reg = bank->base;
1732 switch (bank->method) {
1734 reg += OMAP_MPUIO_IO_CNTL;
1736 case METHOD_GPIO_1510:
1737 reg += OMAP1510_GPIO_DIR_CONTROL;
1739 case METHOD_GPIO_1610:
1740 reg += OMAP1610_GPIO_DIRECTION;
1742 case METHOD_GPIO_730:
1743 reg += OMAP730_GPIO_DIR_CONTROL;
1745 case METHOD_GPIO_24XX:
1746 reg += OMAP24XX_GPIO_OE;
1749 return __raw_readl(reg) & mask;
1753 static int dbg_gpio_show(struct seq_file *s, void *unused)
1755 unsigned i, j, gpio;
1757 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1758 struct gpio_bank *bank = gpio_bank + i;
1759 unsigned bankwidth = 16;
1762 if (bank_is_mpuio(bank))
1763 gpio = OMAP_MPUIO(0);
1764 else if (cpu_class_is_omap2() || cpu_is_omap730())
1767 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1768 unsigned irq, value, is_in, irqstat;
1770 if (!(bank->reserved_map & mask))
1773 irq = bank->virtual_irq_start + j;
1774 value = omap_get_gpio_datain(gpio);
1775 is_in = gpio_is_input(bank, mask);
1777 if (bank_is_mpuio(bank))
1778 seq_printf(s, "MPUIO %2d: ", j);
1780 seq_printf(s, "GPIO %3d: ", gpio);
1781 seq_printf(s, "%s %s",
1782 is_in ? "in " : "out",
1783 value ? "hi" : "lo");
1785 irqstat = irq_desc[irq].status;
1786 if (is_in && ((bank->suspend_wakeup & mask)
1787 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1788 char *trigger = NULL;
1790 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1791 case IRQ_TYPE_EDGE_FALLING:
1792 trigger = "falling";
1794 case IRQ_TYPE_EDGE_RISING:
1797 case IRQ_TYPE_EDGE_BOTH:
1798 trigger = "bothedge";
1800 case IRQ_TYPE_LEVEL_LOW:
1803 case IRQ_TYPE_LEVEL_HIGH:
1807 trigger = "(unspecified)";
1810 seq_printf(s, ", irq-%d %s%s",
1812 (bank->suspend_wakeup & mask)
1815 seq_printf(s, "\n");
1818 if (bank_is_mpuio(bank)) {
1819 seq_printf(s, "\n");
1826 static int dbg_gpio_open(struct inode *inode, struct file *file)
1828 return single_open(file, dbg_gpio_show, &inode->i_private);
1831 static const struct file_operations debug_fops = {
1832 .open = dbg_gpio_open,
1834 .llseek = seq_lseek,
1835 .release = single_release,
1838 static int __init omap_gpio_debuginit(void)
1840 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1841 NULL, NULL, &debug_fops);
1844 late_initcall(omap_gpio_debuginit);