arch/arm/plat-omap/dma.c

   1 /*
   2  * linux/arch/arm/plat-omap/dma.c
   3  *
   4  * Copyright (C) 2003 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  * Graphics DMA and LCD DMA graphics tranformations
   8  * by Imre Deak <imre.deak@nokia.com>
   9  * OMAP2 support Copyright (C) 2004-2005 Texas Instruments, Inc.
  10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Support functions for the OMAP internal DMA channels.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  *
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/sched.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/errno.h>
  26 #include <linux/interrupt.h>
  27
  28 #include <asm/system.h>
  29 #include <asm/irq.h>
  30 #include <asm/hardware.h>
  31 #include <asm/dma.h>
  32 #include <asm/io.h>
  33 #include <asm/mach-types.h>
  34
  35 #include <asm/arch/tc.h>
  36
  37 #define DEBUG_PRINTS
  38 #undef DEBUG_PRINTS
  39 #ifdef DEBUG_PRINTS
  40 #define debug_printk(x) printk x
  41 #else
  42 #define debug_printk(x)
  43 #endif
  44
  45 #define OMAP_DMA_ACTIVE         0x01
  46 #define OMAP_DMA_CCR_EN         (1 << 7)
  47
  48 #define OMAP_FUNC_MUX_ARM_BASE  (0xfffe1000 + 0xec)
  49
  50 static int enable_1510_mode = 0;
  51
  52 struct omap_dma_lch {
  53         int next_lch;
  54         int dev_id;
  55         u16 saved_csr;
  56         u16 enabled_irqs;
  57         const char *dev_name;
  58         void (* callback)(int lch, u16 ch_status, void *data);
  59         void *data;
  60         long flags;
  61 };
  62
  63 static int dma_chan_count;
  64
  65 static spinlock_t dma_chan_lock;
  66 static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT];
  67
  68 static const u8 omap1_dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = {
  69         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
  70         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
  71         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
  72         INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
  73         INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
  74 };
  75
  76 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
  77                                                 __FUNCTION__);
  78
  79 #ifdef CONFIG_ARCH_OMAP15XX
  80 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
  81 int omap_dma_in_1510_mode(void)
  82 {
  83         return enable_1510_mode;
  84 }
  85 #else
  86 #define omap_dma_in_1510_mode()         0
  87 #endif
  88
  89 #ifdef CONFIG_ARCH_OMAP1
  90 static inline int get_gdma_dev(int req)
  91 {
  92         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
  93         int shift = ((req - 1) % 5) * 6;
  94
  95         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
  96 }
  97
  98 static inline void set_gdma_dev(int req, int dev)
  99 {
 100         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 101         int shift = ((req - 1) % 5) * 6;
 102         u32 l;
 103
 104         l = omap_readl(reg);
 105         l &= ~(0x3f << shift);
 106         l |= (dev - 1) << shift;
 107         omap_writel(l, reg);
 108 }
 109 #else
 110 #define set_gdma_dev(req, dev)  do {} while (0)
 111 #endif
 112
 113 static void clear_lch_regs(int lch)
 114 {
 115         int i;
 116         u32 lch_base = OMAP_DMA_BASE + lch * 0x40;
 117
 118         for (i = 0; i < 0x2c; i += 2)
 119                 omap_writew(0, lch_base + i);
 120 }
 121
 122 void omap_set_dma_priority(int dst_port, int priority)
 123 {
 124         unsigned long reg;
 125         u32 l;
 126
 127         switch (dst_port) {
 128         case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 129                 reg = OMAP_TC_OCPT1_PRIOR;
 130                 break;
 131         case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 132                 reg = OMAP_TC_OCPT2_PRIOR;
 133                 break;
 134         case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 135                 reg = OMAP_TC_EMIFF_PRIOR;
 136                 break;
 137         case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 138                 reg = OMAP_TC_EMIFS_PRIOR;
 139                 break;
 140         default:
 141                 BUG();
 142                 return;
 143         }
 144         l = omap_readl(reg);
 145         l &= ~(0xf << 8);
 146         l |= (priority & 0xf) << 8;
 147         omap_writel(l, reg);
 148 }
 149
 150 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 151                                   int frame_count, int sync_mode,
 152                                   int dma_trigger, int src_or_dst_synch)
 153 {
 154         OMAP_DMA_CSDP_REG(lch) &= ~0x03;
 155         OMAP_DMA_CSDP_REG(lch) |= data_type;
 156
 157         if (cpu_class_is_omap1()) {
 158                 OMAP_DMA_CCR_REG(lch) &= ~(1 << 5);
 159                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
 160                         OMAP_DMA_CCR_REG(lch) |= 1 << 5;
 161
 162                 OMAP1_DMA_CCR2_REG(lch) &= ~(1 << 2);
 163                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 164                         OMAP1_DMA_CCR2_REG(lch) |= 1 << 2;
 165         }
 166
 167         if (cpu_is_omap24xx() && dma_trigger) {
 168                 u32 val = OMAP_DMA_CCR_REG(lch);
 169
 170                 if (dma_trigger > 63)
 171                         val |= 1 << 20;
 172                 if (dma_trigger > 31)
 173                         val |= 1 << 19;
 174
 175                 val |= (dma_trigger & 0x1f);
 176
 177                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
 178                         val |= 1 << 5;
 179
 180                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 181                         val |= 1 << 18;
 182
 183                 if (src_or_dst_synch)
 184                         val |= 1 << 24;         /* source synch */
 185                 else
 186                         val &= ~(1 << 24);      /* dest synch */
 187
 188                 OMAP_DMA_CCR_REG(lch) = val;
 189         }
 190
 191         OMAP_DMA_CEN_REG(lch) = elem_count;
 192         OMAP_DMA_CFN_REG(lch) = frame_count;
 193 }
 194
 195 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 196 {
 197         u16 w;
 198
 199         BUG_ON(omap_dma_in_1510_mode());
 200
 201         if (cpu_is_omap24xx()) {
 202                 REVISIT_24XX();
 203                 return;
 204         }
 205
 206         w = OMAP1_DMA_CCR2_REG(lch) & ~0x03;
 207         switch (mode) {
 208         case OMAP_DMA_CONSTANT_FILL:
 209                 w |= 0x01;
 210                 break;
 211         case OMAP_DMA_TRANSPARENT_COPY:
 212                 w |= 0x02;
 213                 break;
 214         case OMAP_DMA_COLOR_DIS:
 215                 break;
 216         default:
 217                 BUG();
 218         }
 219         OMAP1_DMA_CCR2_REG(lch) = w;
 220
 221         w = OMAP1_DMA_LCH_CTRL_REG(lch) & ~0x0f;
 222         /* Default is channel type 2D */
 223         if (mode) {
 224                 OMAP1_DMA_COLOR_L_REG(lch) = (u16)color;
 225                 OMAP1_DMA_COLOR_U_REG(lch) = (u16)(color >> 16);
 226                 w |= 1;         /* Channel type G */
 227         }
 228         OMAP1_DMA_LCH_CTRL_REG(lch) = w;
 229 }
 230
 231 /* Note that src_port is only for omap1 */
 232 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 233                              unsigned long src_start,
 234                              int src_ei, int src_fi)
 235 {
 236         if (cpu_class_is_omap1()) {
 237                 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 2);
 238                 OMAP_DMA_CSDP_REG(lch) |= src_port << 2;
 239         }
 240
 241         OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 12);
 242         OMAP_DMA_CCR_REG(lch) |= src_amode << 12;
 243
 244         if (cpu_class_is_omap1()) {
 245                 OMAP1_DMA_CSSA_U_REG(lch) = src_start >> 16;
 246                 OMAP1_DMA_CSSA_L_REG(lch) = src_start;
 247         }
 248
 249         if (cpu_is_omap24xx())
 250                 OMAP2_DMA_CSSA_REG(lch) = src_start;
 251
 252         OMAP_DMA_CSEI_REG(lch) = src_ei;
 253         OMAP_DMA_CSFI_REG(lch) = src_fi;
 254 }
 255
 256 void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
 257 {
 258         omap_set_dma_transfer_params(lch, params->data_type,
 259                                      params->elem_count, params->frame_count,
 260                                      params->sync_mode, params->trigger,
 261                                      params->src_or_dst_synch);
 262         omap_set_dma_src_params(lch, params->src_port,
 263                                 params->src_amode, params->src_start,
 264                                 params->src_ei, params->src_fi);
 265
 266         omap_set_dma_dest_params(lch, params->dst_port,
 267                                  params->dst_amode, params->dst_start,
 268                                  params->dst_ei, params->dst_fi);
 269 }
 270
 271 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 272 {
 273         if (cpu_is_omap24xx()) {
 274                 REVISIT_24XX();
 275                 return;
 276         }
 277         OMAP_DMA_CSEI_REG(lch) = eidx;
 278         OMAP_DMA_CSFI_REG(lch) = fidx;
 279 }
 280
 281 void omap_set_dma_src_data_pack(int lch, int enable)
 282 {
 283         OMAP_DMA_CSDP_REG(lch) &= ~(1 << 6);
 284         if (enable)
 285                 OMAP_DMA_CSDP_REG(lch) |= (1 << 6);
 286 }
 287
 288 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 289 {
 290         OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 7);
 291
 292         switch (burst_mode) {
 293         case OMAP_DMA_DATA_BURST_DIS:
 294                 break;
 295         case OMAP_DMA_DATA_BURST_4:
 296                 OMAP_DMA_CSDP_REG(lch) |= (0x02 << 7);
 297                 break;
 298         case OMAP_DMA_DATA_BURST_8:
 299                 /* not supported by current hardware
 300                  * w |= (0x03 << 7);
 301                  * fall through
 302                  */
 303         default:
 304                 BUG();
 305         }
 306 }
 307
 308 /* Note that dest_port is only for OMAP1 */
 309 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 310                               unsigned long dest_start,
 311                               int dst_ei, int dst_fi)
 312 {
 313         if (cpu_class_is_omap1()) {
 314                 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 9);
 315                 OMAP_DMA_CSDP_REG(lch) |= dest_port << 9;
 316         }
 317
 318         OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 14);
 319         OMAP_DMA_CCR_REG(lch) |= dest_amode << 14;
 320
 321         if (cpu_class_is_omap1()) {
 322                 OMAP1_DMA_CDSA_U_REG(lch) = dest_start >> 16;
 323                 OMAP1_DMA_CDSA_L_REG(lch) = dest_start;
 324         }
 325
 326         if (cpu_is_omap24xx())
 327                 OMAP2_DMA_CDSA_REG(lch) = dest_start;
 328
 329         OMAP_DMA_CDEI_REG(lch) = dst_ei;
 330         OMAP_DMA_CDFI_REG(lch) = dst_fi;
 331 }
 332
 333 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 334 {
 335         if (cpu_is_omap24xx()) {
 336                 REVISIT_24XX();
 337                 return;
 338         }
 339         OMAP_DMA_CDEI_REG(lch) = eidx;
 340         OMAP_DMA_CDFI_REG(lch) = fidx;
 341 }
 342
 343 void omap_set_dma_dest_data_pack(int lch, int enable)
 344 {
 345         OMAP_DMA_CSDP_REG(lch) &= ~(1 << 13);
 346         if (enable)
 347                 OMAP_DMA_CSDP_REG(lch) |= 1 << 13;
 348 }
 349
 350 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 351 {
 352         OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 14);
 353
 354         switch (burst_mode) {
 355         case OMAP_DMA_DATA_BURST_DIS:
 356                 break;
 357         case OMAP_DMA_DATA_BURST_4:
 358                 OMAP_DMA_CSDP_REG(lch) |= (0x02 << 14);
 359                 break;
 360         case OMAP_DMA_DATA_BURST_8:
 361                 OMAP_DMA_CSDP_REG(lch) |= (0x03 << 14);
 362                 break;
 363         default:
 364                 printk(KERN_ERR "Invalid DMA burst mode\n");
 365                 BUG();
 366                 return;
 367         }
 368 }
 369
 370 static inline void omap_enable_channel_irq(int lch)
 371 {
 372         u32 status;
 373
 374         /* Read CSR to make sure it's cleared. */
 375         status = OMAP_DMA_CSR_REG(lch);
 376
 377         /* Enable some nice interrupts. */
 378         OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs;
 379
 380         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 381 }
 382
 383 static void omap_disable_channel_irq(int lch)
 384 {
 385         if (cpu_is_omap24xx())
 386                 OMAP_DMA_CICR_REG(lch) = 0;
 387 }
 388
 389 void omap_enable_dma_irq(int lch, u16 bits)
 390 {
 391         dma_chan[lch].enabled_irqs |= bits;
 392 }
 393
 394 void omap_disable_dma_irq(int lch, u16 bits)
 395 {
 396         dma_chan[lch].enabled_irqs &= ~bits;
 397 }
 398
 399 static inline void enable_lnk(int lch)
 400 {
 401         if (cpu_class_is_omap1())
 402                 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 14);
 403
 404         /* Set the ENABLE_LNK bits */
 405         if (dma_chan[lch].next_lch != -1)
 406                 OMAP_DMA_CLNK_CTRL_REG(lch) =
 407                         dma_chan[lch].next_lch | (1 << 15);
 408 }
 409
 410 static inline void disable_lnk(int lch)
 411 {
 412         /* Disable interrupts */
 413         if (cpu_class_is_omap1()) {
 414                 OMAP_DMA_CICR_REG(lch) = 0;
 415                 /* Set the STOP_LNK bit */
 416                 OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14;
 417         }
 418
 419         if (cpu_is_omap24xx()) {
 420                 omap_disable_channel_irq(lch);
 421                 /* Clear the ENABLE_LNK bit */
 422                 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15);
 423         }
 424
 425         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 426 }
 427
 428 static inline void omap2_enable_irq_lch(int lch)
 429 {
 430         u32 val;
 431
 432         if (!cpu_is_omap24xx())
 433                 return;
 434
 435         val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
 436         val |= 1 << lch;
 437         omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
 438 }
 439
 440 int omap_request_dma(int dev_id, const char *dev_name,
 441                      void (* callback)(int lch, u16 ch_status, void *data),
 442                      void *data, int *dma_ch_out)
 443 {
 444         int ch, free_ch = -1;
 445         unsigned long flags;
 446         struct omap_dma_lch *chan;
 447
 448         spin_lock_irqsave(&dma_chan_lock, flags);
 449         for (ch = 0; ch < dma_chan_count; ch++) {
 450                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 451                         free_ch = ch;
 452                         if (dev_id == 0)
 453                                 break;
 454                 }
 455         }
 456         if (free_ch == -1) {
 457                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 458                 return -EBUSY;
 459         }
 460         chan = dma_chan + free_ch;
 461         chan->dev_id = dev_id;
 462
 463         if (cpu_class_is_omap1())
 464                 clear_lch_regs(free_ch);
 465
 466         if (cpu_is_omap24xx())
 467                 omap_clear_dma(free_ch);
 468
 469         spin_unlock_irqrestore(&dma_chan_lock, flags);
 470
 471         chan->dev_name = dev_name;
 472         chan->callback = callback;
 473         chan->data = data;
 474         chan->enabled_irqs = OMAP_DMA_TOUT_IRQ | OMAP_DMA_DROP_IRQ |
 475                                 OMAP_DMA_BLOCK_IRQ;
 476
 477         if (cpu_is_omap24xx())
 478                 chan->enabled_irqs |= OMAP2_DMA_TRANS_ERR_IRQ;
 479
 480         if (cpu_is_omap16xx()) {
 481                 /* If the sync device is set, configure it dynamically. */
 482                 if (dev_id != 0) {
 483                         set_gdma_dev(free_ch + 1, dev_id);
 484                         dev_id = free_ch + 1;
 485                 }
 486                 /* Disable the 1510 compatibility mode and set the sync device
 487                  * id. */
 488                 OMAP_DMA_CCR_REG(free_ch) = dev_id | (1 << 10);
 489         } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
 490                 OMAP_DMA_CCR_REG(free_ch) = dev_id;
 491         }
 492
 493         if (cpu_is_omap24xx()) {
 494                 omap2_enable_irq_lch(free_ch);
 495
 496                 omap_enable_channel_irq(free_ch);
 497                 /* Clear the CSR register and IRQ status register */
 498                 OMAP_DMA_CSR_REG(free_ch) = 0x0;
 499                 omap_writel(~0x0, OMAP_DMA4_IRQSTATUS_L0);
 500         }
 501
 502         *dma_ch_out = free_ch;
 503
 504         return 0;
 505 }
 506
 507 void omap_free_dma(int lch)
 508 {
 509         unsigned long flags;
 510
 511         spin_lock_irqsave(&dma_chan_lock, flags);
 512         if (dma_chan[lch].dev_id == -1) {
 513                 printk("omap_dma: trying to free nonallocated DMA channel %d\n",
 514                        lch);
 515                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 516                 return;
 517         }
 518         dma_chan[lch].dev_id = -1;
 519         dma_chan[lch].next_lch = -1;
 520         dma_chan[lch].callback = NULL;
 521         spin_unlock_irqrestore(&dma_chan_lock, flags);
 522
 523         if (cpu_class_is_omap1()) {
 524                 /* Disable all DMA interrupts for the channel. */
 525                 OMAP_DMA_CICR_REG(lch) = 0;
 526                 /* Make sure the DMA transfer is stopped. */
 527                 OMAP_DMA_CCR_REG(lch) = 0;
 528         }
 529
 530         if (cpu_is_omap24xx()) {
 531                 u32 val;
 532                 /* Disable interrupts */
 533                 val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
 534                 val &= ~(1 << lch);
 535                 omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
 536
 537                 /* Clear the CSR register and IRQ status register */
 538                 OMAP_DMA_CSR_REG(lch) = 0x0;
 539
 540                 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
 541                 val |= 1 << lch;
 542                 omap_writel(val, OMAP_DMA4_IRQSTATUS_L0);
 543
 544                 /* Disable all DMA interrupts for the channel. */
 545                 OMAP_DMA_CICR_REG(lch) = 0;
 546
 547                 /* Make sure the DMA transfer is stopped. */
 548                 OMAP_DMA_CCR_REG(lch) = 0;
 549                 omap_clear_dma(lch);
 550         }
 551 }
 552
 553 /*
 554  * Clears any DMA state so the DMA engine is ready to restart with new buffers
 555  * through omap_start_dma(). Any buffers in flight are discarded.
 556  */
 557 void omap_clear_dma(int lch)
 558 {
 559         unsigned long flags;
 560
 561         local_irq_save(flags);
 562
 563         if (cpu_class_is_omap1()) {
 564                 int status;
 565                 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
 566
 567                 /* Clear pending interrupts */
 568                 status = OMAP_DMA_CSR_REG(lch);
 569         }
 570
 571         if (cpu_is_omap24xx()) {
 572                 int i;
 573                 u32 lch_base = OMAP24XX_DMA_BASE + lch * 0x60 + 0x80;
 574                 for (i = 0; i < 0x44; i += 4)
 575                         omap_writel(0, lch_base + i);
 576         }
 577
 578         local_irq_restore(flags);
 579 }
 580
 581 void omap_start_dma(int lch)
 582 {
 583         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 584                 int next_lch, cur_lch;
 585                 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
 586
 587                 dma_chan_link_map[lch] = 1;
 588                 /* Set the link register of the first channel */
 589                 enable_lnk(lch);
 590
 591                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 592                 cur_lch = dma_chan[lch].next_lch;
 593                 do {
 594                         next_lch = dma_chan[cur_lch].next_lch;
 595
 596                         /* The loop case: we've been here already */
 597                         if (dma_chan_link_map[cur_lch])
 598                                 break;
 599                         /* Mark the current channel */
 600                         dma_chan_link_map[cur_lch] = 1;
 601
 602                         enable_lnk(cur_lch);
 603                         omap_enable_channel_irq(cur_lch);
 604
 605                         cur_lch = next_lch;
 606                 } while (next_lch != -1);
 607         } else if (cpu_is_omap24xx()) {
 608                 /* Errata: Need to write lch even if not using chaining */
 609                 OMAP_DMA_CLNK_CTRL_REG(lch) = lch;
 610         }
 611
 612         omap_enable_channel_irq(lch);
 613
 614         /* Errata: On ES2.0 BUFFERING disable must be set.
 615          * This will always fail on ES1.0 */
 616         if (cpu_is_omap24xx()) {
 617                 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
 618         }
 619
 620         OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
 621
 622         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 623 }
 624
 625 void omap_stop_dma(int lch)
 626 {
 627         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 628                 int next_lch, cur_lch = lch;
 629                 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
 630
 631                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 632                 do {
 633                         /* The loop case: we've been here already */
 634                         if (dma_chan_link_map[cur_lch])
 635                                 break;
 636                         /* Mark the current channel */
 637                         dma_chan_link_map[cur_lch] = 1;
 638
 639                         disable_lnk(cur_lch);
 640
 641                         next_lch = dma_chan[cur_lch].next_lch;
 642                         cur_lch = next_lch;
 643                 } while (next_lch != -1);
 644
 645                 return;
 646         }
 647
 648         /* Disable all interrupts on the channel */
 649         if (cpu_class_is_omap1())
 650                 OMAP_DMA_CICR_REG(lch) = 0;
 651
 652         OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
 653         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 654 }
 655
 656 /*
 657  * Returns current physical source address for the given DMA channel.
 658  * If the channel is running the caller must disable interrupts prior calling
 659  * this function and process the returned value before re-enabling interrupt to
 660  * prevent races with the interrupt handler. Note that in continuous mode there
 661  * is a chance for CSSA_L register overflow inbetween the two reads resulting
 662  * in incorrect return value.
 663  */
 664 dma_addr_t omap_get_dma_src_pos(int lch)
 665 {
 666         dma_addr_t offset;
 667
 668         if (cpu_class_is_omap1())
 669                 offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) |
 670                                        (OMAP1_DMA_CSSA_U_REG(lch) << 16));
 671
 672         if (cpu_is_omap24xx())
 673                 offset = OMAP_DMA_CSAC_REG(lch);
 674
 675         return offset;
 676 }
 677
 678 /*
 679  * Returns current physical destination address for the given DMA channel.
 680  * If the channel is running the caller must disable interrupts prior calling
 681  * this function and process the returned value before re-enabling interrupt to
 682  * prevent races with the interrupt handler. Note that in continuous mode there
 683  * is a chance for CDSA_L register overflow inbetween the two reads resulting
 684  * in incorrect return value.
 685  */
 686 dma_addr_t omap_get_dma_dst_pos(int lch)
 687 {
 688         dma_addr_t offset;
 689
 690         if (cpu_class_is_omap1())
 691                 offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) |
 692                                        (OMAP1_DMA_CDSA_U_REG(lch) << 16));
 693
 694         if (cpu_is_omap24xx())
 695                 offset = OMAP2_DMA_CDSA_REG(lch);
 696
 697         return offset;
 698 }
 699
 700 /*
 701  * Returns current source transfer counting for the given DMA channel.
 702  * Can be used to monitor the progress of a transfer inside a block.
 703  * It must be called with disabled interrupts.
 704  */
 705 int omap_get_dma_src_addr_counter(int lch)
 706 {
 707         return (dma_addr_t) OMAP_DMA_CSAC_REG(lch);
 708 }
 709
 710 int omap_dma_running(void)
 711 {
 712         int lch;
 713
 714         /* Check if LCD DMA is running */
 715         if (cpu_is_omap16xx())
 716                 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
 717                         return 1;
 718
 719         for (lch = 0; lch < dma_chan_count; lch++)
 720                 if (OMAP_DMA_CCR_REG(lch) & OMAP_DMA_CCR_EN)
 721                         return 1;
 722
 723         return 0;
 724 }
 725
 726 /*
 727  * lch_queue DMA will start right after lch_head one is finished.
 728  * For this DMA link to start, you still need to start (see omap_start_dma)
 729  * the first one. That will fire up the entire queue.
 730  */
 731 void omap_dma_link_lch (int lch_head, int lch_queue)
 732 {
 733         if (omap_dma_in_1510_mode()) {
 734                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
 735                 BUG();
 736                 return;
 737         }
 738
 739         if ((dma_chan[lch_head].dev_id == -1) ||
 740             (dma_chan[lch_queue].dev_id == -1)) {
 741                 printk(KERN_ERR "omap_dma: trying to link "
 742                        "non requested channels\n");
 743                 dump_stack();
 744         }
 745
 746         dma_chan[lch_head].next_lch = lch_queue;
 747 }
 748
 749 /*
 750  * Once the DMA queue is stopped, we can destroy it.
 751  */
 752 void omap_dma_unlink_lch (int lch_head, int lch_queue)
 753 {
 754         if (omap_dma_in_1510_mode()) {
 755                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
 756                 BUG();
 757                 return;
 758         }
 759
 760         if (dma_chan[lch_head].next_lch != lch_queue ||
 761             dma_chan[lch_head].next_lch == -1) {
 762                 printk(KERN_ERR "omap_dma: trying to unlink "
 763                        "non linked channels\n");
 764                 dump_stack();
 765         }
 766
 767
 768         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
 769             (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
 770                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
 771                        "before unlinking\n");
 772                 dump_stack();
 773         }
 774
 775         dma_chan[lch_head].next_lch = -1;
 776 }
 777
 778 /*----------------------------------------------------------------------------*/
 779
 780 #ifdef CONFIG_ARCH_OMAP1
 781
 782 static int omap1_dma_handle_ch(int ch)
 783 {
 784         u16 csr;
 785
 786         if (enable_1510_mode && ch >= 6) {
 787                 csr = dma_chan[ch].saved_csr;
 788                 dma_chan[ch].saved_csr = 0;
 789         } else
 790                 csr = OMAP_DMA_CSR_REG(ch);
 791         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
 792                 dma_chan[ch + 6].saved_csr = csr >> 7;
 793                 csr &= 0x7f;
 794         }
 795         if ((csr & 0x3f) == 0)
 796                 return 0;
 797         if (unlikely(dma_chan[ch].dev_id == -1)) {
 798                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
 799                        "%d (CSR %04x)\n", ch, csr);
 800                 return 0;
 801         }
 802         if (unlikely(csr & OMAP_DMA_TOUT_IRQ))
 803                 printk(KERN_WARNING "DMA timeout with device %d\n",
 804                        dma_chan[ch].dev_id);
 805         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
 806                 printk(KERN_WARNING "DMA synchronization event drop occurred "
 807                        "with device %d\n", dma_chan[ch].dev_id);
 808         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
 809                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
 810         if (likely(dma_chan[ch].callback != NULL))
 811                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
 812         return 1;
 813 }
 814
 815 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id,
 816                                          struct pt_regs *regs)
 817 {
 818         int ch = ((int) dev_id) - 1;
 819         int handled = 0;
 820
 821         for (;;) {
 822                 int handled_now = 0;
 823
 824                 handled_now += omap1_dma_handle_ch(ch);
 825                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
 826                         handled_now += omap1_dma_handle_ch(ch + 6);
 827                 if (!handled_now)
 828                         break;
 829                 handled += handled_now;
 830         }
 831
 832         return handled ? IRQ_HANDLED : IRQ_NONE;
 833 }
 834
 835 #else
 836 #define omap1_dma_irq_handler   NULL
 837 #endif
 838
 839 #ifdef CONFIG_ARCH_OMAP2
 840
 841 static int omap2_dma_handle_ch(int ch)
 842 {
 843         u32 status = OMAP_DMA_CSR_REG(ch);
 844         u32 val;
 845
 846         if (!status)
 847                 return 0;
 848         if (unlikely(dma_chan[ch].dev_id == -1))
 849                 return 0;
 850         /* REVISIT: According to 24xx TRM, there's no TOUT_IE */
 851         if (unlikely(status & OMAP_DMA_TOUT_IRQ))
 852                 printk(KERN_INFO "DMA timeout with device %d\n",
 853                        dma_chan[ch].dev_id);
 854         if (unlikely(status & OMAP_DMA_DROP_IRQ))
 855                 printk(KERN_INFO
 856                        "DMA synchronization event drop occurred with device "
 857                        "%d\n", dma_chan[ch].dev_id);
 858
 859         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ))
 860                 printk(KERN_INFO "DMA transaction error with device %d\n",
 861                        dma_chan[ch].dev_id);
 862
 863         OMAP_DMA_CSR_REG(ch) = 0x20;
 864
 865         val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
 866         /* ch in this function is from 0-31 while in register it is 1-32 */
 867         val = 1 << (ch);
 868         omap_writel(val, OMAP_DMA4_IRQSTATUS_L0);
 869
 870         if (likely(dma_chan[ch].callback != NULL))
 871                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
 872
 873         return 0;
 874 }
 875
 876 /* STATUS register count is from 1-32 while our is 0-31 */
 877 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id,
 878                                          struct pt_regs *regs)
 879 {
 880         u32 val;
 881         int i;
 882
 883         val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
 884
 885         for (i = 1; i <= OMAP_LOGICAL_DMA_CH_COUNT; i++) {
 886                 int active = val & (1 << (i - 1));
 887                 if (active)
 888                         omap2_dma_handle_ch(i - 1);
 889         }
 890
 891         return IRQ_HANDLED;
 892 }
 893
 894 static struct irqaction omap24xx_dma_irq = {
 895         .name = "DMA",
 896         .handler = omap2_dma_irq_handler,
 897         .flags = SA_INTERRUPT
 898 };
 899
 900 #else
 901 static struct irqaction omap24xx_dma_irq;
 902 #endif
 903
 904 /*----------------------------------------------------------------------------*/
 905
 906 static struct lcd_dma_info {
 907         spinlock_t lock;
 908         int reserved;
 909         void (* callback)(u16 status, void *data);
 910         void *cb_data;
 911
 912         int active;
 913         unsigned long addr, size;
 914         int rotate, data_type, xres, yres;
 915         int vxres;
 916         int mirror;
 917         int xscale, yscale;
 918         int ext_ctrl;
 919         int src_port;
 920         int single_transfer;
 921 } lcd_dma;
 922
 923 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
 924                          int data_type)
 925 {
 926         lcd_dma.addr = addr;
 927         lcd_dma.data_type = data_type;
 928         lcd_dma.xres = fb_xres;
 929         lcd_dma.yres = fb_yres;
 930 }
 931
 932 void omap_set_lcd_dma_src_port(int port)
 933 {
 934         lcd_dma.src_port = port;
 935 }
 936
 937 void omap_set_lcd_dma_ext_controller(int external)
 938 {
 939         lcd_dma.ext_ctrl = external;
 940 }
 941
 942 void omap_set_lcd_dma_single_transfer(int single)
 943 {
 944         lcd_dma.single_transfer = single;
 945 }
 946
 947
 948 void omap_set_lcd_dma_b1_rotation(int rotate)
 949 {
 950         if (omap_dma_in_1510_mode()) {
 951                 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
 952                 BUG();
 953                 return;
 954         }
 955         lcd_dma.rotate = rotate;
 956 }
 957
 958 void omap_set_lcd_dma_b1_mirror(int mirror)
 959 {
 960         if (omap_dma_in_1510_mode()) {
 961                 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
 962                 BUG();
 963         }
 964         lcd_dma.mirror = mirror;
 965 }
 966
 967 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
 968 {
 969         if (omap_dma_in_1510_mode()) {
 970                 printk(KERN_ERR "DMA virtual resulotion is not supported "
 971                                 "in 1510 mode\n");
 972                 BUG();
 973         }
 974         lcd_dma.vxres = vxres;
 975 }
 976
 977 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
 978 {
 979         if (omap_dma_in_1510_mode()) {
 980                 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
 981                 BUG();
 982         }
 983         lcd_dma.xscale = xscale;
 984         lcd_dma.yscale = yscale;
 985 }
 986
 987 static void set_b1_regs(void)
 988 {
 989         unsigned long top, bottom;
 990         int es;
 991         u16 w;
 992         unsigned long en, fn;
 993         long ei, fi;
 994         unsigned long vxres;
 995         unsigned int xscale, yscale;
 996
 997         switch (lcd_dma.data_type) {
 998         case OMAP_DMA_DATA_TYPE_S8:
 999                 es = 1;
1000                 break;
1001         case OMAP_DMA_DATA_TYPE_S16:
1002                 es = 2;
1003                 break;
1004         case OMAP_DMA_DATA_TYPE_S32:
1005                 es = 4;
1006                 break;
1007         default:
1008                 BUG();
1009                 return;
1010         }
1011
1012         vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
1013         xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
1014         yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
1015         BUG_ON(vxres < lcd_dma.xres);
1016 #define PIXADDR(x,y) (lcd_dma.addr + ((y) * vxres * yscale + (x) * xscale) * es)
1017 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
1018         switch (lcd_dma.rotate) {
1019         case 0:
1020                 if (!lcd_dma.mirror) {
1021                         top = PIXADDR(0, 0);
1022                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1023                         /* 1510 DMA requires the bottom address to be 2 more
1024                          * than the actual last memory access location. */
1025                         if (omap_dma_in_1510_mode() &&
1026                             lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
1027                                 bottom += 2;
1028                         ei = PIXSTEP(0, 0, 1, 0);
1029                         fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
1030                 } else {
1031                         top = PIXADDR(lcd_dma.xres - 1, 0);
1032                         bottom = PIXADDR(0, lcd_dma.yres - 1);
1033                         ei = PIXSTEP(1, 0, 0, 0);
1034                         fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
1035                 }
1036                 en = lcd_dma.xres;
1037                 fn = lcd_dma.yres;
1038                 break;
1039         case 90:
1040                 if (!lcd_dma.mirror) {
1041                         top = PIXADDR(0, lcd_dma.yres - 1);
1042                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
1043                         ei = PIXSTEP(0, 1, 0, 0);
1044                         fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
1045                 } else {
1046                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1047                         bottom = PIXADDR(0, 0);
1048                         ei = PIXSTEP(0, 1, 0, 0);
1049                         fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
1050                 }
1051                 en = lcd_dma.yres;
1052                 fn = lcd_dma.xres;
1053                 break;
1054         case 180:
1055                 if (!lcd_dma.mirror) {
1056                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1057                         bottom = PIXADDR(0, 0);
1058                         ei = PIXSTEP(1, 0, 0, 0);
1059                         fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
1060                 } else {
1061                         top = PIXADDR(0, lcd_dma.yres - 1);
1062                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
1063                         ei = PIXSTEP(0, 0, 1, 0);
1064                         fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
1065                 }
1066                 en = lcd_dma.xres;
1067                 fn = lcd_dma.yres;
1068                 break;
1069         case 270:
1070                 if (!lcd_dma.mirror) {
1071                         top = PIXADDR(lcd_dma.xres - 1, 0);
1072                         bottom = PIXADDR(0, lcd_dma.yres - 1);
1073                         ei = PIXSTEP(0, 0, 0, 1);
1074                         fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
1075                 } else {
1076                         top = PIXADDR(0, 0);
1077                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1078                         ei = PIXSTEP(0, 0, 0, 1);
1079                         fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
1080                 }
1081                 en = lcd_dma.yres;
1082                 fn = lcd_dma.xres;
1083                 break;
1084         default:
1085                 BUG();
1086                 return; /* Supress warning about uninitialized vars */
1087         }
1088
1089         if (omap_dma_in_1510_mode()) {
1090                 u16 l = omap_readw(OMAP1510_DMA_LCD_CTRL);
1091                 l &= ~(1 << 6);
1092                 omap_writew (l, OMAP1510_DMA_LCD_CTRL);
1093
1094                 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
1095                 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
1096                 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
1097                 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
1098
1099                 return;
1100         }
1101
1102         /* 1610 regs */
1103         omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
1104         omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
1105         omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
1106         omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
1107
1108         omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
1109         omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
1110
1111         w = omap_readw(OMAP1610_DMA_LCD_CSDP);
1112         w &= ~0x03;
1113         w |= lcd_dma.data_type;
1114         omap_writew(w, OMAP1610_DMA_LCD_CSDP);
1115
1116         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1117         /* Always set the source port as SDRAM for now*/
1118         w &= ~(0x03 << 6);
1119         if (lcd_dma.callback != NULL)
1120                 w |= 1 << 1;            /* Block interrupt enable */
1121         else
1122                 w &= ~(1 << 1);
1123         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1124
1125         if (!(lcd_dma.rotate || lcd_dma.mirror ||
1126               lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
1127                 return;
1128
1129         w = omap_readw(OMAP1610_DMA_LCD_CCR);
1130         /* Set the double-indexed addressing mode */
1131         w |= (0x03 << 12);
1132         omap_writew(w, OMAP1610_DMA_LCD_CCR);
1133
1134         omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
1135         omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
1136         omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
1137 }
1138
1139 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id,
1140                                        struct pt_regs *regs)
1141 {
1142         u16 w;
1143
1144         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1145         if (unlikely(!(w & (1 << 3)))) {
1146                 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
1147                 return IRQ_NONE;
1148         }
1149         /* Ack the IRQ */
1150         w |= (1 << 3);
1151         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1152         lcd_dma.active = 0;
1153         if (lcd_dma.callback != NULL)
1154                 lcd_dma.callback(w, lcd_dma.cb_data);
1155
1156         return IRQ_HANDLED;
1157 }
1158
1159 int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
1160                          void *data)
1161 {
1162         spin_lock_irq(&lcd_dma.lock);
1163         if (lcd_dma.reserved) {
1164                 spin_unlock_irq(&lcd_dma.lock);
1165                 printk(KERN_ERR "LCD DMA channel already reserved\n");
1166                 BUG();
1167                 return -EBUSY;
1168         }
1169         lcd_dma.reserved = 1;
1170         spin_unlock_irq(&lcd_dma.lock);
1171         lcd_dma.callback = callback;
1172         lcd_dma.cb_data = data;
1173         lcd_dma.active = 0;
1174         lcd_dma.single_transfer = 0;
1175         lcd_dma.rotate = 0;
1176         lcd_dma.vxres = 0;
1177         lcd_dma.mirror = 0;
1178         lcd_dma.xscale = 0;
1179         lcd_dma.yscale = 0;
1180         lcd_dma.ext_ctrl = 0;
1181         lcd_dma.src_port = 0;
1182
1183         return 0;
1184 }
1185
1186 void omap_free_lcd_dma(void)
1187 {
1188         spin_lock(&lcd_dma.lock);
1189         if (!lcd_dma.reserved) {
1190                 spin_unlock(&lcd_dma.lock);
1191                 printk(KERN_ERR "LCD DMA is not reserved\n");
1192                 BUG();
1193                 return;
1194         }
1195         if (!enable_1510_mode)
1196                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
1197                             OMAP1610_DMA_LCD_CCR);
1198         lcd_dma.reserved = 0;
1199         spin_unlock(&lcd_dma.lock);
1200 }
1201
1202 void omap_enable_lcd_dma(void)
1203 {
1204         u16 w;
1205
1206         /* Set the Enable bit only if an external controller is
1207          * connected. Otherwise the OMAP internal controller will
1208          * start the transfer when it gets enabled.
1209          */
1210         if (enable_1510_mode || !lcd_dma.ext_ctrl)
1211                 return;
1212
1213         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1214         w |= 1 << 8;
1215         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1216
1217         lcd_dma.active = 1;
1218
1219         w = omap_readw(OMAP1610_DMA_LCD_CCR);
1220         w |= 1 << 7;
1221         omap_writew(w, OMAP1610_DMA_LCD_CCR);
1222 }
1223
1224 void omap_setup_lcd_dma(void)
1225 {
1226         BUG_ON(lcd_dma.active);
1227         if (!enable_1510_mode) {
1228                 /* Set some reasonable defaults */
1229                 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
1230                 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
1231                 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
1232         }
1233         set_b1_regs();
1234         if (!enable_1510_mode) {
1235                 u16 w;
1236
1237                 w = omap_readw(OMAP1610_DMA_LCD_CCR);
1238                 /* If DMA was already active set the end_prog bit to have
1239                  * the programmed register set loaded into the active
1240                  * register set.
1241                  */
1242                 w |= 1 << 11;           /* End_prog */
1243                 if (!lcd_dma.single_transfer)
1244                         w |= (3 << 8);  /* Auto_init, repeat */
1245                 omap_writew(w, OMAP1610_DMA_LCD_CCR);
1246         }
1247 }
1248
1249 void omap_stop_lcd_dma(void)
1250 {
1251         u16 w;
1252
1253         lcd_dma.active = 0;
1254         if (enable_1510_mode || !lcd_dma.ext_ctrl)
1255                 return;
1256
1257         w = omap_readw(OMAP1610_DMA_LCD_CCR);
1258         w &= ~(1 << 7);
1259         omap_writew(w, OMAP1610_DMA_LCD_CCR);
1260
1261         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1262         w &= ~(1 << 8);
1263         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1264 }
1265
1266 int omap_lcd_dma_ext_running(void)
1267 {
1268         return lcd_dma.ext_ctrl && lcd_dma.active;
1269 }
1270
1271 /*----------------------------------------------------------------------------*/
1272
1273 static int __init omap_init_dma(void)
1274 {
1275         int ch, r;
1276
1277         if (cpu_is_omap15xx()) {
1278                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
1279                 dma_chan_count = 9;
1280                 enable_1510_mode = 1;
1281         } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
1282                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
1283                        omap_readw(OMAP_DMA_HW_ID));
1284                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
1285                        (omap_readw(OMAP_DMA_CAPS_0_U) << 16) |
1286                        omap_readw(OMAP_DMA_CAPS_0_L),
1287                        (omap_readw(OMAP_DMA_CAPS_1_U) << 16) |
1288                        omap_readw(OMAP_DMA_CAPS_1_L),
1289                        omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3),
1290                        omap_readw(OMAP_DMA_CAPS_4));
1291                 if (!enable_1510_mode) {
1292                         u16 w;
1293
1294                         /* Disable OMAP 3.0/3.1 compatibility mode. */
1295                         w = omap_readw(OMAP_DMA_GSCR);
1296                         w |= 1 << 3;
1297                         omap_writew(w, OMAP_DMA_GSCR);
1298                         dma_chan_count = 16;
1299                 } else
1300                         dma_chan_count = 9;
1301         } else if (cpu_is_omap24xx()) {
1302                 u8 revision = omap_readb(OMAP_DMA4_REVISION);
1303                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
1304                        revision >> 4, revision & 0xf);
1305                 dma_chan_count = OMAP_LOGICAL_DMA_CH_COUNT;
1306         } else {
1307                 dma_chan_count = 0;
1308                 return 0;
1309         }
1310
1311         memset(&lcd_dma, 0, sizeof(lcd_dma));
1312         spin_lock_init(&lcd_dma.lock);
1313         spin_lock_init(&dma_chan_lock);
1314         memset(&dma_chan, 0, sizeof(dma_chan));
1315
1316         for (ch = 0; ch < dma_chan_count; ch++) {
1317                 omap_clear_dma(ch);
1318                 dma_chan[ch].dev_id = -1;
1319                 dma_chan[ch].next_lch = -1;
1320
1321                 if (ch >= 6 && enable_1510_mode)
1322                         continue;
1323
1324                 if (cpu_class_is_omap1()) {
1325                         /* request_irq() doesn't like dev_id (ie. ch) being
1326                          * zero, so we have to kludge around this. */
1327                         r = request_irq(omap1_dma_irq[ch],
1328                                         omap1_dma_irq_handler, 0, "DMA",
1329                                         (void *) (ch + 1));
1330                         if (r != 0) {
1331                                 int i;
1332
1333                                 printk(KERN_ERR "unable to request IRQ %d "
1334                                        "for DMA (error %d)\n",
1335                                        omap1_dma_irq[ch], r);
1336                                 for (i = 0; i < ch; i++)
1337                                         free_irq(omap1_dma_irq[i],
1338                                                  (void *) (i + 1));
1339                                 return r;
1340                         }
1341                 }
1342         }
1343
1344         if (cpu_is_omap24xx())
1345                 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
1346
1347         /* FIXME: Update LCD DMA to work on 24xx */
1348         if (cpu_class_is_omap1()) {
1349                 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
1350                                 "LCD DMA", NULL);
1351                 if (r != 0) {
1352                         int i;
1353
1354                         printk(KERN_ERR "unable to request IRQ for LCD DMA "
1355                                "(error %d)\n", r);
1356                         for (i = 0; i < dma_chan_count; i++)
1357                                 free_irq(omap1_dma_irq[i], (void *) (i + 1));
1358                         return r;
1359                 }
1360         }
1361
1362         return 0;
1363 }
1364
1365 arch_initcall(omap_init_dma);
1366
1367 EXPORT_SYMBOL(omap_get_dma_src_pos);
1368 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1369 EXPORT_SYMBOL(omap_get_dma_src_addr_counter);
1370 EXPORT_SYMBOL(omap_clear_dma);
1371 EXPORT_SYMBOL(omap_set_dma_priority);
1372 EXPORT_SYMBOL(omap_request_dma);
1373 EXPORT_SYMBOL(omap_free_dma);
1374 EXPORT_SYMBOL(omap_start_dma);
1375 EXPORT_SYMBOL(omap_stop_dma);
1376 EXPORT_SYMBOL(omap_enable_dma_irq);
1377 EXPORT_SYMBOL(omap_disable_dma_irq);
1378
1379 EXPORT_SYMBOL(omap_set_dma_transfer_params);
1380 EXPORT_SYMBOL(omap_set_dma_color_mode);
1381
1382 EXPORT_SYMBOL(omap_set_dma_src_params);
1383 EXPORT_SYMBOL(omap_set_dma_src_index);
1384 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
1385 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
1386
1387 EXPORT_SYMBOL(omap_set_dma_dest_params);
1388 EXPORT_SYMBOL(omap_set_dma_dest_index);
1389 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
1390 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
1391
1392 EXPORT_SYMBOL(omap_set_dma_params);
1393
1394 EXPORT_SYMBOL(omap_dma_link_lch);
1395 EXPORT_SYMBOL(omap_dma_unlink_lch);
1396
1397 EXPORT_SYMBOL(omap_request_lcd_dma);
1398 EXPORT_SYMBOL(omap_free_lcd_dma);
1399 EXPORT_SYMBOL(omap_enable_lcd_dma);
1400 EXPORT_SYMBOL(omap_setup_lcd_dma);
1401 EXPORT_SYMBOL(omap_stop_lcd_dma);
1402 EXPORT_SYMBOL(omap_lcd_dma_ext_running);
1403 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
1404 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
1405 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
1406 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
1407 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
1408 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
1409 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
1410