2 * linux/arch/arm/mm/mmu.c
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/bootmem.h>
15 #include <linux/mman.h>
16 #include <linux/nodemask.h>
18 #include <asm/mach-types.h>
19 #include <asm/setup.h>
20 #include <asm/sizes.h>
23 #include <asm/mach/arch.h>
24 #include <asm/mach/map.h>
28 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
30 extern void _stext, _etext, __data_start, _end;
31 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
34 * empty_zero_page is a special page that is used for
35 * zero-initialized data and COW.
37 struct page *empty_zero_page;
38 EXPORT_SYMBOL(empty_zero_page);
41 * The pmd table for the upper-most set of pages.
45 #define CPOLICY_UNCACHED 0
46 #define CPOLICY_BUFFERED 1
47 #define CPOLICY_WRITETHROUGH 2
48 #define CPOLICY_WRITEBACK 3
49 #define CPOLICY_WRITEALLOC 4
51 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
52 static unsigned int ecc_mask __initdata = 0;
54 pgprot_t pgprot_kernel;
56 EXPORT_SYMBOL(pgprot_user);
57 EXPORT_SYMBOL(pgprot_kernel);
60 const char policy[16];
66 static struct cachepolicy cache_policies[] __initdata = {
70 .pmd = PMD_SECT_UNCACHED,
75 .pmd = PMD_SECT_BUFFERED,
76 .pte = PTE_BUFFERABLE,
78 .policy = "writethrough",
83 .policy = "writeback",
86 .pte = PTE_BUFFERABLE|PTE_CACHEABLE,
88 .policy = "writealloc",
91 .pte = PTE_BUFFERABLE|PTE_CACHEABLE,
96 * These are useful for identifying cache coherency
97 * problems by allowing the cache or the cache and
98 * writebuffer to be turned off. (Note: the write
99 * buffer should not be on and the cache off).
101 static void __init early_cachepolicy(char **p)
105 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
106 int len = strlen(cache_policies[i].policy);
108 if (memcmp(*p, cache_policies[i].policy, len) == 0) {
110 cr_alignment &= ~cache_policies[i].cr_mask;
111 cr_no_alignment &= ~cache_policies[i].cr_mask;
116 if (i == ARRAY_SIZE(cache_policies))
117 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
118 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
119 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
120 cachepolicy = CPOLICY_WRITEBACK;
123 set_cr(cr_alignment);
125 __early_param("cachepolicy=", early_cachepolicy);
127 static void __init early_nocache(char **__unused)
129 char *p = "buffered";
130 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
131 early_cachepolicy(&p);
133 __early_param("nocache", early_nocache);
135 static void __init early_nowrite(char **__unused)
137 char *p = "uncached";
138 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
139 early_cachepolicy(&p);
141 __early_param("nowb", early_nowrite);
143 static void __init early_ecc(char **p)
145 if (memcmp(*p, "on", 2) == 0) {
146 ecc_mask = PMD_PROTECTION;
148 } else if (memcmp(*p, "off", 3) == 0) {
153 __early_param("ecc=", early_ecc);
155 static int __init noalign_setup(char *__unused)
157 cr_alignment &= ~CR_A;
158 cr_no_alignment &= ~CR_A;
159 set_cr(cr_alignment);
162 __setup("noalign", noalign_setup);
165 void adjust_cr(unsigned long mask, unsigned long set)
173 local_irq_save(flags);
175 cr_no_alignment = (cr_no_alignment & ~mask) | set;
176 cr_alignment = (cr_alignment & ~mask) | set;
178 set_cr((get_cr() & ~mask) | set);
180 local_irq_restore(flags);
184 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE
185 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_XN|PMD_SECT_AP_WRITE
187 static struct mem_type mem_types[] = {
188 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
189 .prot_pte = PROT_PTE_DEVICE,
190 .prot_l1 = PMD_TYPE_TABLE,
191 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_UNCACHED,
194 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
195 .prot_pte = PROT_PTE_DEVICE,
196 .prot_pte_ext = PTE_EXT_TEX(2),
197 .prot_l1 = PMD_TYPE_TABLE,
198 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_TEX(2),
201 [MT_DEVICE_CACHED] = { /* ioremap_cached */
202 .prot_pte = PROT_PTE_DEVICE | L_PTE_CACHEABLE | L_PTE_BUFFERABLE,
203 .prot_l1 = PMD_TYPE_TABLE,
204 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
207 [MT_DEVICE_IXP2000] = { /* IXP2400 requires XCB=101 for on-chip I/O */
208 .prot_pte = PROT_PTE_DEVICE,
209 .prot_l1 = PMD_TYPE_TABLE,
210 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_BUFFERABLE |
214 [MT_DEVICE_WC] = { /* ioremap_wc */
215 .prot_pte = PROT_PTE_DEVICE,
216 .prot_l1 = PMD_TYPE_TABLE,
217 .prot_sect = PROT_SECT_DEVICE,
221 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
222 .domain = DOMAIN_KERNEL,
225 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
226 .domain = DOMAIN_KERNEL,
229 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
231 .prot_l1 = PMD_TYPE_TABLE,
232 .domain = DOMAIN_USER,
234 [MT_HIGH_VECTORS] = {
235 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
236 L_PTE_USER | L_PTE_EXEC,
237 .prot_l1 = PMD_TYPE_TABLE,
238 .domain = DOMAIN_USER,
241 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
242 .domain = DOMAIN_KERNEL,
245 .prot_sect = PMD_TYPE_SECT,
246 .domain = DOMAIN_KERNEL,
249 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_UNCACHED,
250 .domain = DOMAIN_KERNEL,
254 const struct mem_type *get_mem_type(unsigned int type)
256 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
260 * Adjust the PMD section entries according to the CPU in use.
262 static void __init build_mem_type_table(void)
264 struct cachepolicy *cp;
265 unsigned int cr = get_cr();
266 unsigned int user_pgprot, kern_pgprot;
267 int cpu_arch = cpu_architecture();
270 if (cpu_arch < CPU_ARCH_ARMv6) {
271 #if defined(CONFIG_CPU_DCACHE_DISABLE)
272 if (cachepolicy > CPOLICY_BUFFERED)
273 cachepolicy = CPOLICY_BUFFERED;
274 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
275 if (cachepolicy > CPOLICY_WRITETHROUGH)
276 cachepolicy = CPOLICY_WRITETHROUGH;
279 if (cpu_arch < CPU_ARCH_ARMv5) {
280 if (cachepolicy >= CPOLICY_WRITEALLOC)
281 cachepolicy = CPOLICY_WRITEBACK;
286 * On non-Xscale3 ARMv5-and-older systems, use CB=01
287 * (Uncached/Buffered) for ioremap_wc() mappings. On XScale3
288 * and ARMv6+, use TEXCB=00100 mappings (Inner/Outer Uncacheable
289 * in xsc3 parlance, Uncached Normal in ARMv6 parlance).
291 if (cpu_is_xsc3() || cpu_arch >= CPU_ARCH_ARMv6) {
292 mem_types[MT_DEVICE_WC].prot_pte_ext |= PTE_EXT_TEX(1);
293 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
295 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_BUFFERABLE;
296 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
300 * ARMv5 and lower, bit 4 must be set for page tables.
301 * (was: cache "update-able on write" bit on ARM610)
302 * However, Xscale cores require this bit to be cleared.
304 if (cpu_is_xscale()) {
305 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
306 mem_types[i].prot_sect &= ~PMD_BIT4;
307 mem_types[i].prot_l1 &= ~PMD_BIT4;
309 } else if (cpu_arch < CPU_ARCH_ARMv6) {
310 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
311 if (mem_types[i].prot_l1)
312 mem_types[i].prot_l1 |= PMD_BIT4;
313 if (mem_types[i].prot_sect)
314 mem_types[i].prot_sect |= PMD_BIT4;
318 cp = &cache_policies[cachepolicy];
319 kern_pgprot = user_pgprot = cp->pte;
322 * Enable CPU-specific coherency if supported.
323 * (Only available on XSC3 at the moment.)
325 if (arch_is_coherent()) {
327 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
328 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
333 * ARMv6 and above have extended page tables.
335 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
337 * Mark cache clean areas and XIP ROM read only
338 * from SVC mode and no access from userspace.
340 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
341 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
342 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
345 * Mark the device area as "shared device"
347 mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE;
348 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
352 * Mark memory with the "shared" attribute for SMP systems
354 user_pgprot |= L_PTE_SHARED;
355 kern_pgprot |= L_PTE_SHARED;
356 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
360 for (i = 0; i < 16; i++) {
361 unsigned long v = pgprot_val(protection_map[i]);
362 v = (v & ~(L_PTE_BUFFERABLE|L_PTE_CACHEABLE)) | user_pgprot;
363 protection_map[i] = __pgprot(v);
366 mem_types[MT_LOW_VECTORS].prot_pte |= kern_pgprot;
367 mem_types[MT_HIGH_VECTORS].prot_pte |= kern_pgprot;
369 if (cpu_arch >= CPU_ARCH_ARMv5) {
372 * Only use write-through for non-SMP systems
374 mem_types[MT_LOW_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
375 mem_types[MT_HIGH_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
378 mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1);
381 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
382 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
383 L_PTE_DIRTY | L_PTE_WRITE |
384 L_PTE_EXEC | kern_pgprot);
386 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
387 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
388 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
389 mem_types[MT_ROM].prot_sect |= cp->pmd;
393 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
397 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
400 printk("Memory policy: ECC %sabled, Data cache %s\n",
401 ecc_mask ? "en" : "dis", cp->policy);
403 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
404 struct mem_type *t = &mem_types[i];
406 t->prot_l1 |= PMD_DOMAIN(t->domain);
408 t->prot_sect |= PMD_DOMAIN(t->domain);
412 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
414 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
415 unsigned long end, unsigned long pfn,
416 const struct mem_type *type)
420 if (pmd_none(*pmd)) {
421 pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t));
422 __pmd_populate(pmd, __pa(pte) | type->prot_l1);
425 pte = pte_offset_kernel(pmd, addr);
427 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)),
430 } while (pte++, addr += PAGE_SIZE, addr != end);
433 static void __init alloc_init_section(pgd_t *pgd, unsigned long addr,
434 unsigned long end, unsigned long phys,
435 const struct mem_type *type)
437 pmd_t *pmd = pmd_offset(pgd, addr);
440 * Try a section mapping - end, addr and phys must all be aligned
441 * to a section boundary. Note that PMDs refer to the individual
442 * L1 entries, whereas PGDs refer to a group of L1 entries making
443 * up one logical pointer to an L2 table.
445 if (((addr | end | phys) & ~SECTION_MASK) == 0) {
448 if (addr & SECTION_SIZE)
452 *pmd = __pmd(phys | type->prot_sect);
453 phys += SECTION_SIZE;
454 } while (pmd++, addr += SECTION_SIZE, addr != end);
459 * No need to loop; pte's aren't interested in the
460 * individual L1 entries.
462 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
466 static void __init create_36bit_mapping(struct map_desc *md,
467 const struct mem_type *type)
469 unsigned long phys, addr, length, end;
473 phys = (unsigned long)__pfn_to_phys(md->pfn);
474 length = PAGE_ALIGN(md->length);
476 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
477 printk(KERN_ERR "MM: CPU does not support supersection "
478 "mapping for 0x%08llx at 0x%08lx\n",
479 __pfn_to_phys((u64)md->pfn), addr);
483 /* N.B. ARMv6 supersections are only defined to work with domain 0.
484 * Since domain assignments can in fact be arbitrary, the
485 * 'domain == 0' check below is required to insure that ARMv6
486 * supersections are only allocated for domain 0 regardless
487 * of the actual domain assignments in use.
490 printk(KERN_ERR "MM: invalid domain in supersection "
491 "mapping for 0x%08llx at 0x%08lx\n",
492 __pfn_to_phys((u64)md->pfn), addr);
496 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
497 printk(KERN_ERR "MM: cannot create mapping for "
498 "0x%08llx at 0x%08lx invalid alignment\n",
499 __pfn_to_phys((u64)md->pfn), addr);
504 * Shift bits [35:32] of address into bits [23:20] of PMD
507 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
509 pgd = pgd_offset_k(addr);
512 pmd_t *pmd = pmd_offset(pgd, addr);
515 for (i = 0; i < 16; i++)
516 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
518 addr += SUPERSECTION_SIZE;
519 phys += SUPERSECTION_SIZE;
520 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
521 } while (addr != end);
525 * Create the page directory entries and any necessary
526 * page tables for the mapping specified by `md'. We
527 * are able to cope here with varying sizes and address
528 * offsets, and we take full advantage of sections and
531 void __init create_mapping(struct map_desc *md)
533 unsigned long phys, addr, length, end;
534 const struct mem_type *type;
537 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
538 printk(KERN_WARNING "BUG: not creating mapping for "
539 "0x%08llx at 0x%08lx in user region\n",
540 __pfn_to_phys((u64)md->pfn), md->virtual);
544 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
545 md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
546 printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
547 "overlaps vmalloc space\n",
548 __pfn_to_phys((u64)md->pfn), md->virtual);
551 type = &mem_types[md->type];
554 * Catch 36-bit addresses
556 if (md->pfn >= 0x100000) {
557 create_36bit_mapping(md, type);
561 addr = md->virtual & PAGE_MASK;
562 phys = (unsigned long)__pfn_to_phys(md->pfn);
563 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
565 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
566 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
567 "be mapped using pages, ignoring.\n",
568 __pfn_to_phys(md->pfn), addr);
572 pgd = pgd_offset_k(addr);
575 unsigned long next = pgd_addr_end(addr, end);
577 alloc_init_section(pgd, addr, next, phys, type);
581 } while (pgd++, addr != end);
585 * Create the architecture specific mappings
587 void __init iotable_init(struct map_desc *io_desc, int nr)
591 for (i = 0; i < nr; i++)
592 create_mapping(io_desc + i);
595 static int __init check_membank_valid(struct membank *mb)
598 * Check whether this memory region has non-zero size.
604 * Check whether this memory region would entirely overlap
607 if (phys_to_virt(mb->start) >= VMALLOC_MIN) {
608 printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx "
609 "(vmalloc region overlap).\n",
610 mb->start, mb->start + mb->size - 1);
615 * Check whether this memory region would partially overlap
618 if (phys_to_virt(mb->start + mb->size) < phys_to_virt(mb->start) ||
619 phys_to_virt(mb->start + mb->size) > VMALLOC_MIN) {
620 unsigned long newsize = VMALLOC_MIN - phys_to_virt(mb->start);
622 printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx "
623 "to -%.8lx (vmalloc region overlap).\n",
624 mb->start, mb->start + mb->size - 1,
625 mb->start + newsize - 1);
632 static void __init sanity_check_meminfo(struct meminfo *mi)
637 for (i = 0, j = 0; i < mi->nr_banks; i++) {
638 if (check_membank_valid(&mi->bank[i]))
639 mi->bank[j++] = mi->bank[i];
644 static inline void prepare_page_table(struct meminfo *mi)
649 * Clear out all the mappings below the kernel image.
651 for (addr = 0; addr < MODULE_START; addr += PGDIR_SIZE)
652 pmd_clear(pmd_off_k(addr));
654 #ifdef CONFIG_XIP_KERNEL
655 /* The XIP kernel is mapped in the module area -- skip over it */
656 addr = ((unsigned long)&_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
658 for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
659 pmd_clear(pmd_off_k(addr));
662 * Clear out all the kernel space mappings, except for the first
663 * memory bank, up to the end of the vmalloc region.
665 for (addr = __phys_to_virt(mi->bank[0].start + mi->bank[0].size);
666 addr < VMALLOC_END; addr += PGDIR_SIZE)
667 pmd_clear(pmd_off_k(addr));
671 * Reserve the various regions of node 0
673 void __init reserve_node_zero(pg_data_t *pgdat)
675 unsigned long res_size = 0;
678 * Register the kernel text and data with bootmem.
679 * Note that this can only be in node 0.
681 #ifdef CONFIG_XIP_KERNEL
682 reserve_bootmem_node(pgdat, __pa(&__data_start), &_end - &__data_start,
685 reserve_bootmem_node(pgdat, __pa(&_stext), &_end - &_stext,
690 * Reserve the page tables. These are already in use,
691 * and can only be in node 0.
693 reserve_bootmem_node(pgdat, __pa(swapper_pg_dir),
694 PTRS_PER_PGD * sizeof(pgd_t), BOOTMEM_DEFAULT);
697 * Hmm... This should go elsewhere, but we really really need to
698 * stop things allocating the low memory; ideally we need a better
699 * implementation of GFP_DMA which does not assume that DMA-able
700 * memory starts at zero.
702 if (machine_is_integrator() || machine_is_cintegrator())
703 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
706 * These should likewise go elsewhere. They pre-reserve the
707 * screen memory region at the start of main system memory.
709 if (machine_is_edb7211())
710 res_size = 0x00020000;
711 if (machine_is_p720t())
712 res_size = 0x00014000;
714 /* H1940 and RX3715 need to reserve this for suspend */
716 if (machine_is_h1940() || machine_is_rx3715()) {
717 reserve_bootmem_node(pgdat, 0x30003000, 0x1000,
719 reserve_bootmem_node(pgdat, 0x30081000, 0x1000,
725 * Because of the SA1111 DMA bug, we want to preserve our
726 * precious DMA-able memory...
728 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
731 reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size,
736 * Set up device the mappings. Since we clear out the page tables for all
737 * mappings above VMALLOC_END, we will remove any debug device mappings.
738 * This means you have to be careful how you debug this function, or any
739 * called function. This means you can't use any function or debugging
740 * method which may touch any device, otherwise the kernel _will_ crash.
742 static void __init devicemaps_init(struct machine_desc *mdesc)
749 * Allocate the vector page early.
751 vectors = alloc_bootmem_low_pages(PAGE_SIZE);
754 for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
755 pmd_clear(pmd_off_k(addr));
758 * Map the kernel if it is XIP.
759 * It is always first in the modulearea.
761 #ifdef CONFIG_XIP_KERNEL
762 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
763 map.virtual = MODULE_START;
764 map.length = ((unsigned long)&_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
766 create_mapping(&map);
770 * Map the cache flushing regions.
773 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
774 map.virtual = FLUSH_BASE;
776 map.type = MT_CACHECLEAN;
777 create_mapping(&map);
779 #ifdef FLUSH_BASE_MINICACHE
780 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
781 map.virtual = FLUSH_BASE_MINICACHE;
783 map.type = MT_MINICLEAN;
784 create_mapping(&map);
788 * Create a mapping for the machine vectors at the high-vectors
789 * location (0xffff0000). If we aren't using high-vectors, also
790 * create a mapping at the low-vectors virtual address.
792 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
793 map.virtual = 0xffff0000;
794 map.length = PAGE_SIZE;
795 map.type = MT_HIGH_VECTORS;
796 create_mapping(&map);
798 if (!vectors_high()) {
800 map.type = MT_LOW_VECTORS;
801 create_mapping(&map);
805 * Ask the machine support to map in the statically mapped devices.
811 * Finally flush the caches and tlb to ensure that we're in a
812 * consistent state wrt the writebuffer. This also ensures that
813 * any write-allocated cache lines in the vector page are written
814 * back. After this point, we can start to touch devices again.
816 local_flush_tlb_all();
821 * paging_init() sets up the page tables, initialises the zone memory
822 * maps, and sets up the zero page, bad page and bad page tables.
824 void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc)
828 build_mem_type_table();
829 sanity_check_meminfo(mi);
830 prepare_page_table(mi);
832 devicemaps_init(mdesc);
834 top_pmd = pmd_off_k(0xffff0000);
837 * allocate the zero page. Note that we count on this going ok.
839 zero_page = alloc_bootmem_low_pages(PAGE_SIZE);
840 memzero(zero_page, PAGE_SIZE);
841 empty_zero_page = virt_to_page(zero_page);
842 flush_dcache_page(empty_zero_page);
846 * In order to soft-boot, we need to insert a 1:1 mapping in place of
847 * the user-mode pages. This will then ensure that we have predictable
848 * results when turning the mmu off
850 void setup_mm_for_reboot(char mode)
852 unsigned long base_pmdval;
856 if (current->mm && current->mm->pgd)
857 pgd = current->mm->pgd;
861 base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
862 if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
863 base_pmdval |= PMD_BIT4;
865 for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
866 unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval;
869 pmd = pmd_off(pgd, i << PGDIR_SHIFT);
870 pmd[0] = __pmd(pmdval);
871 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
872 flush_pmd_entry(pmd);