arch/arm/mach-omap2/serial.c

   1 /*
   2  * arch/arm/mach-omap2/serial.c
   3  *
   4  * OMAP2 serial support.
   5  *
   6  * Copyright (C) 2005-2008 Nokia Corporation
   7  * Author: Paul Mundt <paul.mundt@nokia.com>
   8  *
   9  * Major rework for PM support by Kevin Hilman
  10  *
  11  * Based off of arch/arm/mach-omap/omap1/serial.c
  12  *
  13  * This file is subject to the terms and conditions of the GNU General Public
  14  * License. See the file "COPYING" in the main directory of this archive
  15  * for more details.
  16  */
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/serial_8250.h>
  20 #include <linux/serial_reg.h>
  21 #include <linux/clk.h>
  22 #include <linux/io.h>
  23
  24 #include <mach/common.h>
  25 #include <mach/board.h>
  26 #include <mach/clock.h>
  27 #include <mach/control.h>
  28
  29 #include "prm.h"
  30 #include "pm.h"
  31 #include "prm-regbits-34xx.h"
  32
  33 #define DEFAULT_TIMEOUT (2 * HZ)
  34
  35 struct omap_uart_state {
  36         int num;
  37         int can_sleep;
  38         struct timer_list timer;
  39         u32 timeout;
  40
  41         void __iomem *wk_st;
  42         void __iomem *wk_en;
  43         u32 wk_mask;
  44         u32 padconf;
  45
  46         struct clk *ick;
  47         struct clk *fck;
  48         int clocked;
  49
  50         struct plat_serial8250_port *p;
  51         struct list_head node;
  52
  53 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  54         int context_valid;
  55
  56         /* Registers to be saved/restored for OFF-mode */
  57         u16 dll;
  58         u16 dlh;
  59         u16 ier;
  60         u16 sysc;
  61         u16 scr;
  62         u16 wer;
  63 #endif
  64 };
  65
  66 static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS];
  67 static LIST_HEAD(uart_list);
  68
  69 static struct plat_serial8250_port serial_platform_data[] = {
  70         {
  71                 .membase        = IO_ADDRESS(OMAP_UART1_BASE),
  72                 .mapbase        = OMAP_UART1_BASE,
  73                 .irq            = 72,
  74                 .flags          = UPF_BOOT_AUTOCONF,
  75                 .iotype         = UPIO_MEM,
  76                 .regshift       = 2,
  77                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
  78         }, {
  79                 .membase        = IO_ADDRESS(OMAP_UART2_BASE),
  80                 .mapbase        = OMAP_UART2_BASE,
  81                 .irq            = 73,
  82                 .flags          = UPF_BOOT_AUTOCONF,
  83                 .iotype         = UPIO_MEM,
  84                 .regshift       = 2,
  85                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
  86         }, {
  87                 .membase        = IO_ADDRESS(OMAP_UART3_BASE),
  88                 .mapbase        = OMAP_UART3_BASE,
  89                 .irq            = 74,
  90                 .flags          = UPF_BOOT_AUTOCONF,
  91                 .iotype         = UPIO_MEM,
  92                 .regshift       = 2,
  93                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
  94         }, {
  95                 .flags          = 0
  96         }
  97 };
  98
  99 static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
 100                                            int offset)
 101 {
 102         offset <<= up->regshift;
 103         return (unsigned int)__raw_readb(up->membase + offset);
 104 }
 105
 106 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
 107                                     int value)
 108 {
 109         offset <<= p->regshift;
 110         __raw_writeb(value, p->membase + offset);
 111 }
 112
 113 /*
 114  * Internal UARTs need to be initialized for the 8250 autoconfig to work
 115  * properly. Note that the TX watermark initialization may not be needed
 116  * once the 8250.c watermark handling code is merged.
 117  */
 118 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
 119 {
 120         struct plat_serial8250_port *p = uart->p;
 121
 122         serial_write_reg(p, UART_OMAP_MDR1, 0x07);
 123         serial_write_reg(p, UART_OMAP_SCR, 0x08);
 124         serial_write_reg(p, UART_OMAP_MDR1, 0x00);
 125         serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
 126 }
 127
 128 #ifdef CONFIG_PM
 129 #ifdef CONFIG_ARCH_OMAP3
 130
 131 static int enable_off_mode; /* to be removed by full off-mode patches */
 132
 133 static void omap_uart_save_context(struct omap_uart_state *uart)
 134 {
 135         u16 lcr = 0;
 136         struct plat_serial8250_port *p = uart->p;
 137
 138         if (!enable_off_mode)
 139                 return;
 140
 141         lcr = serial_read_reg(p, UART_LCR);
 142         serial_write_reg(p, UART_LCR, 0xBF);
 143         uart->dll = serial_read_reg(p, UART_DLL);
 144         uart->dlh = serial_read_reg(p, UART_DLM);
 145         serial_write_reg(p, UART_LCR, lcr);
 146         uart->ier = serial_read_reg(p, UART_IER);
 147         uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
 148         uart->scr = serial_read_reg(p, UART_OMAP_SCR);
 149         uart->wer = serial_read_reg(p, UART_OMAP_WER);
 150
 151         uart->context_valid = 1;
 152 }
 153
 154 static void omap_uart_restore_context(struct omap_uart_state *uart)
 155 {
 156         u16 efr = 0;
 157         struct plat_serial8250_port *p = uart->p;
 158
 159         if (!enable_off_mode)
 160                 return;
 161
 162         if (!uart->context_valid)
 163                 return;
 164
 165         uart->context_valid = 0;
 166
 167         serial_write_reg(p, UART_OMAP_MDR1, 0x7);
 168         serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
 169         efr = serial_read_reg(p, UART_EFR);
 170         serial_write_reg(p, UART_EFR, UART_EFR_ECB);
 171         serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
 172         serial_write_reg(p, UART_IER, 0x0);
 173         serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
 174         serial_write_reg(p, UART_DLL, uart->dll);
 175         serial_write_reg(p, UART_DLM, uart->dlh);
 176         serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
 177         serial_write_reg(p, UART_IER, uart->ier);
 178         serial_write_reg(p, UART_FCR, 0xA1);
 179         serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
 180         serial_write_reg(p, UART_EFR, efr);
 181         serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
 182         serial_write_reg(p, UART_OMAP_SCR, uart->scr);
 183         serial_write_reg(p, UART_OMAP_WER, uart->wer);
 184         serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
 185         serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
 186 }
 187 #else
 188 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
 189 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
 190 #endif /* CONFIG_ARCH_OMAP3 */
 191
 192 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
 193                                           int enable)
 194 {
 195         struct plat_serial8250_port *p = uart->p;
 196         u16 sysc;
 197
 198         sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
 199         if (enable)
 200                 sysc |= 0x2 << 3;
 201         else
 202                 sysc |= 0x1 << 3;
 203
 204         serial_write_reg(p, UART_OMAP_SYSC, sysc);
 205 }
 206
 207 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
 208 {
 209         if (uart->clocked)
 210                 return;
 211
 212         clk_enable(uart->ick);
 213         clk_enable(uart->fck);
 214         uart->clocked = 1;
 215         omap_uart_restore_context(uart);
 216 }
 217
 218 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
 219 {
 220         if (!uart->clocked)
 221                 return;
 222
 223         omap_uart_save_context(uart);
 224         uart->clocked = 0;
 225         clk_disable(uart->ick);
 226         clk_disable(uart->fck);
 227 }
 228
 229 static void omap_uart_block_sleep(struct omap_uart_state *uart)
 230 {
 231         omap_uart_enable_clocks(uart);
 232
 233         omap_uart_smart_idle_enable(uart, 0);
 234         uart->can_sleep = 0;
 235         mod_timer(&uart->timer, jiffies + uart->timeout);
 236 }
 237
 238 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
 239 {
 240         if (!uart->clocked)
 241                 return;
 242
 243         omap_uart_smart_idle_enable(uart, 1);
 244         uart->can_sleep = 1;
 245         del_timer(&uart->timer);
 246 }
 247
 248 static void omap_uart_idle_timer(unsigned long data)
 249 {
 250         struct omap_uart_state *uart = (struct omap_uart_state *)data;
 251
 252         omap_uart_allow_sleep(uart);
 253 }
 254
 255 void omap_uart_prepare_idle(int num)
 256 {
 257         struct omap_uart_state *uart;
 258
 259         list_for_each_entry(uart, &uart_list, node) {
 260                 if (!clocks_off_while_idle)
 261                         continue;
 262
 263                 if (num == uart->num && uart->can_sleep) {
 264                         omap_uart_disable_clocks(uart);
 265                         return;
 266                 }
 267         }
 268 }
 269
 270 void omap_uart_resume_idle(int num)
 271 {
 272         struct omap_uart_state *uart;
 273
 274         list_for_each_entry(uart, &uart_list, node) {
 275                 if (num == uart->num) {
 276                         omap_uart_enable_clocks(uart);
 277
 278                         /* Check for IO pad wakeup */
 279                         if (cpu_is_omap34xx() && uart->padconf) {
 280                                 u16 p = omap_ctrl_readw(uart->padconf);
 281
 282                                 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
 283                                         omap_uart_block_sleep(uart);
 284                         }
 285
 286                         /* Check for normal UART wakeup */
 287                         if (__raw_readl(uart->wk_st) & uart->wk_mask)
 288                                 omap_uart_block_sleep(uart);
 289
 290                         return;
 291                 }
 292         }
 293 }
 294
 295 void omap_uart_prepare_suspend(void)
 296 {
 297         struct omap_uart_state *uart;
 298
 299         list_for_each_entry(uart, &uart_list, node) {
 300                 omap_uart_allow_sleep(uart);
 301         }
 302 }
 303
 304 int omap_uart_can_sleep(void)
 305 {
 306         struct omap_uart_state *uart;
 307         int can_sleep = 1;
 308
 309         list_for_each_entry(uart, &uart_list, node) {
 310                 if (!uart->clocked)
 311                         continue;
 312
 313                 if (!uart->can_sleep) {
 314                         can_sleep = 0;
 315                         continue;
 316                 }
 317
 318                 /* This UART can now safely sleep. */
 319                 omap_uart_allow_sleep(uart);
 320         }
 321
 322         return can_sleep;
 323 }
 324
 325 /**
 326  * omap_uart_interrupt()
 327  *
 328  * This handler is used only to detect that *any* UART interrupt has
 329  * occurred.  It does _nothing_ to handle the interrupt.  Rather,
 330  * any UART interrupt will trigger the inactivity timer so the
 331  * UART will not idle or sleep for its timeout period.
 332  *
 333  **/
 334 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
 335 {
 336         struct omap_uart_state *uart = dev_id;
 337
 338         omap_uart_block_sleep(uart);
 339
 340         return IRQ_NONE;
 341 }
 342
 343 static void omap_uart_idle_init(struct omap_uart_state *uart)
 344 {
 345         u32 v;
 346         struct plat_serial8250_port *p = uart->p;
 347         int ret;
 348
 349         uart->can_sleep = 0;
 350         uart->timeout = DEFAULT_TIMEOUT;
 351         setup_timer(&uart->timer, omap_uart_idle_timer,
 352                     (unsigned long) uart);
 353         mod_timer(&uart->timer, jiffies + uart->timeout);
 354         omap_uart_smart_idle_enable(uart, 0);
 355
 356         if (cpu_is_omap34xx()) {
 357                 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
 358                 u32 wk_mask = 0;
 359                 u32 padconf = 0;
 360
 361                 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
 362                 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
 363                 switch (uart->num) {
 364                 case 0:
 365                         wk_mask = OMAP3430_ST_UART1_MASK;
 366                         padconf = 0x182;
 367                         break;
 368                 case 1:
 369                         wk_mask = OMAP3430_ST_UART2_MASK;
 370                         padconf = 0x17a;
 371                         break;
 372                 case 2:
 373                         wk_mask = OMAP3430_ST_UART3_MASK;
 374                         padconf = 0x19e;
 375                         break;
 376                 }
 377                 uart->wk_mask = wk_mask;
 378                 uart->padconf = padconf;
 379         } else if (cpu_is_omap24xx()) {
 380                 u32 wk_mask = 0;
 381
 382                 if (cpu_is_omap2430()) {
 383                         uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
 384                         uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
 385                 } else if (cpu_is_omap2420()) {
 386                         uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
 387                         uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
 388                 }
 389                 switch (uart->num) {
 390                 case 0:
 391                         wk_mask = OMAP24XX_ST_UART1_MASK;
 392                         break;
 393                 case 1:
 394                         wk_mask = OMAP24XX_ST_UART2_MASK;
 395                         break;
 396                 case 2:
 397                         wk_mask = OMAP24XX_ST_UART3_MASK;
 398                         break;
 399                 }
 400                 uart->wk_mask = wk_mask;
 401         } else {
 402                 uart->wk_en = 0;
 403                 uart->wk_st = 0;
 404                 uart->wk_mask = 0;
 405                 uart->padconf = 0;
 406         }
 407
 408         /* Set wake-enable bit */
 409         if (uart->wk_en && uart->wk_mask) {
 410                 v = __raw_readl(uart->wk_en);
 411                 v |= uart->wk_mask;
 412                 __raw_writel(v, uart->wk_en);
 413         }
 414
 415         /* Ensure IOPAD wake-enables are set */
 416         if (cpu_is_omap34xx() && uart->padconf) {
 417                 u16 v;
 418
 419                 v = omap_ctrl_readw(uart->padconf);
 420                 v |= OMAP3_PADCONF_WAKEUPENABLE0;
 421                 omap_ctrl_writew(v, uart->padconf);
 422         }
 423
 424         p->flags |= UPF_SHARE_IRQ;
 425         ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
 426                           "serial idle", (void *)uart);
 427         WARN_ON(ret);
 428 }
 429
 430 #else
 431 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
 432 #endif /* CONFIG_PM */
 433
 434 void __init omap_serial_init(void)
 435 {
 436         int i;
 437         const struct omap_uart_config *info;
 438         char name[16];
 439
 440         /*
 441          * Make sure the serial ports are muxed on at this point.
 442          * You have to mux them off in device drivers later on
 443          * if not needed.
 444          */
 445
 446         info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
 447
 448         if (info == NULL)
 449                 return;
 450
 451         for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
 452                 struct plat_serial8250_port *p = serial_platform_data + i;
 453                 struct omap_uart_state *uart = &omap_uart[i];
 454
 455                 if (!(info->enabled_uarts & (1 << i))) {
 456                         p->membase = NULL;
 457                         p->mapbase = 0;
 458                         continue;
 459                 }
 460
 461                 sprintf(name, "uart%d_ick", i+1);
 462                 uart->ick = clk_get(NULL, name);
 463                 if (IS_ERR(uart->ick)) {
 464                         printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
 465                         uart->ick = NULL;
 466                 }
 467
 468                 sprintf(name, "uart%d_fck", i+1);
 469                 uart->fck = clk_get(NULL, name);
 470                 if (IS_ERR(uart->fck)) {
 471                         printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
 472                         uart->fck = NULL;
 473                 }
 474
 475                 if (!uart->ick || !uart->fck)
 476                         continue;
 477
 478                 uart->num = i;
 479                 p->private_data = uart;
 480                 uart->p = p;
 481                 list_add(&uart->node, &uart_list);
 482
 483                 omap_uart_enable_clocks(uart);
 484                 omap_uart_reset(uart);
 485                 omap_uart_idle_init(uart);
 486         }
 487 }
 488
 489 static struct platform_device serial_device = {
 490         .name                   = "serial8250",
 491         .id                     = PLAT8250_DEV_PLATFORM,
 492         .dev                    = {
 493                 .platform_data  = serial_platform_data,
 494         },
 495 };
 496
 497 static int __init omap_init(void)
 498 {
 499         return platform_device_register(&serial_device);
 500 }
 501 arch_initcall(omap_init);