arch/arm/mach-omap2/powerdomains34xx.h

   1 /*
   2  * OMAP34XX powerdomain definitions
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * Debugging and integration fixes by Jouni Högander
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
  16 #define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
  17
  18 /*
  19  * N.B. If powerdomains are added or removed from this file, update
  20  * the array in mach-omap2/powerdomains.h.
  21  */
  22
  23 #include <mach/powerdomain.h>
  24
  25 #include "prcm-common.h"
  26 #include "prm.h"
  27 #include "prm-regbits-34xx.h"
  28 #include "cm.h"
  29 #include "cm-regbits-34xx.h"
  30
  31 /*
  32  * 34XX-specific powerdomains, dependencies
  33  */
  34
  35 #ifdef CONFIG_ARCH_OMAP34XX
  36
  37 /*
  38  * 3430: PM_WKDEP_{PER,USBHOST}: CORE, IVA2, MPU, WKUP
  39  * (USBHOST is ES2 only)
  40  */
  41 static struct pwrdm_dep per_usbhost_wkdeps[] = {
  42         {
  43                 .pwrdm_name = "core_pwrdm",
  44                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  45         },
  46         {
  47                 .pwrdm_name = "iva2_pwrdm",
  48                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  49         },
  50         {
  51                 .pwrdm_name = "mpu_pwrdm",
  52                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  53         },
  54         {
  55                 .pwrdm_name = "wkup_pwrdm",
  56                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  57         },
  58         { NULL },
  59 };
  60
  61 /*
  62  * 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER
  63  */
  64 static struct pwrdm_dep mpu_34xx_wkdeps[] = {
  65         {
  66                 .pwrdm_name = "core_pwrdm",
  67                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  68         },
  69         {
  70                 .pwrdm_name = "iva2_pwrdm",
  71                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  72         },
  73         {
  74                 .pwrdm_name = "dss_pwrdm",
  75                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  76         },
  77         {
  78                 .pwrdm_name = "per_pwrdm",
  79                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  80         },
  81         { NULL },
  82 };
  83
  84 /*
  85  * 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER
  86  */
  87 static struct pwrdm_dep iva2_wkdeps[] = {
  88         {
  89                 .pwrdm_name = "core_pwrdm",
  90                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  91         },
  92         {
  93                 .pwrdm_name = "mpu_pwrdm",
  94                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  95         },
  96         {
  97                 .pwrdm_name = "wkup_pwrdm",
  98                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  99         },
 100         {
 101                 .pwrdm_name = "dss_pwrdm",
 102                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 103         },
 104         {
 105                 .pwrdm_name = "per_pwrdm",
 106                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 107         },
 108         { NULL },
 109 };
 110
 111
 112 /* 3430 PM_WKDEP_{CAM,DSS}: IVA2, MPU, WKUP */
 113 static struct pwrdm_dep cam_dss_wkdeps[] = {
 114         {
 115                 .pwrdm_name = "iva2_pwrdm",
 116                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 117         },
 118         {
 119                 .pwrdm_name = "mpu_pwrdm",
 120                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 121         },
 122         {
 123                 .pwrdm_name = "wkup_pwrdm",
 124                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 125         },
 126         { NULL },
 127 };
 128
 129 /* 3430: PM_WKDEP_NEON: MPU */
 130 static struct pwrdm_dep neon_wkdeps[] = {
 131         {
 132                 .pwrdm_name = "mpu_pwrdm",
 133                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 134         },
 135         { NULL },
 136 };
 137
 138
 139 /* Sleep dependency source arrays for 34xx-specific pwrdms - 34XX only */
 140
 141 /*
 142  * 3430: CM_SLEEPDEP_{DSS,PER}: MPU, IVA
 143  * 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA
 144  */
 145 static struct pwrdm_dep dss_per_usbhost_sleepdeps[] = {
 146         {
 147                 .pwrdm_name = "mpu_pwrdm",
 148                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 149         },
 150         {
 151                 .pwrdm_name = "iva2_pwrdm",
 152                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 153         },
 154         { NULL },
 155 };
 156
 157
 158 /*
 159  * Powerdomains
 160  */
 161
 162 static struct powerdomain iva2_pwrdm = {
 163         .name             = "iva2_pwrdm",
 164         .prcm_offs        = OMAP3430_IVA2_MOD,
 165         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 166         .dep_bit          = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
 167         .wkdep_srcs       = iva2_wkdeps,
 168         .pwrsts           = PWRSTS_OFF_RET_ON,
 169         .pwrsts_logic_ret = PWRSTS_OFF_RET,
 170         .banks            = 4,
 171         .pwrsts_mem_ret   = {
 172                 [0] = PWRSTS_OFF_RET,
 173                 [1] = PWRSTS_OFF_RET,
 174                 [2] = PWRSTS_OFF_RET,
 175                 [3] = PWRSTS_OFF_RET,
 176         },
 177         .pwrsts_mem_on    = {
 178                 [0] = PWRDM_POWER_ON,
 179                 [1] = PWRDM_POWER_ON,
 180                 [2] = PWRSTS_OFF_ON,
 181                 [3] = PWRDM_POWER_ON,
 182         },
 183 };
 184
 185 static struct powerdomain mpu_34xx_pwrdm = {
 186         .name             = "mpu_pwrdm",
 187         .prcm_offs        = MPU_MOD,
 188         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 189         .dep_bit          = OMAP3430_EN_MPU_SHIFT,
 190         .wkdep_srcs       = mpu_34xx_wkdeps,
 191         .pwrsts           = PWRSTS_OFF_RET_ON,
 192         .pwrsts_logic_ret = PWRSTS_OFF_RET,
 193         .banks            = 1,
 194         .pwrsts_mem_ret   = {
 195                 [0] = PWRSTS_OFF_RET,
 196         },
 197         .pwrsts_mem_on    = {
 198                 [0] = PWRSTS_OFF_ON,
 199         },
 200 };
 201
 202 /* No wkdeps or sleepdeps for 34xx core apparently */
 203 static struct powerdomain core_34xx_es1_pwrdm = {
 204         .name             = "core_pwrdm",
 205         .prcm_offs        = CORE_MOD,
 206         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
 207         .pwrsts           = PWRSTS_OFF_RET_ON,
 208         .dep_bit          = OMAP3430_EN_CORE_SHIFT,
 209         .banks            = 2,
 210         .pwrsts_mem_ret   = {
 211                 [0] = PWRSTS_OFF_RET,    /* MEM1RETSTATE */
 212                 [1] = PWRSTS_OFF_RET,    /* MEM2RETSTATE */
 213         },
 214         .pwrsts_mem_on    = {
 215                 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
 216                 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
 217         },
 218 };
 219
 220 /* No wkdeps or sleepdeps for 34xx core apparently */
 221 static struct powerdomain core_34xx_es2_pwrdm = {
 222         .name             = "core_pwrdm",
 223         .prcm_offs        = CORE_MOD,
 224         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
 225         .pwrsts           = PWRSTS_OFF_RET_ON,
 226         .dep_bit          = OMAP3430_EN_CORE_SHIFT,
 227         .flags            = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
 228         .banks            = 2,
 229         .pwrsts_mem_ret   = {
 230                 [0] = PWRSTS_OFF_RET,    /* MEM1RETSTATE */
 231                 [1] = PWRSTS_OFF_RET,    /* MEM2RETSTATE */
 232         },
 233         .pwrsts_mem_on    = {
 234                 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
 235                 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
 236         },
 237 };
 238
 239 /* Another case of bit name collisions between several registers: EN_DSS */
 240 static struct powerdomain dss_pwrdm = {
 241         .name             = "dss_pwrdm",
 242         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 243         .prcm_offs        = OMAP3430_DSS_MOD,
 244         .dep_bit          = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
 245         .wkdep_srcs       = cam_dss_wkdeps,
 246         .sleepdep_srcs    = dss_per_usbhost_sleepdeps,
 247         .pwrsts           = PWRSTS_OFF_RET_ON,
 248         .pwrsts_logic_ret = PWRDM_POWER_RET,
 249         .banks            = 1,
 250         .pwrsts_mem_ret   = {
 251                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
 252         },
 253         .pwrsts_mem_on    = {
 254                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
 255         },
 256 };
 257
 258 /*
 259  * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
 260  * possible SGX powerstate, the SGX device itself does not support
 261  * retention.
 262  */
 263 static struct powerdomain sgx_pwrdm = {
 264         .name             = "sgx_pwrdm",
 265         .prcm_offs        = OMAP3430ES2_SGX_MOD,
 266         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
 267         .wkdep_srcs       = gfx_sgx_wkdeps,
 268         .sleepdep_srcs    = cam_gfx_sleepdeps,
 269         /* XXX This is accurate for 3430 SGX, but what about GFX? */
 270         .pwrsts           = PWRSTS_OFF_ON,
 271         .pwrsts_logic_ret = PWRDM_POWER_RET,
 272         .banks            = 1,
 273         .pwrsts_mem_ret   = {
 274                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
 275         },
 276         .pwrsts_mem_on    = {
 277                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
 278         },
 279 };
 280
 281 static struct powerdomain cam_pwrdm = {
 282         .name             = "cam_pwrdm",
 283         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 284         .prcm_offs        = OMAP3430_CAM_MOD,
 285         .wkdep_srcs       = cam_dss_wkdeps,
 286         .sleepdep_srcs    = cam_gfx_sleepdeps,
 287         .pwrsts           = PWRSTS_OFF_RET_ON,
 288         .pwrsts_logic_ret = PWRDM_POWER_RET,
 289         .banks            = 1,
 290         .pwrsts_mem_ret   = {
 291                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
 292         },
 293         .pwrsts_mem_on    = {
 294                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
 295         },
 296 };
 297
 298 static struct powerdomain per_pwrdm = {
 299         .name             = "per_pwrdm",
 300         .prcm_offs        = OMAP3430_PER_MOD,
 301         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 302         .dep_bit          = OMAP3430_EN_PER_SHIFT,
 303         .wkdep_srcs       = per_usbhost_wkdeps,
 304         .sleepdep_srcs    = dss_per_usbhost_sleepdeps,
 305         .pwrsts           = PWRSTS_OFF_RET_ON,
 306         .pwrsts_logic_ret = PWRSTS_OFF_RET,
 307         .banks            = 1,
 308         .pwrsts_mem_ret   = {
 309                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
 310         },
 311         .pwrsts_mem_on    = {
 312                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
 313         },
 314 };
 315
 316 static struct powerdomain emu_pwrdm = {
 317         .name           = "emu_pwrdm",
 318         .prcm_offs      = OMAP3430_EMU_MOD,
 319         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 320 };
 321
 322 static struct powerdomain neon_pwrdm = {
 323         .name             = "neon_pwrdm",
 324         .prcm_offs        = OMAP3430_NEON_MOD,
 325         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 326         .wkdep_srcs       = neon_wkdeps,
 327         .pwrsts           = PWRSTS_OFF_RET_ON,
 328         .pwrsts_logic_ret = PWRDM_POWER_RET,
 329 };
 330
 331 static struct powerdomain usbhost_pwrdm = {
 332         .name             = "usbhost_pwrdm",
 333         .prcm_offs        = OMAP3430ES2_USBHOST_MOD,
 334         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
 335         .wkdep_srcs       = per_usbhost_wkdeps,
 336         .sleepdep_srcs    = dss_per_usbhost_sleepdeps,
 337         .pwrsts           = PWRSTS_OFF_RET_ON,
 338         .pwrsts_logic_ret = PWRDM_POWER_RET,
 339         .flags            = PWRDM_HAS_HDWR_SAR, /* for USBHOST ctrlr only */
 340         .banks            = 1,
 341         .pwrsts_mem_ret   = {
 342                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
 343         },
 344         .pwrsts_mem_on    = {
 345                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
 346         },
 347 };
 348
 349 static struct powerdomain dpll1_pwrdm = {
 350         .name           = "dpll1_pwrdm",
 351         .prcm_offs      = MPU_MOD,
 352         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 353 };
 354
 355 static struct powerdomain dpll2_pwrdm = {
 356         .name           = "dpll2_pwrdm",
 357         .prcm_offs      = OMAP3430_IVA2_MOD,
 358         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 359 };
 360
 361 static struct powerdomain dpll3_pwrdm = {
 362         .name           = "dpll3_pwrdm",
 363         .prcm_offs      = PLL_MOD,
 364         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 365 };
 366
 367 static struct powerdomain dpll4_pwrdm = {
 368         .name           = "dpll4_pwrdm",
 369         .prcm_offs      = PLL_MOD,
 370         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 371 };
 372
 373 static struct powerdomain dpll5_pwrdm = {
 374         .name           = "dpll5_pwrdm",
 375         .prcm_offs      = PLL_MOD,
 376         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
 377 };
 378
 379
 380 #endif    /* CONFIG_ARCH_OMAP34XX */
 381
 382
 383 #endif