2 * linux/arch/arm/mach-omap2/pm34xx.c
4 * OMAP3 Power Management Routines
6 * Copyright (C) 2006-2008 Nokia Corporation
7 * Tony Lindgren <tony@atomide.com>
10 * Copyright (C) 2005 Texas Instruments, Inc.
11 * Richard Woodruff <r-woodruff2@ti.com>
13 * Based on pm.c for omap1
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/suspend.h>
22 #include <linux/interrupt.h>
23 #include <linux/module.h>
24 #include <linux/list.h>
25 #include <linux/err.h>
27 #include <mach/gpio.h>
28 #include <mach/sram.h>
30 #include <mach/clockdomain.h>
31 #include <mach/powerdomain.h>
32 #include <mach/serial.h>
35 #include "cm-regbits-34xx.h"
36 #include "prm-regbits-34xx.h"
40 #include "smartreflex.h"
43 struct powerdomain *pwrdm;
46 struct list_head node;
49 static LIST_HEAD(pwrst_list);
51 static void (*_omap_sram_idle)(u32 *addr, int save_state);
53 static void (*saved_idle)(void);
55 static struct powerdomain *mpu_pwrdm;
57 /* PRCM Interrupt Handler for wakeups */
58 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
60 u32 wkst, irqstatus_mpu;
64 wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
66 iclk = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
67 fclk = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
68 cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_ICLKEN);
69 cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_FCLKEN);
70 prm_write_mod_reg(wkst, WKUP_MOD, PM_WKST);
71 while (prm_read_mod_reg(WKUP_MOD, PM_WKST));
72 cm_write_mod_reg(iclk, WKUP_MOD, CM_ICLKEN);
73 cm_write_mod_reg(fclk, WKUP_MOD, CM_FCLKEN);
77 wkst = prm_read_mod_reg(CORE_MOD, PM_WKST1);
79 iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
80 fclk = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
81 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN1);
82 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_FCLKEN1);
83 prm_write_mod_reg(wkst, CORE_MOD, PM_WKST1);
84 while (prm_read_mod_reg(CORE_MOD, PM_WKST1));
85 cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN1);
86 cm_write_mod_reg(fclk, CORE_MOD, CM_FCLKEN1);
88 wkst = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3);
90 iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
91 fclk = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
92 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN3);
93 cm_set_mod_reg_bits(wkst, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
94 prm_write_mod_reg(wkst, CORE_MOD, OMAP3430ES2_PM_WKST3);
95 while (prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3));
96 cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN3);
97 cm_write_mod_reg(fclk, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
101 wkst = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST);
103 iclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
104 fclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
105 cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_ICLKEN);
106 cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_FCLKEN);
107 prm_write_mod_reg(wkst, OMAP3430_PER_MOD, PM_WKST);
108 while (prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST));
109 cm_write_mod_reg(iclk, OMAP3430_PER_MOD, CM_ICLKEN);
110 cm_write_mod_reg(fclk, OMAP3430_PER_MOD, CM_FCLKEN);
113 if (omap_rev() > OMAP3430_REV_ES1_0) {
115 wkst = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKST);
117 iclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
119 fclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
121 cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
123 cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
125 prm_write_mod_reg(wkst, OMAP3430ES2_USBHOST_MOD,
127 while (prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
129 cm_write_mod_reg(iclk, OMAP3430ES2_USBHOST_MOD,
131 cm_write_mod_reg(fclk, OMAP3430ES2_USBHOST_MOD,
136 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
137 OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
138 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
139 OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
141 while (prm_read_mod_reg(OCP_MOD, OMAP2_PRM_IRQSTATUS_MPU_OFFSET));
146 static void omap_sram_idle(void)
148 /* Variable to tell what needs to be saved and restored
149 * in omap_sram_idle*/
150 /* save_state = 0 => Nothing to save and restored */
151 /* save_state = 1 => Only L1 and logic lost */
152 /* save_state = 2 => Only L2 lost */
153 /* save_state = 3 => L1, L2 and logic lost */
154 int save_state = 0, mpu_next_state;
156 if (!_omap_sram_idle)
159 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
160 switch (mpu_next_state) {
161 case PWRDM_POWER_RET:
162 /* No need to save context */
167 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
170 /* Disable smartreflex before entering WFI */
171 disable_smartreflex(SR1);
172 disable_smartreflex(SR2);
174 omap2_gpio_prepare_for_retention();
175 omap_uart_prepare_idle(0);
176 omap_uart_prepare_idle(1);
177 omap_uart_prepare_idle(2);
179 _omap_sram_idle(NULL, save_state);
181 omap_uart_resume_idle(2);
182 omap_uart_resume_idle(1);
183 omap_uart_resume_idle(0);
184 omap2_gpio_resume_after_retention();
186 /* Enable smartreflex after WFI */
187 enable_smartreflex(SR1);
188 enable_smartreflex(SR2);
192 * Check if functional clocks are enabled before entering
193 * sleep. This function could be behind CONFIG_PM_DEBUG
194 * when all drivers are configuring their sysconfig registers
195 * properly and using their clocks properly.
197 static int omap3_fclks_active(void)
199 u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
200 fck_cam = 0, fck_per = 0, fck_usbhost = 0;
202 fck_core1 = cm_read_mod_reg(CORE_MOD,
204 if (omap_rev() > OMAP3430_REV_ES1_0) {
205 fck_core3 = cm_read_mod_reg(CORE_MOD,
206 OMAP3430ES2_CM_FCLKEN3);
207 fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
209 fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
212 fck_sgx = cm_read_mod_reg(GFX_MOD,
213 OMAP3430ES2_CM_FCLKEN3);
214 fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
216 fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
218 fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
221 /* Ignore UART clocks. These are handled by UART core (serial.c) */
222 fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
223 fck_per &= ~OMAP3430_EN_UART3;
225 if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
226 fck_cam | fck_per | fck_usbhost)
231 static int omap3_can_sleep(void)
233 if (!enable_dyn_sleep)
235 if (!omap_uart_can_sleep())
237 if (omap3_fclks_active())
239 if (atomic_read(&sleep_block) > 0)
244 /* This sets pwrdm state (other than mpu & core. Currently only ON &
245 * RET are supported. Function is assuming that clkdm doesn't have
246 * hw_sup mode enabled. */
247 static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
250 int sleep_switch = 0;
253 if (pwrdm == NULL || IS_ERR(pwrdm))
256 while (!(pwrdm->pwrsts & (1 << state))) {
257 if (state == PWRDM_POWER_OFF)
262 cur_state = pwrdm_read_next_pwrst(pwrdm);
263 if (cur_state == state)
266 if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
267 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
269 pwrdm_wait_transition(pwrdm);
272 ret = pwrdm_set_next_pwrst(pwrdm, state);
274 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
280 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
281 pwrdm_wait_transition(pwrdm);
288 static void omap3_pm_idle(void)
293 if (!omap3_can_sleep())
296 if (omap_irq_pending())
306 static int omap3_pm_prepare(void)
308 saved_idle = pm_idle;
313 static int omap3_pm_suspend(void)
315 struct power_state *pwrst;
318 /* Read current next_pwrsts */
319 list_for_each_entry(pwrst, &pwrst_list, node)
320 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
321 /* Set ones wanted by suspend */
322 list_for_each_entry(pwrst, &pwrst_list, node) {
323 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
325 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
329 omap_uart_prepare_suspend();
333 /* Restore next_pwrsts */
334 list_for_each_entry(pwrst, &pwrst_list, node) {
335 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
336 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
337 if (state > pwrst->next_state) {
338 printk(KERN_INFO "Powerdomain (%s) didn't enter "
340 pwrst->pwrdm->name, pwrst->next_state);
345 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
347 printk(KERN_INFO "Successfully put all powerdomains "
348 "to target state\n");
353 static int omap3_pm_enter(suspend_state_t state)
358 case PM_SUSPEND_STANDBY:
360 ret = omap3_pm_suspend();
369 static void omap3_pm_finish(void)
371 pm_idle = saved_idle;
374 static struct platform_suspend_ops omap_pm_ops = {
375 .prepare = omap3_pm_prepare,
376 .enter = omap3_pm_enter,
377 .finish = omap3_pm_finish,
378 .valid = suspend_valid_only_mem,
381 static void __init prcm_setup_regs(void)
383 /* XXX Reset all wkdeps. This should be done when initializing
385 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
386 prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
387 prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
388 prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
389 prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
390 prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
391 if (omap_rev() > OMAP3430_REV_ES1_0) {
392 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
393 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
395 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
398 * Enable interface clock autoidle for all modules.
399 * Note that in the long run this should be done by clockfw
402 OMAP3430ES2_AUTO_MMC3 |
403 OMAP3430ES2_AUTO_ICR |
405 OMAP3430_AUTO_SHA12 |
409 OMAP3430_AUTO_MSPRO |
411 OMAP3430_AUTO_MCSPI4 |
412 OMAP3430_AUTO_MCSPI3 |
413 OMAP3430_AUTO_MCSPI2 |
414 OMAP3430_AUTO_MCSPI1 |
418 OMAP3430_AUTO_UART2 |
419 OMAP3430_AUTO_UART1 |
420 OMAP3430_AUTO_GPT11 |
421 OMAP3430_AUTO_GPT10 |
422 OMAP3430_AUTO_MCBSP5 |
423 OMAP3430_AUTO_MCBSP1 |
424 OMAP3430ES1_AUTO_FAC | /* This is es1 only */
425 OMAP3430_AUTO_MAILBOXES |
426 OMAP3430_AUTO_OMAPCTRL |
427 OMAP3430ES1_AUTO_FSHOSTUSB |
428 OMAP3430_AUTO_HSOTGUSB |
429 OMAP3430ES1_AUTO_D2D | /* This is es1 only */
431 CORE_MOD, CM_AUTOIDLE1);
437 OMAP3430_AUTO_SHA11 |
439 CORE_MOD, CM_AUTOIDLE2);
441 if (omap_rev() > OMAP3430_REV_ES1_0) {
443 OMAP3430ES2_AUTO_USBTLL,
444 CORE_MOD, CM_AUTOIDLE3);
450 OMAP3430_AUTO_GPIO1 |
451 OMAP3430_AUTO_32KSYNC |
452 OMAP3430_AUTO_GPT12 |
454 WKUP_MOD, CM_AUTOIDLE);
467 OMAP3430_AUTO_GPIO6 |
468 OMAP3430_AUTO_GPIO5 |
469 OMAP3430_AUTO_GPIO4 |
470 OMAP3430_AUTO_GPIO3 |
471 OMAP3430_AUTO_GPIO2 |
473 OMAP3430_AUTO_UART3 |
482 OMAP3430_AUTO_MCBSP4 |
483 OMAP3430_AUTO_MCBSP3 |
484 OMAP3430_AUTO_MCBSP2,
488 if (omap_rev() > OMAP3430_REV_ES1_0) {
490 OMAP3430ES2_AUTO_USBHOST,
491 OMAP3430ES2_USBHOST_MOD,
496 * Set all plls to autoidle. This is needed until autoidle is
499 cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
500 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
501 cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
504 cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
505 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
508 cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
513 * Enable control of expternal oscillator through
514 * sys_clkreq. In the long run clock framework should
517 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
518 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
520 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
522 /* setup wakup source */
523 prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
524 OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
526 /* No need to write EN_IO, that is always enabled */
527 prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
529 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
530 /* For some reason IO doesn't generate wakeup event even if
531 * it is selected to mpu wakeup goup */
532 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
533 OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
536 static int __init pwrdms_setup(struct powerdomain *pwrdm)
538 struct power_state *pwrst;
543 pwrst = kmalloc(sizeof(struct power_state), GFP_KERNEL);
546 pwrst->pwrdm = pwrdm;
547 pwrst->next_state = PWRDM_POWER_RET;
548 list_add(&pwrst->node, &pwrst_list);
550 if (pwrdm_has_hdwr_sar(pwrdm))
551 pwrdm_enable_hdwr_sar(pwrdm);
553 return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
556 static int __init clkdms_setup(struct clockdomain *clkdm)
558 omap2_clkdm_allow_idle(clkdm);
562 int __init omap3_pm_init(void)
564 struct power_state *pwrst, *tmp;
567 printk(KERN_ERR "Power Management for TI OMAP3.\n");
569 /* XXX prcm_setup_regs needs to be before enabling hw
570 * supervised mode for powerdomains */
573 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
574 (irq_handler_t)prcm_interrupt_handler,
575 IRQF_DISABLED, "prcm", NULL);
577 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
578 INT_34XX_PRCM_MPU_IRQ);
582 ret = pwrdm_for_each(pwrdms_setup);
584 printk(KERN_ERR "Failed to setup powerdomains\n");
588 (void) clkdm_for_each(clkdms_setup);
590 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
591 if (mpu_pwrdm == NULL) {
592 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
596 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
597 omap34xx_cpu_suspend_sz);
599 suspend_set_ops(&omap_pm_ops);
601 pm_idle = omap3_pm_idle;
606 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
607 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
608 list_del(&pwrst->node);
614 static void __init configure_vc(void)
616 prm_write_mod_reg((R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA1_SHIFT) |
617 (R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA0_SHIFT),
618 OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_SA_OFFSET);
619 prm_write_mod_reg((R_VDD2_SR_CONTROL << OMAP3430_VOLRA1_SHIFT) |
620 (R_VDD1_SR_CONTROL << OMAP3430_VOLRA0_SHIFT),
621 OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET);
623 prm_write_mod_reg((OMAP3430_VC_CMD_VAL0_ON <<
624 OMAP3430_VC_CMD_ON_SHIFT) |
625 (OMAP3430_VC_CMD_VAL0_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) |
626 (OMAP3430_VC_CMD_VAL0_RET << OMAP3430_VC_CMD_RET_SHIFT) |
627 (OMAP3430_VC_CMD_VAL0_OFF << OMAP3430_VC_CMD_OFF_SHIFT),
628 OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
630 prm_write_mod_reg((OMAP3430_VC_CMD_VAL1_ON <<
631 OMAP3430_VC_CMD_ON_SHIFT) |
632 (OMAP3430_VC_CMD_VAL1_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) |
633 (OMAP3430_VC_CMD_VAL1_RET << OMAP3430_VC_CMD_RET_SHIFT) |
634 (OMAP3430_VC_CMD_VAL1_OFF << OMAP3430_VC_CMD_OFF_SHIFT),
635 OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
637 prm_write_mod_reg(OMAP3430_CMD1 | OMAP3430_RAV1,
639 OMAP3_PRM_VC_CH_CONF_OFFSET);
641 prm_write_mod_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN | OMAP3430_SREN,
643 OMAP3_PRM_VC_I2C_CFG_OFFSET);
645 /* Setup voltctrl and other setup times */
646 prm_write_mod_reg(OMAP3430_AUTO_RET, OMAP3430_GR_MOD,
647 OMAP3_PRM_VOLTCTRL_OFFSET);
649 prm_write_mod_reg(OMAP3430_CLKSETUP_DURATION, OMAP3430_GR_MOD,
650 OMAP3_PRM_CLKSETUP_OFFSET);
651 prm_write_mod_reg((OMAP3430_VOLTSETUP_TIME2 <<
652 OMAP3430_SETUP_TIME2_SHIFT) |
653 (OMAP3430_VOLTSETUP_TIME1 <<
654 OMAP3430_SETUP_TIME1_SHIFT),
655 OMAP3430_GR_MOD, OMAP3_PRM_VOLTSETUP1_OFFSET);
657 prm_write_mod_reg(OMAP3430_VOLTOFFSET_DURATION, OMAP3430_GR_MOD,
658 OMAP3_PRM_VOLTOFFSET_OFFSET);
659 prm_write_mod_reg(OMAP3430_VOLTSETUP2_DURATION, OMAP3430_GR_MOD,
660 OMAP3_PRM_VOLTSETUP2_OFFSET);
663 static int __init omap3_pm_early_init(void)
665 prm_clear_mod_reg_bits(OMAP3430_OFFMODE_POL, OMAP3430_GR_MOD,
666 OMAP3_PRM_POLCTRL_OFFSET);
673 arch_initcall(omap3_pm_early_init);