arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * linux/arch/arm/mach-omap2/pm34xx.c
   3  *
   4  * OMAP3 Power Management Routines
   5  *
   6  * Copyright (C) 2006-2008 Nokia Corporation
   7  * Tony Lindgren <tony@atomide.com>
   8  * Jouni Hogander
   9  *
  10  * Copyright (C) 2005 Texas Instruments, Inc.
  11  * Richard Woodruff <r-woodruff2@ti.com>
  12  *
  13  * Based on pm.c for omap1
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/pm.h>
  21 #include <linux/suspend.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/module.h>
  24 #include <linux/list.h>
  25 #include <linux/err.h>
  26
  27 #include <mach/gpio.h>
  28 #include <mach/sram.h>
  29 #include <mach/pm.h>
  30 #include <mach/clockdomain.h>
  31 #include <mach/powerdomain.h>
  32
  33 #include "cm.h"
  34 #include "cm-regbits-34xx.h"
  35 #include "prm-regbits-34xx.h"
  36
  37 #include "prm.h"
  38 #include "pm.h"
  39 #include "smartreflex.h"
  40
  41 struct power_state {
  42         struct powerdomain *pwrdm;
  43         u32 next_state;
  44         u32 saved_state;
  45         struct list_head node;
  46 };
  47
  48 static LIST_HEAD(pwrst_list);
  49
  50 static void (*_omap_sram_idle)(u32 *addr, int save_state);
  51
  52 static void (*saved_idle)(void);
  53
  54 static struct powerdomain *mpu_pwrdm;
  55
  56 /* PRCM Interrupt Handler for wakeups */
  57 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
  58 {
  59         u32 wkst, irqstatus_mpu;
  60         u32 fclk, iclk;
  61
  62         /* WKUP */
  63         wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
  64         if (wkst) {
  65                 iclk = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
  66                 fclk = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
  67                 cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_ICLKEN);
  68                 cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_FCLKEN);
  69                 prm_write_mod_reg(wkst, WKUP_MOD, PM_WKST);
  70                 while (prm_read_mod_reg(WKUP_MOD, PM_WKST));
  71                 cm_write_mod_reg(iclk, WKUP_MOD, CM_ICLKEN);
  72                 cm_write_mod_reg(fclk, WKUP_MOD, CM_FCLKEN);
  73         }
  74
  75         /* CORE */
  76         wkst = prm_read_mod_reg(CORE_MOD, PM_WKST1);
  77         if (wkst) {
  78                 iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
  79                 fclk = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  80                 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN1);
  81                 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_FCLKEN1);
  82                 prm_write_mod_reg(wkst, CORE_MOD, PM_WKST1);
  83                 while (prm_read_mod_reg(CORE_MOD, PM_WKST1));
  84                 cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN1);
  85                 cm_write_mod_reg(fclk, CORE_MOD, CM_FCLKEN1);
  86         }
  87         wkst = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3);
  88         if (wkst) {
  89                 iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
  90                 fclk = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
  91                 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN3);
  92                 cm_set_mod_reg_bits(wkst, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
  93                 prm_write_mod_reg(wkst, CORE_MOD, OMAP3430ES2_PM_WKST3);
  94                 while (prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3));
  95                 cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN3);
  96                 cm_write_mod_reg(fclk, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
  97         }
  98
  99         /* PER */
 100         wkst = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST);
 101         if (wkst) {
 102                 iclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
 103                 fclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
 104                 cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_ICLKEN);
 105                 cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_FCLKEN);
 106                 prm_write_mod_reg(wkst, OMAP3430_PER_MOD, PM_WKST);
 107                 while (prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST));
 108                 cm_write_mod_reg(iclk, OMAP3430_PER_MOD, CM_ICLKEN);
 109                 cm_write_mod_reg(fclk, OMAP3430_PER_MOD, CM_FCLKEN);
 110         }
 111
 112         if (omap_rev() > OMAP3430_REV_ES1_0) {
 113                 /* USBHOST */
 114                 wkst = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKST);
 115                 if (wkst) {
 116                         iclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 117                                                CM_ICLKEN);
 118                         fclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 119                                                CM_FCLKEN);
 120                         cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
 121                                          CM_ICLKEN);
 122                         cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
 123                                          CM_FCLKEN);
 124                         prm_write_mod_reg(wkst, OMAP3430ES2_USBHOST_MOD,
 125                                           PM_WKST);
 126                         while (prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 127                                                 PM_WKST));
 128                         cm_write_mod_reg(iclk, OMAP3430ES2_USBHOST_MOD,
 129                                          CM_ICLKEN);
 130                         cm_write_mod_reg(fclk, OMAP3430ES2_USBHOST_MOD,
 131                                          CM_FCLKEN);
 132                 }
 133         }
 134
 135         irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
 136                                         OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
 137         prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
 138                                         OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
 139
 140         while (prm_read_mod_reg(OCP_MOD, OMAP2_PRM_IRQSTATUS_MPU_OFFSET));
 141
 142         return IRQ_HANDLED;
 143 }
 144
 145 static void omap_sram_idle(void)
 146 {
 147         /* Variable to tell what needs to be saved and restored
 148          * in omap_sram_idle*/
 149         /* save_state = 0 => Nothing to save and restored */
 150         /* save_state = 1 => Only L1 and logic lost */
 151         /* save_state = 2 => Only L2 lost */
 152         /* save_state = 3 => L1, L2 and logic lost */
 153         int save_state = 0, mpu_next_state;
 154
 155         if (!_omap_sram_idle)
 156                 return;
 157
 158         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 159         switch (mpu_next_state) {
 160         case PWRDM_POWER_RET:
 161                 /* No need to save context */
 162                 save_state = 0;
 163                 break;
 164         default:
 165                 /* Invalid state */
 166                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 167                 return;
 168         }
 169         /* Disable smartreflex before entering WFI */
 170         disable_smartreflex(SR1);
 171         disable_smartreflex(SR2);
 172
 173         omap2_gpio_prepare_for_retention();
 174
 175         _omap_sram_idle(NULL, save_state);
 176
 177         omap2_gpio_resume_after_retention();
 178
 179         /* Enable smartreflex after WFI */
 180         enable_smartreflex(SR1);
 181         enable_smartreflex(SR2);
 182 }
 183
 184 /*
 185  * Check if functional clocks are enabled before entering
 186  * sleep. This function could be behind CONFIG_PM_DEBUG
 187  * when all drivers are configuring their sysconfig registers
 188  * properly and using their clocks properly.
 189  */
 190 static int omap3_fclks_active(void)
 191 {
 192         u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
 193                 fck_cam = 0, fck_per = 0, fck_usbhost = 0;
 194
 195         fck_core1 = cm_read_mod_reg(CORE_MOD,
 196                                     CM_FCLKEN1);
 197         if (omap_rev() > OMAP3430_REV_ES1_0) {
 198                 fck_core3 = cm_read_mod_reg(CORE_MOD,
 199                                             OMAP3430ES2_CM_FCLKEN3);
 200                 fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
 201                                           CM_FCLKEN);
 202                 fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 203                                               CM_FCLKEN);
 204         } else
 205                 fck_sgx = cm_read_mod_reg(GFX_MOD,
 206                                           OMAP3430ES2_CM_FCLKEN3);
 207         fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
 208                                   CM_FCLKEN);
 209         fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
 210                                   CM_FCLKEN);
 211         fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
 212                                   CM_FCLKEN);
 213         if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
 214             fck_cam | fck_per | fck_usbhost)
 215                 return 1;
 216         return 0;
 217 }
 218
 219 static int omap3_can_sleep(void)
 220 {
 221         if (!enable_dyn_sleep)
 222                 return 0;
 223         if (omap3_fclks_active())
 224                 return 0;
 225         if (atomic_read(&sleep_block) > 0)
 226                 return 0;
 227         return 1;
 228 }
 229
 230 /* This sets pwrdm state (other than mpu & core. Currently only ON &
 231  * RET are supported. Function is assuming that clkdm doesn't have
 232  * hw_sup mode enabled. */
 233 static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
 234 {
 235         u32 cur_state;
 236         int sleep_switch = 0;
 237         int ret = 0;
 238
 239         if (pwrdm == NULL || IS_ERR(pwrdm))
 240                 return -EINVAL;
 241
 242         cur_state = pwrdm_read_next_pwrst(pwrdm);
 243
 244         if (cur_state == state)
 245                 return ret;
 246
 247         if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
 248                 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
 249                 sleep_switch = 1;
 250                 pwrdm_wait_transition(pwrdm);
 251         }
 252
 253         ret = pwrdm_set_next_pwrst(pwrdm, state);
 254         if (ret) {
 255                 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
 256                        pwrdm->name);
 257                 goto err;
 258         }
 259
 260         if (sleep_switch) {
 261                 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
 262                 pwrdm_wait_transition(pwrdm);
 263         }
 264
 265 err:
 266         return ret;
 267 }
 268
 269 static void omap3_pm_idle(void)
 270 {
 271         local_irq_disable();
 272         local_fiq_disable();
 273
 274         if (!omap3_can_sleep())
 275                 goto out;
 276
 277         if (omap_irq_pending())
 278                 goto out;
 279
 280         omap_sram_idle();
 281
 282 out:
 283         local_fiq_enable();
 284         local_irq_enable();
 285 }
 286
 287 static int omap3_pm_prepare(void)
 288 {
 289         saved_idle = pm_idle;
 290         pm_idle = NULL;
 291         return 0;
 292 }
 293
 294 static int omap3_pm_suspend(void)
 295 {
 296         struct power_state *pwrst;
 297         int state, ret = 0;
 298
 299         /* Read current next_pwrsts */
 300         list_for_each_entry(pwrst, &pwrst_list, node)
 301                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 302         /* Set ones wanted by suspend */
 303         list_for_each_entry(pwrst, &pwrst_list, node) {
 304                 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 305                         goto restore;
 306                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 307                         goto restore;
 308         }
 309
 310         omap_sram_idle();
 311
 312 restore:
 313         /* Restore next_pwrsts */
 314         list_for_each_entry(pwrst, &pwrst_list, node) {
 315                 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 316                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 317                 if (state != pwrst->next_state) {
 318                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 319                                "target state %d\n",
 320                                pwrst->pwrdm->name, pwrst->next_state);
 321                         ret = -1;
 322                 }
 323         }
 324         if (ret)
 325                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 326         else
 327                 printk(KERN_INFO "Successfully put all powerdomains "
 328                        "to target state\n");
 329
 330         return ret;
 331 }
 332
 333 static int omap3_pm_enter(suspend_state_t state)
 334 {
 335         int ret = 0;
 336
 337         switch (state) {
 338         case PM_SUSPEND_STANDBY:
 339         case PM_SUSPEND_MEM:
 340                 ret = omap3_pm_suspend();
 341                 break;
 342         default:
 343                 ret = -EINVAL;
 344         }
 345
 346         return ret;
 347 }
 348
 349 static void omap3_pm_finish(void)
 350 {
 351         pm_idle = saved_idle;
 352 }
 353
 354 static struct platform_suspend_ops omap_pm_ops = {
 355         .prepare        = omap3_pm_prepare,
 356         .enter          = omap3_pm_enter,
 357         .finish         = omap3_pm_finish,
 358         .valid          = suspend_valid_only_mem,
 359 };
 360
 361 static void __init prcm_setup_regs(void)
 362 {
 363         /* XXX Reset all wkdeps. This should be done when initializing
 364          * powerdomains */
 365         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
 366         prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
 367         prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
 368         prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
 369         prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
 370         prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
 371         if (omap_rev() > OMAP3430_REV_ES1_0) {
 372                 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
 373                 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 374         } else
 375                 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 376
 377         /*
 378          * Enable interface clock autoidle for all modules.
 379          * Note that in the long run this should be done by clockfw
 380          */
 381         cm_write_mod_reg(
 382                 OMAP3430ES2_AUTO_MMC3 |
 383                 OMAP3430ES2_AUTO_ICR |
 384                 OMAP3430_AUTO_AES2 |
 385                 OMAP3430_AUTO_SHA12 |
 386                 OMAP3430_AUTO_DES2 |
 387                 OMAP3430_AUTO_MMC2 |
 388                 OMAP3430_AUTO_MMC1 |
 389                 OMAP3430_AUTO_MSPRO |
 390                 OMAP3430_AUTO_HDQ |
 391                 OMAP3430_AUTO_MCSPI4 |
 392                 OMAP3430_AUTO_MCSPI3 |
 393                 OMAP3430_AUTO_MCSPI2 |
 394                 OMAP3430_AUTO_MCSPI1 |
 395                 OMAP3430_AUTO_I2C3 |
 396                 OMAP3430_AUTO_I2C2 |
 397                 OMAP3430_AUTO_I2C1 |
 398                 OMAP3430_AUTO_UART2 |
 399                 OMAP3430_AUTO_UART1 |
 400                 OMAP3430_AUTO_GPT11 |
 401                 OMAP3430_AUTO_GPT10 |
 402                 OMAP3430_AUTO_MCBSP5 |
 403                 OMAP3430_AUTO_MCBSP1 |
 404                 OMAP3430ES1_AUTO_FAC | /* This is es1 only */
 405                 OMAP3430_AUTO_MAILBOXES |
 406                 OMAP3430_AUTO_OMAPCTRL |
 407                 OMAP3430ES1_AUTO_FSHOSTUSB |
 408                 OMAP3430_AUTO_HSOTGUSB |
 409                 OMAP3430ES1_AUTO_D2D | /* This is es1 only */
 410                 OMAP3430_AUTO_SSI,
 411                 CORE_MOD, CM_AUTOIDLE1);
 412
 413         cm_write_mod_reg(
 414                 OMAP3430_AUTO_PKA |
 415                 OMAP3430_AUTO_AES1 |
 416                 OMAP3430_AUTO_RNG |
 417                 OMAP3430_AUTO_SHA11 |
 418                 OMAP3430_AUTO_DES1,
 419                 CORE_MOD, CM_AUTOIDLE2);
 420
 421         if (omap_rev() > OMAP3430_REV_ES1_0) {
 422                 cm_write_mod_reg(
 423                         OMAP3430ES2_AUTO_USBTLL,
 424                         CORE_MOD, CM_AUTOIDLE3);
 425         }
 426
 427         cm_write_mod_reg(
 428                 OMAP3430_AUTO_WDT2 |
 429                 OMAP3430_AUTO_WDT1 |
 430                 OMAP3430_AUTO_GPIO1 |
 431                 OMAP3430_AUTO_32KSYNC |
 432                 OMAP3430_AUTO_GPT12 |
 433                 OMAP3430_AUTO_GPT1 ,
 434                 WKUP_MOD, CM_AUTOIDLE);
 435
 436         cm_write_mod_reg(
 437                 OMAP3430_AUTO_DSS,
 438                 OMAP3430_DSS_MOD,
 439                 CM_AUTOIDLE);
 440
 441         cm_write_mod_reg(
 442                 OMAP3430_AUTO_CAM,
 443                 OMAP3430_CAM_MOD,
 444                 CM_AUTOIDLE);
 445
 446         cm_write_mod_reg(
 447                 OMAP3430_AUTO_GPIO6 |
 448                 OMAP3430_AUTO_GPIO5 |
 449                 OMAP3430_AUTO_GPIO4 |
 450                 OMAP3430_AUTO_GPIO3 |
 451                 OMAP3430_AUTO_GPIO2 |
 452                 OMAP3430_AUTO_WDT3 |
 453                 OMAP3430_AUTO_UART3 |
 454                 OMAP3430_AUTO_GPT9 |
 455                 OMAP3430_AUTO_GPT8 |
 456                 OMAP3430_AUTO_GPT7 |
 457                 OMAP3430_AUTO_GPT6 |
 458                 OMAP3430_AUTO_GPT5 |
 459                 OMAP3430_AUTO_GPT4 |
 460                 OMAP3430_AUTO_GPT3 |
 461                 OMAP3430_AUTO_GPT2 |
 462                 OMAP3430_AUTO_MCBSP4 |
 463                 OMAP3430_AUTO_MCBSP3 |
 464                 OMAP3430_AUTO_MCBSP2,
 465                 OMAP3430_PER_MOD,
 466                 CM_AUTOIDLE);
 467
 468         if (omap_rev() > OMAP3430_REV_ES1_0) {
 469                 cm_write_mod_reg(
 470                         OMAP3430ES2_AUTO_USBHOST,
 471                         OMAP3430ES2_USBHOST_MOD,
 472                         CM_AUTOIDLE);
 473         }
 474
 475         /*
 476          * Set all plls to autoidle. This is needed until autoidle is
 477          * enabled by clockfw
 478          */
 479         cm_write_mod_reg(1 << OMAP3430_CLKTRCTRL_IVA2_SHIFT,
 480                          OMAP3430_IVA2_MOD,
 481                          CM_AUTOIDLE2);
 482         cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
 483                          MPU_MOD,
 484                          CM_AUTOIDLE2);
 485         cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
 486                          (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
 487                          PLL_MOD,
 488                          CM_AUTOIDLE);
 489         cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
 490                          PLL_MOD,
 491                          CM_AUTOIDLE2);
 492
 493         /*
 494          * Enable control of expternal oscillator through
 495          * sys_clkreq. In the long run clock framework should
 496          * take care of this.
 497          */
 498         prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 499                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 500                              OMAP3430_GR_MOD,
 501                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 502
 503         /* setup wakup source */
 504         prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1,
 505                           WKUP_MOD, PM_WKEN);
 506         /* No need to write EN_IO, that is always enabled */
 507         prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1,
 508                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 509         /* For some reason IO doesn't generate wakeup event even if
 510          * it is selected to mpu wakeup goup */
 511         prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
 512                         OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
 513 }
 514
 515 static int __init pwrdms_setup(struct powerdomain *pwrdm)
 516 {
 517         struct power_state *pwrst;
 518
 519         if (!pwrdm->pwrsts)
 520                 return 0;
 521
 522         pwrst = kmalloc(sizeof(struct power_state), GFP_KERNEL);
 523         if (!pwrst)
 524                 return -ENOMEM;
 525         pwrst->pwrdm = pwrdm;
 526         pwrst->next_state = PWRDM_POWER_RET;
 527         list_add(&pwrst->node, &pwrst_list);
 528
 529         if (pwrdm_has_hdwr_sar(pwrdm))
 530                 pwrdm_enable_hdwr_sar(pwrdm);
 531
 532         return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 533 }
 534
 535 static int __init clkdms_setup(struct clockdomain *clkdm)
 536 {
 537         omap2_clkdm_allow_idle(clkdm);
 538         return 0;
 539 }
 540
 541 int __init omap3_pm_init(void)
 542 {
 543         struct power_state *pwrst, *tmp;
 544         int ret;
 545
 546         printk(KERN_ERR "Power Management for TI OMAP3.\n");
 547
 548         /* XXX prcm_setup_regs needs to be before enabling hw
 549          * supervised mode for powerdomains */
 550         prcm_setup_regs();
 551
 552         ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
 553                           (irq_handler_t)prcm_interrupt_handler,
 554                           IRQF_DISABLED, "prcm", NULL);
 555         if (ret) {
 556                 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
 557                        INT_34XX_PRCM_MPU_IRQ);
 558                 goto err1;
 559         }
 560
 561         ret = pwrdm_for_each(pwrdms_setup);
 562         if (ret) {
 563                 printk(KERN_ERR "Failed to setup powerdomains\n");
 564                 goto err2;
 565         }
 566
 567         (void) clkdm_for_each(clkdms_setup);
 568
 569         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 570         if (mpu_pwrdm == NULL) {
 571                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
 572                 goto err2;
 573         }
 574
 575         _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
 576                                         omap34xx_cpu_suspend_sz);
 577
 578         suspend_set_ops(&omap_pm_ops);
 579
 580         pm_idle = omap3_pm_idle;
 581
 582 err1:
 583         return ret;
 584 err2:
 585         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
 586         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
 587                 list_del(&pwrst->node);
 588                 kfree(pwrst);
 589         }
 590         return ret;
 591 }
 592
 593 static void __init configure_vc(void)
 594 {
 595         prm_write_mod_reg((R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA1_SHIFT) |
 596                         (R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA0_SHIFT),
 597                         OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_SA_OFFSET);
 598         prm_write_mod_reg((R_VDD2_SR_CONTROL << OMAP3430_VOLRA1_SHIFT) |
 599                         (R_VDD1_SR_CONTROL << OMAP3430_VOLRA0_SHIFT),
 600                         OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET);
 601
 602         prm_write_mod_reg((OMAP3430_VC_CMD_VAL0_ON <<
 603                 OMAP3430_VC_CMD_ON_SHIFT) |
 604                 (OMAP3430_VC_CMD_VAL0_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) |
 605                 (OMAP3430_VC_CMD_VAL0_RET << OMAP3430_VC_CMD_RET_SHIFT) |
 606                 (OMAP3430_VC_CMD_VAL0_OFF << OMAP3430_VC_CMD_OFF_SHIFT),
 607                 OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
 608
 609         prm_write_mod_reg((OMAP3430_VC_CMD_VAL1_ON <<
 610                 OMAP3430_VC_CMD_ON_SHIFT) |
 611                 (OMAP3430_VC_CMD_VAL1_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) |
 612                 (OMAP3430_VC_CMD_VAL1_RET << OMAP3430_VC_CMD_RET_SHIFT) |
 613                 (OMAP3430_VC_CMD_VAL1_OFF << OMAP3430_VC_CMD_OFF_SHIFT),
 614                 OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
 615
 616         prm_write_mod_reg(OMAP3430_CMD1 | OMAP3430_RAV1,
 617                                 OMAP3430_GR_MOD,
 618                                 OMAP3_PRM_VC_CH_CONF_OFFSET);
 619
 620         prm_write_mod_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN | OMAP3430_SREN,
 621                                 OMAP3430_GR_MOD,
 622                                 OMAP3_PRM_VC_I2C_CFG_OFFSET);
 623
 624         /* Setup voltctrl and other setup times */
 625         prm_write_mod_reg(OMAP3430_AUTO_RET, OMAP3430_GR_MOD,
 626                         OMAP3_PRM_VOLTCTRL_OFFSET);
 627
 628         prm_write_mod_reg(OMAP3430_CLKSETUP_DURATION, OMAP3430_GR_MOD,
 629                         OMAP3_PRM_CLKSETUP_OFFSET);
 630         prm_write_mod_reg((OMAP3430_VOLTSETUP_TIME2 <<
 631                         OMAP3430_SETUP_TIME2_SHIFT) |
 632                         (OMAP3430_VOLTSETUP_TIME1 <<
 633                         OMAP3430_SETUP_TIME1_SHIFT),
 634                         OMAP3430_GR_MOD, OMAP3_PRM_VOLTSETUP1_OFFSET);
 635
 636         prm_write_mod_reg(OMAP3430_VOLTOFFSET_DURATION, OMAP3430_GR_MOD,
 637                         OMAP3_PRM_VOLTOFFSET_OFFSET);
 638         prm_write_mod_reg(OMAP3430_VOLTSETUP2_DURATION, OMAP3430_GR_MOD,
 639                         OMAP3_PRM_VOLTSETUP2_OFFSET);
 640 }
 641
 642 static int __init omap3_pm_early_init(void)
 643 {
 644         prm_clear_mod_reg_bits(OMAP3430_OFFMODE_POL, OMAP3430_GR_MOD,
 645                                 OMAP3_PRM_POLCTRL_OFFSET);
 646
 647         configure_vc();
 648
 649         return 0;
 650 }
 651
 652 arch_initcall(omap3_pm_early_init);