arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * linux/arch/arm/mach-omap2/pm34xx.c
   3  *
   4  * OMAP3 Power Management Routines
   5  *
   6  * Copyright (C) 2006-2008 Nokia Corporation
   7  * Tony Lindgren <tony@atomide.com>
   8  * Jouni Hogander
   9  *
  10  * Copyright (C) 2005 Texas Instruments, Inc.
  11  * Richard Woodruff <r-woodruff2@ti.com>
  12  *
  13  * Based on pm.c for omap1
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/pm.h>
  21 #include <linux/suspend.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/module.h>
  24 #include <linux/list.h>
  25 #include <linux/err.h>
  26
  27 #include <mach/gpio.h>
  28 #include <mach/sram.h>
  29 #include <mach/pm.h>
  30 #include <mach/clockdomain.h>
  31 #include <mach/powerdomain.h>
  32
  33 #include "cm.h"
  34 #include "cm-regbits-34xx.h"
  35 #include "prm-regbits-34xx.h"
  36
  37 #include "prm.h"
  38 #include "pm.h"
  39 #include "smartreflex.h"
  40
  41 struct power_state {
  42         struct powerdomain *pwrdm;
  43         u32 next_state;
  44         u32 saved_state;
  45         struct list_head node;
  46 };
  47
  48 static LIST_HEAD(pwrst_list);
  49
  50 static void (*_omap_sram_idle)(u32 *addr, int save_state);
  51
  52 static void (*saved_idle)(void);
  53
  54 static struct powerdomain *mpu_pwrdm;
  55
  56 /* PRCM Interrupt Handler for wakeups */
  57 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
  58 {
  59         u32 wkst, irqstatus_mpu;
  60         u32 fclk, iclk;
  61
  62         /* WKUP */
  63         wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
  64         if (wkst) {
  65                 iclk = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
  66                 fclk = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
  67                 cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_ICLKEN);
  68                 cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_FCLKEN);
  69                 prm_write_mod_reg(wkst, WKUP_MOD, PM_WKST);
  70                 while (prm_read_mod_reg(WKUP_MOD, PM_WKST));
  71                 cm_write_mod_reg(iclk, WKUP_MOD, CM_ICLKEN);
  72                 cm_write_mod_reg(fclk, WKUP_MOD, CM_FCLKEN);
  73         }
  74
  75         /* CORE */
  76         wkst = prm_read_mod_reg(CORE_MOD, PM_WKST1);
  77         if (wkst) {
  78                 iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
  79                 fclk = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  80                 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN1);
  81                 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_FCLKEN1);
  82                 prm_write_mod_reg(wkst, CORE_MOD, PM_WKST1);
  83                 while (prm_read_mod_reg(CORE_MOD, PM_WKST1));
  84                 cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN1);
  85                 cm_write_mod_reg(fclk, CORE_MOD, CM_FCLKEN1);
  86         }
  87         wkst = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3);
  88         if (wkst) {
  89                 iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
  90                 fclk = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
  91                 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN3);
  92                 cm_set_mod_reg_bits(wkst, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
  93                 prm_write_mod_reg(wkst, CORE_MOD, OMAP3430ES2_PM_WKST3);
  94                 while (prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3));
  95                 cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN3);
  96                 cm_write_mod_reg(fclk, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
  97         }
  98
  99         /* PER */
 100         wkst = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST);
 101         if (wkst) {
 102                 iclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
 103                 fclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
 104                 cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_ICLKEN);
 105                 cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_FCLKEN);
 106                 prm_write_mod_reg(wkst, OMAP3430_PER_MOD, PM_WKST);
 107                 while (prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST));
 108                 cm_write_mod_reg(iclk, OMAP3430_PER_MOD, CM_ICLKEN);
 109                 cm_write_mod_reg(fclk, OMAP3430_PER_MOD, CM_FCLKEN);
 110         }
 111
 112         if (omap_rev() > OMAP3430_REV_ES1_0) {
 113                 /* USBHOST */
 114                 wkst = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKST);
 115                 if (wkst) {
 116                         iclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 117                                                CM_ICLKEN);
 118                         fclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 119                                                CM_FCLKEN);
 120                         cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
 121                                          CM_ICLKEN);
 122                         cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
 123                                          CM_FCLKEN);
 124                         prm_write_mod_reg(wkst, OMAP3430ES2_USBHOST_MOD,
 125                                           PM_WKST);
 126                         while (prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 127                                                 PM_WKST));
 128                         cm_write_mod_reg(iclk, OMAP3430ES2_USBHOST_MOD,
 129                                          CM_ICLKEN);
 130                         cm_write_mod_reg(fclk, OMAP3430ES2_USBHOST_MOD,
 131                                          CM_FCLKEN);
 132                 }
 133         }
 134
 135         irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
 136                                         OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
 137         prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
 138                                         OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
 139
 140         while (prm_read_mod_reg(OCP_MOD, OMAP2_PRM_IRQSTATUS_MPU_OFFSET));
 141
 142         return IRQ_HANDLED;
 143 }
 144
 145 static void omap_sram_idle(void)
 146 {
 147         /* Variable to tell what needs to be saved and restored
 148          * in omap_sram_idle*/
 149         /* save_state = 0 => Nothing to save and restored */
 150         /* save_state = 1 => Only L1 and logic lost */
 151         /* save_state = 2 => Only L2 lost */
 152         /* save_state = 3 => L1, L2 and logic lost */
 153         int save_state = 0, mpu_next_state;
 154
 155         if (!_omap_sram_idle)
 156                 return;
 157
 158         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 159         switch (mpu_next_state) {
 160         case PWRDM_POWER_RET:
 161                 /* No need to save context */
 162                 save_state = 0;
 163                 break;
 164         default:
 165                 /* Invalid state */
 166                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 167                 return;
 168         }
 169         /* Disable smartreflex before entering WFI */
 170         disable_smartreflex(SR1);
 171         disable_smartreflex(SR2);
 172
 173         omap2_gpio_prepare_for_retention();
 174
 175         _omap_sram_idle(NULL, save_state);
 176
 177         omap2_gpio_resume_after_retention();
 178
 179         /* Enable smartreflex after WFI */
 180         enable_smartreflex(SR1);
 181         enable_smartreflex(SR2);
 182 }
 183
 184 /*
 185  * Check if functional clocks are enabled before entering
 186  * sleep. This function could be behind CONFIG_PM_DEBUG
 187  * when all drivers are configuring their sysconfig registers
 188  * properly and using their clocks properly.
 189  */
 190 static int omap3_fclks_active(void)
 191 {
 192         u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
 193                 fck_cam = 0, fck_per = 0, fck_usbhost = 0;
 194
 195         fck_core1 = cm_read_mod_reg(CORE_MOD,
 196                                     CM_FCLKEN1);
 197         if (omap_rev() > OMAP3430_REV_ES1_0) {
 198                 fck_core3 = cm_read_mod_reg(CORE_MOD,
 199                                             OMAP3430ES2_CM_FCLKEN3);
 200                 fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
 201                                           CM_FCLKEN);
 202                 fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 203                                               CM_FCLKEN);
 204         } else
 205                 fck_sgx = cm_read_mod_reg(GFX_MOD,
 206                                           OMAP3430ES2_CM_FCLKEN3);
 207         fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
 208                                   CM_FCLKEN);
 209         fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
 210                                   CM_FCLKEN);
 211         fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
 212                                   CM_FCLKEN);
 213         if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
 214             fck_cam | fck_per | fck_usbhost)
 215                 return 1;
 216         return 0;
 217 }
 218
 219 static int omap3_can_sleep(void)
 220 {
 221         if (!enable_dyn_sleep)
 222                 return 0;
 223         if (omap3_fclks_active())
 224                 return 0;
 225         if (atomic_read(&sleep_block) > 0)
 226                 return 0;
 227         return 1;
 228 }
 229
 230 /* This sets pwrdm state (other than mpu & core. Currently only ON &
 231  * RET are supported. Function is assuming that clkdm doesn't have
 232  * hw_sup mode enabled. */
 233 static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
 234 {
 235         u32 cur_state;
 236         int sleep_switch = 0;
 237         int ret = 0;
 238
 239         if (pwrdm == NULL || IS_ERR(pwrdm))
 240                 return -EINVAL;
 241
 242         while (!(pwrdm->pwrsts & (1 << state))) {
 243                 if (state == PWRDM_POWER_OFF)
 244                         return ret;
 245                 state--;
 246         }
 247
 248         cur_state = pwrdm_read_next_pwrst(pwrdm);
 249         if (cur_state == state)
 250                 return ret;
 251
 252         if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
 253                 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
 254                 sleep_switch = 1;
 255                 pwrdm_wait_transition(pwrdm);
 256         }
 257
 258         ret = pwrdm_set_next_pwrst(pwrdm, state);
 259         if (ret) {
 260                 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
 261                        pwrdm->name);
 262                 goto err;
 263         }
 264
 265         if (sleep_switch) {
 266                 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
 267                 pwrdm_wait_transition(pwrdm);
 268         }
 269
 270 err:
 271         return ret;
 272 }
 273
 274 static void omap3_pm_idle(void)
 275 {
 276         local_irq_disable();
 277         local_fiq_disable();
 278
 279         if (!omap3_can_sleep())
 280                 goto out;
 281
 282         if (omap_irq_pending())
 283                 goto out;
 284
 285         omap_sram_idle();
 286
 287 out:
 288         local_fiq_enable();
 289         local_irq_enable();
 290 }
 291
 292 static int omap3_pm_prepare(void)
 293 {
 294         saved_idle = pm_idle;
 295         pm_idle = NULL;
 296         return 0;
 297 }
 298
 299 static int omap3_pm_suspend(void)
 300 {
 301         struct power_state *pwrst;
 302         int state, ret = 0;
 303
 304         /* Read current next_pwrsts */
 305         list_for_each_entry(pwrst, &pwrst_list, node)
 306                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 307         /* Set ones wanted by suspend */
 308         list_for_each_entry(pwrst, &pwrst_list, node) {
 309                 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 310                         goto restore;
 311                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 312                         goto restore;
 313         }
 314
 315         omap_sram_idle();
 316
 317 restore:
 318         /* Restore next_pwrsts */
 319         list_for_each_entry(pwrst, &pwrst_list, node) {
 320                 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 321                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 322                 if (state > pwrst->next_state) {
 323                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 324                                "target state %d\n",
 325                                pwrst->pwrdm->name, pwrst->next_state);
 326                         ret = -1;
 327                 }
 328         }
 329         if (ret)
 330                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 331         else
 332                 printk(KERN_INFO "Successfully put all powerdomains "
 333                        "to target state\n");
 334
 335         return ret;
 336 }
 337
 338 static int omap3_pm_enter(suspend_state_t state)
 339 {
 340         int ret = 0;
 341
 342         switch (state) {
 343         case PM_SUSPEND_STANDBY:
 344         case PM_SUSPEND_MEM:
 345                 ret = omap3_pm_suspend();
 346                 break;
 347         default:
 348                 ret = -EINVAL;
 349         }
 350
 351         return ret;
 352 }
 353
 354 static void omap3_pm_finish(void)
 355 {
 356         pm_idle = saved_idle;
 357 }
 358
 359 static struct platform_suspend_ops omap_pm_ops = {
 360         .prepare        = omap3_pm_prepare,
 361         .enter          = omap3_pm_enter,
 362         .finish         = omap3_pm_finish,
 363         .valid          = suspend_valid_only_mem,
 364 };
 365
 366 static void __init prcm_setup_regs(void)
 367 {
 368         /* XXX Reset all wkdeps. This should be done when initializing
 369          * powerdomains */
 370         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
 371         prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
 372         prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
 373         prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
 374         prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
 375         prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
 376         if (omap_rev() > OMAP3430_REV_ES1_0) {
 377                 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
 378                 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 379         } else
 380                 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 381
 382         /*
 383          * Enable interface clock autoidle for all modules.
 384          * Note that in the long run this should be done by clockfw
 385          */
 386         cm_write_mod_reg(
 387                 OMAP3430ES2_AUTO_MMC3 |
 388                 OMAP3430ES2_AUTO_ICR |
 389                 OMAP3430_AUTO_AES2 |
 390                 OMAP3430_AUTO_SHA12 |
 391                 OMAP3430_AUTO_DES2 |
 392                 OMAP3430_AUTO_MMC2 |
 393                 OMAP3430_AUTO_MMC1 |
 394                 OMAP3430_AUTO_MSPRO |
 395                 OMAP3430_AUTO_HDQ |
 396                 OMAP3430_AUTO_MCSPI4 |
 397                 OMAP3430_AUTO_MCSPI3 |
 398                 OMAP3430_AUTO_MCSPI2 |
 399                 OMAP3430_AUTO_MCSPI1 |
 400                 OMAP3430_AUTO_I2C3 |
 401                 OMAP3430_AUTO_I2C2 |
 402                 OMAP3430_AUTO_I2C1 |
 403                 OMAP3430_AUTO_UART2 |
 404                 OMAP3430_AUTO_UART1 |
 405                 OMAP3430_AUTO_GPT11 |
 406                 OMAP3430_AUTO_GPT10 |
 407                 OMAP3430_AUTO_MCBSP5 |
 408                 OMAP3430_AUTO_MCBSP1 |
 409                 OMAP3430ES1_AUTO_FAC | /* This is es1 only */
 410                 OMAP3430_AUTO_MAILBOXES |
 411                 OMAP3430_AUTO_OMAPCTRL |
 412                 OMAP3430ES1_AUTO_FSHOSTUSB |
 413                 OMAP3430_AUTO_HSOTGUSB |
 414                 OMAP3430ES1_AUTO_D2D | /* This is es1 only */
 415                 OMAP3430_AUTO_SSI,
 416                 CORE_MOD, CM_AUTOIDLE1);
 417
 418         cm_write_mod_reg(
 419                 OMAP3430_AUTO_PKA |
 420                 OMAP3430_AUTO_AES1 |
 421                 OMAP3430_AUTO_RNG |
 422                 OMAP3430_AUTO_SHA11 |
 423                 OMAP3430_AUTO_DES1,
 424                 CORE_MOD, CM_AUTOIDLE2);
 425
 426         if (omap_rev() > OMAP3430_REV_ES1_0) {
 427                 cm_write_mod_reg(
 428                         OMAP3430ES2_AUTO_USBTLL,
 429                         CORE_MOD, CM_AUTOIDLE3);
 430         }
 431
 432         cm_write_mod_reg(
 433                 OMAP3430_AUTO_WDT2 |
 434                 OMAP3430_AUTO_WDT1 |
 435                 OMAP3430_AUTO_GPIO1 |
 436                 OMAP3430_AUTO_32KSYNC |
 437                 OMAP3430_AUTO_GPT12 |
 438                 OMAP3430_AUTO_GPT1 ,
 439                 WKUP_MOD, CM_AUTOIDLE);
 440
 441         cm_write_mod_reg(
 442                 OMAP3430_AUTO_DSS,
 443                 OMAP3430_DSS_MOD,
 444                 CM_AUTOIDLE);
 445
 446         cm_write_mod_reg(
 447                 OMAP3430_AUTO_CAM,
 448                 OMAP3430_CAM_MOD,
 449                 CM_AUTOIDLE);
 450
 451         cm_write_mod_reg(
 452                 OMAP3430_AUTO_GPIO6 |
 453                 OMAP3430_AUTO_GPIO5 |
 454                 OMAP3430_AUTO_GPIO4 |
 455                 OMAP3430_AUTO_GPIO3 |
 456                 OMAP3430_AUTO_GPIO2 |
 457                 OMAP3430_AUTO_WDT3 |
 458                 OMAP3430_AUTO_UART3 |
 459                 OMAP3430_AUTO_GPT9 |
 460                 OMAP3430_AUTO_GPT8 |
 461                 OMAP3430_AUTO_GPT7 |
 462                 OMAP3430_AUTO_GPT6 |
 463                 OMAP3430_AUTO_GPT5 |
 464                 OMAP3430_AUTO_GPT4 |
 465                 OMAP3430_AUTO_GPT3 |
 466                 OMAP3430_AUTO_GPT2 |
 467                 OMAP3430_AUTO_MCBSP4 |
 468                 OMAP3430_AUTO_MCBSP3 |
 469                 OMAP3430_AUTO_MCBSP2,
 470                 OMAP3430_PER_MOD,
 471                 CM_AUTOIDLE);
 472
 473         if (omap_rev() > OMAP3430_REV_ES1_0) {
 474                 cm_write_mod_reg(
 475                         OMAP3430ES2_AUTO_USBHOST,
 476                         OMAP3430ES2_USBHOST_MOD,
 477                         CM_AUTOIDLE);
 478         }
 479
 480         /*
 481          * Set all plls to autoidle. This is needed until autoidle is
 482          * enabled by clockfw
 483          */
 484         cm_write_mod_reg(1 << OMAP3430_CLKTRCTRL_IVA2_SHIFT,
 485                          OMAP3430_IVA2_MOD,
 486                          CM_AUTOIDLE2);
 487         cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
 488                          MPU_MOD,
 489                          CM_AUTOIDLE2);
 490         cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
 491                          (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
 492                          PLL_MOD,
 493                          CM_AUTOIDLE);
 494         cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
 495                          PLL_MOD,
 496                          CM_AUTOIDLE2);
 497
 498         /*
 499          * Enable control of expternal oscillator through
 500          * sys_clkreq. In the long run clock framework should
 501          * take care of this.
 502          */
 503         prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 504                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 505                              OMAP3430_GR_MOD,
 506                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 507
 508         /* setup wakup source */
 509         prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1,
 510                           WKUP_MOD, PM_WKEN);
 511         /* No need to write EN_IO, that is always enabled */
 512         prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1,
 513                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 514         /* For some reason IO doesn't generate wakeup event even if
 515          * it is selected to mpu wakeup goup */
 516         prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
 517                         OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
 518 }
 519
 520 static int __init pwrdms_setup(struct powerdomain *pwrdm)
 521 {
 522         struct power_state *pwrst;
 523
 524         if (!pwrdm->pwrsts)
 525                 return 0;
 526
 527         pwrst = kmalloc(sizeof(struct power_state), GFP_KERNEL);
 528         if (!pwrst)
 529                 return -ENOMEM;
 530         pwrst->pwrdm = pwrdm;
 531         pwrst->next_state = PWRDM_POWER_RET;
 532         list_add(&pwrst->node, &pwrst_list);
 533
 534         if (pwrdm_has_hdwr_sar(pwrdm))
 535                 pwrdm_enable_hdwr_sar(pwrdm);
 536
 537         return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 538 }
 539
 540 static int __init clkdms_setup(struct clockdomain *clkdm)
 541 {
 542         omap2_clkdm_allow_idle(clkdm);
 543         return 0;
 544 }
 545
 546 int __init omap3_pm_init(void)
 547 {
 548         struct power_state *pwrst, *tmp;
 549         int ret;
 550
 551         printk(KERN_ERR "Power Management for TI OMAP3.\n");
 552
 553         /* XXX prcm_setup_regs needs to be before enabling hw
 554          * supervised mode for powerdomains */
 555         prcm_setup_regs();
 556
 557         ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
 558                           (irq_handler_t)prcm_interrupt_handler,
 559                           IRQF_DISABLED, "prcm", NULL);
 560         if (ret) {
 561                 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
 562                        INT_34XX_PRCM_MPU_IRQ);
 563                 goto err1;
 564         }
 565
 566         ret = pwrdm_for_each(pwrdms_setup);
 567         if (ret) {
 568                 printk(KERN_ERR "Failed to setup powerdomains\n");
 569                 goto err2;
 570         }
 571
 572         (void) clkdm_for_each(clkdms_setup);
 573
 574         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 575         if (mpu_pwrdm == NULL) {
 576                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
 577                 goto err2;
 578         }
 579
 580         _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
 581                                         omap34xx_cpu_suspend_sz);
 582
 583         suspend_set_ops(&omap_pm_ops);
 584
 585         pm_idle = omap3_pm_idle;
 586
 587 err1:
 588         return ret;
 589 err2:
 590         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
 591         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
 592                 list_del(&pwrst->node);
 593                 kfree(pwrst);
 594         }
 595         return ret;
 596 }
 597
 598 static void __init configure_vc(void)
 599 {
 600         prm_write_mod_reg((R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA1_SHIFT) |
 601                         (R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA0_SHIFT),
 602                         OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_SA_OFFSET);
 603         prm_write_mod_reg((R_VDD2_SR_CONTROL << OMAP3430_VOLRA1_SHIFT) |
 604                         (R_VDD1_SR_CONTROL << OMAP3430_VOLRA0_SHIFT),
 605                         OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET);
 606
 607         prm_write_mod_reg((OMAP3430_VC_CMD_VAL0_ON <<
 608                 OMAP3430_VC_CMD_ON_SHIFT) |
 609                 (OMAP3430_VC_CMD_VAL0_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) |
 610                 (OMAP3430_VC_CMD_VAL0_RET << OMAP3430_VC_CMD_RET_SHIFT) |
 611                 (OMAP3430_VC_CMD_VAL0_OFF << OMAP3430_VC_CMD_OFF_SHIFT),
 612                 OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
 613
 614         prm_write_mod_reg((OMAP3430_VC_CMD_VAL1_ON <<
 615                 OMAP3430_VC_CMD_ON_SHIFT) |
 616                 (OMAP3430_VC_CMD_VAL1_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) |
 617                 (OMAP3430_VC_CMD_VAL1_RET << OMAP3430_VC_CMD_RET_SHIFT) |
 618                 (OMAP3430_VC_CMD_VAL1_OFF << OMAP3430_VC_CMD_OFF_SHIFT),
 619                 OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
 620
 621         prm_write_mod_reg(OMAP3430_CMD1 | OMAP3430_RAV1,
 622                                 OMAP3430_GR_MOD,
 623                                 OMAP3_PRM_VC_CH_CONF_OFFSET);
 624
 625         prm_write_mod_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN | OMAP3430_SREN,
 626                                 OMAP3430_GR_MOD,
 627                                 OMAP3_PRM_VC_I2C_CFG_OFFSET);
 628
 629         /* Setup voltctrl and other setup times */
 630         prm_write_mod_reg(OMAP3430_AUTO_RET, OMAP3430_GR_MOD,
 631                         OMAP3_PRM_VOLTCTRL_OFFSET);
 632
 633         prm_write_mod_reg(OMAP3430_CLKSETUP_DURATION, OMAP3430_GR_MOD,
 634                         OMAP3_PRM_CLKSETUP_OFFSET);
 635         prm_write_mod_reg((OMAP3430_VOLTSETUP_TIME2 <<
 636                         OMAP3430_SETUP_TIME2_SHIFT) |
 637                         (OMAP3430_VOLTSETUP_TIME1 <<
 638                         OMAP3430_SETUP_TIME1_SHIFT),
 639                         OMAP3430_GR_MOD, OMAP3_PRM_VOLTSETUP1_OFFSET);
 640
 641         prm_write_mod_reg(OMAP3430_VOLTOFFSET_DURATION, OMAP3430_GR_MOD,
 642                         OMAP3_PRM_VOLTOFFSET_OFFSET);
 643         prm_write_mod_reg(OMAP3430_VOLTSETUP2_DURATION, OMAP3430_GR_MOD,
 644                         OMAP3_PRM_VOLTSETUP2_OFFSET);
 645 }
 646
 647 static int __init omap3_pm_early_init(void)
 648 {
 649         prm_clear_mod_reg_bits(OMAP3430_OFFMODE_POL, OMAP3430_GR_MOD,
 650                                 OMAP3_PRM_POLCTRL_OFFSET);
 651
 652         configure_vc();
 653
 654         return 0;
 655 }
 656
 657 arch_initcall(omap3_pm_early_init);