2 * linux/arch/arm/mach-omap2/pm.c
4 * OMAP2 Power Management Routines
6 * Copyright (C) 2005 Texas Instruments, Inc.
7 * Copyright (C) 2006-2008 Nokia Corporation
10 * Richard Woodruff <r-woodruff2@ti.com>
13 * Amit Kucheria <amit.kucheria@nokia.com>
14 * Igor Stoppa <igor.stoppa@nokia.com>
16 * Based on pm.c for omap1
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
23 #include <linux/suspend.h>
24 #include <linux/sched.h>
25 #include <linux/proc_fs.h>
26 #include <linux/interrupt.h>
27 #include <linux/sysfs.h>
28 #include <linux/module.h>
29 #include <linux/delay.h>
30 #include <linux/clk.h>
32 #include <linux/irq.h>
33 #include <linux/time.h>
35 #include <asm/mach/time.h>
36 #include <asm/mach/irq.h>
37 #include <asm/mach-types.h>
39 #include <mach/irqs.h>
40 #include <mach/clock.h>
41 #include <mach/sram.h>
42 #include <mach/control.h>
43 #include <mach/gpio.h>
47 #include <mach/board.h>
50 #include "prm-regbits-24xx.h"
52 #include "cm-regbits-24xx.h"
56 #include <mach/powerdomain.h>
57 #include <mach/clockdomain.h>
59 static void (*omap2_sram_idle)(void);
60 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
61 void __iomem *sdrc_power);
62 static void (*saved_idle)(void);
64 static struct powerdomain *mpu_pwrdm;
65 static struct powerdomain *core_pwrdm;
67 static struct clockdomain *dsp_clkdm;
68 static struct clockdomain *gfx_clkdm;
70 static struct clk *osc_ck, *emul_ck;
72 static int omap2_fclks_active(void)
76 f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
77 f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
79 /* Ignore UART clocks. These are handled by UART core (serial.c) */
80 f1 &= ~(OMAP24XX_EN_UART1 | OMAP24XX_EN_UART2);
81 f2 &= ~OMAP24XX_EN_UART3;
88 static void omap2_enter_full_retention(void)
91 struct timespec ts_preidle, ts_postidle, ts_idle;
93 /* There is 1 reference hold for all children of the oscillator
94 * clock, the following will remove it. If no one else uses the
95 * oscillator itself it will be disabled if/when we enter retention
100 /* Clear old wake-up events */
101 /* REVISIT: These write to reserved bits? */
102 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
103 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
104 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
107 * Set MPU powerdomain's next power state to RETENTION;
108 * preserve logic state during retention
110 pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
111 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
113 /* Workaround to kill USB */
114 l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
115 omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
117 omap2_gpio_prepare_for_retention();
119 if (omap2_pm_debug) {
120 omap2_pm_dump(0, 0, 0);
121 getnstimeofday(&ts_preidle);
124 /* One last check for pending IRQs to avoid extra latency due
125 * to sleeping unnecessarily. */
126 if (omap_irq_pending())
129 omap_uart_prepare_idle(0);
130 omap_uart_prepare_idle(1);
131 omap_uart_prepare_idle(2);
133 /* Jump to SRAM suspend code */
134 omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
135 OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
136 OMAP_SDRC_REGADDR(SDRC_POWER));
138 omap_uart_resume_idle(2);
139 omap_uart_resume_idle(1);
140 omap_uart_resume_idle(0);
142 if (omap2_pm_debug) {
143 unsigned long long tmp;
145 getnstimeofday(&ts_postidle);
146 ts_idle = timespec_sub(ts_postidle, ts_preidle);
147 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
148 omap2_pm_dump(0, 1, tmp);
150 omap2_gpio_resume_after_retention();
154 /* clear CORE wake-up events */
155 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
156 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
158 /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
159 prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
161 /* MPU domain wake events */
162 l = prm_read_mod_reg(OCP_MOD, OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
164 prm_write_mod_reg(0x01, OCP_MOD,
165 OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
167 prm_write_mod_reg(0x20, OCP_MOD,
168 OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
170 /* Mask future PRCM-to-MPU interrupts */
171 prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
174 static int omap2_i2c_active(void)
178 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
179 return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
182 static int sti_console_enabled;
184 static int omap2_allow_mpu_retention(void)
188 if (atomic_read(&sleep_block))
191 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
192 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
193 if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
194 OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
195 OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
197 /* Check for UART3. */
198 l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
199 if (l & OMAP24XX_EN_UART3)
201 if (sti_console_enabled)
207 static void omap2_enter_mpu_retention(void)
210 struct timespec ts_preidle, ts_postidle, ts_idle;
212 /* Putting MPU into the WFI state while a transfer is active
213 * seems to cause the I2C block to timeout. Why? Good question. */
214 if (omap2_i2c_active())
217 /* The peripherals seem not to be able to wake up the MPU when
218 * it is in retention mode. */
219 if (omap2_allow_mpu_retention()) {
220 /* REVISIT: These write to reserved bits? */
221 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
222 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
223 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
225 /* Try to enter MPU retention */
226 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
228 MPU_MOD, PM_PWSTCTRL);
230 /* Block MPU retention */
232 prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
236 if (omap2_pm_debug) {
237 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
238 getnstimeofday(&ts_preidle);
243 if (omap2_pm_debug) {
244 unsigned long long tmp;
246 getnstimeofday(&ts_postidle);
247 ts_idle = timespec_sub(ts_postidle, ts_preidle);
248 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
249 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp);
253 static int omap2_can_sleep(void)
255 if (!enable_dyn_sleep)
257 if (omap2_fclks_active())
259 if (atomic_read(&sleep_block) > 0)
261 if (osc_ck->usecount > 1)
263 if (omap_dma_running())
270 * Note that you can use clock_event_device->min_delta_ns if you want to
271 * avoid reprogramming timer too often when using CONFIG_NO_HZ.
273 static void omap2_pm_idle(void)
278 if (!omap2_can_sleep()) {
279 if (!atomic_read(&sleep_block) && omap_irq_pending())
281 omap2_enter_mpu_retention();
285 if (omap_irq_pending())
288 omap2_enter_full_retention();
295 static int omap2_pm_prepare(void)
297 /* We cannot sleep in idle until we have resumed */
298 saved_idle = pm_idle;
304 static int omap2_pm_suspend(void)
308 wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
309 prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
312 mir1 = omap_readl(0x480fe0a4);
313 omap_writel(1 << 5, 0x480fe0ac);
315 omap_uart_prepare_suspend();
316 omap2_enter_full_retention();
318 omap_writel(mir1, 0x480fe0a4);
319 prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
324 static int omap2_pm_enter(suspend_state_t state)
329 case PM_SUSPEND_STANDBY:
331 ret = omap2_pm_suspend();
340 static void omap2_pm_finish(void)
342 pm_idle = saved_idle;
345 static struct platform_suspend_ops omap_pm_ops = {
346 .prepare = omap2_pm_prepare,
347 .enter = omap2_pm_enter,
348 .finish = omap2_pm_finish,
349 .valid = suspend_valid_only_mem,
352 static int _pm_clkdm_enable_hwsup(struct clockdomain *clkdm)
354 omap2_clkdm_allow_idle(clkdm);
358 static void __init prcm_setup_regs(void)
360 int i, num_mem_banks;
361 struct powerdomain *pwrdm;
363 /* Enable autoidle */
364 prm_write_mod_reg(OMAP24XX_AUTOIDLE, OCP_MOD,
365 OMAP24XX_PRM_SYSCONFIG_OFFSET);
367 /* Set all domain wakeup dependencies */
368 prm_write_mod_reg(OMAP_EN_WKUP_MASK, MPU_MOD, PM_WKDEP);
369 prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
370 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
371 prm_write_mod_reg(0, CORE_MOD, PM_WKDEP);
372 if (cpu_is_omap2430())
373 prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP);
376 * Set CORE powerdomain memory banks to retain their contents
379 num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
380 for (i = 0; i < num_mem_banks; i++)
381 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
383 /* Set CORE powerdomain's next power state to RETENTION */
384 pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
387 * Set MPU powerdomain's next power state to RETENTION;
388 * preserve logic state during retention
390 pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
391 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
393 /* Force-power down DSP, GFX powerdomains */
395 pwrdm = clkdm_get_pwrdm(dsp_clkdm);
396 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
397 omap2_clkdm_sleep(dsp_clkdm);
399 pwrdm = clkdm_get_pwrdm(gfx_clkdm);
400 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
401 omap2_clkdm_sleep(gfx_clkdm);
403 /* Enable clockdomain hardware-supervised control for all clkdms */
404 clkdm_for_each(_pm_clkdm_enable_hwsup);
406 /* Enable clock autoidle for all domains */
407 cm_write_mod_reg(OMAP24XX_AUTO_CAM |
408 OMAP24XX_AUTO_MAILBOXES |
411 OMAP24XX_AUTO_MSPRO |
416 OMAP24XX_AUTO_UART2 |
417 OMAP24XX_AUTO_UART1 |
420 OMAP24XX_AUTO_MCSPI2 |
421 OMAP24XX_AUTO_MCSPI1 |
422 OMAP24XX_AUTO_MCBSP2 |
423 OMAP24XX_AUTO_MCBSP1 |
424 OMAP24XX_AUTO_GPT12 |
425 OMAP24XX_AUTO_GPT11 |
426 OMAP24XX_AUTO_GPT10 |
435 OMAP2420_AUTO_VLYNQ |
437 CORE_MOD, CM_AUTOIDLE1);
438 cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
441 CORE_MOD, CM_AUTOIDLE2);
442 cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
445 CORE_MOD, CM_AUTOIDLE3);
446 cm_write_mod_reg(OMAP24XX_AUTO_PKA |
451 CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
453 cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
455 /* Put DPLL and both APLLs into autoidle mode */
456 cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
457 (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
458 (0x03 << OMAP24XX_AUTO_54M_SHIFT),
459 PLL_MOD, CM_AUTOIDLE);
461 cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
463 OMAP24XX_AUTO_MPU_WDT |
464 OMAP24XX_AUTO_GPIOS |
465 OMAP24XX_AUTO_32KSYNC |
467 WKUP_MOD, CM_AUTOIDLE);
469 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
471 prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
472 OMAP24XX_PRCM_CLKSSETUP_OFFSET);
474 /* Configure automatic voltage transition */
475 prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
476 OMAP24XX_PRCM_VOLTSETUP_OFFSET);
477 prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT |
478 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
479 OMAP24XX_MEMRETCTRL |
480 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
481 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
482 OMAP24XX_GR_MOD, OMAP24XX_PRCM_VOLTCTRL_OFFSET);
484 /* Enable wake-up events */
485 prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
489 int __init omap2_pm_init(void)
493 printk(KERN_INFO "Power Management for OMAP2 initializing\n");
494 l = prm_read_mod_reg(OCP_MOD, OMAP24XX_PRM_REVISION_OFFSET);
495 printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
497 /* Look up important powerdomains, clockdomains */
499 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
501 pr_err("PM: mpu_pwrdm not found\n");
503 core_pwrdm = pwrdm_lookup("core_pwrdm");
505 pr_err("PM: core_pwrdm not found\n");
507 dsp_clkdm = clkdm_lookup("dsp_clkdm");
509 pr_err("PM: mpu_clkdm not found\n");
511 gfx_clkdm = clkdm_lookup("gfx_clkdm");
513 pr_err("PM: gfx_clkdm not found\n");
516 osc_ck = clk_get(NULL, "osc_ck");
517 if (IS_ERR(osc_ck)) {
518 printk(KERN_ERR "could not get osc_ck\n");
522 if (cpu_is_omap242x()) {
523 emul_ck = clk_get(NULL, "emul_ck");
524 if (IS_ERR(emul_ck)) {
525 printk(KERN_ERR "could not get emul_ck\n");
533 /* Hack to prevent MPU retention when STI console is enabled. */
535 const struct omap_sti_console_config *sti;
537 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
538 struct omap_sti_console_config);
539 if (sti != NULL && sti->enable)
540 sti_console_enabled = 1;
544 * We copy the assembler sleep/wakeup routines to SRAM.
545 * These routines need to be in SRAM as that's the only
546 * memory the MPU can see when it wakes up.
548 if (cpu_is_omap24xx()) {
549 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
550 omap24xx_idle_loop_suspend_sz);
552 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
553 omap24xx_cpu_suspend_sz);
556 suspend_set_ops(&omap_pm_ops);
557 pm_idle = omap2_pm_idle;