arch/arm/mach-omap2/pm24xx.c

   1 /*
   2  * linux/arch/arm/mach-omap2/pm.c
   3  *
   4  * OMAP2 Power Management Routines
   5  *
   6  * Copyright (C) 2005 Texas Instruments, Inc.
   7  * Copyright (C) 2006-2008 Nokia Corporation
   8  *
   9  * Written by:
  10  * Richard Woodruff <r-woodruff2@ti.com>
  11  * Tony Lindgren
  12  * Juha Yrjola
  13  * Amit Kucheria <amit.kucheria@nokia.com>
  14  * Igor Stoppa <igor.stoppa@nokia.com>
  15  *
  16  * Based on pm.c for omap1
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  */
  22
  23 #include <linux/suspend.h>
  24 #include <linux/sched.h>
  25 #include <linux/proc_fs.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/sysfs.h>
  28 #include <linux/module.h>
  29 #include <linux/delay.h>
  30 #include <linux/clk.h>
  31 #include <linux/io.h>
  32 #include <linux/irq.h>
  33
  34 #include <asm/mach/time.h>
  35 #include <asm/mach/irq.h>
  36 #include <asm/mach-types.h>
  37
  38 #include <mach/irqs.h>
  39 #include <mach/clock.h>
  40 #include <mach/sram.h>
  41 #include <mach/control.h>
  42 #include <mach/gpio.h>
  43 #include <mach/pm.h>
  44 #include <mach/mux.h>
  45 #include <mach/dma.h>
  46 #include <mach/board.h>
  47
  48 #include "prm.h"
  49 #include "prm-regbits-24xx.h"
  50 #include "cm.h"
  51 #include "cm-regbits-24xx.h"
  52 #include "sdrc.h"
  53 #include "pm.h"
  54
  55 #include <mach/powerdomain.h>
  56 #include <mach/clockdomain.h>
  57
  58 static void (*omap2_sram_idle)(void);
  59 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
  60                                         void __iomem *sdrc_power);
  61 static void (*saved_idle)(void);
  62
  63 static struct powerdomain *mpu_pwrdm;
  64 static struct powerdomain *core_pwrdm;
  65
  66 static struct clockdomain *dsp_clkdm;
  67 static struct clockdomain *gfx_clkdm;
  68
  69 static struct clk *osc_ck, *emul_ck;
  70
  71 static int omap2_fclks_active(void)
  72 {
  73         u32 f1, f2;
  74
  75         f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  76         f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  77         serial_console_fclk_mask(&f1, &f2);
  78         if (f1 | f2)
  79                 return 1;
  80         return 0;
  81 }
  82
  83 static void omap2_enter_full_retention(void)
  84 {
  85         u32 l, sleep_time = 0;
  86
  87         /* There is 1 reference hold for all children of the oscillator
  88          * clock, the following will remove it. If no one else uses the
  89          * oscillator itself it will be disabled if/when we enter retention
  90          * mode.
  91          */
  92         clk_disable(osc_ck);
  93
  94         /* Clear old wake-up events */
  95         /* REVISIT: These write to reserved bits? */
  96         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
  97         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
  98         prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
  99
 100         /*
 101          * Set MPU powerdomain's next power state to RETENTION;
 102          * preserve logic state during retention
 103          */
 104         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 105         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 106
 107         /* Workaround to kill USB */
 108         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
 109         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
 110
 111         omap2_gpio_prepare_for_retention();
 112
 113         if (omap2_pm_debug) {
 114                 omap2_pm_dump(0, 0, 0);
 115                 sleep_time = omap2_read_32k_sync_counter();
 116         }
 117
 118         /* One last check for pending IRQs to avoid extra latency due
 119          * to sleeping unnecessarily. */
 120         if (omap_irq_pending())
 121                 goto no_sleep;
 122
 123         serial_console_sleep(1);
 124         /* Jump to SRAM suspend code */
 125         omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
 126                                 OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
 127                                 OMAP_SDRC_REGADDR(SDRC_POWER));
 128 no_sleep:
 129         serial_console_sleep(0);
 130
 131         if (omap2_pm_debug) {
 132                 unsigned long long tmp;
 133                 u32 resume_time;
 134
 135                 resume_time = omap2_read_32k_sync_counter();
 136                 tmp = resume_time - sleep_time;
 137                 tmp *= 1000000;
 138                 omap2_pm_dump(0, 1, tmp / 32768);
 139         }
 140         omap2_gpio_resume_after_retention();
 141
 142         clk_enable(osc_ck);
 143
 144         /* clear CORE wake-up events */
 145         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 146         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 147
 148         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
 149         prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 150
 151         /* MPU domain wake events */
 152         l = prm_read_mod_reg(OCP_MOD, OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
 153         if (l & 0x01)
 154                 prm_write_mod_reg(0x01, OCP_MOD,
 155                                 OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
 156         if (l & 0x20)
 157                 prm_write_mod_reg(0x20, OCP_MOD,
 158                                 OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
 159
 160         /* Mask future PRCM-to-MPU interrupts */
 161         prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
 162 }
 163
 164 static int omap2_i2c_active(void)
 165 {
 166         u32 l;
 167
 168         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 169         return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
 170 }
 171
 172 static int sti_console_enabled;
 173
 174 static int omap2_allow_mpu_retention(void)
 175 {
 176         u32 l;
 177
 178         if (atomic_read(&sleep_block))
 179                 return 0;
 180
 181         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 182         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 183         if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
 184                  OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
 185                  OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
 186                 return 0;
 187         /* Check for UART3. */
 188         l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 189         if (l & OMAP24XX_EN_UART3)
 190                 return 0;
 191         if (sti_console_enabled)
 192                 return 0;
 193
 194         return 1;
 195 }
 196
 197 static void omap2_enter_mpu_retention(void)
 198 {
 199         u32 sleep_time = 0;
 200         int only_idle = 0;
 201
 202         /* Putting MPU into the WFI state while a transfer is active
 203          * seems to cause the I2C block to timeout. Why? Good question. */
 204         if (omap2_i2c_active())
 205                 return;
 206
 207         /* The peripherals seem not to be able to wake up the MPU when
 208          * it is in retention mode. */
 209         if (omap2_allow_mpu_retention()) {
 210                 /* REVISIT: These write to reserved bits? */
 211                 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 212                 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 213                 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 214
 215                 /* Try to enter MPU retention */
 216                 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 217                                   OMAP_LOGICRETSTATE,
 218                                   MPU_MOD, PM_PWSTCTRL);
 219         } else {
 220                 /* Block MPU retention */
 221
 222                 prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
 223                 only_idle = 1;
 224         }
 225
 226         if (omap2_pm_debug) {
 227                 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
 228                 sleep_time = omap2_read_32k_sync_counter();
 229         }
 230
 231         omap2_sram_idle();
 232
 233         if (omap2_pm_debug) {
 234                 unsigned long long tmp;
 235                 u32 resume_time;
 236
 237                 resume_time = omap2_read_32k_sync_counter();
 238                 tmp = resume_time - sleep_time;
 239                 tmp *= 1000000;
 240                 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
 241         }
 242 }
 243
 244 static int omap2_can_sleep(void)
 245 {
 246         if (!enable_dyn_sleep)
 247                 return 0;
 248         if (omap2_fclks_active())
 249                 return 0;
 250         if (atomic_read(&sleep_block) > 0)
 251                 return 0;
 252         if (osc_ck->usecount > 1)
 253                 return 0;
 254         if (omap_dma_running())
 255                 return 0;
 256
 257         return 1;
 258 }
 259
 260 /*
 261  * Note that you can use clock_event_device->min_delta_ns if you want to
 262  * avoid reprogramming timer too often when using CONFIG_NO_HZ.
 263  */
 264 static void omap2_pm_idle(void)
 265 {
 266         local_irq_disable();
 267         local_fiq_disable();
 268
 269         if (!omap2_can_sleep()) {
 270                 if (!atomic_read(&sleep_block) && omap_irq_pending())
 271                         goto out;
 272                 omap2_enter_mpu_retention();
 273                 goto out;
 274         }
 275
 276         if (omap_irq_pending())
 277                 goto out;
 278
 279         omap2_enter_full_retention();
 280
 281 out:
 282         local_fiq_enable();
 283         local_irq_enable();
 284 }
 285
 286 static int omap2_pm_prepare(void)
 287 {
 288         /* We cannot sleep in idle until we have resumed */
 289         saved_idle = pm_idle;
 290         pm_idle = NULL;
 291
 292         return 0;
 293 }
 294
 295 static int omap2_pm_suspend(void)
 296 {
 297         u32 wken_wkup, mir1;
 298
 299         wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 300         prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
 301
 302         /* Mask GPT1 */
 303         mir1 = omap_readl(0x480fe0a4);
 304         omap_writel(1 << 5, 0x480fe0ac);
 305
 306         omap2_enter_full_retention();
 307
 308         omap_writel(mir1, 0x480fe0a4);
 309         prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 310
 311         return 0;
 312 }
 313
 314 static int omap2_pm_enter(suspend_state_t state)
 315 {
 316         int ret = 0;
 317
 318         switch (state) {
 319         case PM_SUSPEND_STANDBY:
 320         case PM_SUSPEND_MEM:
 321                 ret = omap2_pm_suspend();
 322                 break;
 323         default:
 324                 ret = -EINVAL;
 325         }
 326
 327         return ret;
 328 }
 329
 330 static void omap2_pm_finish(void)
 331 {
 332         pm_idle = saved_idle;
 333 }
 334
 335 static struct platform_suspend_ops omap_pm_ops = {
 336         .prepare        = omap2_pm_prepare,
 337         .enter          = omap2_pm_enter,
 338         .finish         = omap2_pm_finish,
 339         .valid          = suspend_valid_only_mem,
 340 };
 341
 342 static int _pm_clkdm_enable_hwsup(struct clockdomain *clkdm)
 343 {
 344         omap2_clkdm_allow_idle(clkdm);
 345         return 0;
 346 }
 347
 348 static void __init prcm_setup_regs(void)
 349 {
 350         int i, num_mem_banks;
 351         struct powerdomain *pwrdm;
 352
 353         /* Enable autoidle */
 354         prm_write_mod_reg(OMAP24XX_AUTOIDLE, OCP_MOD,
 355                                 OMAP24XX_PRM_SYSCONFIG_OFFSET);
 356
 357         /* Set all domain wakeup dependencies */
 358         prm_write_mod_reg(OMAP_EN_WKUP_MASK, MPU_MOD, PM_WKDEP);
 359         prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
 360         prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 361         prm_write_mod_reg(0, CORE_MOD, PM_WKDEP);
 362         if (cpu_is_omap2430())
 363                 prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP);
 364
 365         /*
 366          * Set CORE powerdomain memory banks to retain their contents
 367          * during RETENTION
 368          */
 369         num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
 370         for (i = 0; i < num_mem_banks; i++)
 371                 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
 372
 373         /* Set CORE powerdomain's next power state to RETENTION */
 374         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
 375
 376         /*
 377          * Set MPU powerdomain's next power state to RETENTION;
 378          * preserve logic state during retention
 379          */
 380         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 381         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 382
 383         /* Force-power down DSP, GFX powerdomains */
 384
 385         pwrdm = clkdm_get_pwrdm(dsp_clkdm);
 386         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 387         omap2_clkdm_sleep(dsp_clkdm);
 388
 389         pwrdm = clkdm_get_pwrdm(gfx_clkdm);
 390         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 391         omap2_clkdm_sleep(gfx_clkdm);
 392
 393         /* Enable clockdomain hardware-supervised control for all clkdms */
 394         clkdm_for_each(_pm_clkdm_enable_hwsup);
 395
 396         /* Enable clock autoidle for all domains */
 397         cm_write_mod_reg(OMAP24XX_AUTO_CAM |
 398                          OMAP24XX_AUTO_MAILBOXES |
 399                          OMAP24XX_AUTO_WDT4 |
 400                          OMAP2420_AUTO_WDT3 |
 401                          OMAP24XX_AUTO_MSPRO |
 402                          OMAP2420_AUTO_MMC |
 403                          OMAP24XX_AUTO_FAC |
 404                          OMAP2420_AUTO_EAC |
 405                          OMAP24XX_AUTO_HDQ |
 406                          OMAP24XX_AUTO_UART2 |
 407                          OMAP24XX_AUTO_UART1 |
 408                          OMAP24XX_AUTO_I2C2 |
 409                          OMAP24XX_AUTO_I2C1 |
 410                          OMAP24XX_AUTO_MCSPI2 |
 411                          OMAP24XX_AUTO_MCSPI1 |
 412                          OMAP24XX_AUTO_MCBSP2 |
 413                          OMAP24XX_AUTO_MCBSP1 |
 414                          OMAP24XX_AUTO_GPT12 |
 415                          OMAP24XX_AUTO_GPT11 |
 416                          OMAP24XX_AUTO_GPT10 |
 417                          OMAP24XX_AUTO_GPT9 |
 418                          OMAP24XX_AUTO_GPT8 |
 419                          OMAP24XX_AUTO_GPT7 |
 420                          OMAP24XX_AUTO_GPT6 |
 421                          OMAP24XX_AUTO_GPT5 |
 422                          OMAP24XX_AUTO_GPT4 |
 423                          OMAP24XX_AUTO_GPT3 |
 424                          OMAP24XX_AUTO_GPT2 |
 425                          OMAP2420_AUTO_VLYNQ |
 426                          OMAP24XX_AUTO_DSS,
 427                          CORE_MOD, CM_AUTOIDLE1);
 428         cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
 429                          OMAP24XX_AUTO_SSI |
 430                          OMAP24XX_AUTO_USB,
 431                          CORE_MOD, CM_AUTOIDLE2);
 432         cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
 433                          OMAP24XX_AUTO_GPMC |
 434                          OMAP24XX_AUTO_SDMA,
 435                          CORE_MOD, CM_AUTOIDLE3);
 436         cm_write_mod_reg(OMAP24XX_AUTO_PKA |
 437                          OMAP24XX_AUTO_AES |
 438                          OMAP24XX_AUTO_RNG |
 439                          OMAP24XX_AUTO_SHA |
 440                          OMAP24XX_AUTO_DES,
 441                          CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
 442
 443         cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
 444
 445         /* Put DPLL and both APLLs into autoidle mode */
 446         cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
 447                          (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
 448                          (0x03 << OMAP24XX_AUTO_54M_SHIFT),
 449                          PLL_MOD, CM_AUTOIDLE);
 450
 451         cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
 452                          OMAP24XX_AUTO_WDT1 |
 453                          OMAP24XX_AUTO_MPU_WDT |
 454                          OMAP24XX_AUTO_GPIOS |
 455                          OMAP24XX_AUTO_32KSYNC |
 456                          OMAP24XX_AUTO_GPT1,
 457                          WKUP_MOD, CM_AUTOIDLE);
 458
 459         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 460          * stabilisation */
 461         prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 462                                         OMAP24XX_PRCM_CLKSSETUP_OFFSET);
 463
 464         /* Configure automatic voltage transition */
 465         prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 466                                         OMAP24XX_PRCM_VOLTSETUP_OFFSET);
 467         prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT |
 468                       (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 469                       OMAP24XX_MEMRETCTRL |
 470                       (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 471                       (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 472                       OMAP24XX_GR_MOD, OMAP24XX_PRCM_VOLTCTRL_OFFSET);
 473
 474         /* Enable wake-up events */
 475         prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
 476                           WKUP_MOD, PM_WKEN);
 477 }
 478
 479 int __init omap2_pm_init(void)
 480 {
 481         u32 l;
 482
 483         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 484         l = prm_read_mod_reg(OCP_MOD, OMAP24XX_PRM_REVISION_OFFSET);
 485         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 486
 487         /* Look up important powerdomains, clockdomains */
 488
 489         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 490         if (!mpu_pwrdm)
 491                 pr_err("PM: mpu_pwrdm not found\n");
 492
 493         core_pwrdm = pwrdm_lookup("core_pwrdm");
 494         if (!core_pwrdm)
 495                 pr_err("PM: core_pwrdm not found\n");
 496
 497         dsp_clkdm = clkdm_lookup("dsp_clkdm");
 498         if (!dsp_clkdm)
 499                 pr_err("PM: mpu_clkdm not found\n");
 500
 501         gfx_clkdm = clkdm_lookup("gfx_clkdm");
 502         if (!gfx_clkdm)
 503                 pr_err("PM: gfx_clkdm not found\n");
 504
 505
 506         osc_ck = clk_get(NULL, "osc_ck");
 507         if (IS_ERR(osc_ck)) {
 508                 printk(KERN_ERR "could not get osc_ck\n");
 509                 return -ENODEV;
 510         }
 511
 512         if (cpu_is_omap242x()) {
 513                 emul_ck = clk_get(NULL, "emul_ck");
 514                 if (IS_ERR(emul_ck)) {
 515                         printk(KERN_ERR "could not get emul_ck\n");
 516                         clk_put(osc_ck);
 517                         return -ENODEV;
 518                 }
 519         }
 520
 521         prcm_setup_regs();
 522
 523         pm_init_serial_console();
 524
 525         /* Hack to prevent MPU retention when STI console is enabled. */
 526         {
 527                 const struct omap_sti_console_config *sti;
 528
 529                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 530                                       struct omap_sti_console_config);
 531                 if (sti != NULL && sti->enable)
 532                         sti_console_enabled = 1;
 533         }
 534
 535         /*
 536          * We copy the assembler sleep/wakeup routines to SRAM.
 537          * These routines need to be in SRAM as that's the only
 538          * memory the MPU can see when it wakes up.
 539          */
 540         if (cpu_is_omap24xx()) {
 541                 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 542                                                  omap24xx_idle_loop_suspend_sz);
 543
 544                 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 545                                                     omap24xx_cpu_suspend_sz);
 546         }
 547
 548         suspend_set_ops(&omap_pm_ops);
 549         pm_idle = omap2_pm_idle;
 550
 551         return 0;
 552 }