2 * linux/arch/arm/mach-omap2/pm.c
4 * OMAP2 Power Management Routines
6 * Copyright (C) 2005 Texas Instruments, Inc.
7 * Copyright (C) 2006 Nokia Corporation
10 * Richard Woodruff <r-woodruff2@ti.com>
13 * Amit Kucheria <amit.kucheria@nokia.com>
14 * Igor Stoppa <igor.stoppa@nokia.com>
16 * Based on pm.c for omap1
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
23 #include <linux/suspend.h>
24 #include <linux/sched.h>
25 #include <linux/proc_fs.h>
26 #include <linux/interrupt.h>
27 #include <linux/sysfs.h>
28 #include <linux/module.h>
29 #include <linux/delay.h>
30 #include <linux/clk.h>
34 #include <asm/atomic.h>
35 #include <asm/mach/time.h>
36 #include <asm/mach/irq.h>
37 #include <asm/mach-types.h>
39 #include <asm/arch/irqs.h>
40 #include <asm/arch/clock.h>
41 #include <asm/arch/sram.h>
42 #include <asm/arch/gpio.h>
43 #include <asm/arch/pm.h>
44 #include <asm/arch/mux.h>
45 #include <asm/arch/dma.h>
46 #include <asm/arch/board.h>
47 #include <asm/arch/gpio.h>
50 #include "prm_regbits_24xx.h"
52 #include "cm_regbits_24xx.h"
55 static void (*omap2_sram_idle)(void);
56 static void (*omap2_sram_suspend)(void __iomem *dllctrl);
57 static void (*saved_idle)(void);
59 static u32 omap2_read_32k_sync_counter(void)
61 return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
64 #ifdef CONFIG_PM_DEBUG
65 int omap2_pm_debug = 0;
67 static int serial_console_clock_disabled;
68 static int serial_console_uart;
69 static unsigned int serial_console_next_disable;
71 static struct clk *console_iclk, *console_fclk;
73 static void serial_console_kick(void)
75 serial_console_next_disable = omap2_read_32k_sync_counter();
76 /* Keep the clocks on for 4 secs */
77 serial_console_next_disable += 4 * 32768;
80 static void serial_wait_tx(void)
82 static const unsigned long uart_bases[3] = {
83 0x4806a000, 0x4806c000, 0x4806e000
85 unsigned long lsr_reg;
88 /* Wait for TX FIFO and THR to get empty */
89 lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2));
90 while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
93 serial_console_kick();
96 static void serial_console_fclk_mask(u32 *f1, u32 *f2)
98 switch (serial_console_uart) {
111 static void serial_console_sleep(int enable)
113 if (console_iclk == NULL || console_fclk == NULL)
117 BUG_ON(serial_console_clock_disabled);
118 if (clk_get_usecount(console_fclk) == 0)
120 if ((int) serial_console_next_disable - (int) omap2_read_32k_sync_counter() >= 0)
123 clk_disable(console_iclk);
124 clk_disable(console_fclk);
125 serial_console_clock_disabled = 1;
127 int serial_wakeup = 0;
130 switch (serial_console_uart) {
132 l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
133 if (l & OMAP24XX_ST_UART1)
137 l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
138 if (l & OMAP24XX_ST_UART2)
142 l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKST2);
143 if (l & OMAP24XX_ST_UART3)
148 serial_console_kick();
149 if (!serial_console_clock_disabled)
151 clk_enable(console_iclk);
152 clk_enable(console_fclk);
153 serial_console_clock_disabled = 0;
157 static void pm_init_serial_console(void)
159 const struct omap_serial_console_config *conf;
163 conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
164 struct omap_serial_console_config);
167 if (conf->console_uart > 3 || conf->console_uart < 1)
169 serial_console_uart = conf->console_uart;
170 sprintf(name, "uart%d_fck", conf->console_uart);
171 console_fclk = clk_get(NULL, name);
172 if (IS_ERR(console_fclk))
175 console_iclk = clk_get(NULL, name);
176 if (IS_ERR(console_fclk))
178 if (console_fclk == NULL || console_iclk == NULL) {
179 serial_console_uart = 0;
182 switch (serial_console_uart) {
184 l = prm_read_mod_reg(CORE_MOD, PM_WKEN1);
185 l |= OMAP24XX_ST_UART1;
186 prm_write_mod_reg(l, CORE_MOD, PM_WKEN1);
189 l = prm_read_mod_reg(CORE_MOD, PM_WKEN1);
190 l |= OMAP24XX_ST_UART2;
191 prm_write_mod_reg(l, CORE_MOD, PM_WKEN1);
194 l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKEN2);
195 l |= OMAP24XX_ST_UART3;
196 prm_write_mod_reg(l, CORE_MOD, OMAP24XX_PM_WKEN2);
201 #define DUMP_PRM_MOD_REG(mod, reg) \
202 regs[reg_count].name = #mod "." #reg; \
203 regs[reg_count++].val = prm_read_mod_reg(mod, reg)
204 #define DUMP_CM_MOD_REG(mod, reg) \
205 regs[reg_count].name = #mod "." #reg; \
206 regs[reg_count++].val = cm_read_mod_reg(mod, reg)
207 #define DUMP_PRM_REG(reg) \
208 regs[reg_count].name = #reg; \
209 regs[reg_count++].val = prm_read_reg(reg)
210 #define DUMP_CM_REG(reg) \
211 regs[reg_count].name = #reg; \
212 regs[reg_count++].val = cm_read_reg(reg)
213 #define DUMP_INTC_REG(reg, off) \
214 regs[reg_count].name = #reg; \
215 regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off)))
217 static void omap2_pm_dump(int mode, int resume, unsigned int us)
223 int reg_count = 0, i;
224 const char *s1 = NULL, *s2 = NULL;
229 DUMP_PRM_REG(OMAP24XX_PRCM_IRQENABLE_MPU);
230 DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL);
231 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL);
232 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST);
233 DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
237 DUMP_INTC_REG(INTC_MIR0, 0x0084);
238 DUMP_INTC_REG(INTC_MIR1, 0x00a4);
239 DUMP_INTC_REG(INTC_MIR2, 0x00c4);
242 DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
243 DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN2);
244 DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
245 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
246 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
247 DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
248 DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN_PLL);
249 DUMP_PRM_REG(OMAP24XX_PRCM_CLKEMUL_CTRL);
250 DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
251 DUMP_PRM_MOD_REG(CORE_REG, PM_PWSTST);
252 DUMP_PRM_REG(OMAP24XX_PRCM_CLKSRC_CTRL);
256 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
257 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
258 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
259 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
260 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
261 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
262 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL);
263 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST);
264 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL);
265 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST);
268 DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
269 DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
270 DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
271 DUMP_PRM_REG(OMAP24XX_PRCM_IRQSTATUS_MPU);
273 DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
274 DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
275 DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
295 #if defined(CONFIG_NO_IDLE_HZ) || defined(CONFIG_NO_HZ)
296 printk("--- Going to %s %s (next timer after %u ms)\n", s1, s2,
297 jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
300 printk("--- Going to %s %s\n", s1, s2);
303 printk("--- Woke up (slept for %u.%03u ms)\n", us / 1000, us % 1000);
304 for (i = 0; i < reg_count; i++)
305 printk("%-20s: 0x%08x\n", regs[i].name, regs[i].val);
309 static inline void serial_console_sleep(int enable) {}
310 static inline void pm_init_serial_console(void) {}
311 static inline void omap2_pm_dump(int mode, int resume, unsigned int us) {}
312 static inline void serial_console_fclk_mask(u32 *f1, u32 *f2) {}
314 #define omap2_pm_debug 0
318 static unsigned short enable_dyn_sleep = 0; /* disabled till drivers are fixed */
320 static ssize_t omap_pm_sleep_while_idle_show(struct kset * subsys, char *buf)
322 return sprintf(buf, "%hu\n", enable_dyn_sleep);
325 static ssize_t omap_pm_sleep_while_idle_store(struct kset * subsys,
329 unsigned short value;
330 if (sscanf(buf, "%hu", &value) != 1 ||
331 (value != 0 && value != 1)) {
332 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
335 enable_dyn_sleep = value;
339 static struct subsys_attribute sleep_while_idle_attr = {
341 .name = __stringify(sleep_while_idle),
344 .show = omap_pm_sleep_while_idle_show,
345 .store = omap_pm_sleep_while_idle_store,
348 static struct clk *osc_ck, *emul_ck;
350 #define CONTROL_DEVCONF __REG32(OMAP2_CTRL_BASE + 0x274)
352 static int omap2_fclks_active(void)
356 f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
357 f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
358 serial_console_fclk_mask(&f1, &f2);
364 static int omap2_irq_pending(void)
366 u32 pending_reg = IO_ADDRESS(0x480fe098);
369 for (i = 0; i < 4; i++) {
370 if (__raw_readl(pending_reg))
377 static atomic_t sleep_block = ATOMIC_INIT(0);
379 void omap2_block_sleep(void)
381 atomic_inc(&sleep_block);
384 void omap2_allow_sleep(void)
388 i = atomic_dec_return(&sleep_block);
392 static void omap2_enter_full_retention(void)
396 /* There is 1 reference hold for all children of the oscillator
397 * clock, the following will remove it. If no one else uses the
398 * oscillator itself it will be disabled if/when we enter retention
403 /* Clear old wake-up events */
404 /* REVISIT: These write to reserved bits? */
405 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
406 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
407 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
409 /* Try to enter retention */
410 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | OMAP_LOGICRETSTATE,
411 MPU_MOD, PM_PWSTCTRL);
413 /* Workaround to kill USB */
414 CONTROL_DEVCONF |= 0x00008000;
416 omap2_gpio_prepare_for_retention();
418 if (omap2_pm_debug) {
419 omap2_pm_dump(0, 0, 0);
420 sleep_time = omap2_read_32k_sync_counter();
423 /* One last check for pending IRQs to avoid extra latency due
424 * to sleeping unnecessarily. */
425 if (omap2_irq_pending())
428 serial_console_sleep(1);
429 /* Jump to SRAM suspend code */
430 omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
432 serial_console_sleep(0);
434 if (omap2_pm_debug) {
435 unsigned long long tmp;
438 resume_time = omap2_read_32k_sync_counter();
439 tmp = resume_time - sleep_time;
441 omap2_pm_dump(0, 1, tmp / 32768);
443 omap2_gpio_resume_after_retention();
449 static int omap2_i2c_active(void)
453 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
454 return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
457 static int sti_console_enabled;
459 static int omap2_allow_mpu_retention(void)
463 if (atomic_read(&sleep_block))
466 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
467 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
468 if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
469 OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
470 OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
472 /* Check for UART3. */
473 l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
474 if (l & OMAP24XX_EN_UART3)
476 if (sti_console_enabled)
482 static void omap2_enter_mpu_retention(void)
487 /* Putting MPU into the WFI state while a transfer is active
488 * seems to cause the I2C block to timeout. Why? Good question. */
489 if (omap2_i2c_active())
492 /* The peripherals seem not to be able to wake up the MPU when
493 * it is in retention mode. */
494 if (omap2_allow_mpu_retention()) {
495 /* REVISIT: These write to reserved bits? */
496 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
497 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
498 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
500 /* Try to enter MPU retention */
501 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
503 MPU_MOD, PM_PWSTCTRL);
505 /* Block MPU retention */
507 prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
511 if (omap2_pm_debug) {
512 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
513 sleep_time = omap2_read_32k_sync_counter();
518 if (omap2_pm_debug) {
519 unsigned long long tmp;
522 resume_time = omap2_read_32k_sync_counter();
523 tmp = resume_time - sleep_time;
525 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
529 static int omap2_can_sleep(void)
531 if (!enable_dyn_sleep)
533 if (omap2_fclks_active())
535 if (atomic_read(&sleep_block) > 0)
537 if (clk_get_usecount(osc_ck) > 1)
539 if (omap_dma_running())
545 static void omap2_pm_idle(void)
550 if (!omap2_can_sleep()) {
551 /* timer_dyn_reprogram() takes about 100-200 us to complete.
552 * In some contexts (e.g. when waiting for a GPMC-SDRAM DMA
553 * transfer to complete), the increased latency is too much.
555 * omap2_block_sleep() and omap2_allow_sleep() can be used
558 if (atomic_read(&sleep_block) == 0) {
559 timer_dyn_reprogram();
560 if (omap2_irq_pending())
563 omap2_enter_mpu_retention();
568 * Since an interrupt may set up a timer, we don't want to
569 * reprogram the hardware timer with interrupts enabled.
570 * Re-enable interrupts only after returning from idle.
572 timer_dyn_reprogram();
574 if (omap2_irq_pending())
577 omap2_enter_full_retention();
584 static int omap2_pm_prepare(void)
586 /* We cannot sleep in idle until we have resumed */
587 saved_idle = pm_idle;
593 static int omap2_pm_suspend(void)
597 wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
598 prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
601 mir1 = omap_readl(0x480fe0a4);
602 omap_writel(1 << 5, 0x480fe0ac);
604 omap2_enter_full_retention();
606 omap_writel(mir1, 0x480fe0a4);
607 prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
612 static int omap2_pm_enter(suspend_state_t state)
617 case PM_SUSPEND_STANDBY:
619 ret = omap2_pm_suspend();
628 static void omap2_pm_finish(void)
630 pm_idle = saved_idle;
633 static struct platform_suspend_ops omap_pm_ops = {
634 .prepare = omap2_pm_prepare,
635 .enter = omap2_pm_enter,
636 .finish = omap2_pm_finish,
637 .valid = suspend_valid_only_mem,
640 static void __init prcm_setup_regs(void)
644 /* Enable autoidle */
645 prm_write_reg(OMAP24XX_AUTOIDLE, OMAP24XX_PRCM_SYSCONFIG);
647 /* Set all domain wakeup dependencies */
648 prm_write_mod_reg(OMAP_EN_WKUP, MPU_MOD, PM_WKDEP);
649 prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
650 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
652 l = prm_read_mod_reg(CORE_MOD, PM_PWSTCTRL);
653 /* Enable retention for all memory blocks */
654 l |= OMAP24XX_MEM3RETSTATE | OMAP24XX_MEM2RETSTATE |
655 OMAP24XX_MEM1RETSTATE;
657 /* Set power state to RETENTION */
658 l &= ~OMAP_POWERSTATE_MASK;
659 l |= 0x01 << OMAP_POWERSTATE_SHIFT;
660 prm_write_mod_reg(l, CORE_MOD, PM_PWSTCTRL);
662 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
664 MPU_MOD, PM_PWSTCTRL);
666 /* Power down DSP and GFX */
667 prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
668 OMAP24XX_DSP_MOD, PM_PWSTCTRL);
669 prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
670 GFX_MOD, PM_PWSTCTRL);
672 /* Enable clock auto control for all domains */
673 cm_write_mod_reg(OMAP24XX_AUTOSTATE_MPU, MPU_MOD, CM_CLKSTCTRL);
674 cm_write_mod_reg(OMAP24XX_AUTOSTATE_DSS | OMAP24XX_AUTOSTATE_L4 |
675 OMAP24XX_AUTOSTATE_L3,
676 CORE_MOD, CM_CLKSTCTRL);
677 cm_write_mod_reg(OMAP24XX_AUTOSTATE_GFX, GFX_MOD, CM_CLKSTCTRL);
678 cm_write_mod_reg(OMAP2420_AUTOSTATE_IVA | OMAP24XX_AUTOSTATE_DSP,
679 OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
681 /* Enable clock autoidle for all domains */
682 cm_write_mod_reg(OMAP24XX_AUTO_CAM |
683 OMAP24XX_AUTO_MAILBOXES |
686 OMAP24XX_AUTO_MSPRO |
691 OMAP24XX_AUTO_UART2 |
692 OMAP24XX_AUTO_UART1 |
695 OMAP24XX_AUTO_MCSPI2 |
696 OMAP24XX_AUTO_MCSPI1 |
697 OMAP24XX_AUTO_MCBSP2 |
698 OMAP24XX_AUTO_MCBSP1 |
699 OMAP24XX_AUTO_GPT12 |
700 OMAP24XX_AUTO_GPT11 |
701 OMAP24XX_AUTO_GPT10 |
710 OMAP2420_AUTO_VLYNQ |
712 CORE_MOD, CM_AUTOIDLE1);
713 cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
716 CORE_MOD, CM_AUTOIDLE2);
717 cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
720 CORE_MOD, OMAP24XX_CM_AUTOIDLE3);
721 cm_write_mod_reg(OMAP24XX_AUTO_PKA |
726 CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
728 cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
730 /* Put DPLL and both APLLs into autoidle mode */
731 cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
732 (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
733 (0x03 << OMAP24XX_AUTO_54M_SHIFT),
734 PLL_MOD, CM_AUTOIDLE);
736 cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
738 OMAP24XX_AUTO_MPU_WDT |
739 OMAP24XX_AUTO_GPIOS |
740 OMAP24XX_AUTO_32KSYNC |
742 WKUP_MOD, CM_AUTOIDLE);
744 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
746 prm_write_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_CLKSSETUP);
748 /* Configure automatic voltage transition */
749 prm_write_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_VOLTSETUP);
750 prm_write_reg(OMAP24XX_AUTO_EXTVOLT |
751 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
752 OMAP24XX_MEMRETCTRL |
753 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
754 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
755 OMAP24XX_PRCM_VOLTCTRL);
757 /* Enable wake-up events */
758 prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
762 int __init omap2_pm_init(void)
766 printk(KERN_INFO "Power Management for OMAP2 initializing\n");
767 l = prm_read_reg(OMAP24XX_PRCM_REVISION);
768 printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
770 osc_ck = clk_get(NULL, "osc_ck");
771 if (IS_ERR(osc_ck)) {
772 printk(KERN_ERR "could not get osc_ck\n");
776 if (cpu_is_omap242x()) {
777 emul_ck = clk_get(NULL, "emul_ck");
778 if (IS_ERR(emul_ck)) {
779 printk(KERN_ERR "could not get emul_ck\n");
787 pm_init_serial_console();
789 /* Hack to prevent MPU retention when STI console is enabled. */
791 const struct omap_sti_console_config *sti;
793 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
794 struct omap_sti_console_config);
795 if (sti != NULL && sti->enable)
796 sti_console_enabled = 1;
800 * We copy the assembler sleep/wakeup routines to SRAM.
801 * These routines need to be in SRAM as that's the only
802 * memory the MPU can see when it wakes up.
804 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
805 omap24xx_idle_loop_suspend_sz);
806 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
807 omap24xx_cpu_suspend_sz);
809 suspend_set_ops(&omap_pm_ops);
810 pm_idle = omap2_pm_idle;
812 l = subsys_create_file(&power_subsys, &sleep_while_idle_attr);
814 printk(KERN_ERR "subsys_create_file failed: %d\n", l);
819 late_initcall(omap2_pm_init);