arch/arm/mach-omap2/pm.c

   1 /*
   2  * linux/arch/arm/mach-omap2/pm.c
   3  *
   4  * OMAP2 Power Management Routines
   5  *
   6  * Copyright (C) 2005 Texas Instruments, Inc.
   7  * Copyright (C) 2006 Nokia Corporation
   8  *
   9  * Written by:
  10  * Richard Woodruff <r-woodruff2@ti.com>
  11  * Tony Lindgren
  12  * Juha Yrjola
  13  * Amit Kucheria <amit.kucheria@nokia.com>
  14  * Igor Stoppa <igor.stoppa@nokia.com>
  15  *
  16  * Based on pm.c for omap1
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  */
  22
  23 #include <linux/pm.h>
  24 #include <linux/sched.h>
  25 #include <linux/proc_fs.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/sysfs.h>
  28 #include <linux/module.h>
  29 #include <linux/delay.h>
  30 #include <linux/clk.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34 #include <asm/atomic.h>
  35 #include <asm/mach/time.h>
  36 #include <asm/mach/irq.h>
  37 #include <asm/mach-types.h>
  38
  39 #include <asm/arch/irqs.h>
  40 #include <asm/arch/clock.h>
  41 #include <asm/arch/sram.h>
  42 #include <asm/arch/pm.h>
  43 #include <asm/arch/mux.h>
  44 #include <asm/arch/dma.h>
  45 #include <asm/arch/board.h>
  46 #include <asm/arch/gpio.h>
  47
  48 #include "prm.h"
  49 #include "prm_regbits_24xx.h"
  50 #include "cm.h"
  51 #include "cm_regbits_24xx.h"
  52 #include "sdrc.h"
  53
  54 static void (*omap2_sram_idle)(void);
  55 static void (*omap2_sram_suspend)(void __iomem *dllctrl);
  56 static void (*saved_idle)(void);
  57
  58 static u32 omap2_read_32k_sync_counter(void)
  59 {
  60         return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
  61 }
  62
  63 #ifdef CONFIG_PM_DEBUG
  64 int omap2_pm_debug = 0;
  65
  66 static int serial_console_clock_disabled;
  67 static int serial_console_uart;
  68 static unsigned int serial_console_next_disable;
  69
  70 static struct clk *console_iclk, *console_fclk;
  71
  72 static void serial_console_kick(void)
  73 {
  74         serial_console_next_disable = omap2_read_32k_sync_counter();
  75         /* Keep the clocks on for 4 secs */
  76         serial_console_next_disable += 4 * 32768;
  77 }
  78
  79 static void serial_wait_tx(void)
  80 {
  81         static const unsigned long uart_bases[3] = {
  82                 0x4806a000, 0x4806c000, 0x4806e000
  83         };
  84         unsigned long lsr_reg;
  85         int looped = 0;
  86
  87         /* Wait for TX FIFO and THR to get empty */
  88         lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2));
  89         while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
  90                 looped = 1;
  91         if (looped)
  92                 serial_console_kick();
  93 }
  94
  95 static void serial_console_fclk_mask(u32 *f1, u32 *f2)
  96 {
  97         switch (serial_console_uart)  {
  98         case 1:
  99                 *f1 &= ~(1 << 21);
 100                 break;
 101         case 2:
 102                 *f1 &= ~(1 << 22);
 103                 break;
 104         case 3:
 105                 *f2 &= ~(1 << 2);
 106                 break;
 107         }
 108 }
 109
 110 static void serial_console_sleep(int enable)
 111 {
 112         if (console_iclk == NULL || console_fclk == NULL)
 113                 return;
 114
 115         if (enable) {
 116                 BUG_ON(serial_console_clock_disabled);
 117                 if (clk_get_usecount(console_fclk) == 0)
 118                         return;
 119                 if ((int) serial_console_next_disable - (int) omap2_read_32k_sync_counter() >= 0)
 120                         return;
 121                 serial_wait_tx();
 122                 clk_disable(console_iclk);
 123                 clk_disable(console_fclk);
 124                 serial_console_clock_disabled = 1;
 125         } else {
 126                 int serial_wakeup = 0;
 127                 u32 l;
 128
 129                 switch (serial_console_uart)  {
 130                 case 1:
 131                         l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
 132                         if (l & OMAP24XX_ST_UART1)
 133                                 serial_wakeup = 1;
 134                         break;
 135                 case 2:
 136                         l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
 137                         if (l & OMAP24XX_ST_UART2)
 138                                 serial_wakeup = 1;
 139                         break;
 140                 case 3:
 141                         l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKST2);
 142                         if (l & OMAP24XX_ST_UART3)
 143                                 serial_wakeup = 1;
 144                         break;
 145                 }
 146                 if (serial_wakeup)
 147                         serial_console_kick();
 148                 if (!serial_console_clock_disabled)
 149                         return;
 150                 clk_enable(console_iclk);
 151                 clk_enable(console_fclk);
 152                 serial_console_clock_disabled = 0;
 153         }
 154 }
 155
 156 static void pm_init_serial_console(void)
 157 {
 158         const struct omap_serial_console_config *conf;
 159         char name[16];
 160         u32 l;
 161
 162         conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
 163                                struct omap_serial_console_config);
 164         if (conf == NULL)
 165                 return;
 166         if (conf->console_uart > 3 || conf->console_uart < 1)
 167                 return;
 168         serial_console_uart = conf->console_uart;
 169         sprintf(name, "uart%d_fck", conf->console_uart);
 170         console_fclk = clk_get(NULL, name);
 171         if (IS_ERR(console_fclk))
 172                 console_fclk = NULL;
 173         name[6] = 'i';
 174         console_iclk = clk_get(NULL, name);
 175         if (IS_ERR(console_fclk))
 176                 console_iclk = NULL;
 177         if (console_fclk == NULL || console_iclk == NULL) {
 178                 serial_console_uart = 0;
 179                 return;
 180         }
 181         switch (serial_console_uart) {
 182         case 1:
 183                 l = prm_read_mod_reg(CORE_MOD, PM_WKEN1);
 184                 l |= OMAP24XX_ST_UART1;
 185                 prm_write_mod_reg(l, CORE_MOD, PM_WKEN1);
 186                 break;
 187         case 2:
 188                 l = prm_read_mod_reg(CORE_MOD, PM_WKEN1);
 189                 l |= OMAP24XX_ST_UART2;
 190                 prm_write_mod_reg(l, CORE_MOD, PM_WKEN1);
 191                 break;
 192         case 3:
 193                 l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKEN2);
 194                 l |= OMAP24XX_ST_UART3;
 195                 prm_write_mod_reg(l, CORE_MOD, OMAP24XX_PM_WKEN2);
 196                 break;
 197         }
 198 }
 199
 200 #define DUMP_PRM_MOD_REG(mod, reg)    \
 201         regs[reg_count].name = #mod "." #reg; \
 202         regs[reg_count++].val = prm_read_mod_reg(mod, reg)
 203 #define DUMP_CM_MOD_REG(mod, reg)     \
 204         regs[reg_count].name = #mod "." #reg; \
 205         regs[reg_count++].val = cm_read_mod_reg(mod, reg)
 206 #define DUMP_PRM_REG(reg) \
 207         regs[reg_count].name = #reg; \
 208         regs[reg_count++].val = prm_read_reg(reg)
 209 #define DUMP_CM_REG(reg) \
 210         regs[reg_count].name = #reg; \
 211         regs[reg_count++].val = cm_read_reg(reg)
 212 #define DUMP_INTC_REG(reg, off) \
 213         regs[reg_count].name = #reg; \
 214         regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off)))
 215
 216 static void omap2_pm_dump(int mode, int resume, unsigned int us)
 217 {
 218         struct reg {
 219                 const char *name;
 220                 u32 val;
 221         } regs[32];
 222         int reg_count = 0, i;
 223         const char *s1 = NULL, *s2 = NULL;
 224
 225         if (!resume) {
 226 #if 0
 227                 /* MPU */
 228                 DUMP_PRM_REG(OMAP24XX_PRCM_IRQENABLE_MPU);
 229                 DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL);
 230                 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL);
 231                 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST);
 232                 DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
 233 #endif
 234 #if 0
 235                 /* INTC */
 236                 DUMP_INTC_REG(INTC_MIR0, 0x0084);
 237                 DUMP_INTC_REG(INTC_MIR1, 0x00a4);
 238                 DUMP_INTC_REG(INTC_MIR2, 0x00c4);
 239 #endif
 240 #if 0
 241                 DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
 242                 DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN2);
 243                 DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
 244                 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
 245                 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
 246                 DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
 247                 DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN_PLL);
 248                 DUMP_PRM_REG(OMAP24XX_PRCM_CLKEMUL_CTRL);
 249                 DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
 250                 DUMP_PRM_MOD_REG(CORE_REG, PM_PWSTST);
 251                 DUMP_PRM_REG(OMAP24XX_PRCM_CLKSRC_CTRL);
 252 #endif
 253 #if 0
 254                 /* DSP */
 255                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
 256                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
 257                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
 258                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
 259                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
 260                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
 261                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL);
 262                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST);
 263                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL);
 264                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST);
 265 #endif
 266         } else {
 267                 DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
 268                 DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
 269                 DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
 270                 DUMP_PRM_REG(OMAP24XX_PRCM_IRQSTATUS_MPU);
 271 #if 1
 272                 DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
 273                 DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
 274                 DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
 275 #endif
 276         }
 277
 278         switch (mode) {
 279         case 0:
 280                 s1 = "full";
 281                 s2 = "retention";
 282                 break;
 283         case 1:
 284                 s1 = "MPU";
 285                 s2 = "retention";
 286                 break;
 287         case 2:
 288                 s1 = "MPU";
 289                 s2 = "idle";
 290                 break;
 291         }
 292
 293         if (!resume)
 294 #if defined(CONFIG_NO_IDLE_HZ) || defined(CONFIG_NO_HZ)
 295                 printk("--- Going to %s %s (next timer after %u ms)\n", s1, s2,
 296                        jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
 297                                         jiffies));
 298 #else
 299                 printk("--- Going to %s %s\n", s1, s2);
 300 #endif
 301         else
 302                 printk("--- Woke up (slept for %u.%03u ms)\n", us / 1000, us % 1000);
 303         for (i = 0; i < reg_count; i++)
 304                 printk("%-20s: 0x%08x\n", regs[i].name, regs[i].val);
 305 }
 306
 307 #else
 308 static inline void serial_console_sleep(int enable) {}
 309 static inline void pm_init_serial_console(void) {}
 310 static inline void omap2_pm_dump(int mode, int resume, unsigned int us) {}
 311 static inline void serial_console_fclk_mask(u32 *f1, u32 *f2) {}
 312
 313 #define omap2_pm_debug 0
 314
 315 #endif
 316
 317 static unsigned short enable_dyn_sleep = 0; /* disabled till drivers are fixed */
 318
 319 static ssize_t omap_pm_sleep_while_idle_show(struct kset * subsys, char *buf)
 320 {
 321         return sprintf(buf, "%hu\n", enable_dyn_sleep);
 322 }
 323
 324 static ssize_t omap_pm_sleep_while_idle_store(struct kset * subsys,
 325                                               const char * buf,
 326                                               size_t n)
 327 {
 328         unsigned short value;
 329         if (sscanf(buf, "%hu", &value) != 1 ||
 330             (value != 0 && value != 1)) {
 331                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
 332                 return -EINVAL;
 333         }
 334         enable_dyn_sleep = value;
 335         return n;
 336 }
 337
 338 static struct subsys_attribute sleep_while_idle_attr = {
 339         .attr   = {
 340                 .name = __stringify(sleep_while_idle),
 341                 .mode = 0644,
 342         },
 343         .show   = omap_pm_sleep_while_idle_show,
 344         .store  = omap_pm_sleep_while_idle_store,
 345 };
 346
 347 static struct clk *osc_ck, *emul_ck;
 348
 349 #define CONTROL_DEVCONF         __REG32(OMAP2_CTRL_BASE + 0x274)
 350
 351 static int omap2_fclks_active(void)
 352 {
 353         u32 f1, f2;
 354
 355         f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 356         f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 357         serial_console_fclk_mask(&f1, &f2);
 358         if (f1 | f2)
 359                 return 1;
 360         return 0;
 361 }
 362
 363 static int omap2_irq_pending(void)
 364 {
 365         u32 pending_reg = IO_ADDRESS(0x480fe098);
 366         int i;
 367
 368         for (i = 0; i < 4; i++) {
 369                 if (__raw_readl(pending_reg))
 370                         return 1;
 371                 pending_reg += 0x20;
 372         }
 373         return 0;
 374 }
 375
 376 static atomic_t sleep_block = ATOMIC_INIT(0);
 377
 378 void omap2_block_sleep(void)
 379 {
 380         atomic_inc(&sleep_block);
 381 }
 382
 383 void omap2_allow_sleep(void)
 384 {
 385         int i;
 386
 387         i = atomic_dec_return(&sleep_block);
 388         BUG_ON(i < 0);
 389 }
 390
 391 static void omap2_enter_full_retention(void)
 392 {
 393         u32 sleep_time = 0;
 394
 395         /* There is 1 reference hold for all children of the oscillator
 396          * clock, the following will remove it. If no one else uses the
 397          * oscillator itself it will be disabled if/when we enter retention
 398          * mode.
 399          */
 400         clk_disable(osc_ck);
 401
 402         /* Clear old wake-up events */
 403         /* REVISIT: These write to reserved bits? */
 404         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 405         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 406         prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 407
 408         /* Try to enter retention */
 409         prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | OMAP_LOGICRETSTATE,
 410                           MPU_MOD, PM_PWSTCTRL);
 411
 412         /* Workaround to kill USB */
 413         CONTROL_DEVCONF |= 0x00008000;
 414
 415         omap2_gpio_prepare_for_retention();
 416
 417         if (omap2_pm_debug) {
 418                 omap2_pm_dump(0, 0, 0);
 419                 sleep_time = omap2_read_32k_sync_counter();
 420         }
 421
 422         /* One last check for pending IRQs to avoid extra latency due
 423          * to sleeping unnecessarily. */
 424         if (omap2_irq_pending())
 425                 goto no_sleep;
 426
 427         serial_console_sleep(1);
 428         /* Jump to SRAM suspend code */
 429         omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
 430 no_sleep:
 431         serial_console_sleep(0);
 432
 433         if (omap2_pm_debug) {
 434                 unsigned long long tmp;
 435                 u32 resume_time;
 436
 437                 resume_time = omap2_read_32k_sync_counter();
 438                 tmp = resume_time - sleep_time;
 439                 tmp *= 1000000;
 440                 omap2_pm_dump(0, 1, tmp / 32768);
 441         }
 442         omap2_gpio_resume_after_retention();
 443
 444         clk_enable(osc_ck);
 445
 446 }
 447
 448 static int omap2_i2c_active(void)
 449 {
 450         u32 l;
 451
 452         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 453         return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
 454 }
 455
 456 static int sti_console_enabled;
 457
 458 static int omap2_allow_mpu_retention(void)
 459 {
 460         u32 l;
 461
 462         if (atomic_read(&sleep_block))
 463                 return 0;
 464
 465         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 466         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 467         if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
 468                  OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
 469                  OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
 470                 return 0;
 471         /* Check for UART3. */
 472         l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 473         if (l & OMAP24XX_EN_UART3)
 474                 return 0;
 475         if (sti_console_enabled)
 476                 return 0;
 477
 478         return 1;
 479 }
 480
 481 static void omap2_enter_mpu_retention(void)
 482 {
 483         u32 sleep_time = 0;
 484         int only_idle = 0;
 485
 486         /* Putting MPU into the WFI state while a transfer is active
 487          * seems to cause the I2C block to timeout. Why? Good question. */
 488         if (omap2_i2c_active())
 489                 return;
 490
 491         /* The peripherals seem not to be able to wake up the MPU when
 492          * it is in retention mode. */
 493         if (omap2_allow_mpu_retention()) {
 494                 /* REVISIT: These write to reserved bits? */
 495                 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 496                 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 497                 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 498
 499                 /* Try to enter MPU retention */
 500                 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 501                                   OMAP_LOGICRETSTATE,
 502                                   MPU_MOD, PM_PWSTCTRL);
 503         } else {
 504                 /* Block MPU retention */
 505
 506                 prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
 507                 only_idle = 1;
 508         }
 509
 510         if (omap2_pm_debug) {
 511                 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
 512                 sleep_time = omap2_read_32k_sync_counter();
 513         }
 514
 515         omap2_sram_idle();
 516
 517         if (omap2_pm_debug) {
 518                 unsigned long long tmp;
 519                 u32 resume_time;
 520
 521                 resume_time = omap2_read_32k_sync_counter();
 522                 tmp = resume_time - sleep_time;
 523                 tmp *= 1000000;
 524                 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
 525         }
 526 }
 527
 528 static int omap2_can_sleep(void)
 529 {
 530         if (!enable_dyn_sleep)
 531                 return 0;
 532         if (omap2_fclks_active())
 533                 return 0;
 534         if (atomic_read(&sleep_block) > 0)
 535                 return 0;
 536         if (clk_get_usecount(osc_ck) > 1)
 537                 return 0;
 538         if (omap_dma_running())
 539                 return 0;
 540
 541         return 1;
 542 }
 543
 544 static void omap2_pm_idle(void)
 545 {
 546         local_irq_disable();
 547         local_fiq_disable();
 548
 549         if (!omap2_can_sleep()) {
 550                 /* timer_dyn_reprogram() takes about 100-200 us to complete.
 551                  * In some contexts (e.g. when waiting for a GPMC-SDRAM DMA
 552                  * transfer to complete), the increased latency is too much.
 553                  *
 554                  * omap2_block_sleep() and omap2_allow_sleep() can be used
 555                  * to indicate this.
 556                  */
 557                 if (atomic_read(&sleep_block) == 0) {
 558                         timer_dyn_reprogram();
 559                         if (omap2_irq_pending())
 560                                 goto out;
 561                 }
 562                 omap2_enter_mpu_retention();
 563                 goto out;
 564         }
 565
 566         /*
 567          * Since an interrupt may set up a timer, we don't want to
 568          * reprogram the hardware timer with interrupts enabled.
 569          * Re-enable interrupts only after returning from idle.
 570          */
 571         timer_dyn_reprogram();
 572
 573         if (omap2_irq_pending())
 574                 goto out;
 575
 576         omap2_enter_full_retention();
 577
 578 out:
 579         local_fiq_enable();
 580         local_irq_enable();
 581 }
 582
 583 static int omap2_pm_prepare(suspend_state_t state)
 584 {
 585         int error = 0;
 586
 587         /* We cannot sleep in idle until we have resumed */
 588         saved_idle = pm_idle;
 589         pm_idle = NULL;
 590
 591         switch (state) {
 592         case PM_SUSPEND_STANDBY:
 593         case PM_SUSPEND_MEM:
 594                 break;
 595         default:
 596                 return -EINVAL;
 597         }
 598
 599         return error;
 600 }
 601
 602 static int omap2_pm_suspend(void)
 603 {
 604         u32 wken_wkup, mir1;
 605
 606         wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 607         prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
 608
 609         /* Mask GPT1 */
 610         mir1 = omap_readl(0x480fe0a4);
 611         omap_writel(1 << 5, 0x480fe0ac);
 612
 613         omap2_enter_full_retention();
 614
 615         omap_writel(mir1, 0x480fe0a4);
 616         prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 617
 618         return 0;
 619 }
 620
 621 static int omap2_pm_enter(suspend_state_t state)
 622 {
 623         int ret = 0;
 624
 625         switch (state) {
 626         case PM_SUSPEND_STANDBY:
 627         case PM_SUSPEND_MEM:
 628                 ret = omap2_pm_suspend();
 629                 break;
 630         default:
 631                 ret = -EINVAL;
 632         }
 633
 634         return ret;
 635 }
 636
 637 static int omap2_pm_finish(suspend_state_t state)
 638 {
 639         pm_idle = saved_idle;
 640         return 0;
 641 }
 642
 643 static struct pm_ops omap_pm_ops = {
 644         .prepare        = omap2_pm_prepare,
 645         .enter          = omap2_pm_enter,
 646         .finish         = omap2_pm_finish,
 647         .valid          = pm_valid_only_mem,
 648 };
 649
 650 static void __init prcm_setup_regs(void)
 651 {
 652         u32 l;
 653
 654         /* Enable autoidle */
 655         prm_write_reg(OMAP24XX_AUTOIDLE, OMAP24XX_PRCM_SYSCONFIG);
 656
 657         /* Set all domain wakeup dependencies */
 658         prm_write_mod_reg(OMAP_EN_WKUP, MPU_MOD, PM_WKDEP);
 659         prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
 660         prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 661
 662         l = prm_read_mod_reg(CORE_MOD, PM_PWSTCTRL);
 663         /* Enable retention for all memory blocks */
 664         l |= OMAP24XX_MEM3RETSTATE | OMAP24XX_MEM2RETSTATE |
 665                 OMAP24XX_MEM1RETSTATE;
 666
 667         /* Set power state to RETENTION */
 668         l &= ~OMAP_POWERSTATE_MASK;
 669         l |= 0x01 << OMAP_POWERSTATE_SHIFT;
 670         prm_write_mod_reg(l, CORE_MOD, PM_PWSTCTRL);
 671
 672         prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 673                           OMAP_LOGICRETSTATE,
 674                           MPU_MOD, PM_PWSTCTRL);
 675
 676         /* Power down DSP and GFX */
 677         prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
 678                           OMAP24XX_DSP_MOD, PM_PWSTCTRL);
 679         prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
 680                           GFX_MOD, PM_PWSTCTRL);
 681
 682         /* Enable clock auto control for all domains */
 683         cm_write_mod_reg(OMAP24XX_AUTOSTATE_MPU, MPU_MOD, CM_CLKSTCTRL);
 684         cm_write_mod_reg(OMAP24XX_AUTOSTATE_DSS | OMAP24XX_AUTOSTATE_L4 |
 685                          OMAP24XX_AUTOSTATE_L3,
 686                          CORE_MOD, CM_CLKSTCTRL);
 687         cm_write_mod_reg(OMAP24XX_AUTOSTATE_GFX, GFX_MOD, CM_CLKSTCTRL);
 688         cm_write_mod_reg(OMAP2420_AUTOSTATE_IVA | OMAP24XX_AUTOSTATE_DSP,
 689                          OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
 690
 691         /* Enable clock autoidle for all domains */
 692         cm_write_mod_reg(OMAP24XX_AUTO_CAM |
 693                          OMAP24XX_AUTO_MAILBOXES |
 694                          OMAP24XX_AUTO_WDT4 |
 695                          OMAP2420_AUTO_WDT3 |
 696                          OMAP24XX_AUTO_MSPRO |
 697                          OMAP2420_AUTO_MMC |
 698                          OMAP24XX_AUTO_FAC |
 699                          OMAP2420_AUTO_EAC |
 700                          OMAP24XX_AUTO_HDQ |
 701                          OMAP24XX_AUTO_UART2 |
 702                          OMAP24XX_AUTO_UART1 |
 703                          OMAP24XX_AUTO_I2C2 |
 704                          OMAP24XX_AUTO_I2C1 |
 705                          OMAP24XX_AUTO_MCSPI2 |
 706                          OMAP24XX_AUTO_MCSPI1 |
 707                          OMAP24XX_AUTO_MCBSP2 |
 708                          OMAP24XX_AUTO_MCBSP1 |
 709                          OMAP24XX_AUTO_GPT12 |
 710                          OMAP24XX_AUTO_GPT11 |
 711                          OMAP24XX_AUTO_GPT10 |
 712                          OMAP24XX_AUTO_GPT9 |
 713                          OMAP24XX_AUTO_GPT8 |
 714                          OMAP24XX_AUTO_GPT7 |
 715                          OMAP24XX_AUTO_GPT6 |
 716                          OMAP24XX_AUTO_GPT5 |
 717                          OMAP24XX_AUTO_GPT4 |
 718                          OMAP24XX_AUTO_GPT3 |
 719                          OMAP24XX_AUTO_GPT2 |
 720                          OMAP2420_AUTO_VLYNQ |
 721                          OMAP24XX_AUTO_DSS,
 722                          CORE_MOD, CM_AUTOIDLE1);
 723         cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
 724                          OMAP24XX_AUTO_SSI |
 725                          OMAP24XX_AUTO_USB,
 726                          CORE_MOD, CM_AUTOIDLE2);
 727         cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
 728                          OMAP24XX_AUTO_GPMC |
 729                          OMAP24XX_AUTO_SDMA,
 730                          CORE_MOD, OMAP24XX_CM_AUTOIDLE3);
 731         cm_write_mod_reg(OMAP24XX_AUTO_PKA |
 732                          OMAP24XX_AUTO_AES |
 733                          OMAP24XX_AUTO_RNG |
 734                          OMAP24XX_AUTO_SHA |
 735                          OMAP24XX_AUTO_DES,
 736                          CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
 737
 738         cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
 739
 740         /* Put DPLL and both APLLs into autoidle mode */
 741         cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
 742                          (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
 743                          (0x03 << OMAP24XX_AUTO_54M_SHIFT),
 744                          PLL_MOD, CM_AUTOIDLE);
 745
 746         cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
 747                          OMAP24XX_AUTO_WDT1 |
 748                          OMAP24XX_AUTO_MPU_WDT |
 749                          OMAP24XX_AUTO_GPIOS |
 750                          OMAP24XX_AUTO_32KSYNC |
 751                          OMAP24XX_AUTO_GPT1,
 752                          WKUP_MOD, CM_AUTOIDLE);
 753
 754         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 755          * stabilisation */
 756         prm_write_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_CLKSSETUP);
 757
 758         /* Configure automatic voltage transition */
 759         prm_write_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_VOLTSETUP);
 760         prm_write_reg(OMAP24XX_AUTO_EXTVOLT |
 761                       (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 762                       OMAP24XX_MEMRETCTRL |
 763                       (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 764                       (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 765                       OMAP24XX_PRCM_VOLTCTRL);
 766
 767         /* Enable wake-up events */
 768         prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
 769                           WKUP_MOD, PM_WKEN);
 770 }
 771
 772 int __init omap2_pm_init(void)
 773 {
 774         u32 l;
 775
 776         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 777         l = prm_read_reg(OMAP24XX_PRCM_REVISION);
 778         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 779
 780         osc_ck = clk_get(NULL, "osc_ck");
 781         if (IS_ERR(osc_ck)) {
 782                 printk(KERN_ERR "could not get osc_ck\n");
 783                 return -ENODEV;
 784         }
 785
 786         if (cpu_is_omap242x()) {
 787                 emul_ck = clk_get(NULL, "emul_ck");
 788                 if (IS_ERR(emul_ck)) {
 789                         printk(KERN_ERR "could not get emul_ck\n");
 790                         clk_put(osc_ck);
 791                         return -ENODEV;
 792                 }
 793         }
 794
 795         prcm_setup_regs();
 796
 797         pm_init_serial_console();
 798
 799         /* Hack to prevent MPU retention when STI console is enabled. */
 800         {
 801                 const struct omap_sti_console_config *sti;
 802
 803                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 804                                       struct omap_sti_console_config);
 805                 if (sti != NULL && sti->enable)
 806                         sti_console_enabled = 1;
 807         }
 808
 809         /*
 810          * We copy the assembler sleep/wakeup routines to SRAM.
 811          * These routines need to be in SRAM as that's the only
 812          * memory the MPU can see when it wakes up.
 813          */
 814         omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 815                                          omap24xx_idle_loop_suspend_sz);
 816         omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 817                                             omap24xx_cpu_suspend_sz);
 818
 819         pm_set_ops(&omap_pm_ops);
 820         pm_idle = omap2_pm_idle;
 821
 822         l = subsys_create_file(&power_subsys, &sleep_while_idle_attr);
 823         if (l)
 824                 printk(KERN_ERR "subsys_create_file failed: %d\n", l);
 825
 826         return 0;
 827 }
 828
 829 late_initcall(omap2_pm_init);