arch/arm/mach-omap2/pm.c

   1 /*
   2  * linux/arch/arm/mach-omap2/pm.c
   3  *
   4  * OMAP2 Power Management Routines
   5  *
   6  * Copyright (C) 2005 Texas Instruments, Inc.
   7  * Copyright (C) 2006 Nokia Corporation
   8  *
   9  * Written by:
  10  * Richard Woodruff <r-woodruff2@ti.com>
  11  * Tony Lindgren
  12  * Juha Yrjola
  13  * Amit Kucheria <amit.kucheria@nokia.com>
  14  * Igor Stoppa <igor.stoppa@nokia.com>
  15  *
  16  * Based on pm.c for omap1
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  */
  22
  23 #include <linux/pm.h>
  24 #include <linux/sched.h>
  25 #include <linux/proc_fs.h>
  26 #include <linux/pm.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/sysfs.h>
  29 #include <linux/module.h>
  30 #include <linux/delay.h>
  31 #include <linux/clk.h>
  32
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35 #include <asm/atomic.h>
  36 #include <asm/mach/time.h>
  37 #include <asm/mach/irq.h>
  38 #include <asm/mach-types.h>
  39
  40 #include <asm/arch/irqs.h>
  41 #include <asm/arch/clock.h>
  42 #include <asm/arch/sram.h>
  43 #include <asm/arch/pm.h>
  44 #include <asm/arch/mux.h>
  45 #include <asm/arch/dma.h>
  46 #include <asm/arch/board.h>
  47
  48 #define PRCM_REVISION           0x000
  49 #define PRCM_SYSCONFIG          0x010
  50 #define PRCM_IRQSTATUS_MPU      0x018
  51 #define PRCM_IRQENABLE_MPU      0x01c
  52 #define PRCM_VOLTCTRL           0x050
  53 #define         AUTO_EXTVOLT    (1 << 15)
  54 #define         FORCE_EXTVOLT   (1 << 14)
  55 #define         SETOFF_LEVEL(x) (((x) & 0x3) << 12)
  56 #define         MEMRETCTRL      (1 << 8)
  57 #define         SETRET_LEVEL(x) (((x) & 0x3) << 6)
  58 #define         VOLT_LEVEL(x)   (((x) & 0x3) << 0)
  59 #define PRCM_CLKSRC_CTRL        0x060
  60 #define PRCM_CLKOUT_CTRL        0x070
  61 #define PRCM_CLKEMUL_CTRL       0x078
  62 #define PRCM_CLKCFG_CTRL        0x080
  63 #define PRCM_VOLTSETUP          0x090
  64 #define PRCM_CLKSSETUP          0x094
  65
  66
  67 #define CM_CLKSEL_MPU           0x140
  68 #define CM_CLKSTCTRL_MPU        0x148
  69 #define         AUTOSTAT_MPU    (1 << 0)
  70 #define PM_WKDEP_MPU            0x1c8
  71 #define         EN_WKUP         (1 << 4)
  72 #define         EN_GFX          (1 << 3)
  73 #define         EN_DSP          (1 << 2)
  74 #define         EN_MPU          (1 << 1)
  75 #define         EN_CORE         (1 << 0)
  76 #define PM_PWSTCTRL_MPU         0x1e0
  77 #define PM_PWSTST_MPU           0x1e4
  78
  79
  80 #define CM_FCLKEN1_CORE         0x200
  81 #define CM_FCLKEN2_CORE         0x204
  82 #define CM_ICLKEN1_CORE         0x210
  83 #define CM_ICLKEN2_CORE         0x214
  84 #define CM_ICLKEN4_CORE         0x21c
  85 #define CM_IDLEST1_CORE         0x220
  86 #define CM_IDLEST2_CORE         0x224
  87 #define CM_AUTOIDLE1_CORE       0x230
  88 #define CM_AUTOIDLE2_CORE       0x234
  89 #define CM_AUTOIDLE3_CORE       0x238
  90 #define CM_AUTOIDLE4_CORE       0x23c
  91 #define CM_CLKSEL1_CORE         0x240
  92 #define CM_CLKSEL2_CORE         0x244
  93 #define CM_CLKSTCTRL_CORE       0x248
  94 #define         AUTOSTAT_DSS    (1 << 2)
  95 #define         AUTOSTAT_L4     (1 << 1)
  96 #define         AUTOSTAT_L3     (1 << 0)
  97 #define PM_WKEN1_CORE           0x2a0
  98 #define PM_WKEN2_CORE           0x2a4
  99 #define PM_WKST1_CORE           0x2b0
 100 #define PM_WKST2_CORE           0x2b4
 101 #define PM_WKDEP_CORE           0x2c8
 102 #define PM_PWSTCTRL_CORE        0x2e0
 103 #define PM_PWSTST_CORE          0x2e4
 104
 105
 106 #define CM_CLKSTCTRL_GFX        0x348
 107 #define         AUTOSTAT_GFX    (1 << 0)
 108 #define PM_WKDEP_GFX            0x3c8
 109 #define PM_PWSTCTRL_GFX         0x3e0
 110
 111
 112 #define CM_FCLKEN_WKUP          0x400
 113 #define CM_ICLKEN_WKUP          0x410
 114 #define CM_AUTOIDLE_WKUP        0x430
 115 #define PM_WKEN_WKUP            0x4a0
 116 #define         EN_GPIOS        (1 << 2)
 117 #define         EN_GPT1         (1 << 0)
 118 #define PM_WKST_WKUP            0x4b0
 119
 120
 121 #define CM_CLKEN_PLL            0x500
 122 #define CM_IDLEST_CKGEN         0x520
 123 #define CM_AUTOIDLE_PLL         0x530
 124 #define CM_CLKSEL1_PLL          0x540
 125 #define CM_CLKSEL2_PLL          0x544
 126
 127
 128 #define CM_FCLKEN_DSP           0x800
 129 #define CM_ICLKEN_DSP           0x810
 130 #define CM_IDLEST_DSP           0x820
 131 #define CM_AUTOIDLE_DSP         0x830
 132 #define CM_CLKSEL_DSP           0x840
 133 #define CM_CLKSTCTRL_DSP        0x848
 134 #define         AUTOSTAT_IVA    (1 << 8)
 135 #define         AUTOSTAT_DSP    (1 << 0)
 136 #define RM_RSTCTRL_DSP          0x850
 137 #define RM_RSTST_DSP            0x858
 138 #define PM_WKDEP_DSP            0x8c8
 139 #define PM_PWSTCTRL_DSP         0x8e0
 140 #define PM_PWSTST_DSP           0x8e4
 141
 142 static void (*omap2_sram_idle)(void);
 143 static void (*omap2_sram_suspend)(int dllctrl);
 144 static void (*saved_idle)(void);
 145
 146 static u32 prcm_base = IO_ADDRESS(OMAP24XX_PRCM_BASE);
 147
 148 static inline void prcm_write_reg(int idx, u32 val)
 149 {
 150         __raw_writel(val, prcm_base + idx);
 151 }
 152
 153 static inline u32 prcm_read_reg(int idx)
 154 {
 155         return __raw_readl(prcm_base + idx);
 156 }
 157
 158 static u32 omap2_read_32k_sync_counter(void)
 159 {
 160         return omap_readl(0x48004010);
 161 }
 162
 163 #ifdef CONFIG_PM_DEBUG
 164 int omap2_pm_debug = 0;
 165
 166 static int serial_console_clock_disabled;
 167 static int serial_console_uart;
 168 static unsigned int serial_console_next_disable;
 169
 170 static struct clk *console_iclk, *console_fclk;
 171
 172 static void serial_console_kick(void)
 173 {
 174         serial_console_next_disable = omap2_read_32k_sync_counter();
 175         /* Keep the clocks on for 4 secs */
 176         serial_console_next_disable += 4 * 32768;
 177 }
 178
 179 static void serial_wait_tx(void)
 180 {
 181         static const unsigned long uart_bases[3] = {
 182                 0x4806a000, 0x4806c000, 0x4806e000
 183         };
 184         unsigned long lsr_reg;
 185         int looped = 0;
 186
 187         /* Wait for TX FIFO and THR to get empty */
 188         lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2));
 189         while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
 190                 looped = 1;
 191         if (looped)
 192                 serial_console_kick();
 193 }
 194
 195 static void serial_console_fclk_mask(u32 *f1, u32 *f2)
 196 {
 197         switch (serial_console_uart)  {
 198         case 1:
 199                 *f1 &= ~(1 << 21);
 200                 break;
 201         case 2:
 202                 *f1 &= ~(1 << 22);
 203                 break;
 204         case 3:
 205                 *f2 &= ~(1 << 2);
 206                 break;
 207         }
 208 }
 209
 210 static void serial_console_sleep(int enable)
 211 {
 212         if (console_iclk == NULL || console_fclk == NULL)
 213                 return;
 214
 215         if (enable) {
 216                 BUG_ON(serial_console_clock_disabled);
 217                 if (clk_get_usecount(console_fclk) == 0)
 218                         return;
 219                 if ((int) serial_console_next_disable - (int) omap2_read_32k_sync_counter() >= 0)
 220                         return;
 221                 serial_wait_tx();
 222                 clk_disable(console_iclk);
 223                 clk_disable(console_fclk);
 224                 serial_console_clock_disabled = 1;
 225         } else {
 226                 int serial_wakeup = 0;
 227                 u32 l;
 228
 229                 switch (serial_console_uart)  {
 230                 case 1:
 231                         l = prcm_read_reg(PM_WKST1_CORE);
 232                         if (l & (1 << 21))
 233                                 serial_wakeup = 1;
 234                         break;
 235                 case 2:
 236                         l = prcm_read_reg(PM_WKST1_CORE);
 237                         if (l & (1 << 22))
 238                                 serial_wakeup = 1;
 239                         break;
 240                 case 3:
 241                         l = prcm_read_reg(PM_WKST2_CORE);
 242                         if (l & (1 << 2))
 243                                 serial_wakeup = 1;
 244                         break;
 245                 }
 246                 if (serial_wakeup)
 247                         serial_console_kick();
 248                 if (!serial_console_clock_disabled)
 249                         return;
 250                 clk_enable(console_iclk);
 251                 clk_enable(console_fclk);
 252                 serial_console_clock_disabled = 0;
 253         }
 254 }
 255
 256 static void pm_init_serial_console(void)
 257 {
 258         const struct omap_serial_console_config *conf;
 259         char name[16];
 260         u32 l;
 261
 262         conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
 263                                struct omap_serial_console_config);
 264         if (conf == NULL)
 265                 return;
 266         if (conf->console_uart > 3 || conf->console_uart < 1)
 267                 return;
 268         serial_console_uart = conf->console_uart;
 269         sprintf(name, "uart%d_fck", conf->console_uart);
 270         console_fclk = clk_get(NULL, name);
 271         if (IS_ERR(console_fclk))
 272                 console_fclk = NULL;
 273         name[6] = 'i';
 274         console_iclk = clk_get(NULL, name);
 275         if (IS_ERR(console_fclk))
 276                 console_iclk = NULL;
 277         if (console_fclk == NULL || console_iclk == NULL) {
 278                 serial_console_uart = 0;
 279                 return;
 280         }
 281         switch (serial_console_uart) {
 282         case 1:
 283                 l = prcm_read_reg(PM_WKEN1_CORE);
 284                 l |= 1 << 21;
 285                 prcm_write_reg(PM_WKEN1_CORE, l);
 286                 break;
 287         case 2:
 288                 l = prcm_read_reg(PM_WKEN1_CORE);
 289                 l |= 1 << 22;
 290                 prcm_write_reg(PM_WKEN1_CORE, l);
 291                 break;
 292         case 3:
 293                 l = prcm_read_reg(PM_WKEN2_CORE);
 294                 l |= 1 << 2;
 295                 prcm_write_reg(PM_WKEN2_CORE, l);
 296                 break;
 297         }
 298 }
 299
 300 #define DUMP_REG(reg) \
 301         regs[reg_count].name = #reg; \
 302         regs[reg_count++].val = prcm_read_reg(reg)
 303 #define DUMP_INTC_REG(reg, off) \
 304         regs[reg_count].name = #reg; \
 305         regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off)))
 306
 307 static void omap2_pm_dump(int mode, int resume, unsigned int us)
 308 {
 309         struct reg {
 310                 const char *name;
 311                 u32 val;
 312         } regs[32];
 313         int reg_count = 0, i;
 314         const char *s1 = NULL, *s2 = NULL;
 315
 316         if (!resume) {
 317 #if 0
 318                 /* MPU */
 319                 DUMP_REG(PRCM_IRQENABLE_MPU);
 320                 DUMP_REG(CM_CLKSTCTRL_MPU);
 321                 DUMP_REG(PM_PWSTCTRL_MPU);
 322                 DUMP_REG(PM_PWSTST_MPU);
 323                 DUMP_REG(PM_WKDEP_MPU);
 324 #endif
 325 #if 0
 326                 /* INTC */
 327                 DUMP_INTC_REG(INTC_MIR0, 0x0084);
 328                 DUMP_INTC_REG(INTC_MIR1, 0x00a4);
 329                 DUMP_INTC_REG(INTC_MIR2, 0x00c4);
 330 #endif
 331 #if 0
 332                 DUMP_REG(CM_FCLKEN1_CORE);
 333                 DUMP_REG(CM_FCLKEN2_CORE);
 334                 DUMP_REG(CM_FCLKEN_WKUP);
 335                 DUMP_REG(CM_ICLKEN1_CORE);
 336                 DUMP_REG(CM_ICLKEN2_CORE);
 337                 DUMP_REG(CM_ICLKEN_WKUP);
 338                 DUMP_REG(CM_CLKEN_PLL);
 339                 DUMP_REG(PRCM_CLKEMUL_CTRL);
 340                 DUMP_REG(CM_AUTOIDLE_PLL);
 341                 DUMP_REG(PM_PWSTST_CORE);
 342                 DUMP_REG(PRCM_CLKSRC_CTRL);
 343 #endif
 344 #if 0
 345                 /* DSP */
 346                 DUMP_REG(CM_FCLKEN_DSP);
 347                 DUMP_REG(CM_ICLKEN_DSP);
 348                 DUMP_REG(CM_IDLEST_DSP);
 349                 DUMP_REG(CM_AUTOIDLE_DSP);
 350                 DUMP_REG(CM_CLKSEL_DSP);
 351                 DUMP_REG(CM_CLKSTCTRL_DSP);
 352                 DUMP_REG(RM_RSTCTRL_DSP);
 353                 DUMP_REG(RM_RSTST_DSP);
 354                 DUMP_REG(PM_PWSTCTRL_DSP);
 355                 DUMP_REG(PM_PWSTST_DSP);
 356 #endif
 357         } else {
 358                 DUMP_REG(PM_WKST1_CORE);
 359                 DUMP_REG(PM_WKST2_CORE);
 360                 DUMP_REG(PM_WKST_WKUP);
 361                 DUMP_REG(PRCM_IRQSTATUS_MPU);
 362 #if 1
 363                 DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
 364                 DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
 365                 DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
 366 #endif
 367         }
 368
 369         switch (mode) {
 370         case 0:
 371                 s1 = "full";
 372                 s2 = "retention";
 373                 break;
 374         case 1:
 375                 s1 = "MPU";
 376                 s2 = "retention";
 377                 break;
 378         case 2:
 379                 s1 = "MPU";
 380                 s2 = "idle";
 381                 break;
 382         }
 383
 384         if (!resume)
 385 #if defined(CONFIG_NO_IDLE_HZ) || defined(CONFIG_NO_HZ)
 386                 printk("--- Going to %s %s (next timer after %u ms)\n", s1, s2,
 387                        jiffies_to_msecs(next_timer_interrupt() - jiffies));
 388 #else
 389                 printk("--- Going to %s %s\n", s1, s2);
 390 #endif
 391         else
 392                 printk("--- Woke up (slept for %u.%03u ms)\n", us / 1000, us % 1000);
 393         for (i = 0; i < reg_count; i++)
 394                 printk("%-20s: 0x%08x\n", regs[i].name, regs[i].val);
 395 }
 396
 397 #else
 398 static inline void serial_console_sleep(int enable) {}
 399 static inline void pm_init_serial_console(void) {}
 400 static inline void omap2_pm_dump(int mode, int resume, unsigned int us) {}
 401 static inline void serial_console_fclk_mask(u32 *f1, u32 *f2) {}
 402
 403 #define omap2_pm_debug 0
 404
 405 #endif
 406
 407 static unsigned short enable_dyn_sleep = 0; /* disabled till drivers are fixed */
 408
 409 static ssize_t omap_pm_sleep_while_idle_show(struct subsystem * subsys, char *buf)
 410 {
 411         return sprintf(buf, "%hu\n", enable_dyn_sleep);
 412 }
 413
 414 static ssize_t omap_pm_sleep_while_idle_store(struct subsystem * subsys,
 415                                               const char * buf,
 416                                               size_t n)
 417 {
 418         unsigned short value;
 419         if (sscanf(buf, "%hu", &value) != 1 ||
 420             (value != 0 && value != 1)) {
 421                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
 422                 return -EINVAL;
 423         }
 424         enable_dyn_sleep = value;
 425         return n;
 426 }
 427
 428 static struct subsys_attribute sleep_while_idle_attr = {
 429         .attr   = {
 430                 .name = __stringify(sleep_while_idle),
 431                 .mode = 0644,
 432         },
 433         .show   = omap_pm_sleep_while_idle_show,
 434         .store  = omap_pm_sleep_while_idle_store,
 435 };
 436
 437 static struct clk *osc_ck, *emul_ck;
 438
 439 #define CONTROL_DEVCONF         __REG32(0x48000274)
 440 #define SDRC_DLLA_CTRL          __REG32(0x68009060)
 441
 442 static int omap2_fclks_active(void)
 443 {
 444         u32 f1, f2;
 445
 446         f1 = prcm_read_reg(CM_FCLKEN1_CORE);
 447         f2 = prcm_read_reg(CM_FCLKEN2_CORE);
 448         serial_console_fclk_mask(&f1, &f2);
 449         if (f1 | f2)
 450                 return 1;
 451         return 0;
 452 }
 453
 454 static int omap2_irq_pending(void)
 455 {
 456         u32 pending_reg = IO_ADDRESS(0x480fe098);
 457         int i;
 458
 459         for (i = 0; i < 4; i++) {
 460                 if (__raw_readl(pending_reg))
 461                         return 1;
 462                 pending_reg += 0x20;
 463         }
 464         return 0;
 465 }
 466
 467 static atomic_t sleep_block = ATOMIC_INIT(0);
 468
 469 void omap2_block_sleep(void)
 470 {
 471         atomic_inc(&sleep_block);
 472 }
 473
 474 void omap2_allow_sleep(void)
 475 {
 476         int i;
 477
 478         i = atomic_dec_return(&sleep_block);
 479         BUG_ON(i < 0);
 480 }
 481
 482 static void omap2_enter_full_retention(void)
 483 {
 484         u32 sleep_time = 0;
 485
 486         /* There is 1 reference hold for all children of the oscillator
 487          * clock, the following will remove it. If no one else uses the
 488          * oscillator itself it will be disabled if/when we enter retention
 489          * mode.
 490          */
 491         clk_disable(osc_ck);
 492
 493         /* Clear old wake-up events */
 494         prcm_write_reg(PM_WKST1_CORE, 0xffffffff);
 495         prcm_write_reg(PM_WKST2_CORE, 0xffffffff);
 496         prcm_write_reg(PM_WKST_WKUP, 0xffffffff);
 497
 498         /* Try to enter retention */
 499         prcm_write_reg(PM_PWSTCTRL_MPU, (0x01 << 0) | (1 << 2));
 500
 501         /* Workaround to kill USB */
 502         CONTROL_DEVCONF |= 0x00008000;
 503
 504         omap2_gpio_prepare_for_retention();
 505
 506         if (omap2_pm_debug) {
 507                 omap2_pm_dump(0, 0, 0);
 508                 sleep_time = omap2_read_32k_sync_counter();
 509         }
 510
 511         /* One last check for pending IRQs to avoid extra latency due
 512          * to sleeping unnecessarily. */
 513         if (omap2_irq_pending())
 514                 goto no_sleep;
 515
 516         serial_console_sleep(1);
 517         /* Jump to SRAM suspend code */
 518         omap2_sram_suspend(SDRC_DLLA_CTRL);
 519 no_sleep:
 520         serial_console_sleep(0);
 521
 522         if (omap2_pm_debug) {
 523                 unsigned long long tmp;
 524                 u32 resume_time;
 525
 526                 resume_time = omap2_read_32k_sync_counter();
 527                 tmp = resume_time - sleep_time;
 528                 tmp *= 1000000;
 529                 omap2_pm_dump(0, 1, tmp / 32768);
 530         }
 531         omap2_gpio_resume_after_retention();
 532
 533         clk_enable(osc_ck);
 534
 535 }
 536
 537 static int omap2_i2c_active(void)
 538 {
 539         u32 l;
 540
 541         l = prcm_read_reg(CM_FCLKEN1_CORE);
 542         return l & ((1 << 19) | (1 << 20));
 543 }
 544
 545 static int sti_console_enabled;
 546
 547 static int omap2_allow_mpu_retention(void)
 548 {
 549         u32 l;
 550
 551         if (atomic_read(&sleep_block))
 552                 return 0;
 553
 554         /* Check for UART2, UART1, McSPI2, McSPI1 and DSS1. */
 555         l = prcm_read_reg(CM_FCLKEN1_CORE);
 556         if (l & 0x04660001)
 557                 return 0;
 558         /* Check for UART3. */
 559         l = prcm_read_reg(CM_FCLKEN2_CORE);
 560         if (l & (1 << 2))
 561                 return 0;
 562         if (sti_console_enabled)
 563                 return 0;
 564
 565         return 1;
 566 }
 567
 568 static void omap2_enter_mpu_retention(void)
 569 {
 570         u32 sleep_time = 0;
 571         int only_idle = 0;
 572
 573         /* Putting MPU into the WFI state while a transfer is active
 574          * seems to cause the I2C block to timeout. Why? Good question. */
 575         if (omap2_i2c_active())
 576                 return;
 577
 578         /* The peripherals seem not to be able to wake up the MPU when
 579          * it is in retention mode. */
 580         if (omap2_allow_mpu_retention()) {
 581                 prcm_write_reg(PM_WKST1_CORE, 0xffffffff);
 582                 prcm_write_reg(PM_WKST2_CORE, 0xffffffff);
 583                 prcm_write_reg(PM_WKST_WKUP, 0xffffffff);
 584
 585                 /* Try to enter MPU retention */
 586                 prcm_write_reg(PM_PWSTCTRL_MPU, (0x01 << 0) | (1 << 2));
 587         } else {
 588                 /* Block MPU retention */
 589                 prcm_write_reg(PM_PWSTCTRL_MPU, 1 << 2);
 590                 only_idle = 1;
 591         }
 592
 593         if (omap2_pm_debug) {
 594                 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
 595                 sleep_time = omap2_read_32k_sync_counter();
 596         }
 597
 598         omap2_sram_idle();
 599
 600         if (omap2_pm_debug) {
 601                 unsigned long long tmp;
 602                 u32 resume_time;
 603
 604                 resume_time = omap2_read_32k_sync_counter();
 605                 tmp = resume_time - sleep_time;
 606                 tmp *= 1000000;
 607                 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
 608         }
 609 }
 610
 611 static int omap2_can_sleep(void)
 612 {
 613         if (!enable_dyn_sleep)
 614                 return 0;
 615         if (omap2_fclks_active())
 616                 return 0;
 617         if (atomic_read(&sleep_block) > 0)
 618                 return 0;
 619         if (clk_get_usecount(osc_ck) > 1)
 620                 return 0;
 621         if (omap_dma_running())
 622                 return 0;
 623
 624         return 1;
 625 }
 626
 627 static void omap2_pm_idle(void)
 628 {
 629         local_irq_disable();
 630         local_fiq_disable();
 631
 632         if (!omap2_can_sleep()) {
 633                 /* timer_dyn_reprogram() takes about 100-200 us to complete.
 634                  * In some contexts (e.g. when waiting for a GPMC-SDRAM DMA
 635                  * transfer to complete), the increased latency is too much.
 636                  *
 637                  * omap2_block_sleep() and omap2_allow_sleep() can be used
 638                  * to indicate this.
 639                  */
 640                 if (atomic_read(&sleep_block) == 0) {
 641                         timer_dyn_reprogram();
 642                         if (omap2_irq_pending())
 643                                 goto out;
 644                 }
 645                 omap2_enter_mpu_retention();
 646                 goto out;
 647         }
 648
 649         /*
 650          * Since an interrupt may set up a timer, we don't want to
 651          * reprogram the hardware timer with interrupts enabled.
 652          * Re-enable interrupts only after returning from idle.
 653          */
 654         timer_dyn_reprogram();
 655
 656         if (omap2_irq_pending())
 657                 goto out;
 658
 659         omap2_enter_full_retention();
 660
 661 out:
 662         local_fiq_enable();
 663         local_irq_enable();
 664 }
 665
 666 static int omap2_pm_prepare(suspend_state_t state)
 667 {
 668         int error = 0;
 669
 670         /* We cannot sleep in idle until we have resumed */
 671         saved_idle = pm_idle;
 672         pm_idle = NULL;
 673
 674         switch (state) {
 675         case PM_SUSPEND_STANDBY:
 676         case PM_SUSPEND_MEM:
 677                 break;
 678         case PM_SUSPEND_DISK:
 679                 return -ENOTSUPP;
 680         default:
 681                 return -EINVAL;
 682         }
 683
 684         return error;
 685 }
 686
 687 static int omap2_pm_suspend(void)
 688 {
 689         u32 wken_wkup, mir1;
 690
 691         wken_wkup = prcm_read_reg(PM_WKEN_WKUP);
 692         prcm_write_reg(PM_WKEN_WKUP, wken_wkup & ~EN_GPT1);
 693
 694         /* Mask GPT1 */
 695         mir1 = omap_readl(0x480fe0a4);
 696         omap_writel(1 << 5, 0x480fe0ac);
 697
 698         omap2_enter_full_retention();
 699
 700         omap_writel(mir1, 0x480fe0a4);
 701         prcm_write_reg(PM_WKEN_WKUP, wken_wkup);
 702
 703         return 0;
 704 }
 705
 706 static int omap2_pm_enter(suspend_state_t state)
 707 {
 708         int ret = 0;
 709
 710         switch (state) {
 711         case PM_SUSPEND_STANDBY:
 712         case PM_SUSPEND_MEM:
 713                 ret = omap2_pm_suspend();
 714                 break;
 715         case PM_SUSPEND_DISK:
 716                 ret = -ENOTSUPP;
 717                 break;
 718         default:
 719                 ret = -EINVAL;
 720         }
 721
 722         return ret;
 723 }
 724
 725 static int omap2_pm_finish(suspend_state_t state)
 726 {
 727         pm_idle = saved_idle;
 728         return 0;
 729 }
 730
 731 static struct pm_ops omap_pm_ops = {
 732         .prepare        = omap2_pm_prepare,
 733         .enter          = omap2_pm_enter,
 734         .finish         = omap2_pm_finish,
 735         .valid          = pm_valid_only_mem,
 736 };
 737
 738 static void __init prcm_setup_regs(void)
 739 {
 740         u32 l;
 741
 742         /* Enable autoidle */
 743         prcm_write_reg(PRCM_SYSCONFIG, 1 << 0);
 744
 745         /* Set all domain wakeup dependencies */
 746         prcm_write_reg(PM_WKDEP_MPU, EN_WKUP);
 747         prcm_write_reg(PM_WKDEP_DSP, 0);
 748         prcm_write_reg(PM_WKDEP_GFX, 0);
 749
 750         l = prcm_read_reg(PM_PWSTCTRL_CORE);
 751         /* Enable retention for all memory blocks */
 752         l |= (1 << 3) | (1 << 4) | (1 << 5);
 753         /* Set power state to RETENTION */
 754         l &= ~0x03;
 755         l |= 0x01 << 0;
 756         prcm_write_reg(PM_PWSTCTRL_CORE, l);
 757
 758         prcm_write_reg(PM_PWSTCTRL_MPU, (0x01 << 0) | (1 << 2));
 759
 760         /* Power down DSP and GFX */
 761         prcm_write_reg(PM_PWSTCTRL_DSP, (1 << 18) | 0x03);
 762         prcm_write_reg(PM_PWSTCTRL_GFX, (1 << 18) | 0x03);
 763
 764         /* Enable clock auto control for all domains */
 765         prcm_write_reg(CM_CLKSTCTRL_MPU, AUTOSTAT_MPU);
 766         prcm_write_reg(CM_CLKSTCTRL_CORE, AUTOSTAT_DSS | AUTOSTAT_L4 | AUTOSTAT_L3);
 767         prcm_write_reg(CM_CLKSTCTRL_GFX, AUTOSTAT_GFX);
 768         prcm_write_reg(CM_CLKSTCTRL_DSP, AUTOSTAT_IVA | AUTOSTAT_DSP);
 769
 770         /* Enable clock autoidle for all domains */
 771         prcm_write_reg(CM_AUTOIDLE1_CORE, 0xfffffff9);
 772         prcm_write_reg(CM_AUTOIDLE2_CORE, 0x07);
 773         prcm_write_reg(CM_AUTOIDLE3_CORE, 0x07);
 774         prcm_write_reg(CM_AUTOIDLE4_CORE, 0x1f);
 775
 776         prcm_write_reg(CM_AUTOIDLE_DSP, 0x02);
 777
 778         /* Put DPLL and both APLLs into autoidle mode */
 779         prcm_write_reg(CM_AUTOIDLE_PLL, (0x03 << 0) | (0x03 << 2) | (0x03 << 6));
 780
 781         prcm_write_reg(CM_AUTOIDLE_WKUP, 0x3f);
 782
 783         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 784          * stabilisation */
 785         prcm_write_reg(PRCM_CLKSSETUP, 15);
 786
 787         /* Configure automatic voltage transition */
 788         prcm_write_reg(PRCM_VOLTSETUP, 2);
 789         l = AUTO_EXTVOLT | SETOFF_LEVEL(1) | MEMRETCTRL | \
 790                 SETRET_LEVEL(1) | VOLT_LEVEL(0);
 791         prcm_write_reg(PRCM_VOLTCTRL, l);
 792
 793         /* Enable wake-up events */
 794         prcm_write_reg(PM_WKEN_WKUP, EN_GPIOS | EN_GPT1);
 795 }
 796
 797 int __init omap2_pm_init(void)
 798 {
 799         u32 l;
 800
 801         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 802         l = prcm_read_reg(PRCM_REVISION);
 803         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 804
 805         osc_ck = clk_get(NULL, "osc_ck");
 806         if (IS_ERR(osc_ck)) {
 807                 printk(KERN_ERR "could not get osc_ck\n");
 808                 return -ENODEV;
 809         }
 810
 811         emul_ck = clk_get(NULL, "emul_ck");
 812         if (IS_ERR(emul_ck)) {
 813                 printk(KERN_ERR "could not get emul_ck\n");
 814                 clk_put(osc_ck);
 815                 return -ENODEV;
 816         }
 817
 818         prcm_setup_regs();
 819
 820         pm_init_serial_console();
 821
 822         /* Hack to prevent MPU retention when STI console is enabled. */
 823         {
 824                 const struct omap_sti_console_config *sti;
 825
 826                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 827                                       struct omap_sti_console_config);
 828                 if (sti != NULL && sti->enable)
 829                         sti_console_enabled = 1;
 830         }
 831
 832         /*
 833          * We copy the assembler sleep/wakeup routines to SRAM.
 834          * These routines need to be in SRAM as that's the only
 835          * memory the MPU can see when it wakes up.
 836          */
 837         omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 838                                          omap24xx_idle_loop_suspend_sz);
 839         omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 840                                             omap24xx_cpu_suspend_sz);
 841
 842         pm_set_ops(&omap_pm_ops);
 843         pm_idle = omap2_pm_idle;
 844
 845         l = subsys_create_file(&power_subsys, &sleep_while_idle_attr);
 846         if (l)
 847                 printk(KERN_ERR "subsys_create_file failed: %d\n", l);
 848
 849         return 0;
 850 }
 851
 852 late_initcall(omap2_pm_init);