arch/arm/mach-omap2/pm-debug.c

   1 /*
   2  * linux/arch/arm/mach-omap2/pm_debug.c
   3  *
   4  * OMAP Power Management debug routines
   5  *
   6  * Copyright (C) 2005 Texas Instruments, Inc.
   7  * Copyright (C) 2006-2008 Nokia Corporation
   8  *
   9  * Written by:
  10  * Richard Woodruff <r-woodruff2@ti.com>
  11  * Tony Lindgren
  12  * Juha Yrjola
  13  * Amit Kucheria <amit.kucheria@nokia.com>
  14  * Igor Stoppa <igor.stoppa@nokia.com>
  15  * Jouni Hogander
  16  *
  17  * Based on pm.c for omap2
  18  *
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License version 2 as
  21  * published by the Free Software Foundation.
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/timer.h>
  26 #include <linux/clk.h>
  27 #include <linux/err.h>
  28 #include <linux/io.h>
  29
  30 #include <mach/clock.h>
  31 #include <mach/board.h>
  32
  33 #include "prm.h"
  34 #include "cm.h"
  35 #include "pm.h"
  36
  37 #ifdef CONFIG_PM_DEBUG
  38 int omap2_pm_debug = 0;
  39
  40 #define DUMP_PRM_MOD_REG(mod, reg)    \
  41         regs[reg_count].name = #mod "." #reg; \
  42         regs[reg_count++].val = prm_read_mod_reg(mod, reg)
  43 #define DUMP_CM_MOD_REG(mod, reg)     \
  44         regs[reg_count].name = #mod "." #reg; \
  45         regs[reg_count++].val = cm_read_mod_reg(mod, reg)
  46 #define DUMP_PRM_REG(reg) \
  47         regs[reg_count].name = #reg; \
  48         regs[reg_count++].val = __raw_readl(reg)
  49 #define DUMP_CM_REG(reg) \
  50         regs[reg_count].name = #reg; \
  51         regs[reg_count++].val = __raw_readl(reg)
  52 #define DUMP_INTC_REG(reg, off) \
  53         regs[reg_count].name = #reg; \
  54         regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off)))
  55
  56 void omap2_pm_dump(int mode, int resume, unsigned int us)
  57 {
  58         struct reg {
  59                 const char *name;
  60                 u32 val;
  61         } regs[32];
  62         int reg_count = 0, i;
  63         const char *s1 = NULL, *s2 = NULL;
  64
  65         if (!resume) {
  66 #if 0
  67                 /* MPU */
  68                 DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
  69                 DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL);
  70                 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL);
  71                 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST);
  72                 DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
  73 #endif
  74 #if 0
  75                 /* INTC */
  76                 DUMP_INTC_REG(INTC_MIR0, 0x0084);
  77                 DUMP_INTC_REG(INTC_MIR1, 0x00a4);
  78                 DUMP_INTC_REG(INTC_MIR2, 0x00c4);
  79 #endif
  80 #if 0
  81                 DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
  82                 if (cpu_is_omap24xx()) {
  83                         DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  84                         DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
  85                                         OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET);
  86                         DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
  87                                         OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET);
  88                 }
  89                 DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
  90                 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
  91                 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
  92                 DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
  93                 DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN);
  94                 DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
  95                 DUMP_PRM_MOD_REG(CORE_MOD, PM_PWSTST);
  96 #endif
  97 #if 0
  98                 /* DSP */
  99                 if (cpu_is_omap24xx()) {
 100                         DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
 101                         DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
 102                         DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
 103                         DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
 104                         DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
 105                         DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
 106                         DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL);
 107                         DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST);
 108                         DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL);
 109                         DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST);
 110                 }
 111 #endif
 112         } else {
 113                 DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
 114                 if (cpu_is_omap24xx())
 115                         DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
 116                 DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
 117                 DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
 118 #if 1
 119                 DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
 120                 DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
 121                 DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
 122 #endif
 123         }
 124
 125         switch (mode) {
 126         case 0:
 127                 s1 = "full";
 128                 s2 = "retention";
 129                 break;
 130         case 1:
 131                 s1 = "MPU";
 132                 s2 = "retention";
 133                 break;
 134         case 2:
 135                 s1 = "MPU";
 136                 s2 = "idle";
 137                 break;
 138         }
 139
 140         if (!resume)
 141 #if defined(CONFIG_NO_IDLE_HZ) || defined(CONFIG_NO_HZ)
 142                 printk("--- Going to %s %s (next timer after %u ms)\n", s1, s2,
 143                        jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
 144                                         jiffies));
 145 #else
 146                 printk("--- Going to %s %s\n", s1, s2);
 147 #endif
 148         else
 149                 printk("--- Woke up (slept for %u.%03u ms)\n",
 150                         us / 1000, us % 1000);
 151
 152         for (i = 0; i < reg_count; i++)
 153                 printk("%-20s: 0x%08x\n", regs[i].name, regs[i].val);
 154 }
 155
 156 #endif