2 * Mailbox reservation modules for OMAP2/3
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/kernel.h>
14 #include <linux/clk.h>
15 #include <linux/err.h>
16 #include <linux/platform_device.h>
17 #include <mach/mailbox.h>
18 #include <mach/irqs.h>
21 #define DRV_NAME "omap2-mailbox"
23 #define MAILBOX_REVISION 0x000
24 #define MAILBOX_SYSCONFIG 0x010
25 #define MAILBOX_SYSSTATUS 0x014
26 #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
27 #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
28 #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
29 #define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
30 #define MAILBOX_IRQENABLE(u) (0x108 + 8 * (u))
32 #define MAILBOX_IRQ_NEWMSG(u) (1 << (2 * (u)))
33 #define MAILBOX_IRQ_NOTFULL(u) (1 << (2 * (u) + 1))
35 static void __iomem *mbox_base;
37 struct omap_mbox2_fifo {
39 unsigned long fifo_stat;
40 unsigned long msg_stat;
43 struct omap_mbox2_priv {
44 struct omap_mbox2_fifo tx_fifo;
45 struct omap_mbox2_fifo rx_fifo;
46 unsigned long irqenable;
47 unsigned long irqstatus;
52 static struct clk *mbox_ick_handle;
54 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
55 omap_mbox_type_t irq);
57 static inline unsigned int mbox_read_reg(size_t ofs)
59 return __raw_readl(mbox_base + ofs);
62 static inline void mbox_write_reg(u32 val, size_t ofs)
64 __raw_writel(val, mbox_base + ofs);
67 /* Mailbox H/W preparations */
68 static int omap2_mbox_startup(struct omap_mbox *mbox)
72 mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
73 if (IS_ERR(mbox_ick_handle)) {
74 printk("Could not get mailboxes_ick\n");
77 clk_enable(mbox_ick_handle);
79 l = mbox_read_reg(MAILBOX_REVISION);
80 pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
82 /* set smart-idle & autoidle */
83 l = mbox_read_reg(MAILBOX_SYSCONFIG);
85 mbox_write_reg(l, MAILBOX_SYSCONFIG);
87 omap2_mbox_enable_irq(mbox, IRQ_RX);
92 static void omap2_mbox_shutdown(struct omap_mbox *mbox)
94 clk_disable(mbox_ick_handle);
95 clk_put(mbox_ick_handle);
98 /* Mailbox FIFO handle functions */
99 static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
101 struct omap_mbox2_fifo *fifo =
102 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
103 return (mbox_msg_t) mbox_read_reg(fifo->msg);
106 static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
108 struct omap_mbox2_fifo *fifo =
109 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
110 mbox_write_reg(msg, fifo->msg);
113 static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
115 struct omap_mbox2_fifo *fifo =
116 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
117 return (mbox_read_reg(fifo->msg_stat) == 0);
120 static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
122 struct omap_mbox2_fifo *fifo =
123 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
124 return (mbox_read_reg(fifo->fifo_stat));
127 /* Mailbox IRQ handle functions */
128 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
129 omap_mbox_type_t irq)
131 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
132 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
134 l = mbox_read_reg(p->irqenable);
136 mbox_write_reg(l, p->irqenable);
139 static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
140 omap_mbox_type_t irq)
142 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
143 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
145 l = mbox_read_reg(p->irqenable);
147 mbox_write_reg(l, p->irqenable);
150 static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
151 omap_mbox_type_t irq)
153 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
154 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
156 mbox_write_reg(bit, p->irqstatus);
159 static int omap2_mbox_is_irq(struct omap_mbox *mbox,
160 omap_mbox_type_t irq)
162 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
163 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
164 u32 enable = mbox_read_reg(p->irqenable);
165 u32 status = mbox_read_reg(p->irqstatus);
167 return (enable & status & bit);
170 static struct omap_mbox_ops omap2_mbox_ops = {
171 .type = OMAP_MBOX_TYPE2,
172 .startup = omap2_mbox_startup,
173 .shutdown = omap2_mbox_shutdown,
174 .fifo_read = omap2_mbox_fifo_read,
175 .fifo_write = omap2_mbox_fifo_write,
176 .fifo_empty = omap2_mbox_fifo_empty,
177 .fifo_full = omap2_mbox_fifo_full,
178 .enable_irq = omap2_mbox_enable_irq,
179 .disable_irq = omap2_mbox_disable_irq,
180 .ack_irq = omap2_mbox_ack_irq,
181 .is_irq = omap2_mbox_is_irq,
185 * MAILBOX 0: ARM -> DSP,
186 * MAILBOX 1: ARM <- DSP.
187 * MAILBOX 2: ARM -> IVA,
188 * MAILBOX 3: ARM <- IVA.
191 /* FIXME: the following structs should be filled automatically by the user id */
194 static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
196 .msg = MAILBOX_MESSAGE(0),
197 .fifo_stat = MAILBOX_FIFOSTATUS(0),
200 .msg = MAILBOX_MESSAGE(1),
201 .msg_stat = MAILBOX_MSGSTATUS(1),
203 .irqenable = MAILBOX_IRQENABLE(0),
204 .irqstatus = MAILBOX_IRQSTATUS(0),
205 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
206 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
209 struct omap_mbox mbox_dsp_info = {
211 .ops = &omap2_mbox_ops,
212 .priv = &omap2_mbox_dsp_priv,
214 EXPORT_SYMBOL(mbox_dsp_info);
216 #if defined(CONFIG_ARCH_OMAP2420) /* IVA */
217 static struct omap_mbox2_priv omap2_mbox_iva_priv = {
219 .msg = MAILBOX_MESSAGE(2),
220 .fifo_stat = MAILBOX_FIFOSTATUS(2),
223 .msg = MAILBOX_MESSAGE(3),
224 .msg_stat = MAILBOX_MSGSTATUS(3),
226 .irqenable = MAILBOX_IRQENABLE(3),
227 .irqstatus = MAILBOX_IRQSTATUS(3),
228 .notfull_bit = MAILBOX_IRQ_NOTFULL(2),
229 .newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
232 static struct omap_mbox mbox_iva_info = {
234 .ops = &omap2_mbox_ops,
235 .priv = &omap2_mbox_iva_priv,
239 static int __devinit omap2_mbox_probe(struct platform_device *pdev)
241 struct resource *res;
245 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
246 if (unlikely(!res)) {
247 dev_err(&pdev->dev, "invalid mem resource\n");
250 mbox_base = ioremap(res->start, res->end - res->start);
254 /* DSP or IVA2 IRQ */
255 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
256 if (unlikely(!res)) {
257 dev_err(&pdev->dev, "invalid irq resource\n");
261 mbox_dsp_info.irq = res->start;
263 ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info);
267 #if defined(CONFIG_ARCH_OMAP2420) /* IVA */
268 if (cpu_is_omap2420()) {
270 res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
271 if (unlikely(!res)) {
272 dev_err(&pdev->dev, "invalid irq resource\n");
276 mbox_iva_info.irq = res->start;
277 ret = omap_mbox_register(&pdev->dev, &mbox_iva_info);
285 omap_mbox_unregister(&mbox_dsp_info);
291 static int __devexit omap2_mbox_remove(struct platform_device *pdev)
293 #if defined(CONFIG_ARCH_OMAP2420)
294 omap_mbox_unregister(&mbox_iva_info);
296 omap_mbox_unregister(&mbox_dsp_info);
301 static struct platform_driver omap2_mbox_driver = {
302 .probe = omap2_mbox_probe,
303 .remove = __devexit_p(omap2_mbox_remove),
309 static int __init omap2_mbox_init(void)
311 return platform_driver_register(&omap2_mbox_driver);
314 static void __exit omap2_mbox_exit(void)
316 platform_driver_unregister(&omap2_mbox_driver);
319 module_init(omap2_mbox_init);
320 module_exit(omap2_mbox_exit);
322 MODULE_LICENSE("GPL v2");
323 MODULE_DESCRIPTION("omap mailbox: omap2/3 architecture specific functions");
324 MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, Paul Mundt");
325 MODULE_ALIAS("platform:"DRV_NAME);