1 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
2 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
5 * OMAP3430 Clock Management register bits
7 * Copyright (C) 2007-2008 Texas Instruments, Inc.
8 * Copyright (C) 2007-2008 Nokia Corporation
10 * Written by Paul Walmsley
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
19 /* Bits shared between registers */
21 /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
22 #define OMAP3430ES2_EN_MMC3_MASK (1 << 30)
23 #define OMAP3430ES2_EN_MMC3_SHIFT 30
24 #define OMAP3430_EN_MSPRO (1 << 23)
25 #define OMAP3430_EN_MSPRO_SHIFT 23
26 #define OMAP3430_EN_HDQ (1 << 22)
27 #define OMAP3430_EN_HDQ_SHIFT 22
28 #define OMAP3430ES1_EN_FSHOSTUSB (1 << 5)
29 #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5
30 #define OMAP3430ES1_EN_D2D (1 << 3)
31 #define OMAP3430ES1_EN_D2D_SHIFT 3
32 #define OMAP3430_EN_SSI (1 << 0)
33 #define OMAP3430_EN_SSI_SHIFT 0
35 /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
36 #define OMAP3430ES2_EN_USBTLL_SHIFT 2
37 #define OMAP3430ES2_EN_USBTLL_MASK (1 << 2)
39 /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
40 #define OMAP3430_EN_WDT2 (1 << 5)
41 #define OMAP3430_EN_WDT2_SHIFT 5
43 /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
44 #define OMAP3430_EN_CAM (1 << 0)
45 #define OMAP3430_EN_CAM_SHIFT 0
47 /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
48 #define OMAP3430_EN_WDT3 (1 << 12)
49 #define OMAP3430_EN_WDT3_SHIFT 12
51 /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
52 #define OMAP3430_OVERRIDE_ENABLE (1 << 19)
55 /* Bits specific to each register */
58 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2 (1 << 0)
59 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0
61 /* CM_CLKEN_PLL_IVA2 */
62 #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8
63 #define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8)
64 #define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4
65 #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4)
66 #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3
67 #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3)
68 #define OMAP3430_EN_IVA2_DPLL_SHIFT 0
69 #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)
72 #define OMAP3430_ST_IVA2 (1 << 0)
74 /* CM_IDLEST_PLL_IVA2 */
75 #define OMAP3430_ST_IVA2_CLK_SHIFT 0
76 #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0)
78 /* CM_AUTOIDLE_PLL_IVA2 */
79 #define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0
80 #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0)
82 /* CM_CLKSEL1_PLL_IVA2 */
83 #define OMAP3430_IVA2_CLK_SRC_SHIFT 19
84 #define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19)
85 #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8
86 #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)
87 #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0
88 #define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0)
90 /* CM_CLKSEL2_PLL_IVA2 */
91 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0
92 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
94 /* CM_CLKSTCTRL_IVA2 */
95 #define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0
96 #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)
99 #define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0
100 #define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0)
102 /* CM_REVISION specific bits */
104 /* CM_SYSCONFIG specific bits */
106 /* CM_CLKEN_PLL_MPU */
107 #define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8
108 #define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8)
109 #define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4
110 #define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4)
111 #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3
112 #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3)
113 #define OMAP3430_EN_MPU_DPLL_SHIFT 0
114 #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0)
117 #define OMAP3430_ST_MPU (1 << 0)
119 /* CM_IDLEST_PLL_MPU */
120 #define OMAP3430_ST_MPU_CLK_SHIFT 0
121 #define OMAP3430_ST_MPU_CLK_MASK (1 << 0)
123 /* CM_AUTOIDLE_PLL_MPU */
124 #define OMAP3430_AUTO_MPU_DPLL_SHIFT 0
125 #define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0)
127 /* CM_CLKSEL1_PLL_MPU */
128 #define OMAP3430_MPU_CLK_SRC_SHIFT 19
129 #define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19)
130 #define OMAP3430_MPU_DPLL_MULT_SHIFT 8
131 #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)
132 #define OMAP3430_MPU_DPLL_DIV_SHIFT 0
133 #define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0)
135 /* CM_CLKSEL2_PLL_MPU */
136 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0
137 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
139 /* CM_CLKSTCTRL_MPU */
140 #define OMAP3430_CLKTRCTRL_MPU_SHIFT 0
141 #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)
144 #define OMAP3430_CLKACTIVITY_MPU_SHIFT 0
145 #define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0)
147 /* CM_FCLKEN1_CORE specific bits */
149 /* CM_ICLKEN1_CORE specific bits */
150 #define OMAP3430_EN_ICR (1 << 29)
151 #define OMAP3430_EN_ICR_SHIFT 29
152 #define OMAP3430_EN_AES2 (1 << 28)
153 #define OMAP3430_EN_AES2_SHIFT 28
154 #define OMAP3430_EN_SHA12 (1 << 27)
155 #define OMAP3430_EN_SHA12_SHIFT 27
156 #define OMAP3430_EN_DES2 (1 << 26)
157 #define OMAP3430_EN_DES2_SHIFT 26
158 #define OMAP3430ES1_EN_FAC (1 << 8)
159 #define OMAP3430ES1_EN_FAC_SHIFT 8
160 #define OMAP3430_EN_MAILBOXES (1 << 7)
161 #define OMAP3430_EN_MAILBOXES_SHIFT 7
162 #define OMAP3430_EN_OMAPCTRL (1 << 6)
163 #define OMAP3430_EN_OMAPCTRL_SHIFT 6
164 #define OMAP3430_EN_SDRC (1 << 1)
165 #define OMAP3430_EN_SDRC_SHIFT 1
167 /* CM_ICLKEN2_CORE */
168 #define OMAP3430_EN_PKA (1 << 4)
169 #define OMAP3430_EN_PKA_SHIFT 4
170 #define OMAP3430_EN_AES1 (1 << 3)
171 #define OMAP3430_EN_AES1_SHIFT 3
172 #define OMAP3430_EN_RNG (1 << 2)
173 #define OMAP3430_EN_RNG_SHIFT 2
174 #define OMAP3430_EN_SHA11 (1 << 1)
175 #define OMAP3430_EN_SHA11_SHIFT 1
176 #define OMAP3430_EN_DES1 (1 << 0)
177 #define OMAP3430_EN_DES1_SHIFT 0
179 /* CM_FCLKEN3_CORE specific bits */
180 #define OMAP3430ES2_EN_TS_SHIFT 1
181 #define OMAP3430ES2_EN_TS_MASK (1 << 1)
182 #define OMAP3430ES2_EN_CPEFUSE_SHIFT 0
183 #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0)
185 /* CM_IDLEST1_CORE specific bits */
186 #define OMAP3430_ST_ICR (1 << 29)
187 #define OMAP3430_ST_AES2 (1 << 28)
188 #define OMAP3430_ST_SHA12 (1 << 27)
189 #define OMAP3430_ST_DES2 (1 << 26)
190 #define OMAP3430_ST_MSPRO (1 << 23)
191 #define OMAP3430_ST_HDQ (1 << 22)
192 #define OMAP3430ES1_ST_FAC (1 << 8)
193 #define OMAP3430ES1_ST_MAILBOXES (1 << 7)
194 #define OMAP3430_ST_OMAPCTRL (1 << 6)
195 #define OMAP3430_ST_SDMA (1 << 2)
196 #define OMAP3430_ST_SDRC (1 << 1)
197 #define OMAP3430_ST_SSI (1 << 0)
199 /* CM_IDLEST2_CORE */
200 #define OMAP3430_ST_PKA (1 << 4)
201 #define OMAP3430_ST_AES1 (1 << 3)
202 #define OMAP3430_ST_RNG (1 << 2)
203 #define OMAP3430_ST_SHA11 (1 << 1)
204 #define OMAP3430_ST_DES1 (1 << 0)
206 /* CM_IDLEST3_CORE */
207 #define OMAP3430ES2_ST_USBTLL_SHIFT 2
208 #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2)
210 /* CM_AUTOIDLE1_CORE */
211 #define OMAP3430ES2_AUTO_MMC3 (1 << 30)
212 #define OMAP3430ES2_AUTO_MMC3_SHIFT 30
213 #define OMAP3430ES2_AUTO_ICR (1 << 29)
214 #define OMAP3430ES2_AUTO_ICR_SHIFT 29
215 #define OMAP3430_AUTO_AES2 (1 << 28)
216 #define OMAP3430_AUTO_AES2_SHIFT 28
217 #define OMAP3430_AUTO_SHA12 (1 << 27)
218 #define OMAP3430_AUTO_SHA12_SHIFT 27
219 #define OMAP3430_AUTO_DES2 (1 << 26)
220 #define OMAP3430_AUTO_DES2_SHIFT 26
221 #define OMAP3430_AUTO_MMC2 (1 << 25)
222 #define OMAP3430_AUTO_MMC2_SHIFT 25
223 #define OMAP3430_AUTO_MMC1 (1 << 24)
224 #define OMAP3430_AUTO_MMC1_SHIFT 24
225 #define OMAP3430_AUTO_MSPRO (1 << 23)
226 #define OMAP3430_AUTO_MSPRO_SHIFT 23
227 #define OMAP3430_AUTO_HDQ (1 << 22)
228 #define OMAP3430_AUTO_HDQ_SHIFT 22
229 #define OMAP3430_AUTO_MCSPI4 (1 << 21)
230 #define OMAP3430_AUTO_MCSPI4_SHIFT 21
231 #define OMAP3430_AUTO_MCSPI3 (1 << 20)
232 #define OMAP3430_AUTO_MCSPI3_SHIFT 20
233 #define OMAP3430_AUTO_MCSPI2 (1 << 19)
234 #define OMAP3430_AUTO_MCSPI2_SHIFT 19
235 #define OMAP3430_AUTO_MCSPI1 (1 << 18)
236 #define OMAP3430_AUTO_MCSPI1_SHIFT 18
237 #define OMAP3430_AUTO_I2C3 (1 << 17)
238 #define OMAP3430_AUTO_I2C3_SHIFT 17
239 #define OMAP3430_AUTO_I2C2 (1 << 16)
240 #define OMAP3430_AUTO_I2C2_SHIFT 16
241 #define OMAP3430_AUTO_I2C1 (1 << 15)
242 #define OMAP3430_AUTO_I2C1_SHIFT 15
243 #define OMAP3430_AUTO_UART2 (1 << 14)
244 #define OMAP3430_AUTO_UART2_SHIFT 14
245 #define OMAP3430_AUTO_UART1 (1 << 13)
246 #define OMAP3430_AUTO_UART1_SHIFT 13
247 #define OMAP3430_AUTO_GPT11 (1 << 12)
248 #define OMAP3430_AUTO_GPT11_SHIFT 12
249 #define OMAP3430_AUTO_GPT10 (1 << 11)
250 #define OMAP3430_AUTO_GPT10_SHIFT 11
251 #define OMAP3430_AUTO_MCBSP5 (1 << 10)
252 #define OMAP3430_AUTO_MCBSP5_SHIFT 10
253 #define OMAP3430_AUTO_MCBSP1 (1 << 9)
254 #define OMAP3430_AUTO_MCBSP1_SHIFT 9
255 #define OMAP3430ES1_AUTO_FAC (1 << 8)
256 #define OMAP3430ES1_AUTO_FAC_SHIFT 8
257 #define OMAP3430_AUTO_MAILBOXES (1 << 7)
258 #define OMAP3430_AUTO_MAILBOXES_SHIFT 7
259 #define OMAP3430_AUTO_OMAPCTRL (1 << 6)
260 #define OMAP3430_AUTO_OMAPCTRL_SHIFT 6
261 #define OMAP3430ES1_AUTO_FSHOSTUSB (1 << 5)
262 #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5
263 #define OMAP3430_AUTO_HSOTGUSB (1 << 4)
264 #define OMAP3430_AUTO_HSOTGUSB_SHIFT 4
265 #define OMAP3430ES1_AUTO_D2D (1 << 3)
266 #define OMAP3430ES1_AUTO_D2D_SHIFT 3
267 #define OMAP3430_AUTO_SSI (1 << 0)
268 #define OMAP3430_AUTO_SSI_SHIFT 0
270 /* CM_AUTOIDLE2_CORE */
271 #define OMAP3430_AUTO_PKA (1 << 4)
272 #define OMAP3430_AUTO_PKA_SHIFT 4
273 #define OMAP3430_AUTO_AES1 (1 << 3)
274 #define OMAP3430_AUTO_AES1_SHIFT 3
275 #define OMAP3430_AUTO_RNG (1 << 2)
276 #define OMAP3430_AUTO_RNG_SHIFT 2
277 #define OMAP3430_AUTO_SHA11 (1 << 1)
278 #define OMAP3430_AUTO_SHA11_SHIFT 1
279 #define OMAP3430_AUTO_DES1 (1 << 0)
280 #define OMAP3430_AUTO_DES1_SHIFT 0
282 /* CM_AUTOIDLE3_CORE */
283 #define OMAP3430ES2_AUTO_USBHOST (1 << 0)
284 #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
285 #define OMAP3430ES2_AUTO_USBTLL (1 << 2)
286 #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2
287 #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2)
290 #define OMAP3430_CLKSEL_SSI_SHIFT 8
291 #define OMAP3430_CLKSEL_SSI_MASK (0xf << 8)
292 #define OMAP3430_CLKSEL_GPT11_MASK (1 << 7)
293 #define OMAP3430_CLKSEL_GPT11_SHIFT 7
294 #define OMAP3430_CLKSEL_GPT10_MASK (1 << 6)
295 #define OMAP3430_CLKSEL_GPT10_SHIFT 6
296 #define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4
297 #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4)
298 #define OMAP3430_CLKSEL_L4_SHIFT 2
299 #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2)
300 #define OMAP3430_CLKSEL_L3_SHIFT 0
301 #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0)
303 /* CM_CLKSTCTRL_CORE */
304 #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4
305 #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4)
306 #define OMAP3430_CLKTRCTRL_L4_SHIFT 2
307 #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2)
308 #define OMAP3430_CLKTRCTRL_L3_SHIFT 0
309 #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)
311 /* CM_CLKSTST_CORE */
312 #define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2
313 #define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2)
314 #define OMAP3430_CLKACTIVITY_L4_SHIFT 1
315 #define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1)
316 #define OMAP3430_CLKACTIVITY_L3_SHIFT 0
317 #define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0)
320 #define OMAP3430ES1_EN_3D (1 << 2)
321 #define OMAP3430ES1_EN_3D_SHIFT 2
322 #define OMAP3430ES1_EN_2D (1 << 1)
323 #define OMAP3430ES1_EN_2D_SHIFT 1
325 /* CM_ICLKEN_GFX specific bits */
327 /* CM_IDLEST_GFX specific bits */
329 /* CM_CLKSEL_GFX specific bits */
331 /* CM_SLEEPDEP_GFX specific bits */
333 /* CM_CLKSTCTRL_GFX */
334 #define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0
335 #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)
338 #define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0
339 #define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0)
342 #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1
343 #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1)
346 #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0
347 #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0)
350 #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0
351 #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0)
353 /* CM_CLKSTCTRL_SGX */
354 #define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0
355 #define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0)
358 #define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0
359 #define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0)
361 /* CM_FCLKEN_WKUP specific bits */
362 #define OMAP3430ES2_EN_USIMOCP_SHIFT 9
364 /* CM_ICLKEN_WKUP specific bits */
365 #define OMAP3430_EN_WDT1 (1 << 4)
366 #define OMAP3430_EN_WDT1_SHIFT 4
367 #define OMAP3430_EN_32KSYNC (1 << 2)
368 #define OMAP3430_EN_32KSYNC_SHIFT 2
370 /* CM_IDLEST_WKUP specific bits */
371 #define OMAP3430_ST_WDT2 (1 << 5)
372 #define OMAP3430_ST_WDT1 (1 << 4)
373 #define OMAP3430_ST_32KSYNC (1 << 2)
375 /* CM_AUTOIDLE_WKUP */
376 #define OMAP3430_AUTO_WDT2 (1 << 5)
377 #define OMAP3430_AUTO_WDT2_SHIFT 5
378 #define OMAP3430_AUTO_WDT1 (1 << 4)
379 #define OMAP3430_AUTO_WDT1_SHIFT 4
380 #define OMAP3430_AUTO_GPIO1 (1 << 3)
381 #define OMAP3430_AUTO_GPIO1_SHIFT 3
382 #define OMAP3430_AUTO_32KSYNC (1 << 2)
383 #define OMAP3430_AUTO_32KSYNC_SHIFT 2
384 #define OMAP3430_AUTO_GPT12 (1 << 1)
385 #define OMAP3430_AUTO_GPT12_SHIFT 1
386 #define OMAP3430_AUTO_GPT1 (1 << 0)
387 #define OMAP3430_AUTO_GPT1_SHIFT 0
390 #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3)
391 #define OMAP3430_CLKSEL_RM_SHIFT 1
392 #define OMAP3430_CLKSEL_RM_MASK (0x3 << 1)
393 #define OMAP3430_CLKSEL_GPT1_SHIFT 0
394 #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0)
397 #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31
398 #define OMAP3430_PWRDN_CAM_SHIFT 30
399 #define OMAP3430_PWRDN_DSS1_SHIFT 29
400 #define OMAP3430_PWRDN_TV_SHIFT 28
401 #define OMAP3430_PWRDN_96M_SHIFT 27
402 #define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24
403 #define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24)
404 #define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20
405 #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20)
406 #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19
407 #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19)
408 #define OMAP3430_EN_PERIPH_DPLL_SHIFT 16
409 #define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16)
410 #define OMAP3430_PWRDN_EMU_CORE_SHIFT 12
411 #define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8
412 #define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8)
413 #define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4
414 #define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4)
415 #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3
416 #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3)
417 #define OMAP3430_EN_CORE_DPLL_SHIFT 0
418 #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0)
421 #define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10
422 #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8)
423 #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4
424 #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4)
425 #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3
426 #define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0
427 #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0)
429 /* CM_IDLEST_CKGEN */
430 #define OMAP3430_ST_54M_CLK (1 << 5)
431 #define OMAP3430_ST_12M_CLK (1 << 4)
432 #define OMAP3430_ST_48M_CLK (1 << 3)
433 #define OMAP3430_ST_96M_CLK (1 << 2)
434 #define OMAP3430_ST_PERIPH_CLK_SHIFT 1
435 #define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1)
436 #define OMAP3430_ST_CORE_CLK_SHIFT 0
437 #define OMAP3430_ST_CORE_CLK_MASK (1 << 0)
439 /* CM_IDLEST2_CKGEN */
440 #define OMAP3430ES2_ST_120M_CLK_SHIFT 1
441 #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1)
442 #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0
443 #define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0)
445 /* CM_AUTOIDLE_PLL */
446 #define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3
447 #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3)
448 #define OMAP3430_AUTO_CORE_DPLL_SHIFT 0
449 #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0)
451 /* CM_AUTOIDLE2_PLL */
452 #define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0
453 #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0)
456 /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
457 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27
458 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27)
459 #define OMAP3430_CORE_DPLL_MULT_SHIFT 16
460 #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16)
461 #define OMAP3430_CORE_DPLL_DIV_SHIFT 8
462 #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8)
463 #define OMAP3430_SOURCE_96M_SHIFT 6
464 #define OMAP3430_SOURCE_96M_MASK (1 << 6)
465 #define OMAP3430_SOURCE_54M_SHIFT 5
466 #define OMAP3430_SOURCE_54M_MASK (1 << 5)
467 #define OMAP3430_SOURCE_48M_SHIFT 3
468 #define OMAP3430_SOURCE_48M_MASK (1 << 3)
471 #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8
472 #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8)
473 #define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0
474 #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0)
477 #define OMAP3430_DIV_96M_SHIFT 0
478 #define OMAP3430_DIV_96M_MASK (0x1f << 0)
481 #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8
482 #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8)
483 #define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0
484 #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0)
487 #define OMAP3430ES2_DIV_120M_SHIFT 0
488 #define OMAP3430ES2_DIV_120M_MASK (0x1f << 0)
491 #define OMAP3430_CLKOUT2_EN_SHIFT 7
492 #define OMAP3430_CLKOUT2_EN (1 << 7)
493 #define OMAP3430_CLKOUT2_DIV_SHIFT 3
494 #define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3)
495 #define OMAP3430_CLKOUT2SOURCE_SHIFT 0
496 #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0)
499 #define OMAP3430_EN_TV (1 << 2)
500 #define OMAP3430_EN_TV_SHIFT 2
501 #define OMAP3430_EN_DSS2 (1 << 1)
502 #define OMAP3430_EN_DSS2_SHIFT 1
503 #define OMAP3430_EN_DSS1 (1 << 0)
504 #define OMAP3430_EN_DSS1_SHIFT 0
507 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS (1 << 0)
508 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0
511 #define OMAP3430_ST_DSS (1 << 0)
513 /* CM_AUTOIDLE_DSS */
514 #define OMAP3430_AUTO_DSS (1 << 0)
515 #define OMAP3430_AUTO_DSS_SHIFT 0
518 #define OMAP3430_CLKSEL_TV_SHIFT 8
519 #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8)
520 #define OMAP3430_CLKSEL_DSS1_SHIFT 0
521 #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0)
523 /* CM_SLEEPDEP_DSS specific bits */
525 /* CM_CLKSTCTRL_DSS */
526 #define OMAP3430_CLKTRCTRL_DSS_SHIFT 0
527 #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0)
530 #define OMAP3430_CLKACTIVITY_DSS_SHIFT 0
531 #define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0)
533 /* CM_FCLKEN_CAM specific bits */
534 #define OMAP3430_EN_CSI2 (1 << 1)
535 #define OMAP3430_EN_CSI2_SHIFT 1
537 /* CM_ICLKEN_CAM specific bits */
540 #define OMAP3430_ST_CAM (1 << 0)
542 /* CM_AUTOIDLE_CAM */
543 #define OMAP3430_AUTO_CAM (1 << 0)
544 #define OMAP3430_AUTO_CAM_SHIFT 0
547 #define OMAP3430_CLKSEL_CAM_SHIFT 0
548 #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0)
550 /* CM_SLEEPDEP_CAM specific bits */
552 /* CM_CLKSTCTRL_CAM */
553 #define OMAP3430_CLKTRCTRL_CAM_SHIFT 0
554 #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0)
557 #define OMAP3430_CLKACTIVITY_CAM_SHIFT 0
558 #define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0)
560 /* CM_FCLKEN_PER specific bits */
562 /* CM_ICLKEN_PER specific bits */
565 #define OMAP3430_ST_WDT3 (1 << 12)
566 #define OMAP3430_ST_MCBSP4 (1 << 2)
567 #define OMAP3430_ST_MCBSP3 (1 << 1)
568 #define OMAP3430_ST_MCBSP2 (1 << 0)
570 /* CM_AUTOIDLE_PER */
571 #define OMAP3430_AUTO_GPIO6 (1 << 17)
572 #define OMAP3430_AUTO_GPIO6_SHIFT 17
573 #define OMAP3430_AUTO_GPIO5 (1 << 16)
574 #define OMAP3430_AUTO_GPIO5_SHIFT 16
575 #define OMAP3430_AUTO_GPIO4 (1 << 15)
576 #define OMAP3430_AUTO_GPIO4_SHIFT 15
577 #define OMAP3430_AUTO_GPIO3 (1 << 14)
578 #define OMAP3430_AUTO_GPIO3_SHIFT 14
579 #define OMAP3430_AUTO_GPIO2 (1 << 13)
580 #define OMAP3430_AUTO_GPIO2_SHIFT 13
581 #define OMAP3430_AUTO_WDT3 (1 << 12)
582 #define OMAP3430_AUTO_WDT3_SHIFT 12
583 #define OMAP3430_AUTO_UART3 (1 << 11)
584 #define OMAP3430_AUTO_UART3_SHIFT 11
585 #define OMAP3430_AUTO_GPT9 (1 << 10)
586 #define OMAP3430_AUTO_GPT9_SHIFT 10
587 #define OMAP3430_AUTO_GPT8 (1 << 9)
588 #define OMAP3430_AUTO_GPT8_SHIFT 9
589 #define OMAP3430_AUTO_GPT7 (1 << 8)
590 #define OMAP3430_AUTO_GPT7_SHIFT 8
591 #define OMAP3430_AUTO_GPT6 (1 << 7)
592 #define OMAP3430_AUTO_GPT6_SHIFT 7
593 #define OMAP3430_AUTO_GPT5 (1 << 6)
594 #define OMAP3430_AUTO_GPT5_SHIFT 6
595 #define OMAP3430_AUTO_GPT4 (1 << 5)
596 #define OMAP3430_AUTO_GPT4_SHIFT 5
597 #define OMAP3430_AUTO_GPT3 (1 << 4)
598 #define OMAP3430_AUTO_GPT3_SHIFT 4
599 #define OMAP3430_AUTO_GPT2 (1 << 3)
600 #define OMAP3430_AUTO_GPT2_SHIFT 3
601 #define OMAP3430_AUTO_MCBSP4 (1 << 2)
602 #define OMAP3430_AUTO_MCBSP4_SHIFT 2
603 #define OMAP3430_AUTO_MCBSP3 (1 << 1)
604 #define OMAP3430_AUTO_MCBSP3_SHIFT 1
605 #define OMAP3430_AUTO_MCBSP2 (1 << 0)
606 #define OMAP3430_AUTO_MCBSP2_SHIFT 0
609 #define OMAP3430_CLKSEL_GPT9_MASK (1 << 7)
610 #define OMAP3430_CLKSEL_GPT9_SHIFT 7
611 #define OMAP3430_CLKSEL_GPT8_MASK (1 << 6)
612 #define OMAP3430_CLKSEL_GPT8_SHIFT 6
613 #define OMAP3430_CLKSEL_GPT7_MASK (1 << 5)
614 #define OMAP3430_CLKSEL_GPT7_SHIFT 5
615 #define OMAP3430_CLKSEL_GPT6_MASK (1 << 4)
616 #define OMAP3430_CLKSEL_GPT6_SHIFT 4
617 #define OMAP3430_CLKSEL_GPT5_MASK (1 << 3)
618 #define OMAP3430_CLKSEL_GPT5_SHIFT 3
619 #define OMAP3430_CLKSEL_GPT4_MASK (1 << 2)
620 #define OMAP3430_CLKSEL_GPT4_SHIFT 2
621 #define OMAP3430_CLKSEL_GPT3_MASK (1 << 1)
622 #define OMAP3430_CLKSEL_GPT3_SHIFT 1
623 #define OMAP3430_CLKSEL_GPT2_MASK (1 << 0)
624 #define OMAP3430_CLKSEL_GPT2_SHIFT 0
626 /* CM_SLEEPDEP_PER specific bits */
627 #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2 (1 << 2)
629 /* CM_CLKSTCTRL_PER */
630 #define OMAP3430_CLKTRCTRL_PER_SHIFT 0
631 #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0)
634 #define OMAP3430_CLKACTIVITY_PER_SHIFT 0
635 #define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0)
638 #define OMAP3430_DIV_DPLL4_SHIFT 24
639 #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24)
640 #define OMAP3430_DIV_DPLL3_SHIFT 16
641 #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16)
642 #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11
643 #define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11)
644 #define OMAP3430_CLKSEL_PCLK_SHIFT 8
645 #define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8)
646 #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6
647 #define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6)
648 #define OMAP3430_CLKSEL_ATCLK_SHIFT 4
649 #define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4)
650 #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2
651 #define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2)
652 #define OMAP3430_MUX_CTRL_SHIFT 0
653 #define OMAP3430_MUX_CTRL_MASK (0x3 << 0)
655 /* CM_CLKSTCTRL_EMU */
656 #define OMAP3430_CLKTRCTRL_EMU_SHIFT 0
657 #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0)
660 #define OMAP3430_CLKACTIVITY_EMU_SHIFT 0
661 #define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0)
663 /* CM_CLKSEL2_EMU specific bits */
664 #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8
665 #define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8)
666 #define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0
667 #define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0)
669 /* CM_CLKSEL3_EMU specific bits */
670 #define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8
671 #define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8)
672 #define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0
673 #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0)
676 #define OMAP3430_CLKOUT2_POL (1 << 0)
679 #define OMAP3430_ST_NEON (1 << 0)
681 /* CM_CLKSTCTRL_NEON */
682 #define OMAP3430_CLKTRCTRL_NEON_SHIFT 0
683 #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0)
685 /* CM_FCLKEN_USBHOST */
686 #define OMAP3430ES2_EN_USBHOST2_SHIFT 1
687 #define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1)
688 #define OMAP3430ES2_EN_USBHOST1_SHIFT 0
689 #define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0)
691 /* CM_ICLKEN_USBHOST */
692 #define OMAP3430ES2_EN_USBHOST_SHIFT 0
693 #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0)
695 /* CM_IDLEST_USBHOST */
697 /* CM_AUTOIDLE_USBHOST */
698 #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
699 #define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0)
701 /* CM_SLEEPDEP_USBHOST */
702 #define OMAP3430ES2_EN_MPU_SHIFT 1
703 #define OMAP3430ES2_EN_MPU_MASK (1 << 1)
704 #define OMAP3430ES2_EN_IVA2_SHIFT 2
705 #define OMAP3430ES2_EN_IVA2_MASK (1 << 2)
707 /* CM_CLKSTCTRL_USBHOST */
708 #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0
709 #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0)
711 /* CM_CLKSTST_USBHOST */
712 #define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0
713 #define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0)
projects / linux-2.6-omap-h63xx.git / blob