arch/arm/mach-omap2/clockdomains.h

   1 /*
   2  * OMAP2/3 clockdomains
   3  *
   4  * Copyright (C) 2008 Texas Instruments, Inc.
   5  * Copyright (C) 2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  */
   9
  10 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
  11 #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
  12
  13 #include <mach/clockdomain.h>
  14
  15 /*
  16  * OMAP2/3-common clockdomains
  17  *
  18  * Even though the 2420 has a single PRCM module from the
  19  * interconnect's perspective, internally it does appear to have
  20  * separate PRM and CM clockdomains.  The usual test case is
  21  * sys_clkout/sys_clkout2.
  22  */
  23
  24 static struct clockdomain prm_clkdm = {
  25         .name           = "prm_clkdm",
  26         .pwrdm          = { .name = "wkup_pwrdm" },
  27         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
  28 };
  29
  30 static struct clockdomain cm_clkdm = {
  31         .name           = "cm_clkdm",
  32         .pwrdm          = { .name = "core_pwrdm" },
  33         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
  34 };
  35
  36 /*
  37  * virt_opp_clkdm is intended solely for use with virtual OPP clocks,
  38  * e.g., virt_prcm_set, until OPP handling is rationalized.
  39  */
  40 static struct clockdomain virt_opp_clkdm = {
  41         .name           = "virt_opp_clkdm",
  42         .pwrdm          = { .name = "wkup_pwrdm" },
  43         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
  44 };
  45
  46 /*
  47  * 2420-only clockdomains
  48  */
  49
  50 #if defined(CONFIG_ARCH_OMAP2420)
  51
  52 static struct clockdomain mpu_2420_clkdm = {
  53         .name           = "mpu_clkdm",
  54         .pwrdm          = { .name = "mpu_pwrdm" },
  55         .flags          = CLKDM_CAN_HWSUP,
  56         .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
  57         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  58 };
  59
  60 static struct clockdomain iva1_2420_clkdm = {
  61         .name           = "iva1_clkdm",
  62         .pwrdm          = { .name = "dsp_pwrdm" },
  63         .flags          = CLKDM_CAN_HWSUP_SWSUP,
  64         .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
  65         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  66 };
  67
  68 #endif  /* CONFIG_ARCH_OMAP2420 */
  69
  70
  71 /*
  72  * 2430-only clockdomains
  73  */
  74
  75 #if defined(CONFIG_ARCH_OMAP2430)
  76
  77 static struct clockdomain mpu_2430_clkdm = {
  78         .name           = "mpu_clkdm",
  79         .pwrdm          = { .name = "mpu_pwrdm" },
  80         .flags          = CLKDM_CAN_HWSUP_SWSUP,
  81         .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
  82         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
  83 };
  84
  85 static struct clockdomain mdm_clkdm = {
  86         .name           = "mdm_clkdm",
  87         .pwrdm          = { .name = "mdm_pwrdm" },
  88         .flags          = CLKDM_CAN_HWSUP_SWSUP,
  89         .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
  90         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
  91 };
  92
  93 #endif    /* CONFIG_ARCH_OMAP2430 */
  94
  95
  96 /*
  97  * 24XX-only clockdomains
  98  */
  99
 100 #if defined(CONFIG_ARCH_OMAP24XX)
 101
 102 static struct clockdomain dsp_clkdm = {
 103         .name           = "dsp_clkdm",
 104         .pwrdm          = { .name = "dsp_pwrdm" },
 105         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 106         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
 107         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
 108 };
 109
 110 static struct clockdomain gfx_24xx_clkdm = {
 111         .name           = "gfx_clkdm",
 112         .pwrdm          = { .name = "gfx_pwrdm" },
 113         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 114         .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
 115         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
 116 };
 117
 118 static struct clockdomain core_l3_24xx_clkdm = {
 119         .name           = "core_l3_clkdm",
 120         .pwrdm          = { .name = "core_pwrdm" },
 121         .flags          = CLKDM_CAN_HWSUP,
 122         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
 123         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
 124 };
 125
 126 static struct clockdomain core_l4_24xx_clkdm = {
 127         .name           = "core_l4_clkdm",
 128         .pwrdm          = { .name = "core_pwrdm" },
 129         .flags          = CLKDM_CAN_HWSUP,
 130         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
 131         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
 132 };
 133
 134 static struct clockdomain dss_24xx_clkdm = {
 135         .name           = "dss_clkdm",
 136         .pwrdm          = { .name = "core_pwrdm" },
 137         .flags          = CLKDM_CAN_HWSUP,
 138         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
 139         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
 140 };
 141
 142 #endif   /* CONFIG_ARCH_OMAP24XX */
 143
 144
 145 /*
 146  * 34xx clockdomains
 147  */
 148
 149 #if defined(CONFIG_ARCH_OMAP34XX)
 150
 151 static struct clockdomain mpu_34xx_clkdm = {
 152         .name           = "mpu_clkdm",
 153         .pwrdm          = { .name = "mpu_pwrdm" },
 154         .flags          = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
 155         .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
 156         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 157 };
 158
 159 static struct clockdomain neon_clkdm = {
 160         .name           = "neon_clkdm",
 161         .pwrdm          = { .name = "neon_pwrdm" },
 162         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 163         .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
 164         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 165 };
 166
 167 static struct clockdomain iva2_clkdm = {
 168         .name           = "iva2_clkdm",
 169         .pwrdm          = { .name = "iva2_pwrdm" },
 170         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 171         .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
 172         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 173 };
 174
 175 static struct clockdomain gfx_3430es1_clkdm = {
 176         .name           = "gfx_clkdm",
 177         .pwrdm          = { .name = "gfx_pwrdm" },
 178         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 179         .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
 180         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
 181 };
 182
 183 static struct clockdomain sgx_clkdm = {
 184         .name           = "sgx_clkdm",
 185         .pwrdm          = { .name = "sgx_pwrdm" },
 186         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 187         .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
 188         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
 189 };
 190
 191 /*
 192  * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
 193  * then that information was removed from the 34xx ES2+ TRM.  It is
 194  * unclear whether the core is still there, but the clockdomain logic
 195  * is there, and must be programmed to an appropriate state if the
 196  * CORE clockdomain is to become inactive.
 197  */
 198 static struct clockdomain d2d_clkdm = {
 199         .name           = "d2d_clkdm",
 200         .pwrdm          = { .name = "core_pwrdm" },
 201         .flags          = CLKDM_CAN_HWSUP,
 202         .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
 203         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 204 };
 205
 206 static struct clockdomain core_l3_34xx_clkdm = {
 207         .name           = "core_l3_clkdm",
 208         .pwrdm          = { .name = "core_pwrdm" },
 209         .flags          = CLKDM_CAN_HWSUP,
 210         .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
 211         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 212 };
 213
 214 static struct clockdomain core_l4_34xx_clkdm = {
 215         .name           = "core_l4_clkdm",
 216         .pwrdm          = { .name = "core_pwrdm" },
 217         .flags          = CLKDM_CAN_HWSUP,
 218         .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
 219         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 220 };
 221
 222 static struct clockdomain dss_34xx_clkdm = {
 223         .name           = "dss_clkdm",
 224         .pwrdm          = { .name = "dss_pwrdm" },
 225         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 226         .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
 227         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 228 };
 229
 230 static struct clockdomain cam_clkdm = {
 231         .name           = "cam_clkdm",
 232         .pwrdm          = { .name = "cam_pwrdm" },
 233         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 234         .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
 235         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 236 };
 237
 238 static struct clockdomain usbhost_clkdm = {
 239         .name           = "usbhost_clkdm",
 240         .pwrdm          = { .name = "usbhost_pwrdm" },
 241         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 242         .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
 243         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
 244 };
 245
 246 static struct clockdomain per_clkdm = {
 247         .name           = "per_clkdm",
 248         .pwrdm          = { .name = "per_pwrdm" },
 249         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 250         .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
 251         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 252 };
 253
 254 /*
 255  * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
 256  * switched of even if sdti is in use
 257  */
 258 static struct clockdomain emu_clkdm = {
 259         .name           = "emu_clkdm",
 260         .pwrdm          = { .name = "emu_pwrdm" },
 261         .flags          = /* CLKDM_CAN_ENABLE_AUTO |  */CLKDM_CAN_SWSUP,
 262         .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
 263         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 264 };
 265
 266 static struct clockdomain dpll1_clkdm = {
 267         .name           = "dpll1_clkdm",
 268         .pwrdm          = { .name = "dpll1_pwrdm" },
 269         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 270 };
 271
 272 static struct clockdomain dpll2_clkdm = {
 273         .name           = "dpll2_clkdm",
 274         .pwrdm          = { .name = "dpll2_pwrdm" },
 275         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 276 };
 277
 278 static struct clockdomain dpll3_clkdm = {
 279         .name           = "dpll3_clkdm",
 280         .pwrdm          = { .name = "dpll3_pwrdm" },
 281         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 282 };
 283
 284 static struct clockdomain dpll4_clkdm = {
 285         .name           = "dpll4_clkdm",
 286         .pwrdm          = { .name = "dpll4_pwrdm" },
 287         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 288 };
 289
 290 static struct clockdomain dpll5_clkdm = {
 291         .name           = "dpll5_clkdm",
 292         .pwrdm          = { .name = "dpll5_pwrdm" },
 293         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
 294 };
 295
 296 #endif   /* CONFIG_ARCH_OMAP34XX */
 297
 298 /*
 299  * Clockdomain-powerdomain hwsup dependencies (34XX only)
 300  */
 301
 302 static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
 303         {
 304                 .pwrdm     = { .name = "mpu_pwrdm" },
 305                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 306         },
 307         {
 308                 .pwrdm     = { .name = "iva2_pwrdm" },
 309                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 310         },
 311         {
 312                 .pwrdm     = { .name = NULL },
 313         }
 314 };
 315
 316 /*
 317  *
 318  */
 319
 320 static struct clockdomain *clockdomains_omap[] = {
 321
 322         &cm_clkdm,
 323         &prm_clkdm,
 324         &virt_opp_clkdm,
 325
 326 #ifdef CONFIG_ARCH_OMAP2420
 327         &mpu_2420_clkdm,
 328         &iva1_2420_clkdm,
 329 #endif
 330
 331 #ifdef CONFIG_ARCH_OMAP2430
 332         &mpu_2430_clkdm,
 333         &mdm_clkdm,
 334 #endif
 335
 336 #ifdef CONFIG_ARCH_OMAP24XX
 337         &dsp_clkdm,
 338         &gfx_24xx_clkdm,
 339         &core_l3_24xx_clkdm,
 340         &core_l4_24xx_clkdm,
 341         &dss_24xx_clkdm,
 342 #endif
 343
 344 #ifdef CONFIG_ARCH_OMAP34XX
 345         &mpu_34xx_clkdm,
 346         &neon_clkdm,
 347         &iva2_clkdm,
 348         &gfx_3430es1_clkdm,
 349         &sgx_clkdm,
 350         &d2d_clkdm,
 351         &core_l3_34xx_clkdm,
 352         &core_l4_34xx_clkdm,
 353         &dss_34xx_clkdm,
 354         &cam_clkdm,
 355         &usbhost_clkdm,
 356         &per_clkdm,
 357         &emu_clkdm,
 358         &dpll1_clkdm,
 359         &dpll2_clkdm,
 360         &dpll3_clkdm,
 361         &dpll4_clkdm,
 362         &dpll5_clkdm,
 363 #endif
 364
 365         NULL,
 366 };
 367
 368 #endif