2 * OMAP3 clock framework
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
22 #include <mach/control.h>
26 #include "cm-regbits-34xx.h"
28 #include "prm-regbits-34xx.h"
30 static void omap3_dpll_recalc(struct clk *clk);
31 static void omap3_clkoutx2_recalc(struct clk *clk);
32 static void omap3_dpll_allow_idle(struct clk *clk);
33 static void omap3_dpll_deny_idle(struct clk *clk);
34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
35 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
36 static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
38 /* Maximum DPLL multiplier, divider values for OMAP3 */
39 #define OMAP3_MAX_DPLL_MULT 2048
40 #define OMAP3_MAX_DPLL_DIV 128
43 * DPLL1 supplies clock to the MPU.
44 * DPLL2 supplies clock to the IVA2.
45 * DPLL3 supplies CORE domain clocks.
46 * DPLL4 supplies peripheral clocks.
47 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
50 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
51 #define DPLL_LOW_POWER_STOP 0x1
52 #define DPLL_LOW_POWER_BYPASS 0x5
53 #define DPLL_LOCKED 0x7
57 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
58 static struct clk omap_32k_fck = {
59 .name = "omap_32k_fck",
62 .flags = RATE_FIXED | RATE_PROPAGATES,
65 static struct clk secure_32k_fck = {
66 .name = "secure_32k_fck",
69 .flags = RATE_FIXED | RATE_PROPAGATES,
72 /* Virtual source clocks for osc_sys_ck */
73 static struct clk virt_12m_ck = {
74 .name = "virt_12m_ck",
77 .flags = RATE_FIXED | RATE_PROPAGATES,
80 static struct clk virt_13m_ck = {
81 .name = "virt_13m_ck",
84 .flags = RATE_FIXED | RATE_PROPAGATES,
87 static struct clk virt_16_8m_ck = {
88 .name = "virt_16_8m_ck",
91 .flags = RATE_FIXED | RATE_PROPAGATES,
94 static struct clk virt_19_2m_ck = {
95 .name = "virt_19_2m_ck",
98 .flags = RATE_FIXED | RATE_PROPAGATES,
101 static struct clk virt_26m_ck = {
102 .name = "virt_26m_ck",
105 .flags = RATE_FIXED | RATE_PROPAGATES,
108 static struct clk virt_38_4m_ck = {
109 .name = "virt_38_4m_ck",
112 .flags = RATE_FIXED | RATE_PROPAGATES,
115 static const struct clksel_rate osc_sys_12m_rates[] = {
116 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
120 static const struct clksel_rate osc_sys_13m_rates[] = {
121 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
125 static const struct clksel_rate osc_sys_16_8m_rates[] = {
126 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
130 static const struct clksel_rate osc_sys_19_2m_rates[] = {
131 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
135 static const struct clksel_rate osc_sys_26m_rates[] = {
136 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
140 static const struct clksel_rate osc_sys_38_4m_rates[] = {
141 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
145 static const struct clksel osc_sys_clksel[] = {
146 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
147 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
148 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
149 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
150 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
151 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
155 /* Oscillator clock */
156 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
157 static struct clk osc_sys_ck = {
158 .name = "osc_sys_ck",
160 .init = &omap2_init_clksel_parent,
161 .clksel_reg = OMAP3430_PRM_CLKSEL,
162 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
163 .clksel = osc_sys_clksel,
164 /* REVISIT: deal with autoextclkmode? */
165 .flags = RATE_FIXED | RATE_PROPAGATES,
166 .recalc = &omap2_clksel_recalc,
169 static const struct clksel_rate div2_rates[] = {
170 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
171 { .div = 2, .val = 2, .flags = RATE_IN_343X },
175 static const struct clksel sys_clksel[] = {
176 { .parent = &osc_sys_ck, .rates = div2_rates },
180 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
181 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
182 static struct clk sys_ck = {
185 .parent = &osc_sys_ck,
186 .init = &omap2_init_clksel_parent,
187 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
188 .clksel_mask = OMAP_SYSCLKDIV_MASK,
189 .clksel = sys_clksel,
190 .flags = RATE_PROPAGATES,
191 .recalc = &omap2_clksel_recalc,
194 static struct clk sys_altclk = {
195 .name = "sys_altclk",
197 .flags = RATE_PROPAGATES,
200 /* Optional external clock input for some McBSPs */
201 static struct clk mcbsp_clks = {
202 .name = "mcbsp_clks",
204 .flags = RATE_PROPAGATES,
207 /* PRM EXTERNAL CLOCK OUTPUT */
209 static struct clk sys_clkout1 = {
210 .name = "sys_clkout1",
211 .ops = &clkops_omap2_dflt,
212 .parent = &osc_sys_ck,
213 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
214 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
215 .recalc = &followparent_recalc,
222 static const struct clksel_rate dpll_bypass_rates[] = {
223 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
227 static const struct clksel_rate dpll_locked_rates[] = {
228 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
232 static const struct clksel_rate div16_dpll_rates[] = {
233 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
234 { .div = 2, .val = 2, .flags = RATE_IN_343X },
235 { .div = 3, .val = 3, .flags = RATE_IN_343X },
236 { .div = 4, .val = 4, .flags = RATE_IN_343X },
237 { .div = 5, .val = 5, .flags = RATE_IN_343X },
238 { .div = 6, .val = 6, .flags = RATE_IN_343X },
239 { .div = 7, .val = 7, .flags = RATE_IN_343X },
240 { .div = 8, .val = 8, .flags = RATE_IN_343X },
241 { .div = 9, .val = 9, .flags = RATE_IN_343X },
242 { .div = 10, .val = 10, .flags = RATE_IN_343X },
243 { .div = 11, .val = 11, .flags = RATE_IN_343X },
244 { .div = 12, .val = 12, .flags = RATE_IN_343X },
245 { .div = 13, .val = 13, .flags = RATE_IN_343X },
246 { .div = 14, .val = 14, .flags = RATE_IN_343X },
247 { .div = 15, .val = 15, .flags = RATE_IN_343X },
248 { .div = 16, .val = 16, .flags = RATE_IN_343X },
253 /* MPU clock source */
255 static struct dpll_data dpll1_dd = {
256 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
257 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
258 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
259 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
260 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
261 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
262 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
263 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
264 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
265 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
266 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
267 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
268 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
269 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
270 .max_multiplier = OMAP3_MAX_DPLL_MULT,
271 .max_divider = OMAP3_MAX_DPLL_DIV,
272 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
275 static struct clk dpll1_ck = {
279 .dpll_data = &dpll1_dd,
280 .flags = RATE_PROPAGATES,
281 .round_rate = &omap2_dpll_round_rate,
282 .set_rate = &omap3_noncore_dpll_set_rate,
283 .clkdm_name = "dpll1_clkdm",
284 .recalc = &omap3_dpll_recalc,
288 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
289 * DPLL isn't bypassed.
291 static struct clk dpll1_x2_ck = {
292 .name = "dpll1_x2_ck",
295 .flags = RATE_PROPAGATES,
296 .clkdm_name = "dpll1_clkdm",
297 .recalc = &omap3_clkoutx2_recalc,
300 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
301 static const struct clksel div16_dpll1_x2m2_clksel[] = {
302 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
307 * Does not exist in the TRM - needed to separate the M2 divider from
308 * bypass selection in mpu_ck
310 static struct clk dpll1_x2m2_ck = {
311 .name = "dpll1_x2m2_ck",
313 .parent = &dpll1_x2_ck,
314 .init = &omap2_init_clksel_parent,
315 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
316 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
317 .clksel = div16_dpll1_x2m2_clksel,
318 .flags = RATE_PROPAGATES,
319 .clkdm_name = "dpll1_clkdm",
320 .recalc = &omap2_clksel_recalc,
324 /* IVA2 clock source */
327 static struct dpll_data dpll2_dd = {
328 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
329 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
330 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
331 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
332 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
333 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
334 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
335 (1 << DPLL_LOW_POWER_BYPASS),
336 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
337 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
338 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
339 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
340 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
341 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
342 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
343 .max_multiplier = OMAP3_MAX_DPLL_MULT,
344 .max_divider = OMAP3_MAX_DPLL_DIV,
345 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
348 static struct clk dpll2_ck = {
350 .ops = &clkops_noncore_dpll_ops,
352 .dpll_data = &dpll2_dd,
353 .flags = RATE_PROPAGATES,
354 .round_rate = &omap2_dpll_round_rate,
355 .set_rate = &omap3_noncore_dpll_set_rate,
356 .clkdm_name = "dpll2_clkdm",
357 .recalc = &omap3_dpll_recalc,
360 static const struct clksel div16_dpll2_m2x2_clksel[] = {
361 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
366 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
367 * or CLKOUTX2. CLKOUT seems most plausible.
369 static struct clk dpll2_m2_ck = {
370 .name = "dpll2_m2_ck",
373 .init = &omap2_init_clksel_parent,
374 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
375 OMAP3430_CM_CLKSEL2_PLL),
376 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
377 .clksel = div16_dpll2_m2x2_clksel,
378 .flags = RATE_PROPAGATES,
379 .clkdm_name = "dpll2_clkdm",
380 .recalc = &omap2_clksel_recalc,
385 * Source clock for all interfaces and for some device fclks
386 * REVISIT: Also supports fast relock bypass - not included below
388 static struct dpll_data dpll3_dd = {
389 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
390 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
391 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
392 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
393 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
394 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
395 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
396 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
397 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
398 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
399 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
400 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
401 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
402 .max_multiplier = OMAP3_MAX_DPLL_MULT,
403 .max_divider = OMAP3_MAX_DPLL_DIV,
404 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
407 static struct clk dpll3_ck = {
411 .dpll_data = &dpll3_dd,
412 .flags = RATE_PROPAGATES,
413 .round_rate = &omap2_dpll_round_rate,
414 .clkdm_name = "dpll3_clkdm",
415 .recalc = &omap3_dpll_recalc,
419 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
420 * DPLL isn't bypassed
422 static struct clk dpll3_x2_ck = {
423 .name = "dpll3_x2_ck",
426 .flags = RATE_PROPAGATES,
427 .clkdm_name = "dpll3_clkdm",
428 .recalc = &omap3_clkoutx2_recalc,
431 static const struct clksel_rate div31_dpll3_rates[] = {
432 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
433 { .div = 2, .val = 2, .flags = RATE_IN_343X },
434 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
435 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
436 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
437 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
438 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
439 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
440 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
441 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
442 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
443 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
444 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
445 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
446 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
447 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
448 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
449 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
450 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
451 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
452 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
453 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
454 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
455 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
456 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
457 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
458 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
459 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
460 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
461 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
462 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
466 static const struct clksel div31_dpll3m2_clksel[] = {
467 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
473 * REVISIT: This DPLL output divider must be changed in SRAM, so until
474 * that code is ready, this should remain a 'read-only' clksel clock.
476 static struct clk dpll3_m2_ck = {
477 .name = "dpll3_m2_ck",
480 .init = &omap2_init_clksel_parent,
481 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
482 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
483 .clksel = div31_dpll3m2_clksel,
484 .flags = RATE_PROPAGATES,
485 .clkdm_name = "dpll3_clkdm",
486 .recalc = &omap2_clksel_recalc,
489 static const struct clksel core_ck_clksel[] = {
490 { .parent = &sys_ck, .rates = dpll_bypass_rates },
491 { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
495 static struct clk core_ck = {
498 .init = &omap2_init_clksel_parent,
499 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
500 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
501 .clksel = core_ck_clksel,
502 .flags = RATE_PROPAGATES,
503 .recalc = &omap2_clksel_recalc,
506 static const struct clksel dpll3_m2x2_ck_clksel[] = {
507 { .parent = &sys_ck, .rates = dpll_bypass_rates },
508 { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
512 static struct clk dpll3_m2x2_ck = {
513 .name = "dpll3_m2x2_ck",
515 .init = &omap2_init_clksel_parent,
516 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
517 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
518 .clksel = dpll3_m2x2_ck_clksel,
519 .flags = RATE_PROPAGATES,
520 .clkdm_name = "dpll3_clkdm",
521 .recalc = &omap2_clksel_recalc,
524 /* The PWRDN bit is apparently only available on 3430ES2 and above */
525 static const struct clksel div16_dpll3_clksel[] = {
526 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
530 /* This virtual clock is the source for dpll3_m3x2_ck */
531 static struct clk dpll3_m3_ck = {
532 .name = "dpll3_m3_ck",
535 .init = &omap2_init_clksel_parent,
536 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
537 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
538 .clksel = div16_dpll3_clksel,
539 .flags = RATE_PROPAGATES,
540 .clkdm_name = "dpll3_clkdm",
541 .recalc = &omap2_clksel_recalc,
544 /* The PWRDN bit is apparently only available on 3430ES2 and above */
545 static struct clk dpll3_m3x2_ck = {
546 .name = "dpll3_m3x2_ck",
547 .ops = &clkops_omap2_dflt_wait,
548 .parent = &dpll3_m3_ck,
549 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
550 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
551 .flags = RATE_PROPAGATES | INVERT_ENABLE,
552 .clkdm_name = "dpll3_clkdm",
553 .recalc = &omap3_clkoutx2_recalc,
556 static const struct clksel emu_core_alwon_ck_clksel[] = {
557 { .parent = &sys_ck, .rates = dpll_bypass_rates },
558 { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
562 static struct clk emu_core_alwon_ck = {
563 .name = "emu_core_alwon_ck",
565 .parent = &dpll3_m3x2_ck,
566 .init = &omap2_init_clksel_parent,
567 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
568 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
569 .clksel = emu_core_alwon_ck_clksel,
570 .flags = RATE_PROPAGATES,
571 .clkdm_name = "dpll3_clkdm",
572 .recalc = &omap2_clksel_recalc,
576 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
578 static struct dpll_data dpll4_dd = {
579 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
580 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
581 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
582 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
583 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
584 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
585 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
586 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
587 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
588 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
589 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
590 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
591 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
592 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
593 .max_multiplier = OMAP3_MAX_DPLL_MULT,
594 .max_divider = OMAP3_MAX_DPLL_DIV,
595 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
598 static struct clk dpll4_ck = {
600 .ops = &clkops_noncore_dpll_ops,
602 .dpll_data = &dpll4_dd,
603 .flags = RATE_PROPAGATES,
604 .round_rate = &omap2_dpll_round_rate,
605 .set_rate = &omap3_dpll4_set_rate,
606 .clkdm_name = "dpll4_clkdm",
607 .recalc = &omap3_dpll_recalc,
611 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
612 * DPLL isn't bypassed --
613 * XXX does this serve any downstream clocks?
615 static struct clk dpll4_x2_ck = {
616 .name = "dpll4_x2_ck",
619 .flags = RATE_PROPAGATES,
620 .clkdm_name = "dpll4_clkdm",
621 .recalc = &omap3_clkoutx2_recalc,
624 static const struct clksel div16_dpll4_clksel[] = {
625 { .parent = &dpll4_ck, .rates = div16_dpll_rates },
629 /* This virtual clock is the source for dpll4_m2x2_ck */
630 static struct clk dpll4_m2_ck = {
631 .name = "dpll4_m2_ck",
634 .init = &omap2_init_clksel_parent,
635 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
636 .clksel_mask = OMAP3430_DIV_96M_MASK,
637 .clksel = div16_dpll4_clksel,
638 .flags = RATE_PROPAGATES,
639 .clkdm_name = "dpll4_clkdm",
640 .recalc = &omap2_clksel_recalc,
643 /* The PWRDN bit is apparently only available on 3430ES2 and above */
644 static struct clk dpll4_m2x2_ck = {
645 .name = "dpll4_m2x2_ck",
646 .ops = &clkops_omap2_dflt_wait,
647 .parent = &dpll4_m2_ck,
648 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
649 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
650 .flags = RATE_PROPAGATES | INVERT_ENABLE,
651 .clkdm_name = "dpll4_clkdm",
652 .recalc = &omap3_clkoutx2_recalc,
655 static const struct clksel omap_96m_alwon_fck_clksel[] = {
656 { .parent = &sys_ck, .rates = dpll_bypass_rates },
657 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
662 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
663 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
664 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
667 static struct clk omap_96m_alwon_fck = {
668 .name = "omap_96m_alwon_fck",
670 .parent = &dpll4_m2x2_ck,
671 .init = &omap2_init_clksel_parent,
672 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
673 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
674 .clksel = omap_96m_alwon_fck_clksel,
675 .flags = RATE_PROPAGATES,
676 .recalc = &omap2_clksel_recalc,
679 static struct clk cm_96m_fck = {
680 .name = "cm_96m_fck",
682 .parent = &omap_96m_alwon_fck,
683 .flags = RATE_PROPAGATES,
684 .recalc = &followparent_recalc,
687 static const struct clksel_rate omap_96m_dpll_rates[] = {
688 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
692 static const struct clksel_rate omap_96m_sys_rates[] = {
693 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
697 static const struct clksel omap_96m_fck_clksel[] = {
698 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
699 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
703 static struct clk omap_96m_fck = {
704 .name = "omap_96m_fck",
707 .init = &omap2_init_clksel_parent,
708 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
709 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
710 .clksel = omap_96m_fck_clksel,
711 .flags = RATE_PROPAGATES,
712 .recalc = &omap2_clksel_recalc,
715 /* This virtual clock is the source for dpll4_m3x2_ck */
716 static struct clk dpll4_m3_ck = {
717 .name = "dpll4_m3_ck",
720 .init = &omap2_init_clksel_parent,
721 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
722 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
723 .clksel = div16_dpll4_clksel,
724 .flags = RATE_PROPAGATES,
725 .clkdm_name = "dpll4_clkdm",
726 .recalc = &omap2_clksel_recalc,
729 /* The PWRDN bit is apparently only available on 3430ES2 and above */
730 static struct clk dpll4_m3x2_ck = {
731 .name = "dpll4_m3x2_ck",
732 .ops = &clkops_omap2_dflt_wait,
733 .parent = &dpll4_m3_ck,
734 .init = &omap2_init_clksel_parent,
735 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
736 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
737 .flags = RATE_PROPAGATES | INVERT_ENABLE,
738 .clkdm_name = "dpll4_clkdm",
739 .recalc = &omap3_clkoutx2_recalc,
742 static const struct clksel virt_omap_54m_fck_clksel[] = {
743 { .parent = &sys_ck, .rates = dpll_bypass_rates },
744 { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
748 static struct clk virt_omap_54m_fck = {
749 .name = "virt_omap_54m_fck",
751 .parent = &dpll4_m3x2_ck,
752 .init = &omap2_init_clksel_parent,
753 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
754 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
755 .clksel = virt_omap_54m_fck_clksel,
756 .flags = RATE_PROPAGATES,
757 .recalc = &omap2_clksel_recalc,
760 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
761 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
765 static const struct clksel_rate omap_54m_alt_rates[] = {
766 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
770 static const struct clksel omap_54m_clksel[] = {
771 { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
772 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
776 static struct clk omap_54m_fck = {
777 .name = "omap_54m_fck",
779 .init = &omap2_init_clksel_parent,
780 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
781 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
782 .clksel = omap_54m_clksel,
783 .flags = RATE_PROPAGATES,
784 .recalc = &omap2_clksel_recalc,
787 static const struct clksel_rate omap_48m_cm96m_rates[] = {
788 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
792 static const struct clksel_rate omap_48m_alt_rates[] = {
793 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
797 static const struct clksel omap_48m_clksel[] = {
798 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
799 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
803 static struct clk omap_48m_fck = {
804 .name = "omap_48m_fck",
806 .init = &omap2_init_clksel_parent,
807 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
808 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
809 .clksel = omap_48m_clksel,
810 .flags = RATE_PROPAGATES,
811 .recalc = &omap2_clksel_recalc,
814 static struct clk omap_12m_fck = {
815 .name = "omap_12m_fck",
817 .parent = &omap_48m_fck,
819 .flags = RATE_PROPAGATES,
820 .recalc = &omap2_fixed_divisor_recalc,
823 /* This virstual clock is the source for dpll4_m4x2_ck */
824 static struct clk dpll4_m4_ck = {
825 .name = "dpll4_m4_ck",
828 .init = &omap2_init_clksel_parent,
829 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
830 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
831 .clksel = div16_dpll4_clksel,
832 .flags = RATE_PROPAGATES,
833 .clkdm_name = "dpll4_clkdm",
834 .recalc = &omap2_clksel_recalc,
835 .set_rate = &omap2_clksel_set_rate,
836 .round_rate = &omap2_clksel_round_rate,
839 /* The PWRDN bit is apparently only available on 3430ES2 and above */
840 static struct clk dpll4_m4x2_ck = {
841 .name = "dpll4_m4x2_ck",
842 .ops = &clkops_omap2_dflt_wait,
843 .parent = &dpll4_m4_ck,
844 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
845 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
846 .flags = RATE_PROPAGATES | INVERT_ENABLE,
847 .clkdm_name = "dpll4_clkdm",
848 .recalc = &omap3_clkoutx2_recalc,
851 /* This virtual clock is the source for dpll4_m5x2_ck */
852 static struct clk dpll4_m5_ck = {
853 .name = "dpll4_m5_ck",
856 .init = &omap2_init_clksel_parent,
857 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
858 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
859 .clksel = div16_dpll4_clksel,
860 .flags = RATE_PROPAGATES,
861 .clkdm_name = "dpll4_clkdm",
862 .recalc = &omap2_clksel_recalc,
865 /* The PWRDN bit is apparently only available on 3430ES2 and above */
866 static struct clk dpll4_m5x2_ck = {
867 .name = "dpll4_m5x2_ck",
868 .ops = &clkops_omap2_dflt_wait,
869 .parent = &dpll4_m5_ck,
870 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
871 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
872 .flags = RATE_PROPAGATES | INVERT_ENABLE,
873 .clkdm_name = "dpll4_clkdm",
874 .recalc = &omap3_clkoutx2_recalc,
877 /* This virtual clock is the source for dpll4_m6x2_ck */
878 static struct clk dpll4_m6_ck = {
879 .name = "dpll4_m6_ck",
882 .init = &omap2_init_clksel_parent,
883 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
884 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
885 .clksel = div16_dpll4_clksel,
886 .flags = RATE_PROPAGATES,
887 .clkdm_name = "dpll4_clkdm",
888 .recalc = &omap2_clksel_recalc,
891 /* The PWRDN bit is apparently only available on 3430ES2 and above */
892 static struct clk dpll4_m6x2_ck = {
893 .name = "dpll4_m6x2_ck",
894 .ops = &clkops_omap2_dflt_wait,
895 .parent = &dpll4_m6_ck,
896 .init = &omap2_init_clksel_parent,
897 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
898 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
899 .flags = RATE_PROPAGATES | INVERT_ENABLE,
900 .clkdm_name = "dpll4_clkdm",
901 .recalc = &omap3_clkoutx2_recalc,
904 static struct clk emu_per_alwon_ck = {
905 .name = "emu_per_alwon_ck",
907 .parent = &dpll4_m6x2_ck,
908 .flags = RATE_PROPAGATES,
909 .clkdm_name = "dpll4_clkdm",
910 .recalc = &followparent_recalc,
914 /* Supplies 120MHz clock, USIM source clock */
917 static struct dpll_data dpll5_dd = {
918 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
919 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
920 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
921 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
922 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
923 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
924 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
925 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
926 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
927 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
928 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
929 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
930 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
931 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
932 .max_multiplier = OMAP3_MAX_DPLL_MULT,
933 .max_divider = OMAP3_MAX_DPLL_DIV,
934 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
937 static struct clk dpll5_ck = {
939 .ops = &clkops_noncore_dpll_ops,
941 .dpll_data = &dpll5_dd,
942 .flags = RATE_PROPAGATES,
943 .round_rate = &omap2_dpll_round_rate,
944 .set_rate = &omap3_noncore_dpll_set_rate,
945 .clkdm_name = "dpll5_clkdm",
946 .recalc = &omap3_dpll_recalc,
949 static const struct clksel div16_dpll5_clksel[] = {
950 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
954 static struct clk dpll5_m2_ck = {
955 .name = "dpll5_m2_ck",
958 .init = &omap2_init_clksel_parent,
959 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
960 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
961 .clksel = div16_dpll5_clksel,
962 .flags = RATE_PROPAGATES,
963 .clkdm_name = "dpll5_clkdm",
964 .recalc = &omap2_clksel_recalc,
967 static const struct clksel omap_120m_fck_clksel[] = {
968 { .parent = &sys_ck, .rates = dpll_bypass_rates },
969 { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
973 static struct clk omap_120m_fck = {
974 .name = "omap_120m_fck",
976 .parent = &dpll5_m2_ck,
977 .init = &omap2_init_clksel_parent,
978 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
979 .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
980 .clksel = omap_120m_fck_clksel,
981 .flags = RATE_PROPAGATES,
982 .recalc = &omap2_clksel_recalc,
985 /* CM EXTERNAL CLOCK OUTPUTS */
987 static const struct clksel_rate clkout2_src_core_rates[] = {
988 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
992 static const struct clksel_rate clkout2_src_sys_rates[] = {
993 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
997 static const struct clksel_rate clkout2_src_96m_rates[] = {
998 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
1002 static const struct clksel_rate clkout2_src_54m_rates[] = {
1003 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1007 static const struct clksel clkout2_src_clksel[] = {
1008 { .parent = &core_ck, .rates = clkout2_src_core_rates },
1009 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
1010 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
1011 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
1015 static struct clk clkout2_src_ck = {
1016 .name = "clkout2_src_ck",
1017 .ops = &clkops_omap2_dflt,
1018 .init = &omap2_init_clksel_parent,
1019 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
1020 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
1021 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
1022 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
1023 .clksel = clkout2_src_clksel,
1024 .flags = RATE_PROPAGATES,
1025 .clkdm_name = "core_clkdm",
1026 .recalc = &omap2_clksel_recalc,
1029 static const struct clksel_rate sys_clkout2_rates[] = {
1030 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1031 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1032 { .div = 4, .val = 2, .flags = RATE_IN_343X },
1033 { .div = 8, .val = 3, .flags = RATE_IN_343X },
1034 { .div = 16, .val = 4, .flags = RATE_IN_343X },
1038 static const struct clksel sys_clkout2_clksel[] = {
1039 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1043 static struct clk sys_clkout2 = {
1044 .name = "sys_clkout2",
1045 .ops = &clkops_null,
1046 .init = &omap2_init_clksel_parent,
1047 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
1048 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
1049 .clksel = sys_clkout2_clksel,
1050 .recalc = &omap2_clksel_recalc,
1053 /* CM OUTPUT CLOCKS */
1055 static struct clk corex2_fck = {
1056 .name = "corex2_fck",
1057 .ops = &clkops_null,
1058 .parent = &dpll3_m2x2_ck,
1059 .flags = RATE_PROPAGATES,
1060 .recalc = &followparent_recalc,
1063 /* DPLL power domain clock controls */
1065 static const struct clksel_rate div4_rates[] = {
1066 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1067 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1068 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1072 static const struct clksel div4_core_clksel[] = {
1073 { .parent = &core_ck, .rates = div4_rates },
1078 * REVISIT: Are these in DPLL power domain or CM power domain? docs
1079 * may be inconsistent here?
1081 static struct clk dpll1_fck = {
1082 .name = "dpll1_fck",
1083 .ops = &clkops_null,
1085 .init = &omap2_init_clksel_parent,
1086 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1087 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1088 .clksel = div4_core_clksel,
1089 .flags = RATE_PROPAGATES,
1090 .recalc = &omap2_clksel_recalc,
1095 * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1096 * derives from the high-frequency bypass clock originating from DPLL3,
1097 * called 'dpll1_fck'
1099 static const struct clksel mpu_clksel[] = {
1100 { .parent = &dpll1_fck, .rates = dpll_bypass_rates },
1101 { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1105 static struct clk mpu_ck = {
1107 .ops = &clkops_null,
1108 .parent = &dpll1_x2m2_ck,
1109 .init = &omap2_init_clksel_parent,
1110 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1111 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1112 .clksel = mpu_clksel,
1113 .flags = RATE_PROPAGATES,
1114 .clkdm_name = "mpu_clkdm",
1115 .recalc = &omap2_clksel_recalc,
1118 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1119 static const struct clksel_rate arm_fck_rates[] = {
1120 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1121 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1125 static const struct clksel arm_fck_clksel[] = {
1126 { .parent = &mpu_ck, .rates = arm_fck_rates },
1130 static struct clk arm_fck = {
1132 .ops = &clkops_null,
1134 .init = &omap2_init_clksel_parent,
1135 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1136 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1137 .clksel = arm_fck_clksel,
1138 .flags = RATE_PROPAGATES,
1139 .recalc = &omap2_clksel_recalc,
1142 /* XXX What about neon_clkdm ? */
1145 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1146 * although it is referenced - so this is a guess
1148 static struct clk emu_mpu_alwon_ck = {
1149 .name = "emu_mpu_alwon_ck",
1150 .ops = &clkops_null,
1152 .flags = RATE_PROPAGATES,
1153 .recalc = &followparent_recalc,
1156 static struct clk dpll2_fck = {
1157 .name = "dpll2_fck",
1158 .ops = &clkops_null,
1160 .init = &omap2_init_clksel_parent,
1161 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1162 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1163 .clksel = div4_core_clksel,
1164 .flags = RATE_PROPAGATES,
1165 .recalc = &omap2_clksel_recalc,
1170 * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1171 * derives from the high-frequency bypass clock originating from DPLL3,
1172 * called 'dpll2_fck'
1175 static const struct clksel iva2_clksel[] = {
1176 { .parent = &dpll2_fck, .rates = dpll_bypass_rates },
1177 { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1181 static struct clk iva2_ck = {
1183 .ops = &clkops_omap2_dflt_wait,
1184 .parent = &dpll2_m2_ck,
1185 .init = &omap2_init_clksel_parent,
1186 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1187 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1188 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1189 OMAP3430_CM_IDLEST_PLL),
1190 .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK,
1191 .clksel = iva2_clksel,
1192 .flags = RATE_PROPAGATES,
1193 .clkdm_name = "iva2_clkdm",
1194 .recalc = &omap2_clksel_recalc,
1197 /* Common interface clocks */
1199 static const struct clksel div2_core_clksel[] = {
1200 { .parent = &core_ck, .rates = div2_rates },
1204 static struct clk l3_ick = {
1206 .ops = &clkops_null,
1208 .init = &omap2_init_clksel_parent,
1209 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1210 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1211 .clksel = div2_core_clksel,
1212 .flags = RATE_PROPAGATES,
1213 .clkdm_name = "core_l3_clkdm",
1214 .recalc = &omap2_clksel_recalc,
1217 static const struct clksel div2_l3_clksel[] = {
1218 { .parent = &l3_ick, .rates = div2_rates },
1222 static struct clk l4_ick = {
1224 .ops = &clkops_null,
1226 .init = &omap2_init_clksel_parent,
1227 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1228 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1229 .clksel = div2_l3_clksel,
1230 .flags = RATE_PROPAGATES,
1231 .clkdm_name = "core_l4_clkdm",
1232 .recalc = &omap2_clksel_recalc,
1236 static const struct clksel div2_l4_clksel[] = {
1237 { .parent = &l4_ick, .rates = div2_rates },
1241 static struct clk rm_ick = {
1243 .ops = &clkops_null,
1245 .init = &omap2_init_clksel_parent,
1246 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1247 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1248 .clksel = div2_l4_clksel,
1249 .recalc = &omap2_clksel_recalc,
1252 /* GFX power domain */
1254 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1256 static const struct clksel gfx_l3_clksel[] = {
1257 { .parent = &l3_ick, .rates = gfx_l3_rates },
1261 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1262 static struct clk gfx_l3_ck = {
1263 .name = "gfx_l3_ck",
1264 .ops = &clkops_omap2_dflt_wait,
1266 .init = &omap2_init_clksel_parent,
1267 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1268 .enable_bit = OMAP_EN_GFX_SHIFT,
1269 .recalc = &followparent_recalc,
1272 static struct clk gfx_l3_fck = {
1273 .name = "gfx_l3_fck",
1274 .ops = &clkops_null,
1275 .parent = &gfx_l3_ck,
1276 .init = &omap2_init_clksel_parent,
1277 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1278 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1279 .clksel = gfx_l3_clksel,
1280 .flags = RATE_PROPAGATES,
1281 .clkdm_name = "gfx_3430es1_clkdm",
1282 .recalc = &omap2_clksel_recalc,
1285 static struct clk gfx_l3_ick = {
1286 .name = "gfx_l3_ick",
1287 .ops = &clkops_null,
1288 .parent = &gfx_l3_ck,
1289 .clkdm_name = "gfx_3430es1_clkdm",
1290 .recalc = &followparent_recalc,
1293 static struct clk gfx_cg1_ck = {
1294 .name = "gfx_cg1_ck",
1295 .ops = &clkops_omap2_dflt_wait,
1296 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1297 .init = &omap2_init_clk_clkdm,
1298 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1299 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1300 .clkdm_name = "gfx_3430es1_clkdm",
1301 .recalc = &followparent_recalc,
1304 static struct clk gfx_cg2_ck = {
1305 .name = "gfx_cg2_ck",
1306 .ops = &clkops_omap2_dflt_wait,
1307 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1308 .init = &omap2_init_clk_clkdm,
1309 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1310 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1311 .clkdm_name = "gfx_3430es1_clkdm",
1312 .recalc = &followparent_recalc,
1315 /* SGX power domain - 3430ES2 only */
1317 static const struct clksel_rate sgx_core_rates[] = {
1318 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1319 { .div = 4, .val = 1, .flags = RATE_IN_343X },
1320 { .div = 6, .val = 2, .flags = RATE_IN_343X },
1324 static const struct clksel_rate sgx_96m_rates[] = {
1325 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1329 static const struct clksel sgx_clksel[] = {
1330 { .parent = &core_ck, .rates = sgx_core_rates },
1331 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1335 static struct clk sgx_fck = {
1337 .ops = &clkops_omap2_dflt_wait,
1338 .init = &omap2_init_clksel_parent,
1339 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1340 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1341 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1342 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1343 .clksel = sgx_clksel,
1344 .clkdm_name = "sgx_clkdm",
1345 .recalc = &omap2_clksel_recalc,
1348 static struct clk sgx_ick = {
1350 .ops = &clkops_omap2_dflt_wait,
1352 .init = &omap2_init_clk_clkdm,
1353 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1354 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1355 .clkdm_name = "sgx_clkdm",
1356 .recalc = &followparent_recalc,
1359 /* CORE power domain */
1361 static struct clk d2d_26m_fck = {
1362 .name = "d2d_26m_fck",
1363 .ops = &clkops_omap2_dflt_wait,
1365 .init = &omap2_init_clk_clkdm,
1366 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1367 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1368 .clkdm_name = "d2d_clkdm",
1369 .recalc = &followparent_recalc,
1372 static const struct clksel omap343x_gpt_clksel[] = {
1373 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1374 { .parent = &sys_ck, .rates = gpt_sys_rates },
1378 static struct clk gpt10_fck = {
1379 .name = "gpt10_fck",
1380 .ops = &clkops_omap2_dflt_wait,
1382 .init = &omap2_init_clksel_parent,
1383 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1384 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1385 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1386 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1387 .clksel = omap343x_gpt_clksel,
1388 .clkdm_name = "core_l4_clkdm",
1389 .recalc = &omap2_clksel_recalc,
1392 static struct clk gpt11_fck = {
1393 .name = "gpt11_fck",
1394 .ops = &clkops_omap2_dflt_wait,
1396 .init = &omap2_init_clksel_parent,
1397 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1398 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1399 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1400 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1401 .clksel = omap343x_gpt_clksel,
1402 .clkdm_name = "core_l4_clkdm",
1403 .recalc = &omap2_clksel_recalc,
1406 static struct clk cpefuse_fck = {
1407 .name = "cpefuse_fck",
1408 .ops = &clkops_omap2_dflt,
1410 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1411 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1412 .recalc = &followparent_recalc,
1415 static struct clk ts_fck = {
1417 .ops = &clkops_omap2_dflt,
1418 .parent = &omap_32k_fck,
1419 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1420 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1421 .recalc = &followparent_recalc,
1424 static struct clk usbtll_fck = {
1425 .name = "usbtll_fck",
1426 .ops = &clkops_omap2_dflt,
1427 .parent = &omap_120m_fck,
1428 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1429 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1430 .recalc = &followparent_recalc,
1433 /* CORE 96M FCLK-derived clocks */
1435 static struct clk core_96m_fck = {
1436 .name = "core_96m_fck",
1437 .ops = &clkops_null,
1438 .parent = &omap_96m_fck,
1439 .flags = RATE_PROPAGATES,
1440 .clkdm_name = "core_l4_clkdm",
1441 .recalc = &followparent_recalc,
1444 static struct clk mmchs3_fck = {
1445 .name = "mmchs_fck",
1446 .ops = &clkops_omap2_dflt_wait,
1448 .parent = &core_96m_fck,
1449 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1450 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1451 .clkdm_name = "core_l4_clkdm",
1452 .recalc = &followparent_recalc,
1455 static struct clk mmchs2_fck = {
1456 .name = "mmchs_fck",
1457 .ops = &clkops_omap2_dflt_wait,
1459 .parent = &core_96m_fck,
1460 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1461 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1462 .clkdm_name = "core_l4_clkdm",
1463 .recalc = &followparent_recalc,
1466 static struct clk mspro_fck = {
1467 .name = "mspro_fck",
1468 .ops = &clkops_omap2_dflt_wait,
1469 .parent = &core_96m_fck,
1470 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1471 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1472 .clkdm_name = "core_l4_clkdm",
1473 .recalc = &followparent_recalc,
1476 static struct clk mmchs1_fck = {
1477 .name = "mmchs_fck",
1478 .ops = &clkops_omap2_dflt_wait,
1479 .parent = &core_96m_fck,
1480 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1481 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1482 .clkdm_name = "core_l4_clkdm",
1483 .recalc = &followparent_recalc,
1486 static struct clk i2c3_fck = {
1488 .ops = &clkops_omap2_dflt_wait,
1490 .parent = &core_96m_fck,
1491 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1492 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1493 .clkdm_name = "core_l4_clkdm",
1494 .recalc = &followparent_recalc,
1497 static struct clk i2c2_fck = {
1499 .ops = &clkops_omap2_dflt_wait,
1501 .parent = &core_96m_fck,
1502 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1503 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1504 .clkdm_name = "core_l4_clkdm",
1505 .recalc = &followparent_recalc,
1508 static struct clk i2c1_fck = {
1510 .ops = &clkops_omap2_dflt_wait,
1512 .parent = &core_96m_fck,
1513 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1514 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1515 .clkdm_name = "core_l4_clkdm",
1516 .recalc = &followparent_recalc,
1520 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1521 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1523 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1524 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1528 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1529 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1533 static const struct clksel mcbsp_15_clksel[] = {
1534 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1535 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1539 static struct clk mcbsp5_fck = {
1540 .name = "mcbsp_fck",
1541 .ops = &clkops_omap2_dflt_wait,
1543 .init = &omap2_init_clksel_parent,
1544 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1545 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1546 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1547 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1548 .clksel = mcbsp_15_clksel,
1549 .clkdm_name = "core_l4_clkdm",
1550 .recalc = &omap2_clksel_recalc,
1553 static struct clk mcbsp1_fck = {
1554 .name = "mcbsp_fck",
1555 .ops = &clkops_omap2_dflt_wait,
1557 .init = &omap2_init_clksel_parent,
1558 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1559 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1560 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1561 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1562 .clksel = mcbsp_15_clksel,
1563 .clkdm_name = "core_l4_clkdm",
1564 .recalc = &omap2_clksel_recalc,
1567 /* CORE_48M_FCK-derived clocks */
1569 static struct clk core_48m_fck = {
1570 .name = "core_48m_fck",
1571 .ops = &clkops_null,
1572 .parent = &omap_48m_fck,
1573 .flags = RATE_PROPAGATES,
1574 .clkdm_name = "core_l4_clkdm",
1575 .recalc = &followparent_recalc,
1578 static struct clk mcspi4_fck = {
1579 .name = "mcspi_fck",
1580 .ops = &clkops_omap2_dflt_wait,
1582 .parent = &core_48m_fck,
1583 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1584 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1585 .recalc = &followparent_recalc,
1588 static struct clk mcspi3_fck = {
1589 .name = "mcspi_fck",
1590 .ops = &clkops_omap2_dflt_wait,
1592 .parent = &core_48m_fck,
1593 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1594 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1595 .recalc = &followparent_recalc,
1598 static struct clk mcspi2_fck = {
1599 .name = "mcspi_fck",
1600 .ops = &clkops_omap2_dflt_wait,
1602 .parent = &core_48m_fck,
1603 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1604 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1605 .recalc = &followparent_recalc,
1608 static struct clk mcspi1_fck = {
1609 .name = "mcspi_fck",
1610 .ops = &clkops_omap2_dflt_wait,
1612 .parent = &core_48m_fck,
1613 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1614 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1615 .recalc = &followparent_recalc,
1618 static struct clk uart2_fck = {
1619 .name = "uart2_fck",
1620 .ops = &clkops_omap2_dflt_wait,
1621 .parent = &core_48m_fck,
1622 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1623 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1624 .recalc = &followparent_recalc,
1627 static struct clk uart1_fck = {
1628 .name = "uart1_fck",
1629 .ops = &clkops_omap2_dflt_wait,
1630 .parent = &core_48m_fck,
1631 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1632 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1633 .recalc = &followparent_recalc,
1636 static struct clk fshostusb_fck = {
1637 .name = "fshostusb_fck",
1638 .ops = &clkops_omap2_dflt_wait,
1639 .parent = &core_48m_fck,
1640 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1641 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1642 .recalc = &followparent_recalc,
1645 /* CORE_12M_FCK based clocks */
1647 static struct clk core_12m_fck = {
1648 .name = "core_12m_fck",
1649 .ops = &clkops_null,
1650 .parent = &omap_12m_fck,
1651 .flags = RATE_PROPAGATES,
1652 .clkdm_name = "core_l4_clkdm",
1653 .recalc = &followparent_recalc,
1656 static struct clk hdq_fck = {
1658 .ops = &clkops_omap2_dflt_wait,
1659 .parent = &core_12m_fck,
1660 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1661 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1662 .recalc = &followparent_recalc,
1665 /* DPLL3-derived clock */
1667 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1668 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1669 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1670 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1671 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1672 { .div = 6, .val = 6, .flags = RATE_IN_343X },
1673 { .div = 8, .val = 8, .flags = RATE_IN_343X },
1677 static const struct clksel ssi_ssr_clksel[] = {
1678 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1682 static struct clk ssi_ssr_fck = {
1683 .name = "ssi_ssr_fck",
1684 .ops = &clkops_omap2_dflt,
1685 .init = &omap2_init_clksel_parent,
1686 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1687 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1688 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1689 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1690 .clksel = ssi_ssr_clksel,
1691 .flags = RATE_PROPAGATES,
1692 .clkdm_name = "core_l4_clkdm",
1693 .recalc = &omap2_clksel_recalc,
1696 static struct clk ssi_sst_fck = {
1697 .name = "ssi_sst_fck",
1698 .ops = &clkops_null,
1699 .parent = &ssi_ssr_fck,
1701 .recalc = &omap2_fixed_divisor_recalc,
1706 /* CORE_L3_ICK based clocks */
1709 * XXX must add clk_enable/clk_disable for these if standard code won't
1712 static struct clk core_l3_ick = {
1713 .name = "core_l3_ick",
1714 .ops = &clkops_null,
1716 .init = &omap2_init_clk_clkdm,
1717 .flags = RATE_PROPAGATES,
1718 .clkdm_name = "core_l3_clkdm",
1719 .recalc = &followparent_recalc,
1722 static struct clk hsotgusb_ick = {
1723 .name = "hsotgusb_ick",
1724 .ops = &clkops_omap2_dflt_wait,
1725 .parent = &core_l3_ick,
1726 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1727 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1728 .clkdm_name = "core_l3_clkdm",
1729 .recalc = &followparent_recalc,
1732 static struct clk sdrc_ick = {
1734 .ops = &clkops_omap2_dflt_wait,
1735 .parent = &core_l3_ick,
1736 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1737 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1738 .flags = ENABLE_ON_INIT,
1739 .clkdm_name = "core_l3_clkdm",
1740 .recalc = &followparent_recalc,
1743 static struct clk gpmc_fck = {
1745 .ops = &clkops_null,
1746 .parent = &core_l3_ick,
1747 .flags = ENABLE_ON_INIT, /* huh? */
1748 .clkdm_name = "core_l3_clkdm",
1749 .recalc = &followparent_recalc,
1752 /* SECURITY_L3_ICK based clocks */
1754 static struct clk security_l3_ick = {
1755 .name = "security_l3_ick",
1756 .ops = &clkops_null,
1758 .flags = RATE_PROPAGATES,
1759 .recalc = &followparent_recalc,
1762 static struct clk pka_ick = {
1764 .ops = &clkops_omap2_dflt_wait,
1765 .parent = &security_l3_ick,
1766 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1767 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1768 .recalc = &followparent_recalc,
1771 /* CORE_L4_ICK based clocks */
1773 static struct clk core_l4_ick = {
1774 .name = "core_l4_ick",
1775 .ops = &clkops_null,
1777 .init = &omap2_init_clk_clkdm,
1778 .flags = RATE_PROPAGATES,
1779 .clkdm_name = "core_l4_clkdm",
1780 .recalc = &followparent_recalc,
1783 static struct clk usbtll_ick = {
1784 .name = "usbtll_ick",
1785 .ops = &clkops_omap2_dflt_wait,
1786 .parent = &core_l4_ick,
1787 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1788 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1789 .clkdm_name = "core_l4_clkdm",
1790 .recalc = &followparent_recalc,
1793 static struct clk mmchs3_ick = {
1794 .name = "mmchs_ick",
1795 .ops = &clkops_omap2_dflt_wait,
1797 .parent = &core_l4_ick,
1798 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1799 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1800 .clkdm_name = "core_l4_clkdm",
1801 .recalc = &followparent_recalc,
1804 /* Intersystem Communication Registers - chassis mode only */
1805 static struct clk icr_ick = {
1807 .ops = &clkops_omap2_dflt_wait,
1808 .parent = &core_l4_ick,
1809 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1810 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1811 .clkdm_name = "core_l4_clkdm",
1812 .recalc = &followparent_recalc,
1815 static struct clk aes2_ick = {
1817 .ops = &clkops_omap2_dflt_wait,
1818 .parent = &core_l4_ick,
1819 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1820 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1821 .clkdm_name = "core_l4_clkdm",
1822 .recalc = &followparent_recalc,
1825 static struct clk sha12_ick = {
1826 .name = "sha12_ick",
1827 .ops = &clkops_omap2_dflt_wait,
1828 .parent = &core_l4_ick,
1829 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1830 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1831 .clkdm_name = "core_l4_clkdm",
1832 .recalc = &followparent_recalc,
1835 static struct clk des2_ick = {
1837 .ops = &clkops_omap2_dflt_wait,
1838 .parent = &core_l4_ick,
1839 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1840 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1841 .clkdm_name = "core_l4_clkdm",
1842 .recalc = &followparent_recalc,
1845 static struct clk mmchs2_ick = {
1846 .name = "mmchs_ick",
1847 .ops = &clkops_omap2_dflt_wait,
1849 .parent = &core_l4_ick,
1850 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1851 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1852 .clkdm_name = "core_l4_clkdm",
1853 .recalc = &followparent_recalc,
1856 static struct clk mmchs1_ick = {
1857 .name = "mmchs_ick",
1858 .ops = &clkops_omap2_dflt_wait,
1859 .parent = &core_l4_ick,
1860 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1861 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1862 .clkdm_name = "core_l4_clkdm",
1863 .recalc = &followparent_recalc,
1866 static struct clk mspro_ick = {
1867 .name = "mspro_ick",
1868 .ops = &clkops_omap2_dflt_wait,
1869 .parent = &core_l4_ick,
1870 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1871 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1872 .clkdm_name = "core_l4_clkdm",
1873 .recalc = &followparent_recalc,
1876 static struct clk hdq_ick = {
1878 .ops = &clkops_omap2_dflt_wait,
1879 .parent = &core_l4_ick,
1880 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1881 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1882 .clkdm_name = "core_l4_clkdm",
1883 .recalc = &followparent_recalc,
1886 static struct clk mcspi4_ick = {
1887 .name = "mcspi_ick",
1888 .ops = &clkops_omap2_dflt_wait,
1890 .parent = &core_l4_ick,
1891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1892 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1893 .clkdm_name = "core_l4_clkdm",
1894 .recalc = &followparent_recalc,
1897 static struct clk mcspi3_ick = {
1898 .name = "mcspi_ick",
1899 .ops = &clkops_omap2_dflt_wait,
1901 .parent = &core_l4_ick,
1902 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1903 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1904 .clkdm_name = "core_l4_clkdm",
1905 .recalc = &followparent_recalc,
1908 static struct clk mcspi2_ick = {
1909 .name = "mcspi_ick",
1910 .ops = &clkops_omap2_dflt_wait,
1912 .parent = &core_l4_ick,
1913 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1914 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1915 .clkdm_name = "core_l4_clkdm",
1916 .recalc = &followparent_recalc,
1919 static struct clk mcspi1_ick = {
1920 .name = "mcspi_ick",
1921 .ops = &clkops_omap2_dflt_wait,
1923 .parent = &core_l4_ick,
1924 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1925 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1926 .clkdm_name = "core_l4_clkdm",
1927 .recalc = &followparent_recalc,
1930 static struct clk i2c3_ick = {
1932 .ops = &clkops_omap2_dflt_wait,
1934 .parent = &core_l4_ick,
1935 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1936 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1937 .clkdm_name = "core_l4_clkdm",
1938 .recalc = &followparent_recalc,
1941 static struct clk i2c2_ick = {
1943 .ops = &clkops_omap2_dflt_wait,
1945 .parent = &core_l4_ick,
1946 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1947 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1948 .clkdm_name = "core_l4_clkdm",
1949 .recalc = &followparent_recalc,
1952 static struct clk i2c1_ick = {
1954 .ops = &clkops_omap2_dflt_wait,
1956 .parent = &core_l4_ick,
1957 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1958 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1959 .clkdm_name = "core_l4_clkdm",
1960 .recalc = &followparent_recalc,
1963 static struct clk uart2_ick = {
1964 .name = "uart2_ick",
1965 .ops = &clkops_omap2_dflt_wait,
1966 .parent = &core_l4_ick,
1967 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1968 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1969 .clkdm_name = "core_l4_clkdm",
1970 .recalc = &followparent_recalc,
1973 static struct clk uart1_ick = {
1974 .name = "uart1_ick",
1975 .ops = &clkops_omap2_dflt_wait,
1976 .parent = &core_l4_ick,
1977 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1978 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1979 .clkdm_name = "core_l4_clkdm",
1980 .recalc = &followparent_recalc,
1983 static struct clk gpt11_ick = {
1984 .name = "gpt11_ick",
1985 .ops = &clkops_omap2_dflt_wait,
1986 .parent = &core_l4_ick,
1987 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1988 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1989 .clkdm_name = "core_l4_clkdm",
1990 .recalc = &followparent_recalc,
1993 static struct clk gpt10_ick = {
1994 .name = "gpt10_ick",
1995 .ops = &clkops_omap2_dflt_wait,
1996 .parent = &core_l4_ick,
1997 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1998 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1999 .clkdm_name = "core_l4_clkdm",
2000 .recalc = &followparent_recalc,
2003 static struct clk mcbsp5_ick = {
2004 .name = "mcbsp_ick",
2005 .ops = &clkops_omap2_dflt_wait,
2007 .parent = &core_l4_ick,
2008 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2009 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
2010 .clkdm_name = "core_l4_clkdm",
2011 .recalc = &followparent_recalc,
2014 static struct clk mcbsp1_ick = {
2015 .name = "mcbsp_ick",
2016 .ops = &clkops_omap2_dflt_wait,
2018 .parent = &core_l4_ick,
2019 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2020 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2021 .clkdm_name = "core_l4_clkdm",
2022 .recalc = &followparent_recalc,
2025 static struct clk fac_ick = {
2027 .ops = &clkops_omap2_dflt_wait,
2028 .parent = &core_l4_ick,
2029 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2030 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
2031 .clkdm_name = "core_l4_clkdm",
2032 .recalc = &followparent_recalc,
2035 static struct clk mailboxes_ick = {
2036 .name = "mailboxes_ick",
2037 .ops = &clkops_omap2_dflt_wait,
2038 .parent = &core_l4_ick,
2039 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2040 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2041 .clkdm_name = "core_l4_clkdm",
2042 .recalc = &followparent_recalc,
2045 static struct clk omapctrl_ick = {
2046 .name = "omapctrl_ick",
2047 .ops = &clkops_omap2_dflt_wait,
2048 .parent = &core_l4_ick,
2049 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2050 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2051 .flags = ENABLE_ON_INIT,
2052 .recalc = &followparent_recalc,
2055 /* SSI_L4_ICK based clocks */
2057 static struct clk ssi_l4_ick = {
2058 .name = "ssi_l4_ick",
2059 .ops = &clkops_null,
2061 .flags = RATE_PROPAGATES,
2062 .clkdm_name = "core_l4_clkdm",
2063 .recalc = &followparent_recalc,
2066 static struct clk ssi_ick = {
2068 .ops = &clkops_omap2_dflt,
2069 .parent = &ssi_l4_ick,
2070 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2071 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2072 .clkdm_name = "core_l4_clkdm",
2073 .recalc = &followparent_recalc,
2076 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2077 * but l4_ick makes more sense to me */
2079 static const struct clksel usb_l4_clksel[] = {
2080 { .parent = &l4_ick, .rates = div2_rates },
2084 static struct clk usb_l4_ick = {
2085 .name = "usb_l4_ick",
2086 .ops = &clkops_omap2_dflt_wait,
2088 .init = &omap2_init_clksel_parent,
2089 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2090 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2091 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2092 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2093 .clksel = usb_l4_clksel,
2094 .recalc = &omap2_clksel_recalc,
2097 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2099 /* SECURITY_L4_ICK2 based clocks */
2101 static struct clk security_l4_ick2 = {
2102 .name = "security_l4_ick2",
2103 .ops = &clkops_null,
2105 .flags = RATE_PROPAGATES,
2106 .recalc = &followparent_recalc,
2109 static struct clk aes1_ick = {
2111 .ops = &clkops_omap2_dflt_wait,
2112 .parent = &security_l4_ick2,
2113 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2114 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2115 .recalc = &followparent_recalc,
2118 static struct clk rng_ick = {
2120 .ops = &clkops_omap2_dflt_wait,
2121 .parent = &security_l4_ick2,
2122 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2123 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2124 .recalc = &followparent_recalc,
2127 static struct clk sha11_ick = {
2128 .name = "sha11_ick",
2129 .ops = &clkops_omap2_dflt_wait,
2130 .parent = &security_l4_ick2,
2131 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2132 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2133 .recalc = &followparent_recalc,
2136 static struct clk des1_ick = {
2138 .ops = &clkops_omap2_dflt_wait,
2139 .parent = &security_l4_ick2,
2140 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2141 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2142 .recalc = &followparent_recalc,
2146 static const struct clksel dss1_alwon_fck_clksel[] = {
2147 { .parent = &sys_ck, .rates = dpll_bypass_rates },
2148 { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2152 static struct clk dss1_alwon_fck = {
2153 .name = "dss1_alwon_fck",
2154 .ops = &clkops_omap2_dflt,
2155 .parent = &dpll4_m4x2_ck,
2156 .init = &omap2_init_clksel_parent,
2157 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2158 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2159 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2160 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
2161 .clksel = dss1_alwon_fck_clksel,
2162 .clkdm_name = "dss_clkdm",
2163 .recalc = &omap2_clksel_recalc,
2166 static struct clk dss_tv_fck = {
2167 .name = "dss_tv_fck",
2168 .ops = &clkops_omap2_dflt,
2169 .parent = &omap_54m_fck,
2170 .init = &omap2_init_clk_clkdm,
2171 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2172 .enable_bit = OMAP3430_EN_TV_SHIFT,
2173 .clkdm_name = "dss_clkdm",
2174 .recalc = &followparent_recalc,
2177 static struct clk dss_96m_fck = {
2178 .name = "dss_96m_fck",
2179 .ops = &clkops_omap2_dflt,
2180 .parent = &omap_96m_fck,
2181 .init = &omap2_init_clk_clkdm,
2182 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2183 .enable_bit = OMAP3430_EN_TV_SHIFT,
2184 .clkdm_name = "dss_clkdm",
2185 .recalc = &followparent_recalc,
2188 static struct clk dss2_alwon_fck = {
2189 .name = "dss2_alwon_fck",
2190 .ops = &clkops_omap2_dflt,
2192 .init = &omap2_init_clk_clkdm,
2193 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2194 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2195 .clkdm_name = "dss_clkdm",
2196 .recalc = &followparent_recalc,
2199 static struct clk dss_ick = {
2200 /* Handles both L3 and L4 clocks */
2202 .ops = &clkops_omap2_dflt,
2204 .init = &omap2_init_clk_clkdm,
2205 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2206 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2207 .clkdm_name = "dss_clkdm",
2208 .recalc = &followparent_recalc,
2213 static const struct clksel cam_mclk_clksel[] = {
2214 { .parent = &sys_ck, .rates = dpll_bypass_rates },
2215 { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2219 static struct clk cam_mclk = {
2221 .ops = &clkops_omap2_dflt_wait,
2222 .parent = &dpll4_m5x2_ck,
2223 .init = &omap2_init_clksel_parent,
2224 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2225 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
2226 .clksel = cam_mclk_clksel,
2227 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2228 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2229 .clkdm_name = "cam_clkdm",
2230 .recalc = &omap2_clksel_recalc,
2233 static struct clk cam_ick = {
2234 /* Handles both L3 and L4 clocks */
2236 .ops = &clkops_omap2_dflt_wait,
2238 .init = &omap2_init_clk_clkdm,
2239 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2240 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2241 .clkdm_name = "cam_clkdm",
2242 .recalc = &followparent_recalc,
2245 static struct clk csi2_96m_fck = {
2246 .name = "csi2_96m_fck",
2247 .ops = &clkops_omap2_dflt_wait,
2248 .parent = &core_96m_fck,
2249 .init = &omap2_init_clk_clkdm,
2250 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2251 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
2252 .clkdm_name = "cam_clkdm",
2253 .recalc = &followparent_recalc,
2256 /* USBHOST - 3430ES2 only */
2258 static struct clk usbhost_120m_fck = {
2259 .name = "usbhost_120m_fck",
2260 .ops = &clkops_omap2_dflt_wait,
2261 .parent = &omap_120m_fck,
2262 .init = &omap2_init_clk_clkdm,
2263 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2264 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2265 .clkdm_name = "usbhost_clkdm",
2266 .recalc = &followparent_recalc,
2269 static struct clk usbhost_48m_fck = {
2270 .name = "usbhost_48m_fck",
2271 .ops = &clkops_omap2_dflt_wait,
2272 .parent = &omap_48m_fck,
2273 .init = &omap2_init_clk_clkdm,
2274 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2275 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2276 .clkdm_name = "usbhost_clkdm",
2277 .recalc = &followparent_recalc,
2280 static struct clk usbhost_ick = {
2281 /* Handles both L3 and L4 clocks */
2282 .name = "usbhost_ick",
2283 .ops = &clkops_omap2_dflt_wait,
2285 .init = &omap2_init_clk_clkdm,
2286 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2287 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2288 .clkdm_name = "usbhost_clkdm",
2289 .recalc = &followparent_recalc,
2294 static const struct clksel_rate usim_96m_rates[] = {
2295 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2296 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2297 { .div = 8, .val = 5, .flags = RATE_IN_343X },
2298 { .div = 10, .val = 6, .flags = RATE_IN_343X },
2302 static const struct clksel_rate usim_120m_rates[] = {
2303 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
2304 { .div = 8, .val = 8, .flags = RATE_IN_343X },
2305 { .div = 16, .val = 9, .flags = RATE_IN_343X },
2306 { .div = 20, .val = 10, .flags = RATE_IN_343X },
2310 static const struct clksel usim_clksel[] = {
2311 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2312 { .parent = &omap_120m_fck, .rates = usim_120m_rates },
2313 { .parent = &sys_ck, .rates = div2_rates },
2318 static struct clk usim_fck = {
2320 .ops = &clkops_omap2_dflt_wait,
2321 .init = &omap2_init_clksel_parent,
2322 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2323 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2324 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2325 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2326 .clksel = usim_clksel,
2327 .recalc = &omap2_clksel_recalc,
2330 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2331 static struct clk gpt1_fck = {
2333 .ops = &clkops_omap2_dflt_wait,
2334 .init = &omap2_init_clksel_parent,
2335 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2336 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2337 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2338 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2339 .clksel = omap343x_gpt_clksel,
2340 .clkdm_name = "wkup_clkdm",
2341 .recalc = &omap2_clksel_recalc,
2344 static struct clk wkup_32k_fck = {
2345 .name = "wkup_32k_fck",
2346 .ops = &clkops_null,
2347 .init = &omap2_init_clk_clkdm,
2348 .parent = &omap_32k_fck,
2349 .flags = RATE_PROPAGATES,
2350 .clkdm_name = "wkup_clkdm",
2351 .recalc = &followparent_recalc,
2354 static struct clk gpio1_dbck = {
2355 .name = "gpio1_dbck",
2356 .ops = &clkops_omap2_dflt_wait,
2357 .parent = &wkup_32k_fck,
2358 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2359 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2360 .clkdm_name = "wkup_clkdm",
2361 .recalc = &followparent_recalc,
2364 static struct clk wdt2_fck = {
2366 .ops = &clkops_omap2_dflt_wait,
2367 .parent = &wkup_32k_fck,
2368 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2369 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2370 .clkdm_name = "wkup_clkdm",
2371 .recalc = &followparent_recalc,
2374 static struct clk wkup_l4_ick = {
2375 .name = "wkup_l4_ick",
2376 .ops = &clkops_null,
2378 .flags = RATE_PROPAGATES,
2379 .clkdm_name = "wkup_clkdm",
2380 .recalc = &followparent_recalc,
2384 /* Never specifically named in the TRM, so we have to infer a likely name */
2385 static struct clk usim_ick = {
2387 .ops = &clkops_omap2_dflt_wait,
2388 .parent = &wkup_l4_ick,
2389 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2390 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2391 .clkdm_name = "wkup_clkdm",
2392 .recalc = &followparent_recalc,
2395 static struct clk wdt2_ick = {
2397 .ops = &clkops_omap2_dflt_wait,
2398 .parent = &wkup_l4_ick,
2399 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2400 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2401 .clkdm_name = "wkup_clkdm",
2402 .recalc = &followparent_recalc,
2405 static struct clk wdt1_ick = {
2407 .ops = &clkops_omap2_dflt_wait,
2408 .parent = &wkup_l4_ick,
2409 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2410 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2411 .clkdm_name = "wkup_clkdm",
2412 .recalc = &followparent_recalc,
2415 static struct clk gpio1_ick = {
2416 .name = "gpio1_ick",
2417 .ops = &clkops_omap2_dflt_wait,
2418 .parent = &wkup_l4_ick,
2419 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2420 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2421 .clkdm_name = "wkup_clkdm",
2422 .recalc = &followparent_recalc,
2425 static struct clk omap_32ksync_ick = {
2426 .name = "omap_32ksync_ick",
2427 .ops = &clkops_omap2_dflt_wait,
2428 .parent = &wkup_l4_ick,
2429 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2430 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2431 .clkdm_name = "wkup_clkdm",
2432 .recalc = &followparent_recalc,
2435 /* XXX This clock no longer exists in 3430 TRM rev F */
2436 static struct clk gpt12_ick = {
2437 .name = "gpt12_ick",
2438 .ops = &clkops_omap2_dflt_wait,
2439 .parent = &wkup_l4_ick,
2440 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2441 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2442 .clkdm_name = "wkup_clkdm",
2443 .recalc = &followparent_recalc,
2446 static struct clk gpt1_ick = {
2448 .ops = &clkops_omap2_dflt_wait,
2449 .parent = &wkup_l4_ick,
2450 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2451 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2452 .clkdm_name = "wkup_clkdm",
2453 .recalc = &followparent_recalc,
2458 /* PER clock domain */
2460 static struct clk per_96m_fck = {
2461 .name = "per_96m_fck",
2462 .ops = &clkops_null,
2463 .parent = &omap_96m_alwon_fck,
2464 .init = &omap2_init_clk_clkdm,
2465 .flags = RATE_PROPAGATES,
2466 .clkdm_name = "per_clkdm",
2467 .recalc = &followparent_recalc,
2470 static struct clk per_48m_fck = {
2471 .name = "per_48m_fck",
2472 .ops = &clkops_null,
2473 .parent = &omap_48m_fck,
2474 .init = &omap2_init_clk_clkdm,
2475 .flags = RATE_PROPAGATES,
2476 .clkdm_name = "per_clkdm",
2477 .recalc = &followparent_recalc,
2480 static struct clk uart3_fck = {
2481 .name = "uart3_fck",
2482 .ops = &clkops_omap2_dflt_wait,
2483 .parent = &per_48m_fck,
2484 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2485 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2486 .clkdm_name = "per_clkdm",
2487 .recalc = &followparent_recalc,
2490 static struct clk gpt2_fck = {
2492 .ops = &clkops_omap2_dflt_wait,
2493 .init = &omap2_init_clksel_parent,
2494 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2495 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2496 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2497 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2498 .clksel = omap343x_gpt_clksel,
2499 .clkdm_name = "per_clkdm",
2500 .recalc = &omap2_clksel_recalc,
2503 static struct clk gpt3_fck = {
2505 .ops = &clkops_omap2_dflt_wait,
2506 .init = &omap2_init_clksel_parent,
2507 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2508 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2509 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2510 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2511 .clksel = omap343x_gpt_clksel,
2512 .clkdm_name = "per_clkdm",
2513 .recalc = &omap2_clksel_recalc,
2516 static struct clk gpt4_fck = {
2518 .ops = &clkops_omap2_dflt_wait,
2519 .init = &omap2_init_clksel_parent,
2520 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2521 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2522 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2523 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2524 .clksel = omap343x_gpt_clksel,
2525 .clkdm_name = "per_clkdm",
2526 .recalc = &omap2_clksel_recalc,
2529 static struct clk gpt5_fck = {
2531 .ops = &clkops_omap2_dflt_wait,
2532 .init = &omap2_init_clksel_parent,
2533 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2534 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2535 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2536 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2537 .clksel = omap343x_gpt_clksel,
2538 .clkdm_name = "per_clkdm",
2539 .recalc = &omap2_clksel_recalc,
2542 static struct clk gpt6_fck = {
2544 .ops = &clkops_omap2_dflt_wait,
2545 .init = &omap2_init_clksel_parent,
2546 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2547 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2548 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2549 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2550 .clksel = omap343x_gpt_clksel,
2551 .clkdm_name = "per_clkdm",
2552 .recalc = &omap2_clksel_recalc,
2555 static struct clk gpt7_fck = {
2557 .ops = &clkops_omap2_dflt_wait,
2558 .init = &omap2_init_clksel_parent,
2559 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2560 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2561 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2562 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2563 .clksel = omap343x_gpt_clksel,
2564 .clkdm_name = "per_clkdm",
2565 .recalc = &omap2_clksel_recalc,
2568 static struct clk gpt8_fck = {
2570 .ops = &clkops_omap2_dflt_wait,
2571 .init = &omap2_init_clksel_parent,
2572 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2573 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2574 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2575 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2576 .clksel = omap343x_gpt_clksel,
2577 .clkdm_name = "per_clkdm",
2578 .recalc = &omap2_clksel_recalc,
2581 static struct clk gpt9_fck = {
2583 .ops = &clkops_omap2_dflt_wait,
2584 .init = &omap2_init_clksel_parent,
2585 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2586 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2587 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2588 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2589 .clksel = omap343x_gpt_clksel,
2590 .clkdm_name = "per_clkdm",
2591 .recalc = &omap2_clksel_recalc,
2594 static struct clk per_32k_alwon_fck = {
2595 .name = "per_32k_alwon_fck",
2596 .ops = &clkops_null,
2597 .parent = &omap_32k_fck,
2598 .clkdm_name = "per_clkdm",
2599 .flags = RATE_PROPAGATES,
2600 .recalc = &followparent_recalc,
2603 static struct clk gpio6_dbck = {
2604 .name = "gpio6_dbck",
2605 .ops = &clkops_omap2_dflt_wait,
2606 .parent = &per_32k_alwon_fck,
2607 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2608 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2609 .clkdm_name = "per_clkdm",
2610 .recalc = &followparent_recalc,
2613 static struct clk gpio5_dbck = {
2614 .name = "gpio5_dbck",
2615 .ops = &clkops_omap2_dflt_wait,
2616 .parent = &per_32k_alwon_fck,
2617 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2618 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2619 .clkdm_name = "per_clkdm",
2620 .recalc = &followparent_recalc,
2623 static struct clk gpio4_dbck = {
2624 .name = "gpio4_dbck",
2625 .ops = &clkops_omap2_dflt_wait,
2626 .parent = &per_32k_alwon_fck,
2627 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2628 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2629 .clkdm_name = "per_clkdm",
2630 .recalc = &followparent_recalc,
2633 static struct clk gpio3_dbck = {
2634 .name = "gpio3_dbck",
2635 .ops = &clkops_omap2_dflt_wait,
2636 .parent = &per_32k_alwon_fck,
2637 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2638 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2639 .clkdm_name = "per_clkdm",
2640 .recalc = &followparent_recalc,
2643 static struct clk gpio2_dbck = {
2644 .name = "gpio2_dbck",
2645 .ops = &clkops_omap2_dflt_wait,
2646 .parent = &per_32k_alwon_fck,
2647 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2648 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2649 .clkdm_name = "per_clkdm",
2650 .recalc = &followparent_recalc,
2653 static struct clk wdt3_fck = {
2655 .ops = &clkops_omap2_dflt_wait,
2656 .parent = &per_32k_alwon_fck,
2657 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2658 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2659 .clkdm_name = "per_clkdm",
2660 .recalc = &followparent_recalc,
2663 static struct clk per_l4_ick = {
2664 .name = "per_l4_ick",
2665 .ops = &clkops_null,
2667 .flags = RATE_PROPAGATES,
2668 .clkdm_name = "per_clkdm",
2669 .recalc = &followparent_recalc,
2672 static struct clk gpio6_ick = {
2673 .name = "gpio6_ick",
2674 .ops = &clkops_omap2_dflt_wait,
2675 .parent = &per_l4_ick,
2676 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2677 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2678 .clkdm_name = "per_clkdm",
2679 .recalc = &followparent_recalc,
2682 static struct clk gpio5_ick = {
2683 .name = "gpio5_ick",
2684 .ops = &clkops_omap2_dflt_wait,
2685 .parent = &per_l4_ick,
2686 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2687 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2688 .clkdm_name = "per_clkdm",
2689 .recalc = &followparent_recalc,
2692 static struct clk gpio4_ick = {
2693 .name = "gpio4_ick",
2694 .ops = &clkops_omap2_dflt_wait,
2695 .parent = &per_l4_ick,
2696 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2697 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2698 .clkdm_name = "per_clkdm",
2699 .recalc = &followparent_recalc,
2702 static struct clk gpio3_ick = {
2703 .name = "gpio3_ick",
2704 .ops = &clkops_omap2_dflt_wait,
2705 .parent = &per_l4_ick,
2706 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2707 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2708 .clkdm_name = "per_clkdm",
2709 .recalc = &followparent_recalc,
2712 static struct clk gpio2_ick = {
2713 .name = "gpio2_ick",
2714 .ops = &clkops_omap2_dflt_wait,
2715 .parent = &per_l4_ick,
2716 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2717 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2718 .clkdm_name = "per_clkdm",
2719 .recalc = &followparent_recalc,
2722 static struct clk wdt3_ick = {
2724 .ops = &clkops_omap2_dflt_wait,
2725 .parent = &per_l4_ick,
2726 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2727 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2728 .clkdm_name = "per_clkdm",
2729 .recalc = &followparent_recalc,
2732 static struct clk uart3_ick = {
2733 .name = "uart3_ick",
2734 .ops = &clkops_omap2_dflt_wait,
2735 .parent = &per_l4_ick,
2736 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2737 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2738 .clkdm_name = "per_clkdm",
2739 .recalc = &followparent_recalc,
2742 static struct clk gpt9_ick = {
2744 .ops = &clkops_omap2_dflt_wait,
2745 .parent = &per_l4_ick,
2746 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2747 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2748 .clkdm_name = "per_clkdm",
2749 .recalc = &followparent_recalc,
2752 static struct clk gpt8_ick = {
2754 .ops = &clkops_omap2_dflt_wait,
2755 .parent = &per_l4_ick,
2756 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2757 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2758 .clkdm_name = "per_clkdm",
2759 .recalc = &followparent_recalc,
2762 static struct clk gpt7_ick = {
2764 .ops = &clkops_omap2_dflt_wait,
2765 .parent = &per_l4_ick,
2766 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2767 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2768 .clkdm_name = "per_clkdm",
2769 .recalc = &followparent_recalc,
2772 static struct clk gpt6_ick = {
2774 .ops = &clkops_omap2_dflt_wait,
2775 .parent = &per_l4_ick,
2776 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2777 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2778 .clkdm_name = "per_clkdm",
2779 .recalc = &followparent_recalc,
2782 static struct clk gpt5_ick = {
2784 .ops = &clkops_omap2_dflt_wait,
2785 .parent = &per_l4_ick,
2786 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2787 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2788 .clkdm_name = "per_clkdm",
2789 .recalc = &followparent_recalc,
2792 static struct clk gpt4_ick = {
2794 .ops = &clkops_omap2_dflt_wait,
2795 .parent = &per_l4_ick,
2796 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2797 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2798 .clkdm_name = "per_clkdm",
2799 .recalc = &followparent_recalc,
2802 static struct clk gpt3_ick = {
2804 .ops = &clkops_omap2_dflt_wait,
2805 .parent = &per_l4_ick,
2806 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2807 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2808 .clkdm_name = "per_clkdm",
2809 .recalc = &followparent_recalc,
2812 static struct clk gpt2_ick = {
2814 .ops = &clkops_omap2_dflt_wait,
2815 .parent = &per_l4_ick,
2816 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2817 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2818 .clkdm_name = "per_clkdm",
2819 .recalc = &followparent_recalc,
2822 static struct clk mcbsp2_ick = {
2823 .name = "mcbsp_ick",
2824 .ops = &clkops_omap2_dflt_wait,
2826 .parent = &per_l4_ick,
2827 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2828 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2829 .clkdm_name = "per_clkdm",
2830 .recalc = &followparent_recalc,
2833 static struct clk mcbsp3_ick = {
2834 .name = "mcbsp_ick",
2835 .ops = &clkops_omap2_dflt_wait,
2837 .parent = &per_l4_ick,
2838 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2839 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2840 .clkdm_name = "per_clkdm",
2841 .recalc = &followparent_recalc,
2844 static struct clk mcbsp4_ick = {
2845 .name = "mcbsp_ick",
2846 .ops = &clkops_omap2_dflt_wait,
2848 .parent = &per_l4_ick,
2849 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2850 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2851 .clkdm_name = "per_clkdm",
2852 .recalc = &followparent_recalc,
2855 static const struct clksel mcbsp_234_clksel[] = {
2856 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2857 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2861 static struct clk mcbsp2_fck = {
2862 .name = "mcbsp_fck",
2863 .ops = &clkops_omap2_dflt_wait,
2865 .init = &omap2_init_clksel_parent,
2866 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2867 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2868 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2869 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2870 .clksel = mcbsp_234_clksel,
2871 .clkdm_name = "per_clkdm",
2872 .recalc = &omap2_clksel_recalc,
2875 static struct clk mcbsp3_fck = {
2876 .name = "mcbsp_fck",
2877 .ops = &clkops_omap2_dflt_wait,
2879 .init = &omap2_init_clksel_parent,
2880 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2881 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2882 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2883 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2884 .clksel = mcbsp_234_clksel,
2885 .clkdm_name = "per_clkdm",
2886 .recalc = &omap2_clksel_recalc,
2889 static struct clk mcbsp4_fck = {
2890 .name = "mcbsp_fck",
2891 .ops = &clkops_omap2_dflt_wait,
2893 .init = &omap2_init_clksel_parent,
2894 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2895 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2896 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2897 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2898 .clksel = mcbsp_234_clksel,
2899 .clkdm_name = "per_clkdm",
2900 .recalc = &omap2_clksel_recalc,
2905 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2907 static const struct clksel_rate emu_src_sys_rates[] = {
2908 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2912 static const struct clksel_rate emu_src_core_rates[] = {
2913 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2917 static const struct clksel_rate emu_src_per_rates[] = {
2918 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2922 static const struct clksel_rate emu_src_mpu_rates[] = {
2923 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2927 static const struct clksel emu_src_clksel[] = {
2928 { .parent = &sys_ck, .rates = emu_src_sys_rates },
2929 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2930 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
2931 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
2936 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2937 * to switch the source of some of the EMU clocks.
2938 * XXX Are there CLKEN bits for these EMU clks?
2940 static struct clk emu_src_ck = {
2941 .name = "emu_src_ck",
2942 .ops = &clkops_null,
2943 .init = &omap2_init_clksel_parent,
2944 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2945 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2946 .clksel = emu_src_clksel,
2947 .flags = RATE_PROPAGATES,
2948 .clkdm_name = "emu_clkdm",
2949 .recalc = &omap2_clksel_recalc,
2952 static const struct clksel_rate pclk_emu_rates[] = {
2953 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2954 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2955 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2956 { .div = 6, .val = 6, .flags = RATE_IN_343X },
2960 static const struct clksel pclk_emu_clksel[] = {
2961 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2965 static struct clk pclk_fck = {
2967 .ops = &clkops_null,
2968 .init = &omap2_init_clksel_parent,
2969 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2970 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2971 .clksel = pclk_emu_clksel,
2972 .flags = RATE_PROPAGATES,
2973 .clkdm_name = "emu_clkdm",
2974 .recalc = &omap2_clksel_recalc,
2977 static const struct clksel_rate pclkx2_emu_rates[] = {
2978 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2979 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2980 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2984 static const struct clksel pclkx2_emu_clksel[] = {
2985 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2989 static struct clk pclkx2_fck = {
2990 .name = "pclkx2_fck",
2991 .ops = &clkops_null,
2992 .init = &omap2_init_clksel_parent,
2993 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2994 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2995 .clksel = pclkx2_emu_clksel,
2996 .flags = RATE_PROPAGATES,
2997 .clkdm_name = "emu_clkdm",
2998 .recalc = &omap2_clksel_recalc,
3001 static const struct clksel atclk_emu_clksel[] = {
3002 { .parent = &emu_src_ck, .rates = div2_rates },
3006 static struct clk atclk_fck = {
3007 .name = "atclk_fck",
3008 .ops = &clkops_null,
3009 .init = &omap2_init_clksel_parent,
3010 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3011 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
3012 .clksel = atclk_emu_clksel,
3013 .flags = RATE_PROPAGATES,
3014 .clkdm_name = "emu_clkdm",
3015 .recalc = &omap2_clksel_recalc,
3018 static struct clk traceclk_src_fck = {
3019 .name = "traceclk_src_fck",
3020 .ops = &clkops_null,
3021 .init = &omap2_init_clksel_parent,
3022 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3023 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
3024 .clksel = emu_src_clksel,
3025 .flags = RATE_PROPAGATES,
3026 .clkdm_name = "emu_clkdm",
3027 .recalc = &omap2_clksel_recalc,
3030 static const struct clksel_rate traceclk_rates[] = {
3031 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3032 { .div = 2, .val = 2, .flags = RATE_IN_343X },
3033 { .div = 4, .val = 4, .flags = RATE_IN_343X },
3037 static const struct clksel traceclk_clksel[] = {
3038 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3042 static struct clk traceclk_fck = {
3043 .name = "traceclk_fck",
3044 .ops = &clkops_null,
3045 .init = &omap2_init_clksel_parent,
3046 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3047 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
3048 .clksel = traceclk_clksel,
3049 .clkdm_name = "emu_clkdm",
3050 .recalc = &omap2_clksel_recalc,
3055 /* SmartReflex fclk (VDD1) */
3056 static struct clk sr1_fck = {
3058 .ops = &clkops_omap2_dflt_wait,
3060 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3061 .enable_bit = OMAP3430_EN_SR1_SHIFT,
3062 .flags = RATE_PROPAGATES,
3063 .recalc = &followparent_recalc,
3066 /* SmartReflex fclk (VDD2) */
3067 static struct clk sr2_fck = {
3069 .ops = &clkops_omap2_dflt_wait,
3071 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3072 .enable_bit = OMAP3430_EN_SR2_SHIFT,
3073 .flags = RATE_PROPAGATES,
3074 .recalc = &followparent_recalc,
3077 static struct clk sr_l4_ick = {
3078 .name = "sr_l4_ick",
3079 .ops = &clkops_null, /* RMK: missing? */
3081 .clkdm_name = "core_l4_clkdm",
3082 .recalc = &followparent_recalc,
3085 /* SECURE_32K_FCK clocks */
3087 /* XXX This clock no longer exists in 3430 TRM rev F */
3088 static struct clk gpt12_fck = {
3089 .name = "gpt12_fck",
3090 .ops = &clkops_null,
3091 .parent = &secure_32k_fck,
3092 .recalc = &followparent_recalc,
3095 static struct clk wdt1_fck = {
3097 .ops = &clkops_null,
3098 .parent = &secure_32k_fck,
3099 .recalc = &followparent_recalc,