arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35
  36 /* Maximum DPLL multiplier, divider values for OMAP3 */
  37 #define OMAP3_MAX_DPLL_MULT             2048
  38 #define OMAP3_MAX_DPLL_DIV              128
  39
  40 /*
  41  * DPLL1 supplies clock to the MPU.
  42  * DPLL2 supplies clock to the IVA2.
  43  * DPLL3 supplies CORE domain clocks.
  44  * DPLL4 supplies peripheral clocks.
  45  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  46  */
  47
  48 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  49 #define DPLL_LOW_POWER_STOP             0x1
  50 #define DPLL_LOW_POWER_BYPASS           0x5
  51 #define DPLL_LOCKED                     0x7
  52
  53 /* PRM CLOCKS */
  54
  55 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  56 static struct clk omap_32k_fck = {
  57         .name           = "omap_32k_fck",
  58         .ops            = &clkops_null,
  59         .rate           = 32768,
  60         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
  61         .recalc         = &propagate_rate,
  62 };
  63
  64 static struct clk secure_32k_fck = {
  65         .name           = "secure_32k_fck",
  66         .ops            = &clkops_null,
  67         .rate           = 32768,
  68         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
  69         .recalc         = &propagate_rate,
  70 };
  71
  72 /* Virtual source clocks for osc_sys_ck */
  73 static struct clk virt_12m_ck = {
  74         .name           = "virt_12m_ck",
  75         .ops            = &clkops_null,
  76         .rate           = 12000000,
  77         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
  78         .recalc         = &propagate_rate,
  79 };
  80
  81 static struct clk virt_13m_ck = {
  82         .name           = "virt_13m_ck",
  83         .ops            = &clkops_null,
  84         .rate           = 13000000,
  85         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
  86         .recalc         = &propagate_rate,
  87 };
  88
  89 static struct clk virt_16_8m_ck = {
  90         .name           = "virt_16_8m_ck",
  91         .ops            = &clkops_null,
  92         .rate           = 16800000,
  93         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES,
  94         .recalc         = &propagate_rate,
  95 };
  96
  97 static struct clk virt_19_2m_ck = {
  98         .name           = "virt_19_2m_ck",
  99         .ops            = &clkops_null,
 100         .rate           = 19200000,
 101         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
 102         .recalc         = &propagate_rate,
 103 };
 104
 105 static struct clk virt_26m_ck = {
 106         .name           = "virt_26m_ck",
 107         .ops            = &clkops_null,
 108         .rate           = 26000000,
 109         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
 110         .recalc         = &propagate_rate,
 111 };
 112
 113 static struct clk virt_38_4m_ck = {
 114         .name           = "virt_38_4m_ck",
 115         .ops            = &clkops_null,
 116         .rate           = 38400000,
 117         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
 118         .recalc         = &propagate_rate,
 119 };
 120
 121 static const struct clksel_rate osc_sys_12m_rates[] = {
 122         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 123         { .div = 0 }
 124 };
 125
 126 static const struct clksel_rate osc_sys_13m_rates[] = {
 127         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 128         { .div = 0 }
 129 };
 130
 131 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 132         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 133         { .div = 0 }
 134 };
 135
 136 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 137         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 138         { .div = 0 }
 139 };
 140
 141 static const struct clksel_rate osc_sys_26m_rates[] = {
 142         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 143         { .div = 0 }
 144 };
 145
 146 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 147         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 148         { .div = 0 }
 149 };
 150
 151 static const struct clksel osc_sys_clksel[] = {
 152         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 153         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 154         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 155         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 156         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 157         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 158         { .parent = NULL },
 159 };
 160
 161 /* Oscillator clock */
 162 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 163 static struct clk osc_sys_ck = {
 164         .name           = "osc_sys_ck",
 165         .ops            = &clkops_null,
 166         .init           = &omap2_init_clksel_parent,
 167         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 168         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 169         .clksel         = osc_sys_clksel,
 170         /* REVISIT: deal with autoextclkmode? */
 171         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
 172         .recalc         = &omap2_clksel_recalc,
 173 };
 174
 175 static const struct clksel_rate div2_rates[] = {
 176         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 177         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 178         { .div = 0 }
 179 };
 180
 181 static const struct clksel sys_clksel[] = {
 182         { .parent = &osc_sys_ck, .rates = div2_rates },
 183         { .parent = NULL }
 184 };
 185
 186 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 187 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 188 static struct clk sys_ck = {
 189         .name           = "sys_ck",
 190         .ops            = &clkops_null,
 191         .parent         = &osc_sys_ck,
 192         .init           = &omap2_init_clksel_parent,
 193         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 194         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 195         .clksel         = sys_clksel,
 196         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 197         .recalc         = &omap2_clksel_recalc,
 198 };
 199
 200 static struct clk sys_altclk = {
 201         .name           = "sys_altclk",
 202         .ops            = &clkops_null,
 203         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 204         .recalc         = &propagate_rate,
 205 };
 206
 207 /* Optional external clock input for some McBSPs */
 208 static struct clk mcbsp_clks = {
 209         .name           = "mcbsp_clks",
 210         .ops            = &clkops_null,
 211         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 212         .recalc         = &propagate_rate,
 213 };
 214
 215 /* PRM EXTERNAL CLOCK OUTPUT */
 216
 217 static struct clk sys_clkout1 = {
 218         .name           = "sys_clkout1",
 219         .ops            = &clkops_omap2_dflt_wait,
 220         .parent         = &osc_sys_ck,
 221         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 222         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 223         .flags          = CLOCK_IN_OMAP343X,
 224         .recalc         = &followparent_recalc,
 225 };
 226
 227 /* DPLLS */
 228
 229 /* CM CLOCKS */
 230
 231 static const struct clksel_rate dpll_bypass_rates[] = {
 232         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 233         { .div = 0 }
 234 };
 235
 236 static const struct clksel_rate dpll_locked_rates[] = {
 237         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 238         { .div = 0 }
 239 };
 240
 241 static const struct clksel_rate div16_dpll_rates[] = {
 242         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 243         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 244         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 245         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 246         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 247         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 248         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 249         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 250         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 251         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 252         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 253         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 254         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 255         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 256         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 257         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 258         { .div = 0 }
 259 };
 260
 261 /* DPLL1 */
 262 /* MPU clock source */
 263 /* Type: DPLL */
 264 static struct dpll_data dpll1_dd = {
 265         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 266         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 267         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 268         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 269         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 270         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 271         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 272         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 273         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 274         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 275         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 276         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 277         .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
 278         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 279         .max_divider    = OMAP3_MAX_DPLL_DIV,
 280         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 281 };
 282
 283 static struct clk dpll1_ck = {
 284         .name           = "dpll1_ck",
 285         .ops            = &clkops_null,
 286         .parent         = &sys_ck,
 287         .dpll_data      = &dpll1_dd,
 288         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 289         .round_rate     = &omap2_dpll_round_rate,
 290         .recalc         = &omap3_dpll_recalc,
 291 };
 292
 293 /*
 294  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 295  * DPLL isn't bypassed.
 296  */
 297 static struct clk dpll1_x2_ck = {
 298         .name           = "dpll1_x2_ck",
 299         .ops            = &clkops_null,
 300         .parent         = &dpll1_ck,
 301         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 302         .recalc         = &omap3_clkoutx2_recalc,
 303 };
 304
 305 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 306 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 307         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 308         { .parent = NULL }
 309 };
 310
 311 /*
 312  * Does not exist in the TRM - needed to separate the M2 divider from
 313  * bypass selection in mpu_ck
 314  */
 315 static struct clk dpll1_x2m2_ck = {
 316         .name           = "dpll1_x2m2_ck",
 317         .ops            = &clkops_null,
 318         .parent         = &dpll1_x2_ck,
 319         .init           = &omap2_init_clksel_parent,
 320         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 321         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 322         .clksel         = div16_dpll1_x2m2_clksel,
 323         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 324         .recalc         = &omap2_clksel_recalc,
 325 };
 326
 327 /* DPLL2 */
 328 /* IVA2 clock source */
 329 /* Type: DPLL */
 330
 331 static struct dpll_data dpll2_dd = {
 332         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 333         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 334         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 335         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 336         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 337         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 338                                 (1 << DPLL_LOW_POWER_BYPASS),
 339         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 340         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 341         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 342         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 343         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 344         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 345         .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
 346         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 347         .max_divider    = OMAP3_MAX_DPLL_DIV,
 348         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 349 };
 350
 351 static struct clk dpll2_ck = {
 352         .name           = "dpll2_ck",
 353         .ops            = &clkops_noncore_dpll_ops,
 354         .parent         = &sys_ck,
 355         .dpll_data      = &dpll2_dd,
 356         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 357         .round_rate     = &omap2_dpll_round_rate,
 358         .recalc         = &omap3_dpll_recalc,
 359 };
 360
 361 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 362         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 363         { .parent = NULL }
 364 };
 365
 366 /*
 367  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 368  * or CLKOUTX2. CLKOUT seems most plausible.
 369  */
 370 static struct clk dpll2_m2_ck = {
 371         .name           = "dpll2_m2_ck",
 372         .ops            = &clkops_null,
 373         .parent         = &dpll2_ck,
 374         .init           = &omap2_init_clksel_parent,
 375         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 376                                           OMAP3430_CM_CLKSEL2_PLL),
 377         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 378         .clksel         = div16_dpll2_m2x2_clksel,
 379         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 380         .recalc         = &omap2_clksel_recalc,
 381 };
 382
 383 /*
 384  * DPLL3
 385  * Source clock for all interfaces and for some device fclks
 386  * REVISIT: Also supports fast relock bypass - not included below
 387  */
 388 static struct dpll_data dpll3_dd = {
 389         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 390         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 391         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 392         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 393         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 394         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 395         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 396         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 397         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 398         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 399         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 400         .max_divider    = OMAP3_MAX_DPLL_DIV,
 401         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 402 };
 403
 404 static struct clk dpll3_ck = {
 405         .name           = "dpll3_ck",
 406         .ops            = &clkops_null,
 407         .parent         = &sys_ck,
 408         .dpll_data      = &dpll3_dd,
 409         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 410         .round_rate     = &omap2_dpll_round_rate,
 411         .recalc         = &omap3_dpll_recalc,
 412 };
 413
 414 /*
 415  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 416  * DPLL isn't bypassed
 417  */
 418 static struct clk dpll3_x2_ck = {
 419         .name           = "dpll3_x2_ck",
 420         .ops            = &clkops_null,
 421         .parent         = &dpll3_ck,
 422         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 423         .recalc         = &omap3_clkoutx2_recalc,
 424 };
 425
 426 static const struct clksel_rate div31_dpll3_rates[] = {
 427         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 428         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 429         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 430         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 431         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 432         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 433         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 434         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 435         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 436         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 437         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 438         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 439         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 440         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 441         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 442         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 443         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 444         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 445         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 446         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 447         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 448         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 449         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 450         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 451         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 452         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 453         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 454         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 455         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 456         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 457         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 458         { .div = 0 },
 459 };
 460
 461 static const struct clksel div31_dpll3m2_clksel[] = {
 462         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 463         { .parent = NULL }
 464 };
 465
 466 /*
 467  * DPLL3 output M2
 468  * REVISIT: This DPLL output divider must be changed in SRAM, so until
 469  * that code is ready, this should remain a 'read-only' clksel clock.
 470  */
 471 static struct clk dpll3_m2_ck = {
 472         .name           = "dpll3_m2_ck",
 473         .ops            = &clkops_null,
 474         .parent         = &dpll3_ck,
 475         .init           = &omap2_init_clksel_parent,
 476         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 477         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 478         .clksel         = div31_dpll3m2_clksel,
 479         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 480         .recalc         = &omap2_clksel_recalc,
 481 };
 482
 483 static const struct clksel core_ck_clksel[] = {
 484         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 485         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 486         { .parent = NULL }
 487 };
 488
 489 static struct clk core_ck = {
 490         .name           = "core_ck",
 491         .ops            = &clkops_null,
 492         .init           = &omap2_init_clksel_parent,
 493         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 494         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 495         .clksel         = core_ck_clksel,
 496         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 497         .recalc         = &omap2_clksel_recalc,
 498 };
 499
 500 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 501         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 502         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 503         { .parent = NULL }
 504 };
 505
 506 static struct clk dpll3_m2x2_ck = {
 507         .name           = "dpll3_m2x2_ck",
 508         .ops            = &clkops_null,
 509         .init           = &omap2_init_clksel_parent,
 510         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 511         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 512         .clksel         = dpll3_m2x2_ck_clksel,
 513         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 514         .recalc         = &omap2_clksel_recalc,
 515 };
 516
 517 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 518 static const struct clksel div16_dpll3_clksel[] = {
 519         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 520         { .parent = NULL }
 521 };
 522
 523 /* This virtual clock is the source for dpll3_m3x2_ck */
 524 static struct clk dpll3_m3_ck = {
 525         .name           = "dpll3_m3_ck",
 526         .ops            = &clkops_null,
 527         .parent         = &dpll3_ck,
 528         .init           = &omap2_init_clksel_parent,
 529         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 530         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 531         .clksel         = div16_dpll3_clksel,
 532         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 533         .recalc         = &omap2_clksel_recalc,
 534 };
 535
 536 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 537 static struct clk dpll3_m3x2_ck = {
 538         .name           = "dpll3_m3x2_ck",
 539         .ops            = &clkops_omap2_dflt_wait,
 540         .parent         = &dpll3_m3_ck,
 541         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 542         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 543         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 544         .recalc         = &omap3_clkoutx2_recalc,
 545 };
 546
 547 static const struct clksel emu_core_alwon_ck_clksel[] = {
 548         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 549         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 550         { .parent = NULL }
 551 };
 552
 553 static struct clk emu_core_alwon_ck = {
 554         .name           = "emu_core_alwon_ck",
 555         .ops            = &clkops_null,
 556         .parent         = &dpll3_m3x2_ck,
 557         .init           = &omap2_init_clksel_parent,
 558         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 559         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 560         .clksel         = emu_core_alwon_ck_clksel,
 561         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 562         .recalc         = &omap2_clksel_recalc,
 563 };
 564
 565 /* DPLL4 */
 566 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 567 /* Type: DPLL */
 568 static struct dpll_data dpll4_dd = {
 569         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 570         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 571         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 572         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 573         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 574         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 575         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 576         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 577         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 578         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 579         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 580         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 581         .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
 582         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 583         .max_divider    = OMAP3_MAX_DPLL_DIV,
 584         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 585 };
 586
 587 static struct clk dpll4_ck = {
 588         .name           = "dpll4_ck",
 589         .ops            = &clkops_noncore_dpll_ops,
 590         .parent         = &sys_ck,
 591         .dpll_data      = &dpll4_dd,
 592         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 593         .round_rate     = &omap2_dpll_round_rate,
 594         .recalc         = &omap3_dpll_recalc,
 595 };
 596
 597 /*
 598  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 599  * DPLL isn't bypassed --
 600  * XXX does this serve any downstream clocks?
 601  */
 602 static struct clk dpll4_x2_ck = {
 603         .name           = "dpll4_x2_ck",
 604         .ops            = &clkops_null,
 605         .parent         = &dpll4_ck,
 606         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 607         .recalc         = &omap3_clkoutx2_recalc,
 608 };
 609
 610 static const struct clksel div16_dpll4_clksel[] = {
 611         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 612         { .parent = NULL }
 613 };
 614
 615 /* This virtual clock is the source for dpll4_m2x2_ck */
 616 static struct clk dpll4_m2_ck = {
 617         .name           = "dpll4_m2_ck",
 618         .ops            = &clkops_null,
 619         .parent         = &dpll4_ck,
 620         .init           = &omap2_init_clksel_parent,
 621         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 622         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 623         .clksel         = div16_dpll4_clksel,
 624         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 625         .recalc         = &omap2_clksel_recalc,
 626 };
 627
 628 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 629 static struct clk dpll4_m2x2_ck = {
 630         .name           = "dpll4_m2x2_ck",
 631         .ops            = &clkops_omap2_dflt_wait,
 632         .parent         = &dpll4_m2_ck,
 633         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 634         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 635         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 636         .recalc         = &omap3_clkoutx2_recalc,
 637 };
 638
 639 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 640         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 641         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 642         { .parent = NULL }
 643 };
 644
 645 static struct clk omap_96m_alwon_fck = {
 646         .name           = "omap_96m_alwon_fck",
 647         .ops            = &clkops_null,
 648         .parent         = &dpll4_m2x2_ck,
 649         .init           = &omap2_init_clksel_parent,
 650         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 651         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 652         .clksel         = omap_96m_alwon_fck_clksel,
 653         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 654         .recalc         = &omap2_clksel_recalc,
 655 };
 656
 657 static struct clk omap_96m_fck = {
 658         .name           = "omap_96m_fck",
 659         .ops            = &clkops_null,
 660         .parent         = &omap_96m_alwon_fck,
 661         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 662         .recalc         = &followparent_recalc,
 663 };
 664
 665 static const struct clksel cm_96m_fck_clksel[] = {
 666         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 667         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 668         { .parent = NULL }
 669 };
 670
 671 static struct clk cm_96m_fck = {
 672         .name           = "cm_96m_fck",
 673         .ops            = &clkops_null,
 674         .parent         = &dpll4_m2x2_ck,
 675         .init           = &omap2_init_clksel_parent,
 676         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 677         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 678         .clksel         = cm_96m_fck_clksel,
 679         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 680         .recalc         = &omap2_clksel_recalc,
 681 };
 682
 683 /* This virtual clock is the source for dpll4_m3x2_ck */
 684 static struct clk dpll4_m3_ck = {
 685         .name           = "dpll4_m3_ck",
 686         .ops            = &clkops_null,
 687         .parent         = &dpll4_ck,
 688         .init           = &omap2_init_clksel_parent,
 689         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 690         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 691         .clksel         = div16_dpll4_clksel,
 692         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 693         .recalc         = &omap2_clksel_recalc,
 694 };
 695
 696 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 697 static struct clk dpll4_m3x2_ck = {
 698         .name           = "dpll4_m3x2_ck",
 699         .ops            = &clkops_omap2_dflt_wait,
 700         .parent         = &dpll4_m3_ck,
 701         .init           = &omap2_init_clksel_parent,
 702         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 703         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 704         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 705         .recalc         = &omap3_clkoutx2_recalc,
 706 };
 707
 708 static const struct clksel virt_omap_54m_fck_clksel[] = {
 709         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 710         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 711         { .parent = NULL }
 712 };
 713
 714 static struct clk virt_omap_54m_fck = {
 715         .name           = "virt_omap_54m_fck",
 716         .ops            = &clkops_null,
 717         .parent         = &dpll4_m3x2_ck,
 718         .init           = &omap2_init_clksel_parent,
 719         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 720         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 721         .clksel         = virt_omap_54m_fck_clksel,
 722         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 723         .recalc         = &omap2_clksel_recalc,
 724 };
 725
 726 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 727         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 728         { .div = 0 }
 729 };
 730
 731 static const struct clksel_rate omap_54m_alt_rates[] = {
 732         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 733         { .div = 0 }
 734 };
 735
 736 static const struct clksel omap_54m_clksel[] = {
 737         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 738         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 739         { .parent = NULL }
 740 };
 741
 742 static struct clk omap_54m_fck = {
 743         .name           = "omap_54m_fck",
 744         .ops            = &clkops_null,
 745         .init           = &omap2_init_clksel_parent,
 746         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 747         .clksel_mask    = OMAP3430_SOURCE_54M,
 748         .clksel         = omap_54m_clksel,
 749         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 750         .recalc         = &omap2_clksel_recalc,
 751 };
 752
 753 static const struct clksel_rate omap_48m_96md2_rates[] = {
 754         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 755         { .div = 0 }
 756 };
 757
 758 static const struct clksel_rate omap_48m_alt_rates[] = {
 759         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 760         { .div = 0 }
 761 };
 762
 763 static const struct clksel omap_48m_clksel[] = {
 764         { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
 765         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 766         { .parent = NULL }
 767 };
 768
 769 static struct clk omap_48m_fck = {
 770         .name           = "omap_48m_fck",
 771         .ops            = &clkops_null,
 772         .init           = &omap2_init_clksel_parent,
 773         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 774         .clksel_mask    = OMAP3430_SOURCE_48M,
 775         .clksel         = omap_48m_clksel,
 776         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 777         .recalc         = &omap2_clksel_recalc,
 778 };
 779
 780 static struct clk omap_12m_fck = {
 781         .name           = "omap_12m_fck",
 782         .ops            = &clkops_null,
 783         .parent         = &omap_48m_fck,
 784         .fixed_div      = 4,
 785         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 786         .recalc         = &omap2_fixed_divisor_recalc,
 787 };
 788
 789 /* This virstual clock is the source for dpll4_m4x2_ck */
 790 static struct clk dpll4_m4_ck = {
 791         .name           = "dpll4_m4_ck",
 792         .ops            = &clkops_null,
 793         .parent         = &dpll4_ck,
 794         .init           = &omap2_init_clksel_parent,
 795         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 796         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 797         .clksel         = div16_dpll4_clksel,
 798         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 799         .recalc         = &omap2_clksel_recalc,
 800 };
 801
 802 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 803 static struct clk dpll4_m4x2_ck = {
 804         .name           = "dpll4_m4x2_ck",
 805         .ops            = &clkops_omap2_dflt_wait,
 806         .parent         = &dpll4_m4_ck,
 807         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 808         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 809         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 810         .recalc         = &omap3_clkoutx2_recalc,
 811 };
 812
 813 /* This virtual clock is the source for dpll4_m5x2_ck */
 814 static struct clk dpll4_m5_ck = {
 815         .name           = "dpll4_m5_ck",
 816         .ops            = &clkops_null,
 817         .parent         = &dpll4_ck,
 818         .init           = &omap2_init_clksel_parent,
 819         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 820         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 821         .clksel         = div16_dpll4_clksel,
 822         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 823         .recalc         = &omap2_clksel_recalc,
 824 };
 825
 826 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 827 static struct clk dpll4_m5x2_ck = {
 828         .name           = "dpll4_m5x2_ck",
 829         .ops            = &clkops_omap2_dflt_wait,
 830         .parent         = &dpll4_m5_ck,
 831         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 832         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 833         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 834         .recalc         = &omap3_clkoutx2_recalc,
 835 };
 836
 837 /* This virtual clock is the source for dpll4_m6x2_ck */
 838 static struct clk dpll4_m6_ck = {
 839         .name           = "dpll4_m6_ck",
 840         .ops            = &clkops_null,
 841         .parent         = &dpll4_ck,
 842         .init           = &omap2_init_clksel_parent,
 843         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 844         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 845         .clksel         = div16_dpll4_clksel,
 846         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 847         .recalc         = &omap2_clksel_recalc,
 848 };
 849
 850 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 851 static struct clk dpll4_m6x2_ck = {
 852         .name           = "dpll4_m6x2_ck",
 853         .ops            = &clkops_omap2_dflt_wait,
 854         .parent         = &dpll4_m6_ck,
 855         .init           = &omap2_init_clksel_parent,
 856         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 857         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 858         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 859         .recalc         = &omap3_clkoutx2_recalc,
 860 };
 861
 862 static struct clk emu_per_alwon_ck = {
 863         .name           = "emu_per_alwon_ck",
 864         .ops            = &clkops_null,
 865         .parent         = &dpll4_m6x2_ck,
 866         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 867         .recalc         = &followparent_recalc,
 868 };
 869
 870 /* DPLL5 */
 871 /* Supplies 120MHz clock, USIM source clock */
 872 /* Type: DPLL */
 873 /* 3430ES2 only */
 874 static struct dpll_data dpll5_dd = {
 875         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 876         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 877         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 878         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 879         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 880         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 881         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 882         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 883         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 884         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 885         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 886         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 887         .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
 888         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 889         .max_divider    = OMAP3_MAX_DPLL_DIV,
 890         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 891 };
 892
 893 static struct clk dpll5_ck = {
 894         .name           = "dpll5_ck",
 895         .ops            = &clkops_noncore_dpll_ops,
 896         .parent         = &sys_ck,
 897         .dpll_data      = &dpll5_dd,
 898         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 899         .round_rate     = &omap2_dpll_round_rate,
 900         .recalc         = &omap3_dpll_recalc,
 901 };
 902
 903 static const struct clksel div16_dpll5_clksel[] = {
 904         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 905         { .parent = NULL }
 906 };
 907
 908 static struct clk dpll5_m2_ck = {
 909         .name           = "dpll5_m2_ck",
 910         .ops            = &clkops_null,
 911         .parent         = &dpll5_ck,
 912         .init           = &omap2_init_clksel_parent,
 913         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 914         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 915         .clksel         = div16_dpll5_clksel,
 916         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 917         .recalc         = &omap2_clksel_recalc,
 918 };
 919
 920 static const struct clksel omap_120m_fck_clksel[] = {
 921         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 922         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
 923         { .parent = NULL }
 924 };
 925
 926 static struct clk omap_120m_fck = {
 927         .name           = "omap_120m_fck",
 928         .ops            = &clkops_null,
 929         .parent         = &dpll5_m2_ck,
 930         .init           = &omap2_init_clksel_parent,
 931         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 932         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 933         .clksel         = omap_120m_fck_clksel,
 934         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 935         .recalc         = &omap2_clksel_recalc,
 936 };
 937
 938 /* CM EXTERNAL CLOCK OUTPUTS */
 939
 940 static const struct clksel_rate clkout2_src_core_rates[] = {
 941         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 942         { .div = 0 }
 943 };
 944
 945 static const struct clksel_rate clkout2_src_sys_rates[] = {
 946         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 947         { .div = 0 }
 948 };
 949
 950 static const struct clksel_rate clkout2_src_96m_rates[] = {
 951         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 952         { .div = 0 }
 953 };
 954
 955 static const struct clksel_rate clkout2_src_54m_rates[] = {
 956         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 957         { .div = 0 }
 958 };
 959
 960 static const struct clksel clkout2_src_clksel[] = {
 961         { .parent = &core_ck,             .rates = clkout2_src_core_rates },
 962         { .parent = &sys_ck,              .rates = clkout2_src_sys_rates },
 963         { .parent = &omap_96m_alwon_fck,  .rates = clkout2_src_96m_rates },
 964         { .parent = &omap_54m_fck,        .rates = clkout2_src_54m_rates },
 965         { .parent = NULL }
 966 };
 967
 968 static struct clk clkout2_src_ck = {
 969         .name           = "clkout2_src_ck",
 970         .ops            = &clkops_omap2_dflt_wait,
 971         .init           = &omap2_init_clksel_parent,
 972         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
 973         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 974         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 975         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 976         .clksel         = clkout2_src_clksel,
 977         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 978         .recalc         = &omap2_clksel_recalc,
 979 };
 980
 981 static const struct clksel_rate sys_clkout2_rates[] = {
 982         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 983         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 984         { .div = 4, .val = 2, .flags = RATE_IN_343X },
 985         { .div = 8, .val = 3, .flags = RATE_IN_343X },
 986         { .div = 16, .val = 4, .flags = RATE_IN_343X },
 987         { .div = 0 },
 988 };
 989
 990 static const struct clksel sys_clkout2_clksel[] = {
 991         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
 992         { .parent = NULL },
 993 };
 994
 995 static struct clk sys_clkout2 = {
 996         .name           = "sys_clkout2",
 997         .ops            = &clkops_null,
 998         .init           = &omap2_init_clksel_parent,
 999         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
1000         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1001         .clksel         = sys_clkout2_clksel,
1002         .flags          = CLOCK_IN_OMAP343X,
1003         .recalc         = &omap2_clksel_recalc,
1004 };
1005
1006 /* CM OUTPUT CLOCKS */
1007
1008 static struct clk corex2_fck = {
1009         .name           = "corex2_fck",
1010         .ops            = &clkops_null,
1011         .parent         = &dpll3_m2x2_ck,
1012         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1013         .recalc         = &followparent_recalc,
1014 };
1015
1016 /* DPLL power domain clock controls */
1017
1018 static const struct clksel div2_core_clksel[] = {
1019         { .parent = &core_ck, .rates = div2_rates },
1020         { .parent = NULL }
1021 };
1022
1023 /*
1024  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1025  * may be inconsistent here?
1026  */
1027 static struct clk dpll1_fck = {
1028         .name           = "dpll1_fck",
1029         .ops            = &clkops_null,
1030         .parent         = &core_ck,
1031         .init           = &omap2_init_clksel_parent,
1032         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1033         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1034         .clksel         = div2_core_clksel,
1035         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1036         .recalc         = &omap2_clksel_recalc,
1037 };
1038
1039 /*
1040  * MPU clksel:
1041  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1042  * derives from the high-frequency bypass clock originating from DPLL3,
1043  * called 'dpll1_fck'
1044  */
1045 static const struct clksel mpu_clksel[] = {
1046         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1047         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1048         { .parent = NULL }
1049 };
1050
1051 static struct clk mpu_ck = {
1052         .name           = "mpu_ck",
1053         .ops            = &clkops_null,
1054         .parent         = &dpll1_x2m2_ck,
1055         .init           = &omap2_init_clksel_parent,
1056         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1057         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1058         .clksel         = mpu_clksel,
1059         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1060         .clkdm_name     = "mpu_clkdm",
1061         .recalc         = &omap2_clksel_recalc,
1062 };
1063
1064 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1065 static const struct clksel_rate arm_fck_rates[] = {
1066         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1067         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1068         { .div = 0 },
1069 };
1070
1071 static const struct clksel arm_fck_clksel[] = {
1072         { .parent = &mpu_ck, .rates = arm_fck_rates },
1073         { .parent = NULL }
1074 };
1075
1076 static struct clk arm_fck = {
1077         .name           = "arm_fck",
1078         .ops            = &clkops_null,
1079         .parent         = &mpu_ck,
1080         .init           = &omap2_init_clksel_parent,
1081         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1082         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1083         .clksel         = arm_fck_clksel,
1084         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1085         .recalc         = &omap2_clksel_recalc,
1086 };
1087
1088 /* XXX What about neon_clkdm ? */
1089
1090 /*
1091  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1092  * although it is referenced - so this is a guess
1093  */
1094 static struct clk emu_mpu_alwon_ck = {
1095         .name           = "emu_mpu_alwon_ck",
1096         .ops            = &clkops_null,
1097         .parent         = &mpu_ck,
1098         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1099         .recalc         = &followparent_recalc,
1100 };
1101
1102 static struct clk dpll2_fck = {
1103         .name           = "dpll2_fck",
1104         .ops            = &clkops_null,
1105         .parent         = &core_ck,
1106         .init           = &omap2_init_clksel_parent,
1107         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1108         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1109         .clksel         = div2_core_clksel,
1110         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1111         .recalc         = &omap2_clksel_recalc,
1112 };
1113
1114 /*
1115  * IVA2 clksel:
1116  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1117  * derives from the high-frequency bypass clock originating from DPLL3,
1118  * called 'dpll2_fck'
1119  */
1120
1121 static const struct clksel iva2_clksel[] = {
1122         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1123         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1124         { .parent = NULL }
1125 };
1126
1127 static struct clk iva2_ck = {
1128         .name           = "iva2_ck",
1129         .ops            = &clkops_omap2_dflt_wait,
1130         .parent         = &dpll2_m2_ck,
1131         .init           = &omap2_init_clksel_parent,
1132         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1133         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1134         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1135                                           OMAP3430_CM_IDLEST_PLL),
1136         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1137         .clksel         = iva2_clksel,
1138         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1139         .clkdm_name     = "iva2_clkdm",
1140         .recalc         = &omap2_clksel_recalc,
1141 };
1142
1143 /* Common interface clocks */
1144
1145 static struct clk l3_ick = {
1146         .name           = "l3_ick",
1147         .ops            = &clkops_null,
1148         .parent         = &core_ck,
1149         .init           = &omap2_init_clksel_parent,
1150         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1151         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1152         .clksel         = div2_core_clksel,
1153         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1154         .clkdm_name     = "core_l3_clkdm",
1155         .recalc         = &omap2_clksel_recalc,
1156 };
1157
1158 static const struct clksel div2_l3_clksel[] = {
1159         { .parent = &l3_ick, .rates = div2_rates },
1160         { .parent = NULL }
1161 };
1162
1163 static struct clk l4_ick = {
1164         .name           = "l4_ick",
1165         .ops            = &clkops_null,
1166         .parent         = &l3_ick,
1167         .init           = &omap2_init_clksel_parent,
1168         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1169         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1170         .clksel         = div2_l3_clksel,
1171         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1172         .clkdm_name     = "core_l4_clkdm",
1173         .recalc         = &omap2_clksel_recalc,
1174
1175 };
1176
1177 static const struct clksel div2_l4_clksel[] = {
1178         { .parent = &l4_ick, .rates = div2_rates },
1179         { .parent = NULL }
1180 };
1181
1182 static struct clk rm_ick = {
1183         .name           = "rm_ick",
1184         .ops            = &clkops_null,
1185         .parent         = &l4_ick,
1186         .init           = &omap2_init_clksel_parent,
1187         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1188         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1189         .clksel         = div2_l4_clksel,
1190         .flags          = CLOCK_IN_OMAP343X,
1191         .recalc         = &omap2_clksel_recalc,
1192 };
1193
1194 /* GFX power domain */
1195
1196 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1197
1198 static const struct clksel gfx_l3_clksel[] = {
1199         { .parent = &l3_ick, .rates = gfx_l3_rates },
1200         { .parent = NULL }
1201 };
1202
1203 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1204 static struct clk gfx_l3_ck = {
1205         .name           = "gfx_l3_ck",
1206         .ops            = &clkops_omap2_dflt_wait,
1207         .parent         = &l3_ick,
1208         .init           = &omap2_init_clksel_parent,
1209         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1210         .enable_bit     = OMAP_EN_GFX_SHIFT,
1211         .flags          = CLOCK_IN_OMAP3430ES1,
1212         .recalc         = &followparent_recalc,
1213 };
1214
1215 static struct clk gfx_l3_fck = {
1216         .name           = "gfx_l3_fck",
1217         .ops            = &clkops_null,
1218         .parent         = &gfx_l3_ck,
1219         .init           = &omap2_init_clksel_parent,
1220         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1221         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1222         .clksel         = gfx_l3_clksel,
1223         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
1224         .clkdm_name     = "gfx_3430es1_clkdm",
1225         .recalc         = &omap2_clksel_recalc,
1226 };
1227
1228 static struct clk gfx_l3_ick = {
1229         .name           = "gfx_l3_ick",
1230         .ops            = &clkops_null,
1231         .parent         = &gfx_l3_ck,
1232         .flags          = CLOCK_IN_OMAP3430ES1,
1233         .clkdm_name     = "gfx_3430es1_clkdm",
1234         .recalc         = &followparent_recalc,
1235 };
1236
1237 static struct clk gfx_cg1_ck = {
1238         .name           = "gfx_cg1_ck",
1239         .ops            = &clkops_omap2_dflt_wait,
1240         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1241         .init           = &omap2_init_clk_clkdm,
1242         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1243         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1244         .flags          = CLOCK_IN_OMAP3430ES1,
1245         .clkdm_name     = "gfx_3430es1_clkdm",
1246         .recalc         = &followparent_recalc,
1247 };
1248
1249 static struct clk gfx_cg2_ck = {
1250         .name           = "gfx_cg2_ck",
1251         .ops            = &clkops_omap2_dflt_wait,
1252         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1253         .init           = &omap2_init_clk_clkdm,
1254         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1255         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1256         .flags          = CLOCK_IN_OMAP3430ES1,
1257         .clkdm_name     = "gfx_3430es1_clkdm",
1258         .recalc         = &followparent_recalc,
1259 };
1260
1261 /* SGX power domain - 3430ES2 only */
1262
1263 static const struct clksel_rate sgx_core_rates[] = {
1264         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1265         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1266         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1267         { .div = 0 },
1268 };
1269
1270 static const struct clksel_rate sgx_96m_rates[] = {
1271         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1272         { .div = 0 },
1273 };
1274
1275 static const struct clksel sgx_clksel[] = {
1276         { .parent = &core_ck,    .rates = sgx_core_rates },
1277         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1278         { .parent = NULL },
1279 };
1280
1281 static struct clk sgx_fck = {
1282         .name           = "sgx_fck",
1283         .ops            = &clkops_omap2_dflt_wait,
1284         .init           = &omap2_init_clksel_parent,
1285         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1286         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1287         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1288         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1289         .clksel         = sgx_clksel,
1290         .flags          = CLOCK_IN_OMAP3430ES2,
1291         .clkdm_name     = "sgx_clkdm",
1292         .recalc         = &omap2_clksel_recalc,
1293 };
1294
1295 static struct clk sgx_ick = {
1296         .name           = "sgx_ick",
1297         .ops            = &clkops_omap2_dflt_wait,
1298         .parent         = &l3_ick,
1299         .init           = &omap2_init_clk_clkdm,
1300         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1301         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1302         .flags          = CLOCK_IN_OMAP3430ES2,
1303         .clkdm_name     = "sgx_clkdm",
1304         .recalc         = &followparent_recalc,
1305 };
1306
1307 /* CORE power domain */
1308
1309 static struct clk d2d_26m_fck = {
1310         .name           = "d2d_26m_fck",
1311         .ops            = &clkops_omap2_dflt_wait,
1312         .parent         = &sys_ck,
1313         .init           = &omap2_init_clk_clkdm,
1314         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1315         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1316         .flags          = CLOCK_IN_OMAP3430ES1,
1317         .clkdm_name     = "d2d_clkdm",
1318         .recalc         = &followparent_recalc,
1319 };
1320
1321 static const struct clksel omap343x_gpt_clksel[] = {
1322         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1323         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1324         { .parent = NULL}
1325 };
1326
1327 static struct clk gpt10_fck = {
1328         .name           = "gpt10_fck",
1329         .ops            = &clkops_omap2_dflt_wait,
1330         .parent         = &sys_ck,
1331         .init           = &omap2_init_clksel_parent,
1332         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1333         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1334         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1335         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1336         .clksel         = omap343x_gpt_clksel,
1337         .flags          = CLOCK_IN_OMAP343X,
1338         .clkdm_name     = "core_l4_clkdm",
1339         .recalc         = &omap2_clksel_recalc,
1340 };
1341
1342 static struct clk gpt11_fck = {
1343         .name           = "gpt11_fck",
1344         .ops            = &clkops_omap2_dflt_wait,
1345         .parent         = &sys_ck,
1346         .init           = &omap2_init_clksel_parent,
1347         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1348         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1349         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1350         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1351         .clksel         = omap343x_gpt_clksel,
1352         .flags          = CLOCK_IN_OMAP343X,
1353         .clkdm_name     = "core_l4_clkdm",
1354         .recalc         = &omap2_clksel_recalc,
1355 };
1356
1357 static struct clk cpefuse_fck = {
1358         .name           = "cpefuse_fck",
1359         .ops            = &clkops_omap2_dflt_wait,
1360         .parent         = &sys_ck,
1361         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1362         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1363         .flags          = CLOCK_IN_OMAP3430ES2,
1364         .recalc         = &followparent_recalc,
1365 };
1366
1367 static struct clk ts_fck = {
1368         .name           = "ts_fck",
1369         .ops            = &clkops_omap2_dflt_wait,
1370         .parent         = &omap_32k_fck,
1371         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1372         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1373         .flags          = CLOCK_IN_OMAP3430ES2,
1374         .recalc         = &followparent_recalc,
1375 };
1376
1377 static struct clk usbtll_fck = {
1378         .name           = "usbtll_fck",
1379         .ops            = &clkops_omap2_dflt_wait,
1380         .parent         = &omap_120m_fck,
1381         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1382         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1383         .flags          = CLOCK_IN_OMAP3430ES2,
1384         .recalc         = &followparent_recalc,
1385 };
1386
1387 /* CORE 96M FCLK-derived clocks */
1388
1389 static struct clk core_96m_fck = {
1390         .name           = "core_96m_fck",
1391         .ops            = &clkops_null,
1392         .parent         = &omap_96m_fck,
1393         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1394         .clkdm_name     = "core_l4_clkdm",
1395         .recalc         = &followparent_recalc,
1396 };
1397
1398 static struct clk mmchs3_fck = {
1399         .name           = "mmchs_fck",
1400         .ops            = &clkops_omap2_dflt_wait,
1401         .id             = 2,
1402         .parent         = &core_96m_fck,
1403         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1404         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1405         .flags          = CLOCK_IN_OMAP3430ES2,
1406         .clkdm_name     = "core_l4_clkdm",
1407         .recalc         = &followparent_recalc,
1408 };
1409
1410 static struct clk mmchs2_fck = {
1411         .name           = "mmchs_fck",
1412         .ops            = &clkops_omap2_dflt_wait,
1413         .id             = 1,
1414         .parent         = &core_96m_fck,
1415         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1416         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1417         .flags          = CLOCK_IN_OMAP343X,
1418         .clkdm_name     = "core_l4_clkdm",
1419         .recalc         = &followparent_recalc,
1420 };
1421
1422 static struct clk mspro_fck = {
1423         .name           = "mspro_fck",
1424         .ops            = &clkops_omap2_dflt_wait,
1425         .parent         = &core_96m_fck,
1426         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1427         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1428         .flags          = CLOCK_IN_OMAP343X,
1429         .clkdm_name     = "core_l4_clkdm",
1430         .recalc         = &followparent_recalc,
1431 };
1432
1433 static struct clk mmchs1_fck = {
1434         .name           = "mmchs_fck",
1435         .ops            = &clkops_omap2_dflt_wait,
1436         .parent         = &core_96m_fck,
1437         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1438         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1439         .flags          = CLOCK_IN_OMAP343X,
1440         .clkdm_name     = "core_l4_clkdm",
1441         .recalc         = &followparent_recalc,
1442 };
1443
1444 static struct clk i2c3_fck = {
1445         .name           = "i2c_fck",
1446         .ops            = &clkops_omap2_dflt_wait,
1447         .id             = 3,
1448         .parent         = &core_96m_fck,
1449         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1450         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1451         .flags          = CLOCK_IN_OMAP343X,
1452         .clkdm_name     = "core_l4_clkdm",
1453         .recalc         = &followparent_recalc,
1454 };
1455
1456 static struct clk i2c2_fck = {
1457         .name           = "i2c_fck",
1458         .ops            = &clkops_omap2_dflt_wait,
1459         .id             = 2,
1460         .parent         = &core_96m_fck,
1461         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1462         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1463         .flags          = CLOCK_IN_OMAP343X,
1464         .clkdm_name     = "core_l4_clkdm",
1465         .recalc         = &followparent_recalc,
1466 };
1467
1468 static struct clk i2c1_fck = {
1469         .name           = "i2c_fck",
1470         .ops            = &clkops_omap2_dflt_wait,
1471         .id             = 1,
1472         .parent         = &core_96m_fck,
1473         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1474         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1475         .flags          = CLOCK_IN_OMAP343X,
1476         .clkdm_name     = "core_l4_clkdm",
1477         .recalc         = &followparent_recalc,
1478 };
1479
1480 /*
1481  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1482  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1483  */
1484 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1485         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1486         { .div = 0 }
1487 };
1488
1489 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1490         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1491         { .div = 0 }
1492 };
1493
1494 static const struct clksel mcbsp_15_clksel[] = {
1495         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1496         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1497         { .parent = NULL }
1498 };
1499
1500 static struct clk mcbsp5_fck = {
1501         .name           = "mcbsp_fck",
1502         .ops            = &clkops_omap2_dflt_wait,
1503         .id             = 5,
1504         .init           = &omap2_init_clksel_parent,
1505         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1506         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1507         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1508         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1509         .clksel         = mcbsp_15_clksel,
1510         .flags          = CLOCK_IN_OMAP343X,
1511         .clkdm_name     = "core_l4_clkdm",
1512         .recalc         = &omap2_clksel_recalc,
1513 };
1514
1515 static struct clk mcbsp1_fck = {
1516         .name           = "mcbsp_fck",
1517         .ops            = &clkops_omap2_dflt_wait,
1518         .id             = 1,
1519         .init           = &omap2_init_clksel_parent,
1520         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1521         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1522         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1523         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1524         .clksel         = mcbsp_15_clksel,
1525         .flags          = CLOCK_IN_OMAP343X,
1526         .clkdm_name     = "core_l4_clkdm",
1527         .recalc         = &omap2_clksel_recalc,
1528 };
1529
1530 /* CORE_48M_FCK-derived clocks */
1531
1532 static struct clk core_48m_fck = {
1533         .name           = "core_48m_fck",
1534         .ops            = &clkops_null,
1535         .parent         = &omap_48m_fck,
1536         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1537         .clkdm_name     = "core_l4_clkdm",
1538         .recalc         = &followparent_recalc,
1539 };
1540
1541 static struct clk mcspi4_fck = {
1542         .name           = "mcspi_fck",
1543         .ops            = &clkops_omap2_dflt_wait,
1544         .id             = 4,
1545         .parent         = &core_48m_fck,
1546         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1547         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1548         .flags          = CLOCK_IN_OMAP343X,
1549         .recalc         = &followparent_recalc,
1550 };
1551
1552 static struct clk mcspi3_fck = {
1553         .name           = "mcspi_fck",
1554         .ops            = &clkops_omap2_dflt_wait,
1555         .id             = 3,
1556         .parent         = &core_48m_fck,
1557         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1558         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1559         .flags          = CLOCK_IN_OMAP343X,
1560         .recalc         = &followparent_recalc,
1561 };
1562
1563 static struct clk mcspi2_fck = {
1564         .name           = "mcspi_fck",
1565         .ops            = &clkops_omap2_dflt_wait,
1566         .id             = 2,
1567         .parent         = &core_48m_fck,
1568         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1569         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1570         .flags          = CLOCK_IN_OMAP343X,
1571         .recalc         = &followparent_recalc,
1572 };
1573
1574 static struct clk mcspi1_fck = {
1575         .name           = "mcspi_fck",
1576         .ops            = &clkops_omap2_dflt_wait,
1577         .id             = 1,
1578         .parent         = &core_48m_fck,
1579         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1580         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1581         .flags          = CLOCK_IN_OMAP343X,
1582         .recalc         = &followparent_recalc,
1583 };
1584
1585 static struct clk uart2_fck = {
1586         .name           = "uart2_fck",
1587         .ops            = &clkops_omap2_dflt_wait,
1588         .parent         = &core_48m_fck,
1589         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1590         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1591         .flags          = CLOCK_IN_OMAP343X,
1592         .recalc         = &followparent_recalc,
1593 };
1594
1595 static struct clk uart1_fck = {
1596         .name           = "uart1_fck",
1597         .ops            = &clkops_omap2_dflt_wait,
1598         .parent         = &core_48m_fck,
1599         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1600         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1601         .flags          = CLOCK_IN_OMAP343X,
1602         .recalc         = &followparent_recalc,
1603 };
1604
1605 static struct clk fshostusb_fck = {
1606         .name           = "fshostusb_fck",
1607         .ops            = &clkops_omap2_dflt_wait,
1608         .parent         = &core_48m_fck,
1609         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1610         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1611         .flags          = CLOCK_IN_OMAP3430ES1,
1612         .recalc         = &followparent_recalc,
1613 };
1614
1615 /* CORE_12M_FCK based clocks */
1616
1617 static struct clk core_12m_fck = {
1618         .name           = "core_12m_fck",
1619         .ops            = &clkops_null,
1620         .parent         = &omap_12m_fck,
1621         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1622         .clkdm_name     = "core_l4_clkdm",
1623         .recalc         = &followparent_recalc,
1624 };
1625
1626 static struct clk hdq_fck = {
1627         .name           = "hdq_fck",
1628         .ops            = &clkops_omap2_dflt_wait,
1629         .parent         = &core_12m_fck,
1630         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1631         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1632         .flags          = CLOCK_IN_OMAP343X,
1633         .recalc         = &followparent_recalc,
1634 };
1635
1636 /* DPLL3-derived clock */
1637
1638 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1639         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1640         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1641         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1642         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1643         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1644         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1645         { .div = 0 }
1646 };
1647
1648 static const struct clksel ssi_ssr_clksel[] = {
1649         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1650         { .parent = NULL }
1651 };
1652
1653 static struct clk ssi_ssr_fck = {
1654         .name           = "ssi_ssr_fck",
1655         .ops            = &clkops_omap2_dflt,
1656         .init           = &omap2_init_clksel_parent,
1657         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1658         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1659         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1660         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1661         .clksel         = ssi_ssr_clksel,
1662         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1663         .clkdm_name     = "core_l4_clkdm",
1664         .recalc         = &omap2_clksel_recalc,
1665 };
1666
1667 static struct clk ssi_sst_fck = {
1668         .name           = "ssi_sst_fck",
1669         .ops            = &clkops_null,
1670         .parent         = &ssi_ssr_fck,
1671         .fixed_div      = 2,
1672         .flags          = CLOCK_IN_OMAP343X,
1673         .recalc         = &omap2_fixed_divisor_recalc,
1674 };
1675
1676
1677
1678 /* CORE_L3_ICK based clocks */
1679
1680 /*
1681  * XXX must add clk_enable/clk_disable for these if standard code won't
1682  * handle it
1683  */
1684 static struct clk core_l3_ick = {
1685         .name           = "core_l3_ick",
1686         .ops            = &clkops_null,
1687         .parent         = &l3_ick,
1688         .init           = &omap2_init_clk_clkdm,
1689         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1690         .clkdm_name     = "core_l3_clkdm",
1691         .recalc         = &followparent_recalc,
1692 };
1693
1694 static struct clk hsotgusb_ick = {
1695         .name           = "hsotgusb_ick",
1696         .ops            = &clkops_omap2_dflt_wait,
1697         .parent         = &core_l3_ick,
1698         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1699         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1700         .flags          = CLOCK_IN_OMAP343X,
1701         .clkdm_name     = "core_l3_clkdm",
1702         .recalc         = &followparent_recalc,
1703 };
1704
1705 static struct clk sdrc_ick = {
1706         .name           = "sdrc_ick",
1707         .ops            = &clkops_omap2_dflt_wait,
1708         .parent         = &core_l3_ick,
1709         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1710         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1711         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1712         .clkdm_name     = "core_l3_clkdm",
1713         .recalc         = &followparent_recalc,
1714 };
1715
1716 static struct clk gpmc_fck = {
1717         .name           = "gpmc_fck",
1718         .ops            = &clkops_null,
1719         .parent         = &core_l3_ick,
1720         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, /* huh? */
1721         .clkdm_name     = "core_l3_clkdm",
1722         .recalc         = &followparent_recalc,
1723 };
1724
1725 /* SECURITY_L3_ICK based clocks */
1726
1727 static struct clk security_l3_ick = {
1728         .name           = "security_l3_ick",
1729         .ops            = &clkops_null,
1730         .parent         = &l3_ick,
1731         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1732         .recalc         = &followparent_recalc,
1733 };
1734
1735 static struct clk pka_ick = {
1736         .name           = "pka_ick",
1737         .ops            = &clkops_omap2_dflt_wait,
1738         .parent         = &security_l3_ick,
1739         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1740         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1741         .flags          = CLOCK_IN_OMAP343X,
1742         .recalc         = &followparent_recalc,
1743 };
1744
1745 /* CORE_L4_ICK based clocks */
1746
1747 static struct clk core_l4_ick = {
1748         .name           = "core_l4_ick",
1749         .ops            = &clkops_null,
1750         .parent         = &l4_ick,
1751         .init           = &omap2_init_clk_clkdm,
1752         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1753         .clkdm_name     = "core_l4_clkdm",
1754         .recalc         = &followparent_recalc,
1755 };
1756
1757 static struct clk usbtll_ick = {
1758         .name           = "usbtll_ick",
1759         .ops            = &clkops_omap2_dflt_wait,
1760         .parent         = &core_l4_ick,
1761         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1762         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1763         .flags          = CLOCK_IN_OMAP3430ES2,
1764         .clkdm_name     = "core_l4_clkdm",
1765         .recalc         = &followparent_recalc,
1766 };
1767
1768 static struct clk mmchs3_ick = {
1769         .name           = "mmchs_ick",
1770         .ops            = &clkops_omap2_dflt_wait,
1771         .id             = 2,
1772         .parent         = &core_l4_ick,
1773         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1774         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1775         .flags          = CLOCK_IN_OMAP3430ES2,
1776         .clkdm_name     = "core_l4_clkdm",
1777         .recalc         = &followparent_recalc,
1778 };
1779
1780 /* Intersystem Communication Registers - chassis mode only */
1781 static struct clk icr_ick = {
1782         .name           = "icr_ick",
1783         .ops            = &clkops_omap2_dflt_wait,
1784         .parent         = &core_l4_ick,
1785         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1786         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1787         .flags          = CLOCK_IN_OMAP343X,
1788         .clkdm_name     = "core_l4_clkdm",
1789         .recalc         = &followparent_recalc,
1790 };
1791
1792 static struct clk aes2_ick = {
1793         .name           = "aes2_ick",
1794         .ops            = &clkops_omap2_dflt_wait,
1795         .parent         = &core_l4_ick,
1796         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1797         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1798         .flags          = CLOCK_IN_OMAP343X,
1799         .clkdm_name     = "core_l4_clkdm",
1800         .recalc         = &followparent_recalc,
1801 };
1802
1803 static struct clk sha12_ick = {
1804         .name           = "sha12_ick",
1805         .ops            = &clkops_omap2_dflt_wait,
1806         .parent         = &core_l4_ick,
1807         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1808         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1809         .flags          = CLOCK_IN_OMAP343X,
1810         .clkdm_name     = "core_l4_clkdm",
1811         .recalc         = &followparent_recalc,
1812 };
1813
1814 static struct clk des2_ick = {
1815         .name           = "des2_ick",
1816         .ops            = &clkops_omap2_dflt_wait,
1817         .parent         = &core_l4_ick,
1818         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1819         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1820         .flags          = CLOCK_IN_OMAP343X,
1821         .clkdm_name     = "core_l4_clkdm",
1822         .recalc         = &followparent_recalc,
1823 };
1824
1825 static struct clk mmchs2_ick = {
1826         .name           = "mmchs_ick",
1827         .ops            = &clkops_omap2_dflt_wait,
1828         .id             = 1,
1829         .parent         = &core_l4_ick,
1830         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1831         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1832         .flags          = CLOCK_IN_OMAP343X,
1833         .clkdm_name     = "core_l4_clkdm",
1834         .recalc         = &followparent_recalc,
1835 };
1836
1837 static struct clk mmchs1_ick = {
1838         .name           = "mmchs_ick",
1839         .ops            = &clkops_omap2_dflt_wait,
1840         .parent         = &core_l4_ick,
1841         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1842         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1843         .flags          = CLOCK_IN_OMAP343X,
1844         .clkdm_name     = "core_l4_clkdm",
1845         .recalc         = &followparent_recalc,
1846 };
1847
1848 static struct clk mspro_ick = {
1849         .name           = "mspro_ick",
1850         .ops            = &clkops_omap2_dflt_wait,
1851         .parent         = &core_l4_ick,
1852         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1853         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1854         .flags          = CLOCK_IN_OMAP343X,
1855         .clkdm_name     = "core_l4_clkdm",
1856         .recalc         = &followparent_recalc,
1857 };
1858
1859 static struct clk hdq_ick = {
1860         .name           = "hdq_ick",
1861         .ops            = &clkops_omap2_dflt_wait,
1862         .parent         = &core_l4_ick,
1863         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1864         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1865         .flags          = CLOCK_IN_OMAP343X,
1866         .clkdm_name     = "core_l4_clkdm",
1867         .recalc         = &followparent_recalc,
1868 };
1869
1870 static struct clk mcspi4_ick = {
1871         .name           = "mcspi_ick",
1872         .ops            = &clkops_omap2_dflt_wait,
1873         .id             = 4,
1874         .parent         = &core_l4_ick,
1875         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1876         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1877         .flags          = CLOCK_IN_OMAP343X,
1878         .clkdm_name     = "core_l4_clkdm",
1879         .recalc         = &followparent_recalc,
1880 };
1881
1882 static struct clk mcspi3_ick = {
1883         .name           = "mcspi_ick",
1884         .ops            = &clkops_omap2_dflt_wait,
1885         .id             = 3,
1886         .parent         = &core_l4_ick,
1887         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1888         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1889         .flags          = CLOCK_IN_OMAP343X,
1890         .clkdm_name     = "core_l4_clkdm",
1891         .recalc         = &followparent_recalc,
1892 };
1893
1894 static struct clk mcspi2_ick = {
1895         .name           = "mcspi_ick",
1896         .ops            = &clkops_omap2_dflt_wait,
1897         .id             = 2,
1898         .parent         = &core_l4_ick,
1899         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1900         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1901         .flags          = CLOCK_IN_OMAP343X,
1902         .clkdm_name     = "core_l4_clkdm",
1903         .recalc         = &followparent_recalc,
1904 };
1905
1906 static struct clk mcspi1_ick = {
1907         .name           = "mcspi_ick",
1908         .ops            = &clkops_omap2_dflt_wait,
1909         .id             = 1,
1910         .parent         = &core_l4_ick,
1911         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1912         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1913         .flags          = CLOCK_IN_OMAP343X,
1914         .clkdm_name     = "core_l4_clkdm",
1915         .recalc         = &followparent_recalc,
1916 };
1917
1918 static struct clk i2c3_ick = {
1919         .name           = "i2c_ick",
1920         .ops            = &clkops_omap2_dflt_wait,
1921         .id             = 3,
1922         .parent         = &core_l4_ick,
1923         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1924         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1925         .flags          = CLOCK_IN_OMAP343X,
1926         .clkdm_name     = "core_l4_clkdm",
1927         .recalc         = &followparent_recalc,
1928 };
1929
1930 static struct clk i2c2_ick = {
1931         .name           = "i2c_ick",
1932         .ops            = &clkops_omap2_dflt_wait,
1933         .id             = 2,
1934         .parent         = &core_l4_ick,
1935         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1936         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1937         .flags          = CLOCK_IN_OMAP343X,
1938         .clkdm_name     = "core_l4_clkdm",
1939         .recalc         = &followparent_recalc,
1940 };
1941
1942 static struct clk i2c1_ick = {
1943         .name           = "i2c_ick",
1944         .ops            = &clkops_omap2_dflt_wait,
1945         .id             = 1,
1946         .parent         = &core_l4_ick,
1947         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1948         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1949         .flags          = CLOCK_IN_OMAP343X,
1950         .clkdm_name     = "core_l4_clkdm",
1951         .recalc         = &followparent_recalc,
1952 };
1953
1954 static struct clk uart2_ick = {
1955         .name           = "uart2_ick",
1956         .ops            = &clkops_omap2_dflt_wait,
1957         .parent         = &core_l4_ick,
1958         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1959         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1960         .flags          = CLOCK_IN_OMAP343X,
1961         .clkdm_name     = "core_l4_clkdm",
1962         .recalc         = &followparent_recalc,
1963 };
1964
1965 static struct clk uart1_ick = {
1966         .name           = "uart1_ick",
1967         .ops            = &clkops_omap2_dflt_wait,
1968         .parent         = &core_l4_ick,
1969         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1970         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1971         .flags          = CLOCK_IN_OMAP343X,
1972         .clkdm_name     = "core_l4_clkdm",
1973         .recalc         = &followparent_recalc,
1974 };
1975
1976 static struct clk gpt11_ick = {
1977         .name           = "gpt11_ick",
1978         .ops            = &clkops_omap2_dflt_wait,
1979         .parent         = &core_l4_ick,
1980         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1981         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1982         .flags          = CLOCK_IN_OMAP343X,
1983         .clkdm_name     = "core_l4_clkdm",
1984         .recalc         = &followparent_recalc,
1985 };
1986
1987 static struct clk gpt10_ick = {
1988         .name           = "gpt10_ick",
1989         .ops            = &clkops_omap2_dflt_wait,
1990         .parent         = &core_l4_ick,
1991         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1992         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1993         .flags          = CLOCK_IN_OMAP343X,
1994         .clkdm_name     = "core_l4_clkdm",
1995         .recalc         = &followparent_recalc,
1996 };
1997
1998 static struct clk mcbsp5_ick = {
1999         .name           = "mcbsp_ick",
2000         .ops            = &clkops_omap2_dflt_wait,
2001         .id             = 5,
2002         .parent         = &core_l4_ick,
2003         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2004         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
2005         .flags          = CLOCK_IN_OMAP343X,
2006         .clkdm_name     = "core_l4_clkdm",
2007         .recalc         = &followparent_recalc,
2008 };
2009
2010 static struct clk mcbsp1_ick = {
2011         .name           = "mcbsp_ick",
2012         .ops            = &clkops_omap2_dflt_wait,
2013         .id             = 1,
2014         .parent         = &core_l4_ick,
2015         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2016         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2017         .flags          = CLOCK_IN_OMAP343X,
2018         .clkdm_name     = "core_l4_clkdm",
2019         .recalc         = &followparent_recalc,
2020 };
2021
2022 static struct clk fac_ick = {
2023         .name           = "fac_ick",
2024         .ops            = &clkops_omap2_dflt_wait,
2025         .parent         = &core_l4_ick,
2026         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2027         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
2028         .flags          = CLOCK_IN_OMAP3430ES1,
2029         .clkdm_name     = "core_l4_clkdm",
2030         .recalc         = &followparent_recalc,
2031 };
2032
2033 static struct clk mailboxes_ick = {
2034         .name           = "mailboxes_ick",
2035         .ops            = &clkops_omap2_dflt_wait,
2036         .parent         = &core_l4_ick,
2037         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2038         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2039         .flags          = CLOCK_IN_OMAP343X,
2040         .clkdm_name     = "core_l4_clkdm",
2041         .recalc         = &followparent_recalc,
2042 };
2043
2044 static struct clk omapctrl_ick = {
2045         .name           = "omapctrl_ick",
2046         .ops            = &clkops_omap2_dflt_wait,
2047         .parent         = &core_l4_ick,
2048         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2049         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2050         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
2051         .recalc         = &followparent_recalc,
2052 };
2053
2054 /* SSI_L4_ICK based clocks */
2055
2056 static struct clk ssi_l4_ick = {
2057         .name           = "ssi_l4_ick",
2058         .ops            = &clkops_null,
2059         .parent         = &l4_ick,
2060         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2061         .clkdm_name     = "core_l4_clkdm",
2062         .recalc         = &followparent_recalc,
2063 };
2064
2065 static struct clk ssi_ick = {
2066         .name           = "ssi_ick",
2067         .ops            = &clkops_omap2_dflt,
2068         .parent         = &ssi_l4_ick,
2069         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2070         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2071         .flags          = CLOCK_IN_OMAP343X,
2072         .clkdm_name     = "core_l4_clkdm",
2073         .recalc         = &followparent_recalc,
2074 };
2075
2076 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2077  * but l4_ick makes more sense to me */
2078
2079 static const struct clksel usb_l4_clksel[] = {
2080         { .parent = &l4_ick, .rates = div2_rates },
2081         { .parent = NULL },
2082 };
2083
2084 static struct clk usb_l4_ick = {
2085         .name           = "usb_l4_ick",
2086         .ops            = &clkops_omap2_dflt_wait,
2087         .parent         = &l4_ick,
2088         .init           = &omap2_init_clksel_parent,
2089         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2090         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2091         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2092         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2093         .clksel         = usb_l4_clksel,
2094         .flags          = CLOCK_IN_OMAP3430ES1,
2095         .recalc         = &omap2_clksel_recalc,
2096 };
2097
2098 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2099
2100 /* SECURITY_L4_ICK2 based clocks */
2101
2102 static struct clk security_l4_ick2 = {
2103         .name           = "security_l4_ick2",
2104         .ops            = &clkops_null,
2105         .parent         = &l4_ick,
2106         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2107         .recalc         = &followparent_recalc,
2108 };
2109
2110 static struct clk aes1_ick = {
2111         .name           = "aes1_ick",
2112         .ops            = &clkops_omap2_dflt_wait,
2113         .parent         = &security_l4_ick2,
2114         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2115         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2116         .flags          = CLOCK_IN_OMAP343X,
2117         .recalc         = &followparent_recalc,
2118 };
2119
2120 static struct clk rng_ick = {
2121         .name           = "rng_ick",
2122         .ops            = &clkops_omap2_dflt_wait,
2123         .parent         = &security_l4_ick2,
2124         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2125         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2126         .flags          = CLOCK_IN_OMAP343X,
2127         .recalc         = &followparent_recalc,
2128 };
2129
2130 static struct clk sha11_ick = {
2131         .name           = "sha11_ick",
2132         .ops            = &clkops_omap2_dflt_wait,
2133         .parent         = &security_l4_ick2,
2134         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2135         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2136         .flags          = CLOCK_IN_OMAP343X,
2137         .recalc         = &followparent_recalc,
2138 };
2139
2140 static struct clk des1_ick = {
2141         .name           = "des1_ick",
2142         .ops            = &clkops_omap2_dflt_wait,
2143         .parent         = &security_l4_ick2,
2144         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2145         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2146         .flags          = CLOCK_IN_OMAP343X,
2147         .recalc         = &followparent_recalc,
2148 };
2149
2150 /* DSS */
2151 static const struct clksel dss1_alwon_fck_clksel[] = {
2152         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2153         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2154         { .parent = NULL }
2155 };
2156
2157 static struct clk dss1_alwon_fck = {
2158         .name           = "dss1_alwon_fck",
2159         .ops            = &clkops_omap2_dflt,
2160         .parent         = &dpll4_m4x2_ck,
2161         .init           = &omap2_init_clksel_parent,
2162         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2163         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2164         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2165         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2166         .clksel         = dss1_alwon_fck_clksel,
2167         .flags          = CLOCK_IN_OMAP343X,
2168         .clkdm_name     = "dss_clkdm",
2169         .recalc         = &omap2_clksel_recalc,
2170 };
2171
2172 static struct clk dss_tv_fck = {
2173         .name           = "dss_tv_fck",
2174         .ops            = &clkops_omap2_dflt,
2175         .parent         = &omap_54m_fck,
2176         .init           = &omap2_init_clk_clkdm,
2177         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2178         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2179         .flags          = CLOCK_IN_OMAP343X,
2180         .clkdm_name     = "dss_clkdm",
2181         .recalc         = &followparent_recalc,
2182 };
2183
2184 static struct clk dss_96m_fck = {
2185         .name           = "dss_96m_fck",
2186         .ops            = &clkops_omap2_dflt,
2187         .parent         = &omap_96m_fck,
2188         .init           = &omap2_init_clk_clkdm,
2189         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2190         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2191         .flags          = CLOCK_IN_OMAP343X,
2192         .clkdm_name     = "dss_clkdm",
2193         .recalc         = &followparent_recalc,
2194 };
2195
2196 static struct clk dss2_alwon_fck = {
2197         .name           = "dss2_alwon_fck",
2198         .ops            = &clkops_omap2_dflt,
2199         .parent         = &sys_ck,
2200         .init           = &omap2_init_clk_clkdm,
2201         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2202         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2203         .flags          = CLOCK_IN_OMAP343X,
2204         .clkdm_name     = "dss_clkdm",
2205         .recalc         = &followparent_recalc,
2206 };
2207
2208 static struct clk dss_ick = {
2209         /* Handles both L3 and L4 clocks */
2210         .name           = "dss_ick",
2211         .ops            = &clkops_omap2_dflt,
2212         .parent         = &l4_ick,
2213         .init           = &omap2_init_clk_clkdm,
2214         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2215         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2216         .flags          = CLOCK_IN_OMAP343X,
2217         .clkdm_name     = "dss_clkdm",
2218         .recalc         = &followparent_recalc,
2219 };
2220
2221 /* CAM */
2222
2223 static const struct clksel cam_mclk_clksel[] = {
2224         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2225         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2226         { .parent = NULL }
2227 };
2228
2229 static struct clk cam_mclk = {
2230         .name           = "cam_mclk",
2231         .ops            = &clkops_omap2_dflt_wait,
2232         .parent         = &dpll4_m5x2_ck,
2233         .init           = &omap2_init_clksel_parent,
2234         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2235         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2236         .clksel         = cam_mclk_clksel,
2237         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2238         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2239         .flags          = CLOCK_IN_OMAP343X,
2240         .clkdm_name     = "cam_clkdm",
2241         .recalc         = &omap2_clksel_recalc,
2242 };
2243
2244 static struct clk cam_ick = {
2245         /* Handles both L3 and L4 clocks */
2246         .name           = "cam_ick",
2247         .ops            = &clkops_omap2_dflt_wait,
2248         .parent         = &l4_ick,
2249         .init           = &omap2_init_clk_clkdm,
2250         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2251         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2252         .flags          = CLOCK_IN_OMAP343X,
2253         .clkdm_name     = "cam_clkdm",
2254         .recalc         = &followparent_recalc,
2255 };
2256
2257 /* USBHOST - 3430ES2 only */
2258
2259 static struct clk usbhost_120m_fck = {
2260         .name           = "usbhost_120m_fck",
2261         .ops            = &clkops_omap2_dflt_wait,
2262         .parent         = &omap_120m_fck,
2263         .init           = &omap2_init_clk_clkdm,
2264         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2265         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2266         .flags          = CLOCK_IN_OMAP3430ES2,
2267         .clkdm_name     = "usbhost_clkdm",
2268         .recalc         = &followparent_recalc,
2269 };
2270
2271 static struct clk usbhost_48m_fck = {
2272         .name           = "usbhost_48m_fck",
2273         .ops            = &clkops_omap2_dflt_wait,
2274         .parent         = &omap_48m_fck,
2275         .init           = &omap2_init_clk_clkdm,
2276         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2277         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2278         .flags          = CLOCK_IN_OMAP3430ES2,
2279         .clkdm_name     = "usbhost_clkdm",
2280         .recalc         = &followparent_recalc,
2281 };
2282
2283 static struct clk usbhost_ick = {
2284         /* Handles both L3 and L4 clocks */
2285         .name           = "usbhost_ick",
2286         .ops            = &clkops_omap2_dflt_wait,
2287         .parent         = &l4_ick,
2288         .init           = &omap2_init_clk_clkdm,
2289         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2290         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2291         .flags          = CLOCK_IN_OMAP3430ES2,
2292         .clkdm_name     = "usbhost_clkdm",
2293         .recalc         = &followparent_recalc,
2294 };
2295
2296 static struct clk usbhost_sar_fck = {
2297         .name           = "usbhost_sar_fck",
2298         .ops            = &clkops_omap2_dflt_wait,
2299         .parent         = &osc_sys_ck,
2300         .init           = &omap2_init_clk_clkdm,
2301         .enable_reg     = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
2302         .enable_bit     = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
2303         .flags          = CLOCK_IN_OMAP3430ES2,
2304         .clkdm_name     = "usbhost_clkdm",
2305         .recalc         = &followparent_recalc,
2306 };
2307
2308 /* WKUP */
2309
2310 static const struct clksel_rate usim_96m_rates[] = {
2311         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2312         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2313         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2314         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2315         { .div = 0 },
2316 };
2317
2318 static const struct clksel_rate usim_120m_rates[] = {
2319         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2320         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2321         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2322         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2323         { .div = 0 },
2324 };
2325
2326 static const struct clksel usim_clksel[] = {
2327         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2328         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2329         { .parent = &sys_ck,            .rates = div2_rates },
2330         { .parent = NULL },
2331 };
2332
2333 /* 3430ES2 only */
2334 static struct clk usim_fck = {
2335         .name           = "usim_fck",
2336         .ops            = &clkops_omap2_dflt_wait,
2337         .init           = &omap2_init_clksel_parent,
2338         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2339         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2340         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2341         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2342         .clksel         = usim_clksel,
2343         .flags          = CLOCK_IN_OMAP3430ES2,
2344         .recalc         = &omap2_clksel_recalc,
2345 };
2346
2347 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2348 static struct clk gpt1_fck = {
2349         .name           = "gpt1_fck",
2350         .ops            = &clkops_omap2_dflt_wait,
2351         .init           = &omap2_init_clksel_parent,
2352         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2353         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2354         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2355         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2356         .clksel         = omap343x_gpt_clksel,
2357         .flags          = CLOCK_IN_OMAP343X,
2358         .clkdm_name     = "wkup_clkdm",
2359         .recalc         = &omap2_clksel_recalc,
2360 };
2361
2362 static struct clk wkup_32k_fck = {
2363         .name           = "wkup_32k_fck",
2364         .ops            = &clkops_null,
2365         .init           = &omap2_init_clk_clkdm,
2366         .parent         = &omap_32k_fck,
2367         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2368         .clkdm_name     = "wkup_clkdm",
2369         .recalc         = &followparent_recalc,
2370 };
2371
2372 static struct clk gpio1_dbck = {
2373         .name           = "gpio1_dbck",
2374         .ops            = &clkops_omap2_dflt_wait,
2375         .parent         = &wkup_32k_fck,
2376         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2377         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2378         .flags          = CLOCK_IN_OMAP343X,
2379         .clkdm_name     = "wkup_clkdm",
2380         .recalc         = &followparent_recalc,
2381 };
2382
2383 static struct clk wdt2_fck = {
2384         .name           = "wdt2_fck",
2385         .ops            = &clkops_omap2_dflt_wait,
2386         .parent         = &wkup_32k_fck,
2387         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2388         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2389         .flags          = CLOCK_IN_OMAP343X,
2390         .clkdm_name     = "wkup_clkdm",
2391         .recalc         = &followparent_recalc,
2392 };
2393
2394 static struct clk wkup_l4_ick = {
2395         .name           = "wkup_l4_ick",
2396         .ops            = &clkops_null,
2397         .parent         = &sys_ck,
2398         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2399         .clkdm_name     = "wkup_clkdm",
2400         .recalc         = &followparent_recalc,
2401 };
2402
2403 /* 3430ES2 only */
2404 /* Never specifically named in the TRM, so we have to infer a likely name */
2405 static struct clk usim_ick = {
2406         .name           = "usim_ick",
2407         .ops            = &clkops_omap2_dflt_wait,
2408         .parent         = &wkup_l4_ick,
2409         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2410         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2411         .flags          = CLOCK_IN_OMAP3430ES2,
2412         .clkdm_name     = "wkup_clkdm",
2413         .recalc         = &followparent_recalc,
2414 };
2415
2416 static struct clk wdt2_ick = {
2417         .name           = "wdt2_ick",
2418         .ops            = &clkops_omap2_dflt_wait,
2419         .parent         = &wkup_l4_ick,
2420         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2421         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2422         .flags          = CLOCK_IN_OMAP343X,
2423         .clkdm_name     = "wkup_clkdm",
2424         .recalc         = &followparent_recalc,
2425 };
2426
2427 static struct clk wdt1_ick = {
2428         .name           = "wdt1_ick",
2429         .ops            = &clkops_omap2_dflt_wait,
2430         .parent         = &wkup_l4_ick,
2431         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2432         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2433         .flags          = CLOCK_IN_OMAP343X,
2434         .clkdm_name     = "wkup_clkdm",
2435         .recalc         = &followparent_recalc,
2436 };
2437
2438 static struct clk gpio1_ick = {
2439         .name           = "gpio1_ick",
2440         .ops            = &clkops_omap2_dflt_wait,
2441         .parent         = &wkup_l4_ick,
2442         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2443         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2444         .flags          = CLOCK_IN_OMAP343X,
2445         .clkdm_name     = "wkup_clkdm",
2446         .recalc         = &followparent_recalc,
2447 };
2448
2449 static struct clk omap_32ksync_ick = {
2450         .name           = "omap_32ksync_ick",
2451         .ops            = &clkops_omap2_dflt_wait,
2452         .parent         = &wkup_l4_ick,
2453         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2454         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2455         .flags          = CLOCK_IN_OMAP343X,
2456         .clkdm_name     = "wkup_clkdm",
2457         .recalc         = &followparent_recalc,
2458 };
2459
2460 /* XXX This clock no longer exists in 3430 TRM rev F */
2461 static struct clk gpt12_ick = {
2462         .name           = "gpt12_ick",
2463         .ops            = &clkops_omap2_dflt_wait,
2464         .parent         = &wkup_l4_ick,
2465         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2466         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2467         .flags          = CLOCK_IN_OMAP343X,
2468         .clkdm_name     = "wkup_clkdm",
2469         .recalc         = &followparent_recalc,
2470 };
2471
2472 static struct clk gpt1_ick = {
2473         .name           = "gpt1_ick",
2474         .ops            = &clkops_omap2_dflt_wait,
2475         .parent         = &wkup_l4_ick,
2476         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2477         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2478         .flags          = CLOCK_IN_OMAP343X,
2479         .clkdm_name     = "wkup_clkdm",
2480         .recalc         = &followparent_recalc,
2481 };
2482
2483
2484
2485 /* PER clock domain */
2486
2487 static struct clk per_96m_fck = {
2488         .name           = "per_96m_fck",
2489         .ops            = &clkops_null,
2490         .parent         = &omap_96m_alwon_fck,
2491         .init           = &omap2_init_clk_clkdm,
2492         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2493         .clkdm_name     = "per_clkdm",
2494         .recalc         = &followparent_recalc,
2495 };
2496
2497 static struct clk per_48m_fck = {
2498         .name           = "per_48m_fck",
2499         .ops            = &clkops_null,
2500         .parent         = &omap_48m_fck,
2501         .init           = &omap2_init_clk_clkdm,
2502         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2503         .clkdm_name     = "per_clkdm",
2504         .recalc         = &followparent_recalc,
2505 };
2506
2507 static struct clk uart3_fck = {
2508         .name           = "uart3_fck",
2509         .ops            = &clkops_omap2_dflt_wait,
2510         .parent         = &per_48m_fck,
2511         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2512         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2513         .flags          = CLOCK_IN_OMAP343X,
2514         .clkdm_name     = "per_clkdm",
2515         .recalc         = &followparent_recalc,
2516 };
2517
2518 static struct clk gpt2_fck = {
2519         .name           = "gpt2_fck",
2520         .ops            = &clkops_omap2_dflt_wait,
2521         .init           = &omap2_init_clksel_parent,
2522         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2523         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2524         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2525         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2526         .clksel         = omap343x_gpt_clksel,
2527         .flags          = CLOCK_IN_OMAP343X,
2528         .clkdm_name     = "per_clkdm",
2529         .recalc         = &omap2_clksel_recalc,
2530 };
2531
2532 static struct clk gpt3_fck = {
2533         .name           = "gpt3_fck",
2534         .ops            = &clkops_omap2_dflt_wait,
2535         .init           = &omap2_init_clksel_parent,
2536         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2537         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2538         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2539         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2540         .clksel         = omap343x_gpt_clksel,
2541         .flags          = CLOCK_IN_OMAP343X,
2542         .clkdm_name     = "per_clkdm",
2543         .recalc         = &omap2_clksel_recalc,
2544 };
2545
2546 static struct clk gpt4_fck = {
2547         .name           = "gpt4_fck",
2548         .ops            = &clkops_omap2_dflt_wait,
2549         .init           = &omap2_init_clksel_parent,
2550         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2551         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2552         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2553         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2554         .clksel         = omap343x_gpt_clksel,
2555         .flags          = CLOCK_IN_OMAP343X,
2556         .clkdm_name     = "per_clkdm",
2557         .recalc         = &omap2_clksel_recalc,
2558 };
2559
2560 static struct clk gpt5_fck = {
2561         .name           = "gpt5_fck",
2562         .ops            = &clkops_omap2_dflt_wait,
2563         .init           = &omap2_init_clksel_parent,
2564         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2565         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2566         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2567         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2568         .clksel         = omap343x_gpt_clksel,
2569         .flags          = CLOCK_IN_OMAP343X,
2570         .clkdm_name     = "per_clkdm",
2571         .recalc         = &omap2_clksel_recalc,
2572 };
2573
2574 static struct clk gpt6_fck = {
2575         .name           = "gpt6_fck",
2576         .ops            = &clkops_omap2_dflt_wait,
2577         .init           = &omap2_init_clksel_parent,
2578         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2579         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2580         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2581         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2582         .clksel         = omap343x_gpt_clksel,
2583         .flags          = CLOCK_IN_OMAP343X,
2584         .clkdm_name     = "per_clkdm",
2585         .recalc         = &omap2_clksel_recalc,
2586 };
2587
2588 static struct clk gpt7_fck = {
2589         .name           = "gpt7_fck",
2590         .ops            = &clkops_omap2_dflt_wait,
2591         .init           = &omap2_init_clksel_parent,
2592         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2593         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2594         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2595         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2596         .clksel         = omap343x_gpt_clksel,
2597         .flags          = CLOCK_IN_OMAP343X,
2598         .clkdm_name     = "per_clkdm",
2599         .recalc         = &omap2_clksel_recalc,
2600 };
2601
2602 static struct clk gpt8_fck = {
2603         .name           = "gpt8_fck",
2604         .ops            = &clkops_omap2_dflt_wait,
2605         .init           = &omap2_init_clksel_parent,
2606         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2607         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2608         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2609         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2610         .clksel         = omap343x_gpt_clksel,
2611         .flags          = CLOCK_IN_OMAP343X,
2612         .clkdm_name     = "per_clkdm",
2613         .recalc         = &omap2_clksel_recalc,
2614 };
2615
2616 static struct clk gpt9_fck = {
2617         .name           = "gpt9_fck",
2618         .ops            = &clkops_omap2_dflt_wait,
2619         .init           = &omap2_init_clksel_parent,
2620         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2621         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2622         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2623         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2624         .clksel         = omap343x_gpt_clksel,
2625         .flags          = CLOCK_IN_OMAP343X,
2626         .clkdm_name     = "per_clkdm",
2627         .recalc         = &omap2_clksel_recalc,
2628 };
2629
2630 static struct clk per_32k_alwon_fck = {
2631         .name           = "per_32k_alwon_fck",
2632         .ops            = &clkops_null,
2633         .parent         = &omap_32k_fck,
2634         .clkdm_name     = "per_clkdm",
2635         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2636         .recalc         = &followparent_recalc,
2637 };
2638
2639 static struct clk gpio6_dbck = {
2640         .name           = "gpio6_dbck",
2641         .ops            = &clkops_omap2_dflt_wait,
2642         .parent         = &per_32k_alwon_fck,
2643         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2644         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2645         .flags          = CLOCK_IN_OMAP343X,
2646         .clkdm_name     = "per_clkdm",
2647         .recalc         = &followparent_recalc,
2648 };
2649
2650 static struct clk gpio5_dbck = {
2651         .name           = "gpio5_dbck",
2652         .ops            = &clkops_omap2_dflt_wait,
2653         .parent         = &per_32k_alwon_fck,
2654         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2655         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2656         .flags          = CLOCK_IN_OMAP343X,
2657         .clkdm_name     = "per_clkdm",
2658         .recalc         = &followparent_recalc,
2659 };
2660
2661 static struct clk gpio4_dbck = {
2662         .name           = "gpio4_dbck",
2663         .ops            = &clkops_omap2_dflt_wait,
2664         .parent         = &per_32k_alwon_fck,
2665         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2666         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2667         .flags          = CLOCK_IN_OMAP343X,
2668         .clkdm_name     = "per_clkdm",
2669         .recalc         = &followparent_recalc,
2670 };
2671
2672 static struct clk gpio3_dbck = {
2673         .name           = "gpio3_dbck",
2674         .ops            = &clkops_omap2_dflt_wait,
2675         .parent         = &per_32k_alwon_fck,
2676         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2677         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2678         .flags          = CLOCK_IN_OMAP343X,
2679         .clkdm_name     = "per_clkdm",
2680         .recalc         = &followparent_recalc,
2681 };
2682
2683 static struct clk gpio2_dbck = {
2684         .name           = "gpio2_dbck",
2685         .ops            = &clkops_omap2_dflt_wait,
2686         .parent         = &per_32k_alwon_fck,
2687         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2688         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2689         .flags          = CLOCK_IN_OMAP343X,
2690         .clkdm_name     = "per_clkdm",
2691         .recalc         = &followparent_recalc,
2692 };
2693
2694 static struct clk wdt3_fck = {
2695         .name           = "wdt3_fck",
2696         .ops            = &clkops_omap2_dflt_wait,
2697         .parent         = &per_32k_alwon_fck,
2698         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2699         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2700         .flags          = CLOCK_IN_OMAP343X,
2701         .clkdm_name     = "per_clkdm",
2702         .recalc         = &followparent_recalc,
2703 };
2704
2705 static struct clk per_l4_ick = {
2706         .name           = "per_l4_ick",
2707         .ops            = &clkops_null,
2708         .parent         = &l4_ick,
2709         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2710         .clkdm_name     = "per_clkdm",
2711         .recalc         = &followparent_recalc,
2712 };
2713
2714 static struct clk gpio6_ick = {
2715         .name           = "gpio6_ick",
2716         .ops            = &clkops_omap2_dflt_wait,
2717         .parent         = &per_l4_ick,
2718         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2719         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2720         .flags          = CLOCK_IN_OMAP343X,
2721         .clkdm_name     = "per_clkdm",
2722         .recalc         = &followparent_recalc,
2723 };
2724
2725 static struct clk gpio5_ick = {
2726         .name           = "gpio5_ick",
2727         .ops            = &clkops_omap2_dflt_wait,
2728         .parent         = &per_l4_ick,
2729         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2730         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2731         .flags          = CLOCK_IN_OMAP343X,
2732         .clkdm_name     = "per_clkdm",
2733         .recalc         = &followparent_recalc,
2734 };
2735
2736 static struct clk gpio4_ick = {
2737         .name           = "gpio4_ick",
2738         .ops            = &clkops_omap2_dflt_wait,
2739         .parent         = &per_l4_ick,
2740         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2741         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2742         .flags          = CLOCK_IN_OMAP343X,
2743         .clkdm_name     = "per_clkdm",
2744         .recalc         = &followparent_recalc,
2745 };
2746
2747 static struct clk gpio3_ick = {
2748         .name           = "gpio3_ick",
2749         .ops            = &clkops_omap2_dflt_wait,
2750         .parent         = &per_l4_ick,
2751         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2752         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2753         .flags          = CLOCK_IN_OMAP343X,
2754         .clkdm_name     = "per_clkdm",
2755         .recalc         = &followparent_recalc,
2756 };
2757
2758 static struct clk gpio2_ick = {
2759         .name           = "gpio2_ick",
2760         .ops            = &clkops_omap2_dflt_wait,
2761         .parent         = &per_l4_ick,
2762         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2763         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2764         .flags          = CLOCK_IN_OMAP343X,
2765         .clkdm_name     = "per_clkdm",
2766         .recalc         = &followparent_recalc,
2767 };
2768
2769 static struct clk wdt3_ick = {
2770         .name           = "wdt3_ick",
2771         .ops            = &clkops_omap2_dflt_wait,
2772         .parent         = &per_l4_ick,
2773         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2774         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2775         .flags          = CLOCK_IN_OMAP343X,
2776         .clkdm_name     = "per_clkdm",
2777         .recalc         = &followparent_recalc,
2778 };
2779
2780 static struct clk uart3_ick = {
2781         .name           = "uart3_ick",
2782         .ops            = &clkops_omap2_dflt_wait,
2783         .parent         = &per_l4_ick,
2784         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2785         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2786         .flags          = CLOCK_IN_OMAP343X,
2787         .clkdm_name     = "per_clkdm",
2788         .recalc         = &followparent_recalc,
2789 };
2790
2791 static struct clk gpt9_ick = {
2792         .name           = "gpt9_ick",
2793         .ops            = &clkops_omap2_dflt_wait,
2794         .parent         = &per_l4_ick,
2795         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2796         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2797         .flags          = CLOCK_IN_OMAP343X,
2798         .clkdm_name     = "per_clkdm",
2799         .recalc         = &followparent_recalc,
2800 };
2801
2802 static struct clk gpt8_ick = {
2803         .name           = "gpt8_ick",
2804         .ops            = &clkops_omap2_dflt_wait,
2805         .parent         = &per_l4_ick,
2806         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2807         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2808         .flags          = CLOCK_IN_OMAP343X,
2809         .clkdm_name     = "per_clkdm",
2810         .recalc         = &followparent_recalc,
2811 };
2812
2813 static struct clk gpt7_ick = {
2814         .name           = "gpt7_ick",
2815         .ops            = &clkops_omap2_dflt_wait,
2816         .parent         = &per_l4_ick,
2817         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2818         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2819         .flags          = CLOCK_IN_OMAP343X,
2820         .clkdm_name     = "per_clkdm",
2821         .recalc         = &followparent_recalc,
2822 };
2823
2824 static struct clk gpt6_ick = {
2825         .name           = "gpt6_ick",
2826         .ops            = &clkops_omap2_dflt_wait,
2827         .parent         = &per_l4_ick,
2828         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2829         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2830         .flags          = CLOCK_IN_OMAP343X,
2831         .clkdm_name     = "per_clkdm",
2832         .recalc         = &followparent_recalc,
2833 };
2834
2835 static struct clk gpt5_ick = {
2836         .name           = "gpt5_ick",
2837         .ops            = &clkops_omap2_dflt_wait,
2838         .parent         = &per_l4_ick,
2839         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2840         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2841         .flags          = CLOCK_IN_OMAP343X,
2842         .clkdm_name     = "per_clkdm",
2843         .recalc         = &followparent_recalc,
2844 };
2845
2846 static struct clk gpt4_ick = {
2847         .name           = "gpt4_ick",
2848         .ops            = &clkops_omap2_dflt_wait,
2849         .parent         = &per_l4_ick,
2850         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2851         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2852         .flags          = CLOCK_IN_OMAP343X,
2853         .clkdm_name     = "per_clkdm",
2854         .recalc         = &followparent_recalc,
2855 };
2856
2857 static struct clk gpt3_ick = {
2858         .name           = "gpt3_ick",
2859         .ops            = &clkops_omap2_dflt_wait,
2860         .parent         = &per_l4_ick,
2861         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2862         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2863         .flags          = CLOCK_IN_OMAP343X,
2864         .clkdm_name     = "per_clkdm",
2865         .recalc         = &followparent_recalc,
2866 };
2867
2868 static struct clk gpt2_ick = {
2869         .name           = "gpt2_ick",
2870         .ops            = &clkops_omap2_dflt_wait,
2871         .parent         = &per_l4_ick,
2872         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2873         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2874         .flags          = CLOCK_IN_OMAP343X,
2875         .clkdm_name     = "per_clkdm",
2876         .recalc         = &followparent_recalc,
2877 };
2878
2879 static struct clk mcbsp2_ick = {
2880         .name           = "mcbsp_ick",
2881         .ops            = &clkops_omap2_dflt_wait,
2882         .id             = 2,
2883         .parent         = &per_l4_ick,
2884         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2885         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2886         .flags          = CLOCK_IN_OMAP343X,
2887         .clkdm_name     = "per_clkdm",
2888         .recalc         = &followparent_recalc,
2889 };
2890
2891 static struct clk mcbsp3_ick = {
2892         .name           = "mcbsp_ick",
2893         .ops            = &clkops_omap2_dflt_wait,
2894         .id             = 3,
2895         .parent         = &per_l4_ick,
2896         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2897         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2898         .flags          = CLOCK_IN_OMAP343X,
2899         .clkdm_name     = "per_clkdm",
2900         .recalc         = &followparent_recalc,
2901 };
2902
2903 static struct clk mcbsp4_ick = {
2904         .name           = "mcbsp_ick",
2905         .ops            = &clkops_omap2_dflt_wait,
2906         .id             = 4,
2907         .parent         = &per_l4_ick,
2908         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2909         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2910         .flags          = CLOCK_IN_OMAP343X,
2911         .clkdm_name     = "per_clkdm",
2912         .recalc         = &followparent_recalc,
2913 };
2914
2915 static const struct clksel mcbsp_234_clksel[] = {
2916         { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2917         { .parent = &mcbsp_clks,  .rates = common_mcbsp_mcbsp_rates },
2918         { .parent = NULL }
2919 };
2920
2921 static struct clk mcbsp2_fck = {
2922         .name           = "mcbsp_fck",
2923         .ops            = &clkops_omap2_dflt_wait,
2924         .id             = 2,
2925         .init           = &omap2_init_clksel_parent,
2926         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2927         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2928         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2929         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2930         .clksel         = mcbsp_234_clksel,
2931         .flags          = CLOCK_IN_OMAP343X,
2932         .clkdm_name     = "per_clkdm",
2933         .recalc         = &omap2_clksel_recalc,
2934 };
2935
2936 static struct clk mcbsp3_fck = {
2937         .name           = "mcbsp_fck",
2938         .ops            = &clkops_omap2_dflt_wait,
2939         .id             = 3,
2940         .init           = &omap2_init_clksel_parent,
2941         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2942         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2943         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2944         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2945         .clksel         = mcbsp_234_clksel,
2946         .flags          = CLOCK_IN_OMAP343X,
2947         .clkdm_name     = "per_clkdm",
2948         .recalc         = &omap2_clksel_recalc,
2949 };
2950
2951 static struct clk mcbsp4_fck = {
2952         .name           = "mcbsp_fck",
2953         .ops            = &clkops_omap2_dflt_wait,
2954         .id             = 4,
2955         .init           = &omap2_init_clksel_parent,
2956         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2957         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2958         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2959         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2960         .clksel         = mcbsp_234_clksel,
2961         .flags          = CLOCK_IN_OMAP343X,
2962         .clkdm_name     = "per_clkdm",
2963         .recalc         = &omap2_clksel_recalc,
2964 };
2965
2966 /* EMU clocks */
2967
2968 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2969
2970 static const struct clksel_rate emu_src_sys_rates[] = {
2971         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2972         { .div = 0 },
2973 };
2974
2975 static const struct clksel_rate emu_src_core_rates[] = {
2976         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2977         { .div = 0 },
2978 };
2979
2980 static const struct clksel_rate emu_src_per_rates[] = {
2981         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2982         { .div = 0 },
2983 };
2984
2985 static const struct clksel_rate emu_src_mpu_rates[] = {
2986         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2987         { .div = 0 },
2988 };
2989
2990 static const struct clksel emu_src_clksel[] = {
2991         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2992         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2993         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2994         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2995         { .parent = NULL },
2996 };
2997
2998 /*
2999  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
3000  * to switch the source of some of the EMU clocks.
3001  * XXX Are there CLKEN bits for these EMU clks?
3002  */
3003 static struct clk emu_src_ck = {
3004         .name           = "emu_src_ck",
3005         .ops            = &clkops_null,
3006         .init           = &omap2_init_clksel_parent,
3007         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3008         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
3009         .clksel         = emu_src_clksel,
3010         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3011         .clkdm_name     = "emu_clkdm",
3012         .recalc         = &omap2_clksel_recalc,
3013 };
3014
3015 static const struct clksel_rate pclk_emu_rates[] = {
3016         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3017         { .div = 3, .val = 3, .flags = RATE_IN_343X },
3018         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3019         { .div = 6, .val = 6, .flags = RATE_IN_343X },
3020         { .div = 0 },
3021 };
3022
3023 static const struct clksel pclk_emu_clksel[] = {
3024         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
3025         { .parent = NULL },
3026 };
3027
3028 static struct clk pclk_fck = {
3029         .name           = "pclk_fck",
3030         .ops            = &clkops_null,
3031         .init           = &omap2_init_clksel_parent,
3032         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3033         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
3034         .clksel         = pclk_emu_clksel,
3035         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3036         .clkdm_name     = "emu_clkdm",
3037         .recalc         = &omap2_clksel_recalc,
3038 };
3039
3040 static const struct clksel_rate pclkx2_emu_rates[] = {
3041         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3042         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3043         { .div = 3, .val = 3, .flags = RATE_IN_343X },
3044         { .div = 0 },
3045 };
3046
3047 static const struct clksel pclkx2_emu_clksel[] = {
3048         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
3049         { .parent = NULL },
3050 };
3051
3052 static struct clk pclkx2_fck = {
3053         .name           = "pclkx2_fck",
3054         .ops            = &clkops_null,
3055         .init           = &omap2_init_clksel_parent,
3056         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3057         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
3058         .clksel         = pclkx2_emu_clksel,
3059         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3060         .clkdm_name     = "emu_clkdm",
3061         .recalc         = &omap2_clksel_recalc,
3062 };
3063
3064 static const struct clksel atclk_emu_clksel[] = {
3065         { .parent = &emu_src_ck, .rates = div2_rates },
3066         { .parent = NULL },
3067 };
3068
3069 static struct clk atclk_fck = {
3070         .name           = "atclk_fck",
3071         .ops            = &clkops_null,
3072         .init           = &omap2_init_clksel_parent,
3073         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3074         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
3075         .clksel         = atclk_emu_clksel,
3076         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3077         .clkdm_name     = "emu_clkdm",
3078         .recalc         = &omap2_clksel_recalc,
3079 };
3080
3081 static struct clk traceclk_src_fck = {
3082         .name           = "traceclk_src_fck",
3083         .ops            = &clkops_null,
3084         .init           = &omap2_init_clksel_parent,
3085         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3086         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
3087         .clksel         = emu_src_clksel,
3088         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3089         .clkdm_name     = "emu_clkdm",
3090         .recalc         = &omap2_clksel_recalc,
3091 };
3092
3093 static const struct clksel_rate traceclk_rates[] = {
3094         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3095         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3096         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3097         { .div = 0 },
3098 };
3099
3100 static const struct clksel traceclk_clksel[] = {
3101         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3102         { .parent = NULL },
3103 };
3104
3105 static struct clk traceclk_fck = {
3106         .name           = "traceclk_fck",
3107         .ops            = &clkops_null,
3108         .init           = &omap2_init_clksel_parent,
3109         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3110         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3111         .clksel         = traceclk_clksel,
3112         .flags          = CLOCK_IN_OMAP343X,
3113         .clkdm_name     = "emu_clkdm",
3114         .recalc         = &omap2_clksel_recalc,
3115 };
3116
3117 /* SR clocks */
3118
3119 /* SmartReflex fclk (VDD1) */
3120 static struct clk sr1_fck = {
3121         .name           = "sr1_fck",
3122         .ops            = &clkops_omap2_dflt_wait,
3123         .parent         = &sys_ck,
3124         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3125         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3126         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3127         .recalc         = &followparent_recalc,
3128 };
3129
3130 /* SmartReflex fclk (VDD2) */
3131 static struct clk sr2_fck = {
3132         .name           = "sr2_fck",
3133         .ops            = &clkops_omap2_dflt_wait,
3134         .parent         = &sys_ck,
3135         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3136         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3137         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3138         .recalc         = &followparent_recalc,
3139 };
3140
3141 static struct clk sr_l4_ick = {
3142         .name           = "sr_l4_ick",
3143         .ops            = &clkops_null, /* RMK: missing? */
3144         .parent         = &l4_ick,
3145         .flags          = CLOCK_IN_OMAP343X,
3146         .clkdm_name     = "core_l4_clkdm",
3147         .recalc         = &followparent_recalc,
3148 };
3149
3150 /* SECURE_32K_FCK clocks */
3151
3152 /* XXX This clock no longer exists in 3430 TRM rev F */
3153 static struct clk gpt12_fck = {
3154         .name           = "gpt12_fck",
3155         .ops            = &clkops_null,
3156         .parent         = &secure_32k_fck,
3157         .flags          = CLOCK_IN_OMAP343X,
3158         .recalc         = &followparent_recalc,
3159 };
3160
3161 static struct clk wdt1_fck = {
3162         .name           = "wdt1_fck",
3163         .ops            = &clkops_null,
3164         .parent         = &secure_32k_fck,
3165         .flags          = CLOCK_IN_OMAP343X,
3166         .recalc         = &followparent_recalc,
3167 };
3168
3169 static struct clk *onchip_34xx_clks[] __initdata = {
3170         &omap_32k_fck,
3171         &virt_12m_ck,
3172         &virt_13m_ck,
3173         &virt_16_8m_ck,
3174         &virt_19_2m_ck,
3175         &virt_26m_ck,
3176         &virt_38_4m_ck,
3177         &osc_sys_ck,
3178         &sys_ck,
3179         &sys_altclk,
3180         &mcbsp_clks,
3181         &sys_clkout1,
3182         &dpll1_ck,
3183         &dpll1_x2_ck,
3184         &dpll1_x2m2_ck,
3185         &dpll2_ck,
3186         &dpll2_m2_ck,
3187         &dpll3_ck,
3188         &core_ck,
3189         &dpll3_x2_ck,
3190         &dpll3_m2_ck,
3191         &dpll3_m2x2_ck,
3192         &dpll3_m3_ck,
3193         &dpll3_m3x2_ck,
3194         &emu_core_alwon_ck,
3195         &dpll4_ck,
3196         &dpll4_x2_ck,
3197         &omap_96m_alwon_fck,
3198         &omap_96m_fck,
3199         &cm_96m_fck,
3200         &virt_omap_54m_fck,
3201         &omap_54m_fck,
3202         &omap_48m_fck,
3203         &omap_12m_fck,
3204         &dpll4_m2_ck,
3205         &dpll4_m2x2_ck,
3206         &dpll4_m3_ck,
3207         &dpll4_m3x2_ck,
3208         &dpll4_m4_ck,
3209         &dpll4_m4x2_ck,
3210         &dpll4_m5_ck,
3211         &dpll4_m5x2_ck,
3212         &dpll4_m6_ck,
3213         &dpll4_m6x2_ck,
3214         &emu_per_alwon_ck,
3215         &dpll5_ck,
3216         &dpll5_m2_ck,
3217         &omap_120m_fck,
3218         &clkout2_src_ck,
3219         &sys_clkout2,
3220         &corex2_fck,
3221         &dpll1_fck,
3222         &mpu_ck,
3223         &arm_fck,
3224         &emu_mpu_alwon_ck,
3225         &dpll2_fck,
3226         &iva2_ck,
3227         &l3_ick,
3228         &l4_ick,
3229         &rm_ick,
3230         &gfx_l3_ck,
3231         &gfx_l3_fck,
3232         &gfx_l3_ick,
3233         &gfx_cg1_ck,
3234         &gfx_cg2_ck,
3235         &sgx_fck,
3236         &sgx_ick,
3237         &d2d_26m_fck,
3238         &gpt10_fck,
3239         &gpt11_fck,
3240         &cpefuse_fck,
3241         &ts_fck,
3242         &usbtll_fck,
3243         &core_96m_fck,
3244         &mmchs3_fck,
3245         &mmchs2_fck,
3246         &mspro_fck,
3247         &mmchs1_fck,
3248         &i2c3_fck,
3249         &i2c2_fck,
3250         &i2c1_fck,
3251         &mcbsp5_fck,
3252         &mcbsp1_fck,
3253         &core_48m_fck,
3254         &mcspi4_fck,
3255         &mcspi3_fck,
3256         &mcspi2_fck,
3257         &mcspi1_fck,
3258         &uart2_fck,
3259         &uart1_fck,
3260         &fshostusb_fck,
3261         &core_12m_fck,
3262         &hdq_fck,
3263         &ssi_ssr_fck,
3264         &ssi_sst_fck,
3265         &core_l3_ick,
3266         &hsotgusb_ick,
3267         &sdrc_ick,
3268         &gpmc_fck,
3269         &security_l3_ick,
3270         &pka_ick,
3271         &core_l4_ick,
3272         &usbtll_ick,
3273         &mmchs3_ick,
3274         &icr_ick,
3275         &aes2_ick,
3276         &sha12_ick,
3277         &des2_ick,
3278         &mmchs2_ick,
3279         &mmchs1_ick,
3280         &mspro_ick,
3281         &hdq_ick,
3282         &mcspi4_ick,
3283         &mcspi3_ick,
3284         &mcspi2_ick,
3285         &mcspi1_ick,
3286         &i2c3_ick,
3287         &i2c2_ick,
3288         &i2c1_ick,
3289         &uart2_ick,
3290         &uart1_ick,
3291         &gpt11_ick,
3292         &gpt10_ick,
3293         &mcbsp5_ick,
3294         &mcbsp1_ick,
3295         &fac_ick,
3296         &mailboxes_ick,
3297         &omapctrl_ick,
3298         &ssi_l4_ick,
3299         &ssi_ick,
3300         &usb_l4_ick,
3301         &security_l4_ick2,
3302         &aes1_ick,
3303         &rng_ick,
3304         &sha11_ick,
3305         &des1_ick,
3306         &dss1_alwon_fck,
3307         &dss_tv_fck,
3308         &dss_96m_fck,
3309         &dss2_alwon_fck,
3310         &dss_ick,
3311         &cam_mclk,
3312         &cam_ick,
3313         &usbhost_120m_fck,
3314         &usbhost_48m_fck,
3315         &usbhost_ick,
3316         &usbhost_sar_fck,
3317         &usim_fck,
3318         &gpt1_fck,
3319         &wkup_32k_fck,
3320         &gpio1_dbck,
3321         &wdt2_fck,
3322         &wkup_l4_ick,
3323         &usim_ick,
3324         &wdt2_ick,
3325         &wdt1_ick,
3326         &gpio1_ick,
3327         &omap_32ksync_ick,
3328         &gpt12_ick,
3329         &gpt1_ick,
3330         &per_96m_fck,
3331         &per_48m_fck,
3332         &uart3_fck,
3333         &gpt2_fck,
3334         &gpt3_fck,
3335         &gpt4_fck,
3336         &gpt5_fck,
3337         &gpt6_fck,
3338         &gpt7_fck,
3339         &gpt8_fck,
3340         &gpt9_fck,
3341         &per_32k_alwon_fck,
3342         &gpio6_dbck,
3343         &gpio5_dbck,
3344         &gpio4_dbck,
3345         &gpio3_dbck,
3346         &gpio2_dbck,
3347         &wdt3_fck,
3348         &per_l4_ick,
3349         &gpio6_ick,
3350         &gpio5_ick,
3351         &gpio4_ick,
3352         &gpio3_ick,
3353         &gpio2_ick,
3354         &wdt3_ick,
3355         &uart3_ick,
3356         &gpt9_ick,
3357         &gpt8_ick,
3358         &gpt7_ick,
3359         &gpt6_ick,
3360         &gpt5_ick,
3361         &gpt4_ick,
3362         &gpt3_ick,
3363         &gpt2_ick,
3364         &mcbsp2_ick,
3365         &mcbsp3_ick,
3366         &mcbsp4_ick,
3367         &mcbsp2_fck,
3368         &mcbsp3_fck,
3369         &mcbsp4_fck,
3370         &emu_src_ck,
3371         &pclk_fck,
3372         &pclkx2_fck,
3373         &atclk_fck,
3374         &traceclk_src_fck,
3375         &traceclk_fck,
3376         &sr1_fck,
3377         &sr2_fck,
3378         &sr_l4_ick,
3379         &secure_32k_fck,
3380         &gpt12_fck,
3381         &wdt1_fck,
3382 };
3383
3384 #endif