arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35
  36 /* Maximum DPLL multiplier, divider values for OMAP3 */
  37 #define OMAP3_MAX_DPLL_MULT             2048
  38 #define OMAP3_MAX_DPLL_DIV              128
  39
  40 /*
  41  * DPLL1 supplies clock to the MPU.
  42  * DPLL2 supplies clock to the IVA2.
  43  * DPLL3 supplies CORE domain clocks.
  44  * DPLL4 supplies peripheral clocks.
  45  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  46  */
  47
  48 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  49 #define DPLL_LOW_POWER_STOP             0x1
  50 #define DPLL_LOW_POWER_BYPASS           0x5
  51 #define DPLL_LOCKED                     0x7
  52
  53 /* PRM CLOCKS */
  54
  55 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  56 static struct clk omap_32k_fck = {
  57         .name           = "omap_32k_fck",
  58         .ops            = &clkops_null,
  59         .rate           = 32768,
  60         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
  61         .recalc         = &propagate_rate,
  62 };
  63
  64 static struct clk secure_32k_fck = {
  65         .name           = "secure_32k_fck",
  66         .ops            = &clkops_null,
  67         .rate           = 32768,
  68         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
  69         .recalc         = &propagate_rate,
  70 };
  71
  72 /* Virtual source clocks for osc_sys_ck */
  73 static struct clk virt_12m_ck = {
  74         .name           = "virt_12m_ck",
  75         .ops            = &clkops_null,
  76         .rate           = 12000000,
  77         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
  78         .recalc         = &propagate_rate,
  79 };
  80
  81 static struct clk virt_13m_ck = {
  82         .name           = "virt_13m_ck",
  83         .ops            = &clkops_null,
  84         .rate           = 13000000,
  85         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
  86         .recalc         = &propagate_rate,
  87 };
  88
  89 static struct clk virt_16_8m_ck = {
  90         .name           = "virt_16_8m_ck",
  91         .ops            = &clkops_null,
  92         .rate           = 16800000,
  93         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES,
  94         .recalc         = &propagate_rate,
  95 };
  96
  97 static struct clk virt_19_2m_ck = {
  98         .name           = "virt_19_2m_ck",
  99         .ops            = &clkops_null,
 100         .rate           = 19200000,
 101         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
 102         .recalc         = &propagate_rate,
 103 };
 104
 105 static struct clk virt_26m_ck = {
 106         .name           = "virt_26m_ck",
 107         .ops            = &clkops_null,
 108         .rate           = 26000000,
 109         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
 110         .recalc         = &propagate_rate,
 111 };
 112
 113 static struct clk virt_38_4m_ck = {
 114         .name           = "virt_38_4m_ck",
 115         .ops            = &clkops_null,
 116         .rate           = 38400000,
 117         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
 118         .recalc         = &propagate_rate,
 119 };
 120
 121 static const struct clksel_rate osc_sys_12m_rates[] = {
 122         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 123         { .div = 0 }
 124 };
 125
 126 static const struct clksel_rate osc_sys_13m_rates[] = {
 127         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 128         { .div = 0 }
 129 };
 130
 131 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 132         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 133         { .div = 0 }
 134 };
 135
 136 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 137         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 138         { .div = 0 }
 139 };
 140
 141 static const struct clksel_rate osc_sys_26m_rates[] = {
 142         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 143         { .div = 0 }
 144 };
 145
 146 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 147         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 148         { .div = 0 }
 149 };
 150
 151 static const struct clksel osc_sys_clksel[] = {
 152         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 153         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 154         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 155         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 156         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 157         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 158         { .parent = NULL },
 159 };
 160
 161 /* Oscillator clock */
 162 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 163 static struct clk osc_sys_ck = {
 164         .name           = "osc_sys_ck",
 165         .ops            = &clkops_null,
 166         .init           = &omap2_init_clksel_parent,
 167         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 168         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 169         .clksel         = osc_sys_clksel,
 170         /* REVISIT: deal with autoextclkmode? */
 171         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
 172         .recalc         = &omap2_clksel_recalc,
 173 };
 174
 175 static const struct clksel_rate div2_rates[] = {
 176         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 177         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 178         { .div = 0 }
 179 };
 180
 181 static const struct clksel sys_clksel[] = {
 182         { .parent = &osc_sys_ck, .rates = div2_rates },
 183         { .parent = NULL }
 184 };
 185
 186 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 187 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 188 static struct clk sys_ck = {
 189         .name           = "sys_ck",
 190         .ops            = &clkops_null,
 191         .parent         = &osc_sys_ck,
 192         .init           = &omap2_init_clksel_parent,
 193         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 194         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 195         .clksel         = sys_clksel,
 196         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 197         .recalc         = &omap2_clksel_recalc,
 198 };
 199
 200 static struct clk sys_altclk = {
 201         .name           = "sys_altclk",
 202         .ops            = &clkops_null,
 203         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 204         .recalc         = &propagate_rate,
 205 };
 206
 207 /* Optional external clock input for some McBSPs */
 208 static struct clk mcbsp_clks = {
 209         .name           = "mcbsp_clks",
 210         .ops            = &clkops_null,
 211         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 212         .recalc         = &propagate_rate,
 213 };
 214
 215 /* PRM EXTERNAL CLOCK OUTPUT */
 216
 217 static struct clk sys_clkout1 = {
 218         .name           = "sys_clkout1",
 219         .parent         = &osc_sys_ck,
 220         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 221         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 222         .flags          = CLOCK_IN_OMAP343X,
 223         .recalc         = &followparent_recalc,
 224 };
 225
 226 /* DPLLS */
 227
 228 /* CM CLOCKS */
 229
 230 static const struct clksel_rate dpll_bypass_rates[] = {
 231         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 232         { .div = 0 }
 233 };
 234
 235 static const struct clksel_rate dpll_locked_rates[] = {
 236         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 237         { .div = 0 }
 238 };
 239
 240 static const struct clksel_rate div16_dpll_rates[] = {
 241         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 242         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 243         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 244         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 245         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 246         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 247         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 248         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 249         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 250         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 251         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 252         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 253         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 254         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 255         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 256         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 257         { .div = 0 }
 258 };
 259
 260 /* DPLL1 */
 261 /* MPU clock source */
 262 /* Type: DPLL */
 263 static struct dpll_data dpll1_dd = {
 264         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 265         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 266         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 267         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 268         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 269         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 270         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 271         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 272         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 273         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 274         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 275         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 276         .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
 277         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 278         .max_divider    = OMAP3_MAX_DPLL_DIV,
 279         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 280 };
 281
 282 static struct clk dpll1_ck = {
 283         .name           = "dpll1_ck",
 284         .ops            = &clkops_null,
 285         .parent         = &sys_ck,
 286         .dpll_data      = &dpll1_dd,
 287         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 288         .round_rate     = &omap2_dpll_round_rate,
 289         .recalc         = &omap3_dpll_recalc,
 290 };
 291
 292 /*
 293  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 294  * DPLL isn't bypassed.
 295  */
 296 static struct clk dpll1_x2_ck = {
 297         .name           = "dpll1_x2_ck",
 298         .parent         = &dpll1_ck,
 299         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 300                                 PARENT_CONTROLS_CLOCK,
 301         .recalc         = &omap3_clkoutx2_recalc,
 302 };
 303
 304 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 305 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 306         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 307         { .parent = NULL }
 308 };
 309
 310 /*
 311  * Does not exist in the TRM - needed to separate the M2 divider from
 312  * bypass selection in mpu_ck
 313  */
 314 static struct clk dpll1_x2m2_ck = {
 315         .name           = "dpll1_x2m2_ck",
 316         .parent         = &dpll1_x2_ck,
 317         .init           = &omap2_init_clksel_parent,
 318         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 319         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 320         .clksel         = div16_dpll1_x2m2_clksel,
 321         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 322                                 PARENT_CONTROLS_CLOCK,
 323         .recalc         = &omap2_clksel_recalc,
 324 };
 325
 326 /* DPLL2 */
 327 /* IVA2 clock source */
 328 /* Type: DPLL */
 329
 330 static struct dpll_data dpll2_dd = {
 331         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 332         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 333         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 334         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 335         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 336         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 337                                 (1 << DPLL_LOW_POWER_BYPASS),
 338         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 339         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 340         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 341         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 342         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 343         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 344         .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
 345         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 346         .max_divider    = OMAP3_MAX_DPLL_DIV,
 347         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 348 };
 349
 350 static struct clk dpll2_ck = {
 351         .name           = "dpll2_ck",
 352         .ops            = &clkops_noncore_dpll_ops,
 353         .parent         = &sys_ck,
 354         .dpll_data      = &dpll2_dd,
 355         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 356         .round_rate     = &omap2_dpll_round_rate,
 357         .recalc         = &omap3_dpll_recalc,
 358 };
 359
 360 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 361         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 362         { .parent = NULL }
 363 };
 364
 365 /*
 366  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 367  * or CLKOUTX2. CLKOUT seems most plausible.
 368  */
 369 static struct clk dpll2_m2_ck = {
 370         .name           = "dpll2_m2_ck",
 371         .parent         = &dpll2_ck,
 372         .init           = &omap2_init_clksel_parent,
 373         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 374                                           OMAP3430_CM_CLKSEL2_PLL),
 375         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 376         .clksel         = div16_dpll2_m2x2_clksel,
 377         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 378                                 PARENT_CONTROLS_CLOCK,
 379         .recalc         = &omap2_clksel_recalc,
 380 };
 381
 382 /*
 383  * DPLL3
 384  * Source clock for all interfaces and for some device fclks
 385  * REVISIT: Also supports fast relock bypass - not included below
 386  */
 387 static struct dpll_data dpll3_dd = {
 388         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 389         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 390         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 391         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 392         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 393         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 394         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 395         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 396         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 397         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 398         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 399         .max_divider    = OMAP3_MAX_DPLL_DIV,
 400         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 401 };
 402
 403 static struct clk dpll3_ck = {
 404         .name           = "dpll3_ck",
 405         .ops            = &clkops_null,
 406         .parent         = &sys_ck,
 407         .dpll_data      = &dpll3_dd,
 408         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 409         .round_rate     = &omap2_dpll_round_rate,
 410         .recalc         = &omap3_dpll_recalc,
 411 };
 412
 413 /*
 414  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 415  * DPLL isn't bypassed
 416  */
 417 static struct clk dpll3_x2_ck = {
 418         .name           = "dpll3_x2_ck",
 419         .parent         = &dpll3_ck,
 420         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 421                                 PARENT_CONTROLS_CLOCK,
 422         .recalc         = &omap3_clkoutx2_recalc,
 423 };
 424
 425 static const struct clksel_rate div31_dpll3_rates[] = {
 426         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 427         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 428         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 429         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 430         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 431         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 432         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 433         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 434         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 435         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 436         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 437         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 438         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 439         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 440         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 441         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 442         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 443         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 444         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 445         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 446         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 447         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 448         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 449         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 450         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 451         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 452         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 453         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 454         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 455         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 456         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 457         { .div = 0 },
 458 };
 459
 460 static const struct clksel div31_dpll3m2_clksel[] = {
 461         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 462         { .parent = NULL }
 463 };
 464
 465 /*
 466  * DPLL3 output M2
 467  * REVISIT: This DPLL output divider must be changed in SRAM, so until
 468  * that code is ready, this should remain a 'read-only' clksel clock.
 469  */
 470 static struct clk dpll3_m2_ck = {
 471         .name           = "dpll3_m2_ck",
 472         .parent         = &dpll3_ck,
 473         .init           = &omap2_init_clksel_parent,
 474         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 475         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 476         .clksel         = div31_dpll3m2_clksel,
 477         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 478                                 PARENT_CONTROLS_CLOCK,
 479         .recalc         = &omap2_clksel_recalc,
 480 };
 481
 482 static const struct clksel core_ck_clksel[] = {
 483         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 484         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 485         { .parent = NULL }
 486 };
 487
 488 static struct clk core_ck = {
 489         .name           = "core_ck",
 490         .init           = &omap2_init_clksel_parent,
 491         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 492         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 493         .clksel         = core_ck_clksel,
 494         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 495                                 PARENT_CONTROLS_CLOCK,
 496         .recalc         = &omap2_clksel_recalc,
 497 };
 498
 499 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 500         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 501         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 502         { .parent = NULL }
 503 };
 504
 505 static struct clk dpll3_m2x2_ck = {
 506         .name           = "dpll3_m2x2_ck",
 507         .init           = &omap2_init_clksel_parent,
 508         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 509         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 510         .clksel         = dpll3_m2x2_ck_clksel,
 511         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 512                                 PARENT_CONTROLS_CLOCK,
 513         .recalc         = &omap2_clksel_recalc,
 514 };
 515
 516 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 517 static const struct clksel div16_dpll3_clksel[] = {
 518         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 519         { .parent = NULL }
 520 };
 521
 522 /* This virtual clock is the source for dpll3_m3x2_ck */
 523 static struct clk dpll3_m3_ck = {
 524         .name           = "dpll3_m3_ck",
 525         .parent         = &dpll3_ck,
 526         .init           = &omap2_init_clksel_parent,
 527         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 528         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 529         .clksel         = div16_dpll3_clksel,
 530         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 531                                 PARENT_CONTROLS_CLOCK,
 532         .recalc         = &omap2_clksel_recalc,
 533 };
 534
 535 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 536 static struct clk dpll3_m3x2_ck = {
 537         .name           = "dpll3_m3x2_ck",
 538         .parent         = &dpll3_m3_ck,
 539         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 540         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 541         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 542         .recalc         = &omap3_clkoutx2_recalc,
 543 };
 544
 545 static const struct clksel emu_core_alwon_ck_clksel[] = {
 546         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 547         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 548         { .parent = NULL }
 549 };
 550
 551 static struct clk emu_core_alwon_ck = {
 552         .name           = "emu_core_alwon_ck",
 553         .parent         = &dpll3_m3x2_ck,
 554         .init           = &omap2_init_clksel_parent,
 555         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 556         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 557         .clksel         = emu_core_alwon_ck_clksel,
 558         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 559                                 PARENT_CONTROLS_CLOCK,
 560         .recalc         = &omap2_clksel_recalc,
 561 };
 562
 563 /* DPLL4 */
 564 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 565 /* Type: DPLL */
 566 static struct dpll_data dpll4_dd = {
 567         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 568         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 569         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 570         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 571         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 572         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 573         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 574         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 575         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 576         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 577         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 578         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 579         .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
 580         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 581         .max_divider    = OMAP3_MAX_DPLL_DIV,
 582         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 583 };
 584
 585 static struct clk dpll4_ck = {
 586         .name           = "dpll4_ck",
 587         .ops            = &clkops_noncore_dpll_ops,
 588         .parent         = &sys_ck,
 589         .dpll_data      = &dpll4_dd,
 590         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 591         .round_rate     = &omap2_dpll_round_rate,
 592         .recalc         = &omap3_dpll_recalc,
 593 };
 594
 595 /*
 596  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 597  * DPLL isn't bypassed --
 598  * XXX does this serve any downstream clocks?
 599  */
 600 static struct clk dpll4_x2_ck = {
 601         .name           = "dpll4_x2_ck",
 602         .parent         = &dpll4_ck,
 603         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 604                                 PARENT_CONTROLS_CLOCK,
 605         .recalc         = &omap3_clkoutx2_recalc,
 606 };
 607
 608 static const struct clksel div16_dpll4_clksel[] = {
 609         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 610         { .parent = NULL }
 611 };
 612
 613 /* This virtual clock is the source for dpll4_m2x2_ck */
 614 static struct clk dpll4_m2_ck = {
 615         .name           = "dpll4_m2_ck",
 616         .parent         = &dpll4_ck,
 617         .init           = &omap2_init_clksel_parent,
 618         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 619         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 620         .clksel         = div16_dpll4_clksel,
 621         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 622                                 PARENT_CONTROLS_CLOCK,
 623         .recalc         = &omap2_clksel_recalc,
 624 };
 625
 626 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 627 static struct clk dpll4_m2x2_ck = {
 628         .name           = "dpll4_m2x2_ck",
 629         .parent         = &dpll4_m2_ck,
 630         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 631         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 632         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 633         .recalc         = &omap3_clkoutx2_recalc,
 634 };
 635
 636 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 637         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 638         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 639         { .parent = NULL }
 640 };
 641
 642 static struct clk omap_96m_alwon_fck = {
 643         .name           = "omap_96m_alwon_fck",
 644         .parent         = &dpll4_m2x2_ck,
 645         .init           = &omap2_init_clksel_parent,
 646         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 647         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 648         .clksel         = omap_96m_alwon_fck_clksel,
 649         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 650                                  PARENT_CONTROLS_CLOCK,
 651         .recalc         = &omap2_clksel_recalc,
 652 };
 653
 654 static struct clk omap_96m_fck = {
 655         .name           = "omap_96m_fck",
 656         .parent         = &omap_96m_alwon_fck,
 657         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 658                                 PARENT_CONTROLS_CLOCK,
 659         .recalc         = &followparent_recalc,
 660 };
 661
 662 static const struct clksel cm_96m_fck_clksel[] = {
 663         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 664         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 665         { .parent = NULL }
 666 };
 667
 668 static struct clk cm_96m_fck = {
 669         .name           = "cm_96m_fck",
 670         .parent         = &dpll4_m2x2_ck,
 671         .init           = &omap2_init_clksel_parent,
 672         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 673         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 674         .clksel         = cm_96m_fck_clksel,
 675         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 676                                 PARENT_CONTROLS_CLOCK,
 677         .recalc         = &omap2_clksel_recalc,
 678 };
 679
 680 /* This virtual clock is the source for dpll4_m3x2_ck */
 681 static struct clk dpll4_m3_ck = {
 682         .name           = "dpll4_m3_ck",
 683         .parent         = &dpll4_ck,
 684         .init           = &omap2_init_clksel_parent,
 685         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 686         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 687         .clksel         = div16_dpll4_clksel,
 688         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 689                                 PARENT_CONTROLS_CLOCK,
 690         .recalc         = &omap2_clksel_recalc,
 691 };
 692
 693 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 694 static struct clk dpll4_m3x2_ck = {
 695         .name           = "dpll4_m3x2_ck",
 696         .parent         = &dpll4_m3_ck,
 697         .init           = &omap2_init_clksel_parent,
 698         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 699         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 700         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 701         .recalc         = &omap3_clkoutx2_recalc,
 702 };
 703
 704 static const struct clksel virt_omap_54m_fck_clksel[] = {
 705         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 706         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 707         { .parent = NULL }
 708 };
 709
 710 static struct clk virt_omap_54m_fck = {
 711         .name           = "virt_omap_54m_fck",
 712         .parent         = &dpll4_m3x2_ck,
 713         .init           = &omap2_init_clksel_parent,
 714         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 715         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 716         .clksel         = virt_omap_54m_fck_clksel,
 717         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 718                                 PARENT_CONTROLS_CLOCK,
 719         .recalc         = &omap2_clksel_recalc,
 720 };
 721
 722 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 723         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 724         { .div = 0 }
 725 };
 726
 727 static const struct clksel_rate omap_54m_alt_rates[] = {
 728         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 729         { .div = 0 }
 730 };
 731
 732 static const struct clksel omap_54m_clksel[] = {
 733         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 734         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 735         { .parent = NULL }
 736 };
 737
 738 static struct clk omap_54m_fck = {
 739         .name           = "omap_54m_fck",
 740         .init           = &omap2_init_clksel_parent,
 741         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 742         .clksel_mask    = OMAP3430_SOURCE_54M,
 743         .clksel         = omap_54m_clksel,
 744         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 745                                 PARENT_CONTROLS_CLOCK,
 746         .recalc         = &omap2_clksel_recalc,
 747 };
 748
 749 static const struct clksel_rate omap_48m_96md2_rates[] = {
 750         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 751         { .div = 0 }
 752 };
 753
 754 static const struct clksel_rate omap_48m_alt_rates[] = {
 755         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 756         { .div = 0 }
 757 };
 758
 759 static const struct clksel omap_48m_clksel[] = {
 760         { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
 761         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 762         { .parent = NULL }
 763 };
 764
 765 static struct clk omap_48m_fck = {
 766         .name           = "omap_48m_fck",
 767         .init           = &omap2_init_clksel_parent,
 768         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 769         .clksel_mask    = OMAP3430_SOURCE_48M,
 770         .clksel         = omap_48m_clksel,
 771         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 772                                 PARENT_CONTROLS_CLOCK,
 773         .recalc         = &omap2_clksel_recalc,
 774 };
 775
 776 static struct clk omap_12m_fck = {
 777         .name           = "omap_12m_fck",
 778         .parent         = &omap_48m_fck,
 779         .fixed_div      = 4,
 780         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 781                                 PARENT_CONTROLS_CLOCK,
 782         .recalc         = &omap2_fixed_divisor_recalc,
 783 };
 784
 785 /* This virstual clock is the source for dpll4_m4x2_ck */
 786 static struct clk dpll4_m4_ck = {
 787         .name           = "dpll4_m4_ck",
 788         .parent         = &dpll4_ck,
 789         .init           = &omap2_init_clksel_parent,
 790         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 791         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 792         .clksel         = div16_dpll4_clksel,
 793         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 794                                 PARENT_CONTROLS_CLOCK,
 795         .recalc         = &omap2_clksel_recalc,
 796 };
 797
 798 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 799 static struct clk dpll4_m4x2_ck = {
 800         .name           = "dpll4_m4x2_ck",
 801         .parent         = &dpll4_m4_ck,
 802         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 803         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 804         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 805         .recalc         = &omap3_clkoutx2_recalc,
 806 };
 807
 808 /* This virtual clock is the source for dpll4_m5x2_ck */
 809 static struct clk dpll4_m5_ck = {
 810         .name           = "dpll4_m5_ck",
 811         .parent         = &dpll4_ck,
 812         .init           = &omap2_init_clksel_parent,
 813         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 814         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 815         .clksel         = div16_dpll4_clksel,
 816         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 817                                 PARENT_CONTROLS_CLOCK,
 818         .recalc         = &omap2_clksel_recalc,
 819 };
 820
 821 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 822 static struct clk dpll4_m5x2_ck = {
 823         .name           = "dpll4_m5x2_ck",
 824         .parent         = &dpll4_m5_ck,
 825         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 826         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 827         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 828         .recalc         = &omap3_clkoutx2_recalc,
 829 };
 830
 831 /* This virtual clock is the source for dpll4_m6x2_ck */
 832 static struct clk dpll4_m6_ck = {
 833         .name           = "dpll4_m6_ck",
 834         .parent         = &dpll4_ck,
 835         .init           = &omap2_init_clksel_parent,
 836         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 837         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 838         .clksel         = div16_dpll4_clksel,
 839         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 840                                 PARENT_CONTROLS_CLOCK,
 841         .recalc         = &omap2_clksel_recalc,
 842 };
 843
 844 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 845 static struct clk dpll4_m6x2_ck = {
 846         .name           = "dpll4_m6x2_ck",
 847         .parent         = &dpll4_m6_ck,
 848         .init           = &omap2_init_clksel_parent,
 849         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 850         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 851         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 852         .recalc         = &omap3_clkoutx2_recalc,
 853 };
 854
 855 static struct clk emu_per_alwon_ck = {
 856         .name           = "emu_per_alwon_ck",
 857         .parent         = &dpll4_m6x2_ck,
 858         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 859                                 PARENT_CONTROLS_CLOCK,
 860         .recalc         = &followparent_recalc,
 861 };
 862
 863 /* DPLL5 */
 864 /* Supplies 120MHz clock, USIM source clock */
 865 /* Type: DPLL */
 866 /* 3430ES2 only */
 867 static struct dpll_data dpll5_dd = {
 868         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 869         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 870         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 871         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 872         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 873         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 874         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 875         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 876         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 877         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 878         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 879         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 880         .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
 881         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 882         .max_divider    = OMAP3_MAX_DPLL_DIV,
 883         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 884 };
 885
 886 static struct clk dpll5_ck = {
 887         .name           = "dpll5_ck",
 888         .ops            = &clkops_noncore_dpll_ops,
 889         .parent         = &sys_ck,
 890         .dpll_data      = &dpll5_dd,
 891         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 892         .round_rate     = &omap2_dpll_round_rate,
 893         .recalc         = &omap3_dpll_recalc,
 894 };
 895
 896 static const struct clksel div16_dpll5_clksel[] = {
 897         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 898         { .parent = NULL }
 899 };
 900
 901 static struct clk dpll5_m2_ck = {
 902         .name           = "dpll5_m2_ck",
 903         .parent         = &dpll5_ck,
 904         .init           = &omap2_init_clksel_parent,
 905         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 906         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 907         .clksel         = div16_dpll5_clksel,
 908         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 909                                 PARENT_CONTROLS_CLOCK,
 910         .recalc         = &omap2_clksel_recalc,
 911 };
 912
 913 static const struct clksel omap_120m_fck_clksel[] = {
 914         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 915         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
 916         { .parent = NULL }
 917 };
 918
 919 static struct clk omap_120m_fck = {
 920         .name           = "omap_120m_fck",
 921         .parent         = &dpll5_m2_ck,
 922         .init           = &omap2_init_clksel_parent,
 923         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 924         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 925         .clksel         = omap_120m_fck_clksel,
 926         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 927                                 PARENT_CONTROLS_CLOCK,
 928         .recalc         = &omap2_clksel_recalc,
 929 };
 930
 931 /* CM EXTERNAL CLOCK OUTPUTS */
 932
 933 static const struct clksel_rate clkout2_src_core_rates[] = {
 934         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 935         { .div = 0 }
 936 };
 937
 938 static const struct clksel_rate clkout2_src_sys_rates[] = {
 939         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 940         { .div = 0 }
 941 };
 942
 943 static const struct clksel_rate clkout2_src_96m_rates[] = {
 944         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 945         { .div = 0 }
 946 };
 947
 948 static const struct clksel_rate clkout2_src_54m_rates[] = {
 949         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 950         { .div = 0 }
 951 };
 952
 953 static const struct clksel clkout2_src_clksel[] = {
 954         { .parent = &core_ck,             .rates = clkout2_src_core_rates },
 955         { .parent = &sys_ck,              .rates = clkout2_src_sys_rates },
 956         { .parent = &omap_96m_alwon_fck,  .rates = clkout2_src_96m_rates },
 957         { .parent = &omap_54m_fck,        .rates = clkout2_src_54m_rates },
 958         { .parent = NULL }
 959 };
 960
 961 static struct clk clkout2_src_ck = {
 962         .name           = "clkout2_src_ck",
 963         .init           = &omap2_init_clksel_parent,
 964         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
 965         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 966         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 967         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 968         .clksel         = clkout2_src_clksel,
 969         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 970         .recalc         = &omap2_clksel_recalc,
 971 };
 972
 973 static const struct clksel_rate sys_clkout2_rates[] = {
 974         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 975         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 976         { .div = 4, .val = 2, .flags = RATE_IN_343X },
 977         { .div = 8, .val = 3, .flags = RATE_IN_343X },
 978         { .div = 16, .val = 4, .flags = RATE_IN_343X },
 979         { .div = 0 },
 980 };
 981
 982 static const struct clksel sys_clkout2_clksel[] = {
 983         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
 984         { .parent = NULL },
 985 };
 986
 987 static struct clk sys_clkout2 = {
 988         .name           = "sys_clkout2",
 989         .init           = &omap2_init_clksel_parent,
 990         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 991         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
 992         .clksel         = sys_clkout2_clksel,
 993         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 994         .recalc         = &omap2_clksel_recalc,
 995 };
 996
 997 /* CM OUTPUT CLOCKS */
 998
 999 static struct clk corex2_fck = {
1000         .name           = "corex2_fck",
1001         .parent         = &dpll3_m2x2_ck,
1002         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1003                                 PARENT_CONTROLS_CLOCK,
1004         .recalc         = &followparent_recalc,
1005 };
1006
1007 /* DPLL power domain clock controls */
1008
1009 static const struct clksel div2_core_clksel[] = {
1010         { .parent = &core_ck, .rates = div2_rates },
1011         { .parent = NULL }
1012 };
1013
1014 /*
1015  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1016  * may be inconsistent here?
1017  */
1018 static struct clk dpll1_fck = {
1019         .name           = "dpll1_fck",
1020         .parent         = &core_ck,
1021         .init           = &omap2_init_clksel_parent,
1022         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1023         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1024         .clksel         = div2_core_clksel,
1025         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1026                                 PARENT_CONTROLS_CLOCK,
1027         .recalc         = &omap2_clksel_recalc,
1028 };
1029
1030 /*
1031  * MPU clksel:
1032  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1033  * derives from the high-frequency bypass clock originating from DPLL3,
1034  * called 'dpll1_fck'
1035  */
1036 static const struct clksel mpu_clksel[] = {
1037         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1038         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1039         { .parent = NULL }
1040 };
1041
1042 static struct clk mpu_ck = {
1043         .name           = "mpu_ck",
1044         .parent         = &dpll1_x2m2_ck,
1045         .init           = &omap2_init_clksel_parent,
1046         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1047         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1048         .clksel         = mpu_clksel,
1049         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1050                                 PARENT_CONTROLS_CLOCK,
1051         .clkdm_name     = "mpu_clkdm",
1052         .recalc         = &omap2_clksel_recalc,
1053 };
1054
1055 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1056 static const struct clksel_rate arm_fck_rates[] = {
1057         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1058         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1059         { .div = 0 },
1060 };
1061
1062 static const struct clksel arm_fck_clksel[] = {
1063         { .parent = &mpu_ck, .rates = arm_fck_rates },
1064         { .parent = NULL }
1065 };
1066
1067 static struct clk arm_fck = {
1068         .name           = "arm_fck",
1069         .parent         = &mpu_ck,
1070         .init           = &omap2_init_clksel_parent,
1071         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1072         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1073         .clksel         = arm_fck_clksel,
1074         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1075                                 PARENT_CONTROLS_CLOCK,
1076         .recalc         = &omap2_clksel_recalc,
1077 };
1078
1079 /* XXX What about neon_clkdm ? */
1080
1081 /*
1082  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1083  * although it is referenced - so this is a guess
1084  */
1085 static struct clk emu_mpu_alwon_ck = {
1086         .name           = "emu_mpu_alwon_ck",
1087         .parent         = &mpu_ck,
1088         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1089                                 PARENT_CONTROLS_CLOCK,
1090         .recalc         = &followparent_recalc,
1091 };
1092
1093 static struct clk dpll2_fck = {
1094         .name           = "dpll2_fck",
1095         .parent         = &core_ck,
1096         .init           = &omap2_init_clksel_parent,
1097         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1098         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1099         .clksel         = div2_core_clksel,
1100         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1101                                 PARENT_CONTROLS_CLOCK,
1102         .recalc         = &omap2_clksel_recalc,
1103 };
1104
1105 /*
1106  * IVA2 clksel:
1107  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1108  * derives from the high-frequency bypass clock originating from DPLL3,
1109  * called 'dpll2_fck'
1110  */
1111
1112 static const struct clksel iva2_clksel[] = {
1113         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1114         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1115         { .parent = NULL }
1116 };
1117
1118 static struct clk iva2_ck = {
1119         .name           = "iva2_ck",
1120         .parent         = &dpll2_m2_ck,
1121         .init           = &omap2_init_clksel_parent,
1122         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1123         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1124         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1125                                           OMAP3430_CM_IDLEST_PLL),
1126         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1127         .clksel         = iva2_clksel,
1128         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1129         .clkdm_name     = "iva2_clkdm",
1130         .recalc         = &omap2_clksel_recalc,
1131 };
1132
1133 /* Common interface clocks */
1134
1135 static struct clk l3_ick = {
1136         .name           = "l3_ick",
1137         .parent         = &core_ck,
1138         .init           = &omap2_init_clksel_parent,
1139         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1140         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1141         .clksel         = div2_core_clksel,
1142         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1143                                 PARENT_CONTROLS_CLOCK,
1144         .clkdm_name     = "core_l3_clkdm",
1145         .recalc         = &omap2_clksel_recalc,
1146 };
1147
1148 static const struct clksel div2_l3_clksel[] = {
1149         { .parent = &l3_ick, .rates = div2_rates },
1150         { .parent = NULL }
1151 };
1152
1153 static struct clk l4_ick = {
1154         .name           = "l4_ick",
1155         .parent         = &l3_ick,
1156         .init           = &omap2_init_clksel_parent,
1157         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1158         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1159         .clksel         = div2_l3_clksel,
1160         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1161                                 PARENT_CONTROLS_CLOCK,
1162         .clkdm_name     = "core_l4_clkdm",
1163         .recalc         = &omap2_clksel_recalc,
1164
1165 };
1166
1167 static const struct clksel div2_l4_clksel[] = {
1168         { .parent = &l4_ick, .rates = div2_rates },
1169         { .parent = NULL }
1170 };
1171
1172 static struct clk rm_ick = {
1173         .name           = "rm_ick",
1174         .parent         = &l4_ick,
1175         .init           = &omap2_init_clksel_parent,
1176         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1177         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1178         .clksel         = div2_l4_clksel,
1179         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1180         .recalc         = &omap2_clksel_recalc,
1181 };
1182
1183 /* GFX power domain */
1184
1185 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1186
1187 static const struct clksel gfx_l3_clksel[] = {
1188         { .parent = &l3_ick, .rates = gfx_l3_rates },
1189         { .parent = NULL }
1190 };
1191
1192 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1193 static struct clk gfx_l3_ck = {
1194         .name           = "gfx_l3_ck",
1195         .parent         = &l3_ick,
1196         .init           = &omap2_init_clksel_parent,
1197         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1198         .enable_bit     = OMAP_EN_GFX_SHIFT,
1199         .flags          = CLOCK_IN_OMAP3430ES1,
1200         .recalc         = &followparent_recalc,
1201 };
1202
1203 static struct clk gfx_l3_fck = {
1204         .name           = "gfx_l3_fck",
1205         .parent         = &gfx_l3_ck,
1206         .init           = &omap2_init_clksel_parent,
1207         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1208         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1209         .clksel         = gfx_l3_clksel,
1210         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1211                                 PARENT_CONTROLS_CLOCK,
1212         .clkdm_name     = "gfx_3430es1_clkdm",
1213         .recalc         = &omap2_clksel_recalc,
1214 };
1215
1216 static struct clk gfx_l3_ick = {
1217         .name           = "gfx_l3_ick",
1218         .parent         = &gfx_l3_ck,
1219         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1220         .clkdm_name     = "gfx_3430es1_clkdm",
1221         .recalc         = &followparent_recalc,
1222 };
1223
1224 static struct clk gfx_cg1_ck = {
1225         .name           = "gfx_cg1_ck",
1226         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1227         .init           = &omap2_init_clk_clkdm,
1228         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1229         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1230         .flags          = CLOCK_IN_OMAP3430ES1,
1231         .clkdm_name     = "gfx_3430es1_clkdm",
1232         .recalc         = &followparent_recalc,
1233 };
1234
1235 static struct clk gfx_cg2_ck = {
1236         .name           = "gfx_cg2_ck",
1237         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1238         .init           = &omap2_init_clk_clkdm,
1239         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1240         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1241         .flags          = CLOCK_IN_OMAP3430ES1,
1242         .clkdm_name     = "gfx_3430es1_clkdm",
1243         .recalc         = &followparent_recalc,
1244 };
1245
1246 /* SGX power domain - 3430ES2 only */
1247
1248 static const struct clksel_rate sgx_core_rates[] = {
1249         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1250         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1251         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1252         { .div = 0 },
1253 };
1254
1255 static const struct clksel_rate sgx_96m_rates[] = {
1256         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1257         { .div = 0 },
1258 };
1259
1260 static const struct clksel sgx_clksel[] = {
1261         { .parent = &core_ck,    .rates = sgx_core_rates },
1262         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1263         { .parent = NULL },
1264 };
1265
1266 static struct clk sgx_fck = {
1267         .name           = "sgx_fck",
1268         .init           = &omap2_init_clksel_parent,
1269         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1270         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1271         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1272         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1273         .clksel         = sgx_clksel,
1274         .flags          = CLOCK_IN_OMAP3430ES2,
1275         .clkdm_name     = "sgx_clkdm",
1276         .recalc         = &omap2_clksel_recalc,
1277 };
1278
1279 static struct clk sgx_ick = {
1280         .name           = "sgx_ick",
1281         .parent         = &l3_ick,
1282         .init           = &omap2_init_clk_clkdm,
1283         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1284         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1285         .flags          = CLOCK_IN_OMAP3430ES2,
1286         .clkdm_name     = "sgx_clkdm",
1287         .recalc         = &followparent_recalc,
1288 };
1289
1290 /* CORE power domain */
1291
1292 static struct clk d2d_26m_fck = {
1293         .name           = "d2d_26m_fck",
1294         .parent         = &sys_ck,
1295         .init           = &omap2_init_clk_clkdm,
1296         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1297         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1298         .flags          = CLOCK_IN_OMAP3430ES1,
1299         .clkdm_name     = "d2d_clkdm",
1300         .recalc         = &followparent_recalc,
1301 };
1302
1303 static const struct clksel omap343x_gpt_clksel[] = {
1304         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1305         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1306         { .parent = NULL}
1307 };
1308
1309 static struct clk gpt10_fck = {
1310         .name           = "gpt10_fck",
1311         .parent         = &sys_ck,
1312         .init           = &omap2_init_clksel_parent,
1313         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1314         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1315         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1316         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1317         .clksel         = omap343x_gpt_clksel,
1318         .flags          = CLOCK_IN_OMAP343X,
1319         .clkdm_name     = "core_l4_clkdm",
1320         .recalc         = &omap2_clksel_recalc,
1321 };
1322
1323 static struct clk gpt11_fck = {
1324         .name           = "gpt11_fck",
1325         .parent         = &sys_ck,
1326         .init           = &omap2_init_clksel_parent,
1327         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1328         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1329         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1330         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1331         .clksel         = omap343x_gpt_clksel,
1332         .flags          = CLOCK_IN_OMAP343X,
1333         .clkdm_name     = "core_l4_clkdm",
1334         .recalc         = &omap2_clksel_recalc,
1335 };
1336
1337 static struct clk cpefuse_fck = {
1338         .name           = "cpefuse_fck",
1339         .parent         = &sys_ck,
1340         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1341         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1342         .flags          = CLOCK_IN_OMAP3430ES2,
1343         .recalc         = &followparent_recalc,
1344 };
1345
1346 static struct clk ts_fck = {
1347         .name           = "ts_fck",
1348         .parent         = &omap_32k_fck,
1349         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1350         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1351         .flags          = CLOCK_IN_OMAP3430ES2,
1352         .recalc         = &followparent_recalc,
1353 };
1354
1355 static struct clk usbtll_fck = {
1356         .name           = "usbtll_fck",
1357         .parent         = &omap_120m_fck,
1358         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1359         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1360         .flags          = CLOCK_IN_OMAP3430ES2,
1361         .recalc         = &followparent_recalc,
1362 };
1363
1364 /* CORE 96M FCLK-derived clocks */
1365
1366 static struct clk core_96m_fck = {
1367         .name           = "core_96m_fck",
1368         .parent         = &omap_96m_fck,
1369         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1370                                 PARENT_CONTROLS_CLOCK,
1371         .clkdm_name     = "core_l4_clkdm",
1372         .recalc         = &followparent_recalc,
1373 };
1374
1375 static struct clk mmchs3_fck = {
1376         .name           = "mmchs_fck",
1377         .id             = 2,
1378         .parent         = &core_96m_fck,
1379         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1380         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1381         .flags          = CLOCK_IN_OMAP3430ES2,
1382         .clkdm_name     = "core_l4_clkdm",
1383         .recalc         = &followparent_recalc,
1384 };
1385
1386 static struct clk mmchs2_fck = {
1387         .name           = "mmchs_fck",
1388         .id             = 1,
1389         .parent         = &core_96m_fck,
1390         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1391         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1392         .flags          = CLOCK_IN_OMAP343X,
1393         .clkdm_name     = "core_l4_clkdm",
1394         .recalc         = &followparent_recalc,
1395 };
1396
1397 static struct clk mspro_fck = {
1398         .name           = "mspro_fck",
1399         .parent         = &core_96m_fck,
1400         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1401         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1402         .flags          = CLOCK_IN_OMAP343X,
1403         .clkdm_name     = "core_l4_clkdm",
1404         .recalc         = &followparent_recalc,
1405 };
1406
1407 static struct clk mmchs1_fck = {
1408         .name           = "mmchs_fck",
1409         .parent         = &core_96m_fck,
1410         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1411         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1412         .flags          = CLOCK_IN_OMAP343X,
1413         .clkdm_name     = "core_l4_clkdm",
1414         .recalc         = &followparent_recalc,
1415 };
1416
1417 static struct clk i2c3_fck = {
1418         .name           = "i2c_fck",
1419         .id             = 3,
1420         .parent         = &core_96m_fck,
1421         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1422         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1423         .flags          = CLOCK_IN_OMAP343X,
1424         .clkdm_name     = "core_l4_clkdm",
1425         .recalc         = &followparent_recalc,
1426 };
1427
1428 static struct clk i2c2_fck = {
1429         .name           = "i2c_fck",
1430         .id             = 2,
1431         .parent         = &core_96m_fck,
1432         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1433         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1434         .flags          = CLOCK_IN_OMAP343X,
1435         .clkdm_name     = "core_l4_clkdm",
1436         .recalc         = &followparent_recalc,
1437 };
1438
1439 static struct clk i2c1_fck = {
1440         .name           = "i2c_fck",
1441         .id             = 1,
1442         .parent         = &core_96m_fck,
1443         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1444         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1445         .flags          = CLOCK_IN_OMAP343X,
1446         .clkdm_name     = "core_l4_clkdm",
1447         .recalc         = &followparent_recalc,
1448 };
1449
1450 /*
1451  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1452  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1453  */
1454 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1455         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1456         { .div = 0 }
1457 };
1458
1459 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1460         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1461         { .div = 0 }
1462 };
1463
1464 static const struct clksel mcbsp_15_clksel[] = {
1465         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1466         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1467         { .parent = NULL }
1468 };
1469
1470 static struct clk mcbsp5_fck = {
1471         .name           = "mcbsp_fck",
1472         .id             = 5,
1473         .init           = &omap2_init_clksel_parent,
1474         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1475         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1476         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1477         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1478         .clksel         = mcbsp_15_clksel,
1479         .flags          = CLOCK_IN_OMAP343X,
1480         .clkdm_name     = "core_l4_clkdm",
1481         .recalc         = &omap2_clksel_recalc,
1482 };
1483
1484 static struct clk mcbsp1_fck = {
1485         .name           = "mcbsp_fck",
1486         .id             = 1,
1487         .init           = &omap2_init_clksel_parent,
1488         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1489         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1490         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1491         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1492         .clksel         = mcbsp_15_clksel,
1493         .flags          = CLOCK_IN_OMAP343X,
1494         .clkdm_name     = "core_l4_clkdm",
1495         .recalc         = &omap2_clksel_recalc,
1496 };
1497
1498 /* CORE_48M_FCK-derived clocks */
1499
1500 static struct clk core_48m_fck = {
1501         .name           = "core_48m_fck",
1502         .parent         = &omap_48m_fck,
1503         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1504                                 PARENT_CONTROLS_CLOCK,
1505         .clkdm_name     = "core_l4_clkdm",
1506         .recalc         = &followparent_recalc,
1507 };
1508
1509 static struct clk mcspi4_fck = {
1510         .name           = "mcspi_fck",
1511         .id             = 4,
1512         .parent         = &core_48m_fck,
1513         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1514         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1515         .flags          = CLOCK_IN_OMAP343X,
1516         .recalc         = &followparent_recalc,
1517 };
1518
1519 static struct clk mcspi3_fck = {
1520         .name           = "mcspi_fck",
1521         .id             = 3,
1522         .parent         = &core_48m_fck,
1523         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1524         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1525         .flags          = CLOCK_IN_OMAP343X,
1526         .recalc         = &followparent_recalc,
1527 };
1528
1529 static struct clk mcspi2_fck = {
1530         .name           = "mcspi_fck",
1531         .id             = 2,
1532         .parent         = &core_48m_fck,
1533         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1534         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1535         .flags          = CLOCK_IN_OMAP343X,
1536         .recalc         = &followparent_recalc,
1537 };
1538
1539 static struct clk mcspi1_fck = {
1540         .name           = "mcspi_fck",
1541         .id             = 1,
1542         .parent         = &core_48m_fck,
1543         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1544         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1545         .flags          = CLOCK_IN_OMAP343X,
1546         .recalc         = &followparent_recalc,
1547 };
1548
1549 static struct clk uart2_fck = {
1550         .name           = "uart2_fck",
1551         .parent         = &core_48m_fck,
1552         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1553         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1554         .flags          = CLOCK_IN_OMAP343X,
1555         .recalc         = &followparent_recalc,
1556 };
1557
1558 static struct clk uart1_fck = {
1559         .name           = "uart1_fck",
1560         .parent         = &core_48m_fck,
1561         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1562         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1563         .flags          = CLOCK_IN_OMAP343X,
1564         .recalc         = &followparent_recalc,
1565 };
1566
1567 static struct clk fshostusb_fck = {
1568         .name           = "fshostusb_fck",
1569         .parent         = &core_48m_fck,
1570         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1571         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1572         .flags          = CLOCK_IN_OMAP3430ES1,
1573         .recalc         = &followparent_recalc,
1574 };
1575
1576 /* CORE_12M_FCK based clocks */
1577
1578 static struct clk core_12m_fck = {
1579         .name           = "core_12m_fck",
1580         .parent         = &omap_12m_fck,
1581         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1582                                 PARENT_CONTROLS_CLOCK,
1583         .clkdm_name     = "core_l4_clkdm",
1584         .recalc         = &followparent_recalc,
1585 };
1586
1587 static struct clk hdq_fck = {
1588         .name           = "hdq_fck",
1589         .parent         = &core_12m_fck,
1590         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1591         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1592         .flags          = CLOCK_IN_OMAP343X,
1593         .recalc         = &followparent_recalc,
1594 };
1595
1596 /* DPLL3-derived clock */
1597
1598 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1599         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1600         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1601         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1602         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1603         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1604         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1605         { .div = 0 }
1606 };
1607
1608 static const struct clksel ssi_ssr_clksel[] = {
1609         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1610         { .parent = NULL }
1611 };
1612
1613 static struct clk ssi_ssr_fck = {
1614         .name           = "ssi_ssr_fck",
1615         .init           = &omap2_init_clksel_parent,
1616         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1617         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1618         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1619         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1620         .clksel         = ssi_ssr_clksel,
1621         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1622         .clkdm_name     = "core_l4_clkdm",
1623         .recalc         = &omap2_clksel_recalc,
1624 };
1625
1626 static struct clk ssi_sst_fck = {
1627         .name           = "ssi_sst_fck",
1628         .parent         = &ssi_ssr_fck,
1629         .fixed_div      = 2,
1630         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1631         .recalc         = &omap2_fixed_divisor_recalc,
1632 };
1633
1634
1635
1636 /* CORE_L3_ICK based clocks */
1637
1638 /*
1639  * XXX must add clk_enable/clk_disable for these if standard code won't
1640  * handle it
1641  */
1642 static struct clk core_l3_ick = {
1643         .name           = "core_l3_ick",
1644         .parent         = &l3_ick,
1645         .init           = &omap2_init_clk_clkdm,
1646         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1647                                 PARENT_CONTROLS_CLOCK,
1648         .clkdm_name     = "core_l3_clkdm",
1649         .recalc         = &followparent_recalc,
1650 };
1651
1652 static struct clk hsotgusb_ick = {
1653         .name           = "hsotgusb_ick",
1654         .parent         = &core_l3_ick,
1655         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1656         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1657         .flags          = CLOCK_IN_OMAP343X,
1658         .clkdm_name     = "core_l3_clkdm",
1659         .recalc         = &followparent_recalc,
1660 };
1661
1662 static struct clk sdrc_ick = {
1663         .name           = "sdrc_ick",
1664         .parent         = &core_l3_ick,
1665         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1666         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1667         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1668         .clkdm_name     = "core_l3_clkdm",
1669         .recalc         = &followparent_recalc,
1670 };
1671
1672 static struct clk gpmc_fck = {
1673         .name           = "gpmc_fck",
1674         .parent         = &core_l3_ick,
1675         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1676                                 ENABLE_ON_INIT,
1677         .clkdm_name     = "core_l3_clkdm",
1678         .recalc         = &followparent_recalc,
1679 };
1680
1681 /* SECURITY_L3_ICK based clocks */
1682
1683 static struct clk security_l3_ick = {
1684         .name           = "security_l3_ick",
1685         .parent         = &l3_ick,
1686         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1687                                 PARENT_CONTROLS_CLOCK,
1688         .recalc         = &followparent_recalc,
1689 };
1690
1691 static struct clk pka_ick = {
1692         .name           = "pka_ick",
1693         .parent         = &security_l3_ick,
1694         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1695         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1696         .flags          = CLOCK_IN_OMAP343X,
1697         .recalc         = &followparent_recalc,
1698 };
1699
1700 /* CORE_L4_ICK based clocks */
1701
1702 static struct clk core_l4_ick = {
1703         .name           = "core_l4_ick",
1704         .parent         = &l4_ick,
1705         .init           = &omap2_init_clk_clkdm,
1706         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1707                                 PARENT_CONTROLS_CLOCK,
1708         .clkdm_name     = "core_l4_clkdm",
1709         .recalc         = &followparent_recalc,
1710 };
1711
1712 static struct clk usbtll_ick = {
1713         .name           = "usbtll_ick",
1714         .parent         = &core_l4_ick,
1715         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1716         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1717         .flags          = CLOCK_IN_OMAP3430ES2,
1718         .clkdm_name     = "core_l4_clkdm",
1719         .recalc         = &followparent_recalc,
1720 };
1721
1722 static struct clk mmchs3_ick = {
1723         .name           = "mmchs_ick",
1724         .id             = 2,
1725         .parent         = &core_l4_ick,
1726         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1727         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1728         .flags          = CLOCK_IN_OMAP3430ES2,
1729         .clkdm_name     = "core_l4_clkdm",
1730         .recalc         = &followparent_recalc,
1731 };
1732
1733 /* Intersystem Communication Registers - chassis mode only */
1734 static struct clk icr_ick = {
1735         .name           = "icr_ick",
1736         .parent         = &core_l4_ick,
1737         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1738         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1739         .flags          = CLOCK_IN_OMAP343X,
1740         .clkdm_name     = "core_l4_clkdm",
1741         .recalc         = &followparent_recalc,
1742 };
1743
1744 static struct clk aes2_ick = {
1745         .name           = "aes2_ick",
1746         .parent         = &core_l4_ick,
1747         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1748         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1749         .flags          = CLOCK_IN_OMAP343X,
1750         .clkdm_name     = "core_l4_clkdm",
1751         .recalc         = &followparent_recalc,
1752 };
1753
1754 static struct clk sha12_ick = {
1755         .name           = "sha12_ick",
1756         .parent         = &core_l4_ick,
1757         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1758         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1759         .flags          = CLOCK_IN_OMAP343X,
1760         .clkdm_name     = "core_l4_clkdm",
1761         .recalc         = &followparent_recalc,
1762 };
1763
1764 static struct clk des2_ick = {
1765         .name           = "des2_ick",
1766         .parent         = &core_l4_ick,
1767         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1768         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1769         .flags          = CLOCK_IN_OMAP343X,
1770         .clkdm_name     = "core_l4_clkdm",
1771         .recalc         = &followparent_recalc,
1772 };
1773
1774 static struct clk mmchs2_ick = {
1775         .name           = "mmchs_ick",
1776         .id             = 1,
1777         .parent         = &core_l4_ick,
1778         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1779         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1780         .flags          = CLOCK_IN_OMAP343X,
1781         .clkdm_name     = "core_l4_clkdm",
1782         .recalc         = &followparent_recalc,
1783 };
1784
1785 static struct clk mmchs1_ick = {
1786         .name           = "mmchs_ick",
1787         .parent         = &core_l4_ick,
1788         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1789         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1790         .flags          = CLOCK_IN_OMAP343X,
1791         .clkdm_name     = "core_l4_clkdm",
1792         .recalc         = &followparent_recalc,
1793 };
1794
1795 static struct clk mspro_ick = {
1796         .name           = "mspro_ick",
1797         .parent         = &core_l4_ick,
1798         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1799         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1800         .flags          = CLOCK_IN_OMAP343X,
1801         .clkdm_name     = "core_l4_clkdm",
1802         .recalc         = &followparent_recalc,
1803 };
1804
1805 static struct clk hdq_ick = {
1806         .name           = "hdq_ick",
1807         .parent         = &core_l4_ick,
1808         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1809         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1810         .flags          = CLOCK_IN_OMAP343X,
1811         .clkdm_name     = "core_l4_clkdm",
1812         .recalc         = &followparent_recalc,
1813 };
1814
1815 static struct clk mcspi4_ick = {
1816         .name           = "mcspi_ick",
1817         .id             = 4,
1818         .parent         = &core_l4_ick,
1819         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1820         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1821         .flags          = CLOCK_IN_OMAP343X,
1822         .clkdm_name     = "core_l4_clkdm",
1823         .recalc         = &followparent_recalc,
1824 };
1825
1826 static struct clk mcspi3_ick = {
1827         .name           = "mcspi_ick",
1828         .id             = 3,
1829         .parent         = &core_l4_ick,
1830         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1831         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1832         .flags          = CLOCK_IN_OMAP343X,
1833         .clkdm_name     = "core_l4_clkdm",
1834         .recalc         = &followparent_recalc,
1835 };
1836
1837 static struct clk mcspi2_ick = {
1838         .name           = "mcspi_ick",
1839         .id             = 2,
1840         .parent         = &core_l4_ick,
1841         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1842         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1843         .flags          = CLOCK_IN_OMAP343X,
1844         .clkdm_name     = "core_l4_clkdm",
1845         .recalc         = &followparent_recalc,
1846 };
1847
1848 static struct clk mcspi1_ick = {
1849         .name           = "mcspi_ick",
1850         .id             = 1,
1851         .parent         = &core_l4_ick,
1852         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1853         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1854         .flags          = CLOCK_IN_OMAP343X,
1855         .clkdm_name     = "core_l4_clkdm",
1856         .recalc         = &followparent_recalc,
1857 };
1858
1859 static struct clk i2c3_ick = {
1860         .name           = "i2c_ick",
1861         .id             = 3,
1862         .parent         = &core_l4_ick,
1863         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1864         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1865         .flags          = CLOCK_IN_OMAP343X,
1866         .clkdm_name     = "core_l4_clkdm",
1867         .recalc         = &followparent_recalc,
1868 };
1869
1870 static struct clk i2c2_ick = {
1871         .name           = "i2c_ick",
1872         .id             = 2,
1873         .parent         = &core_l4_ick,
1874         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1875         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1876         .flags          = CLOCK_IN_OMAP343X,
1877         .clkdm_name     = "core_l4_clkdm",
1878         .recalc         = &followparent_recalc,
1879 };
1880
1881 static struct clk i2c1_ick = {
1882         .name           = "i2c_ick",
1883         .id             = 1,
1884         .parent         = &core_l4_ick,
1885         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1886         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1887         .flags          = CLOCK_IN_OMAP343X,
1888         .clkdm_name     = "core_l4_clkdm",
1889         .recalc         = &followparent_recalc,
1890 };
1891
1892 static struct clk uart2_ick = {
1893         .name           = "uart2_ick",
1894         .parent         = &core_l4_ick,
1895         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1896         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1897         .flags          = CLOCK_IN_OMAP343X,
1898         .clkdm_name     = "core_l4_clkdm",
1899         .recalc         = &followparent_recalc,
1900 };
1901
1902 static struct clk uart1_ick = {
1903         .name           = "uart1_ick",
1904         .parent         = &core_l4_ick,
1905         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1906         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1907         .flags          = CLOCK_IN_OMAP343X,
1908         .clkdm_name     = "core_l4_clkdm",
1909         .recalc         = &followparent_recalc,
1910 };
1911
1912 static struct clk gpt11_ick = {
1913         .name           = "gpt11_ick",
1914         .parent         = &core_l4_ick,
1915         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1916         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1917         .flags          = CLOCK_IN_OMAP343X,
1918         .clkdm_name     = "core_l4_clkdm",
1919         .recalc         = &followparent_recalc,
1920 };
1921
1922 static struct clk gpt10_ick = {
1923         .name           = "gpt10_ick",
1924         .parent         = &core_l4_ick,
1925         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1926         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1927         .flags          = CLOCK_IN_OMAP343X,
1928         .clkdm_name     = "core_l4_clkdm",
1929         .recalc         = &followparent_recalc,
1930 };
1931
1932 static struct clk mcbsp5_ick = {
1933         .name           = "mcbsp_ick",
1934         .id             = 5,
1935         .parent         = &core_l4_ick,
1936         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1937         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1938         .flags          = CLOCK_IN_OMAP343X,
1939         .clkdm_name     = "core_l4_clkdm",
1940         .recalc         = &followparent_recalc,
1941 };
1942
1943 static struct clk mcbsp1_ick = {
1944         .name           = "mcbsp_ick",
1945         .id             = 1,
1946         .parent         = &core_l4_ick,
1947         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1948         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1949         .flags          = CLOCK_IN_OMAP343X,
1950         .clkdm_name     = "core_l4_clkdm",
1951         .recalc         = &followparent_recalc,
1952 };
1953
1954 static struct clk fac_ick = {
1955         .name           = "fac_ick",
1956         .parent         = &core_l4_ick,
1957         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1958         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1959         .flags          = CLOCK_IN_OMAP3430ES1,
1960         .clkdm_name     = "core_l4_clkdm",
1961         .recalc         = &followparent_recalc,
1962 };
1963
1964 static struct clk mailboxes_ick = {
1965         .name           = "mailboxes_ick",
1966         .parent         = &core_l4_ick,
1967         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1968         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
1969         .flags          = CLOCK_IN_OMAP343X,
1970         .clkdm_name     = "core_l4_clkdm",
1971         .recalc         = &followparent_recalc,
1972 };
1973
1974 static struct clk omapctrl_ick = {
1975         .name           = "omapctrl_ick",
1976         .parent         = &core_l4_ick,
1977         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1978         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
1979         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1980         .recalc         = &followparent_recalc,
1981 };
1982
1983 /* SSI_L4_ICK based clocks */
1984
1985 static struct clk ssi_l4_ick = {
1986         .name           = "ssi_l4_ick",
1987         .parent         = &l4_ick,
1988         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1989                                 PARENT_CONTROLS_CLOCK,
1990         .clkdm_name     = "core_l4_clkdm",
1991         .recalc         = &followparent_recalc,
1992 };
1993
1994 static struct clk ssi_ick = {
1995         .name           = "ssi_ick",
1996         .parent         = &ssi_l4_ick,
1997         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1998         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1999         .flags          = CLOCK_IN_OMAP343X,
2000         .clkdm_name     = "core_l4_clkdm",
2001         .recalc         = &followparent_recalc,
2002 };
2003
2004 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2005  * but l4_ick makes more sense to me */
2006
2007 static const struct clksel usb_l4_clksel[] = {
2008         { .parent = &l4_ick, .rates = div2_rates },
2009         { .parent = NULL },
2010 };
2011
2012 static struct clk usb_l4_ick = {
2013         .name           = "usb_l4_ick",
2014         .parent         = &l4_ick,
2015         .init           = &omap2_init_clksel_parent,
2016         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2017         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2018         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2019         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2020         .clksel         = usb_l4_clksel,
2021         .flags          = CLOCK_IN_OMAP3430ES1,
2022         .recalc         = &omap2_clksel_recalc,
2023 };
2024
2025 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2026
2027 /* SECURITY_L4_ICK2 based clocks */
2028
2029 static struct clk security_l4_ick2 = {
2030         .name           = "security_l4_ick2",
2031         .parent         = &l4_ick,
2032         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2033                                 PARENT_CONTROLS_CLOCK,
2034         .recalc         = &followparent_recalc,
2035 };
2036
2037 static struct clk aes1_ick = {
2038         .name           = "aes1_ick",
2039         .parent         = &security_l4_ick2,
2040         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2041         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2042         .flags          = CLOCK_IN_OMAP343X,
2043         .recalc         = &followparent_recalc,
2044 };
2045
2046 static struct clk rng_ick = {
2047         .name           = "rng_ick",
2048         .parent         = &security_l4_ick2,
2049         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2050         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2051         .flags          = CLOCK_IN_OMAP343X,
2052         .recalc         = &followparent_recalc,
2053 };
2054
2055 static struct clk sha11_ick = {
2056         .name           = "sha11_ick",
2057         .parent         = &security_l4_ick2,
2058         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2059         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2060         .flags          = CLOCK_IN_OMAP343X,
2061         .recalc         = &followparent_recalc,
2062 };
2063
2064 static struct clk des1_ick = {
2065         .name           = "des1_ick",
2066         .parent         = &security_l4_ick2,
2067         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2068         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2069         .flags          = CLOCK_IN_OMAP343X,
2070         .recalc         = &followparent_recalc,
2071 };
2072
2073 /* DSS */
2074 static const struct clksel dss1_alwon_fck_clksel[] = {
2075         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2076         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2077         { .parent = NULL }
2078 };
2079
2080 static struct clk dss1_alwon_fck = {
2081         .name           = "dss1_alwon_fck",
2082         .parent         = &dpll4_m4x2_ck,
2083         .init           = &omap2_init_clksel_parent,
2084         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2085         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2086         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2087         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2088         .clksel         = dss1_alwon_fck_clksel,
2089         .flags          = CLOCK_IN_OMAP343X,
2090         .clkdm_name     = "dss_clkdm",
2091         .recalc         = &omap2_clksel_recalc,
2092 };
2093
2094 static struct clk dss_tv_fck = {
2095         .name           = "dss_tv_fck",
2096         .parent         = &omap_54m_fck,
2097         .init           = &omap2_init_clk_clkdm,
2098         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2099         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2100         .flags          = CLOCK_IN_OMAP343X,
2101         .clkdm_name     = "dss_clkdm",
2102         .recalc         = &followparent_recalc,
2103 };
2104
2105 static struct clk dss_96m_fck = {
2106         .name           = "dss_96m_fck",
2107         .parent         = &omap_96m_fck,
2108         .init           = &omap2_init_clk_clkdm,
2109         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2110         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2111         .flags          = CLOCK_IN_OMAP343X,
2112         .clkdm_name     = "dss_clkdm",
2113         .recalc         = &followparent_recalc,
2114 };
2115
2116 static struct clk dss2_alwon_fck = {
2117         .name           = "dss2_alwon_fck",
2118         .parent         = &sys_ck,
2119         .init           = &omap2_init_clk_clkdm,
2120         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2121         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2122         .flags          = CLOCK_IN_OMAP343X,
2123         .clkdm_name     = "dss_clkdm",
2124         .recalc         = &followparent_recalc,
2125 };
2126
2127 static struct clk dss_ick = {
2128         /* Handles both L3 and L4 clocks */
2129         .name           = "dss_ick",
2130         .parent         = &l4_ick,
2131         .init           = &omap2_init_clk_clkdm,
2132         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2133         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2134         .flags          = CLOCK_IN_OMAP343X,
2135         .clkdm_name     = "dss_clkdm",
2136         .recalc         = &followparent_recalc,
2137 };
2138
2139 /* CAM */
2140
2141 static const struct clksel cam_mclk_clksel[] = {
2142         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2143         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2144         { .parent = NULL }
2145 };
2146
2147 static struct clk cam_mclk = {
2148         .name           = "cam_mclk",
2149         .parent         = &dpll4_m5x2_ck,
2150         .init           = &omap2_init_clksel_parent,
2151         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2152         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2153         .clksel         = cam_mclk_clksel,
2154         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2155         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2156         .flags          = CLOCK_IN_OMAP343X,
2157         .clkdm_name     = "cam_clkdm",
2158         .recalc         = &omap2_clksel_recalc,
2159 };
2160
2161 static struct clk cam_ick = {
2162         /* Handles both L3 and L4 clocks */
2163         .name           = "cam_ick",
2164         .parent         = &l4_ick,
2165         .init           = &omap2_init_clk_clkdm,
2166         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2167         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2168         .flags          = CLOCK_IN_OMAP343X,
2169         .clkdm_name     = "cam_clkdm",
2170         .recalc         = &followparent_recalc,
2171 };
2172
2173 /* USBHOST - 3430ES2 only */
2174
2175 static struct clk usbhost_120m_fck = {
2176         .name           = "usbhost_120m_fck",
2177         .parent         = &omap_120m_fck,
2178         .init           = &omap2_init_clk_clkdm,
2179         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2180         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2181         .flags          = CLOCK_IN_OMAP3430ES2,
2182         .clkdm_name     = "usbhost_clkdm",
2183         .recalc         = &followparent_recalc,
2184 };
2185
2186 static struct clk usbhost_48m_fck = {
2187         .name           = "usbhost_48m_fck",
2188         .parent         = &omap_48m_fck,
2189         .init           = &omap2_init_clk_clkdm,
2190         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2191         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2192         .flags          = CLOCK_IN_OMAP3430ES2,
2193         .clkdm_name     = "usbhost_clkdm",
2194         .recalc         = &followparent_recalc,
2195 };
2196
2197 static struct clk usbhost_ick = {
2198         /* Handles both L3 and L4 clocks */
2199         .name           = "usbhost_ick",
2200         .parent         = &l4_ick,
2201         .init           = &omap2_init_clk_clkdm,
2202         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2203         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2204         .flags          = CLOCK_IN_OMAP3430ES2,
2205         .clkdm_name     = "usbhost_clkdm",
2206         .recalc         = &followparent_recalc,
2207 };
2208
2209 static struct clk usbhost_sar_fck = {
2210         .name           = "usbhost_sar_fck",
2211         .parent         = &osc_sys_ck,
2212         .init           = &omap2_init_clk_clkdm,
2213         .enable_reg     = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
2214         .enable_bit     = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
2215         .flags          = CLOCK_IN_OMAP3430ES2,
2216         .clkdm_name     = "usbhost_clkdm",
2217         .recalc         = &followparent_recalc,
2218 };
2219
2220 /* WKUP */
2221
2222 static const struct clksel_rate usim_96m_rates[] = {
2223         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2224         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2225         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2226         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2227         { .div = 0 },
2228 };
2229
2230 static const struct clksel_rate usim_120m_rates[] = {
2231         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2232         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2233         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2234         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2235         { .div = 0 },
2236 };
2237
2238 static const struct clksel usim_clksel[] = {
2239         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2240         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2241         { .parent = &sys_ck,            .rates = div2_rates },
2242         { .parent = NULL },
2243 };
2244
2245 /* 3430ES2 only */
2246 static struct clk usim_fck = {
2247         .name           = "usim_fck",
2248         .init           = &omap2_init_clksel_parent,
2249         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2250         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2251         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2252         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2253         .clksel         = usim_clksel,
2254         .flags          = CLOCK_IN_OMAP3430ES2,
2255         .recalc         = &omap2_clksel_recalc,
2256 };
2257
2258 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2259 static struct clk gpt1_fck = {
2260         .name           = "gpt1_fck",
2261         .init           = &omap2_init_clksel_parent,
2262         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2263         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2264         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2265         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2266         .clksel         = omap343x_gpt_clksel,
2267         .flags          = CLOCK_IN_OMAP343X,
2268         .clkdm_name     = "wkup_clkdm",
2269         .recalc         = &omap2_clksel_recalc,
2270 };
2271
2272 static struct clk wkup_32k_fck = {
2273         .name           = "wkup_32k_fck",
2274         .ops            = &clkops_null,
2275         .init           = &omap2_init_clk_clkdm,
2276         .parent         = &omap_32k_fck,
2277         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2278         .clkdm_name     = "wkup_clkdm",
2279         .recalc         = &followparent_recalc,
2280 };
2281
2282 static struct clk gpio1_dbck = {
2283         .name           = "gpio1_dbck",
2284         .parent         = &wkup_32k_fck,
2285         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2286         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2287         .flags          = CLOCK_IN_OMAP343X,
2288         .clkdm_name     = "wkup_clkdm",
2289         .recalc         = &followparent_recalc,
2290 };
2291
2292 static struct clk wdt2_fck = {
2293         .name           = "wdt2_fck",
2294         .parent         = &wkup_32k_fck,
2295         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2296         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2297         .flags          = CLOCK_IN_OMAP343X,
2298         .clkdm_name     = "wkup_clkdm",
2299         .recalc         = &followparent_recalc,
2300 };
2301
2302 static struct clk wkup_l4_ick = {
2303         .name           = "wkup_l4_ick",
2304         .ops            = &clkops_null,
2305         .parent         = &sys_ck,
2306         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2307         .clkdm_name     = "wkup_clkdm",
2308         .recalc         = &followparent_recalc,
2309 };
2310
2311 /* 3430ES2 only */
2312 /* Never specifically named in the TRM, so we have to infer a likely name */
2313 static struct clk usim_ick = {
2314         .name           = "usim_ick",
2315         .parent         = &wkup_l4_ick,
2316         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2317         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2318         .flags          = CLOCK_IN_OMAP3430ES2,
2319         .clkdm_name     = "wkup_clkdm",
2320         .recalc         = &followparent_recalc,
2321 };
2322
2323 static struct clk wdt2_ick = {
2324         .name           = "wdt2_ick",
2325         .parent         = &wkup_l4_ick,
2326         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2327         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2328         .flags          = CLOCK_IN_OMAP343X,
2329         .clkdm_name     = "wkup_clkdm",
2330         .recalc         = &followparent_recalc,
2331 };
2332
2333 static struct clk wdt1_ick = {
2334         .name           = "wdt1_ick",
2335         .parent         = &wkup_l4_ick,
2336         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2337         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2338         .flags          = CLOCK_IN_OMAP343X,
2339         .clkdm_name     = "wkup_clkdm",
2340         .recalc         = &followparent_recalc,
2341 };
2342
2343 static struct clk gpio1_ick = {
2344         .name           = "gpio1_ick",
2345         .parent         = &wkup_l4_ick,
2346         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2347         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2348         .flags          = CLOCK_IN_OMAP343X,
2349         .clkdm_name     = "wkup_clkdm",
2350         .recalc         = &followparent_recalc,
2351 };
2352
2353 static struct clk omap_32ksync_ick = {
2354         .name           = "omap_32ksync_ick",
2355         .parent         = &wkup_l4_ick,
2356         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2357         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2358         .flags          = CLOCK_IN_OMAP343X,
2359         .clkdm_name     = "wkup_clkdm",
2360         .recalc         = &followparent_recalc,
2361 };
2362
2363 /* XXX This clock no longer exists in 3430 TRM rev F */
2364 static struct clk gpt12_ick = {
2365         .name           = "gpt12_ick",
2366         .parent         = &wkup_l4_ick,
2367         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2368         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2369         .flags          = CLOCK_IN_OMAP343X,
2370         .clkdm_name     = "wkup_clkdm",
2371         .recalc         = &followparent_recalc,
2372 };
2373
2374 static struct clk gpt1_ick = {
2375         .name           = "gpt1_ick",
2376         .parent         = &wkup_l4_ick,
2377         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2378         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2379         .flags          = CLOCK_IN_OMAP343X,
2380         .clkdm_name     = "wkup_clkdm",
2381         .recalc         = &followparent_recalc,
2382 };
2383
2384
2385
2386 /* PER clock domain */
2387
2388 static struct clk per_96m_fck = {
2389         .name           = "per_96m_fck",
2390         .parent         = &omap_96m_alwon_fck,
2391         .init           = &omap2_init_clk_clkdm,
2392         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2393                                 PARENT_CONTROLS_CLOCK,
2394         .clkdm_name     = "per_clkdm",
2395         .recalc         = &followparent_recalc,
2396 };
2397
2398 static struct clk per_48m_fck = {
2399         .name           = "per_48m_fck",
2400         .parent         = &omap_48m_fck,
2401         .init           = &omap2_init_clk_clkdm,
2402         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2403                                 PARENT_CONTROLS_CLOCK,
2404         .clkdm_name     = "per_clkdm",
2405         .recalc         = &followparent_recalc,
2406 };
2407
2408 static struct clk uart3_fck = {
2409         .name           = "uart3_fck",
2410         .parent         = &per_48m_fck,
2411         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2412         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2413         .flags          = CLOCK_IN_OMAP343X,
2414         .clkdm_name     = "per_clkdm",
2415         .recalc         = &followparent_recalc,
2416 };
2417
2418 static struct clk gpt2_fck = {
2419         .name           = "gpt2_fck",
2420         .init           = &omap2_init_clksel_parent,
2421         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2422         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2423         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2424         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2425         .clksel         = omap343x_gpt_clksel,
2426         .flags          = CLOCK_IN_OMAP343X,
2427         .clkdm_name     = "per_clkdm",
2428         .recalc         = &omap2_clksel_recalc,
2429 };
2430
2431 static struct clk gpt3_fck = {
2432         .name           = "gpt3_fck",
2433         .init           = &omap2_init_clksel_parent,
2434         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2435         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2436         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2437         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2438         .clksel         = omap343x_gpt_clksel,
2439         .flags          = CLOCK_IN_OMAP343X,
2440         .clkdm_name     = "per_clkdm",
2441         .recalc         = &omap2_clksel_recalc,
2442 };
2443
2444 static struct clk gpt4_fck = {
2445         .name           = "gpt4_fck",
2446         .init           = &omap2_init_clksel_parent,
2447         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2448         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2449         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2450         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2451         .clksel         = omap343x_gpt_clksel,
2452         .flags          = CLOCK_IN_OMAP343X,
2453         .clkdm_name     = "per_clkdm",
2454         .recalc         = &omap2_clksel_recalc,
2455 };
2456
2457 static struct clk gpt5_fck = {
2458         .name           = "gpt5_fck",
2459         .init           = &omap2_init_clksel_parent,
2460         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2461         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2462         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2463         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2464         .clksel         = omap343x_gpt_clksel,
2465         .flags          = CLOCK_IN_OMAP343X,
2466         .clkdm_name     = "per_clkdm",
2467         .recalc         = &omap2_clksel_recalc,
2468 };
2469
2470 static struct clk gpt6_fck = {
2471         .name           = "gpt6_fck",
2472         .init           = &omap2_init_clksel_parent,
2473         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2474         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2475         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2476         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2477         .clksel         = omap343x_gpt_clksel,
2478         .flags          = CLOCK_IN_OMAP343X,
2479         .clkdm_name     = "per_clkdm",
2480         .recalc         = &omap2_clksel_recalc,
2481 };
2482
2483 static struct clk gpt7_fck = {
2484         .name           = "gpt7_fck",
2485         .init           = &omap2_init_clksel_parent,
2486         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2487         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2488         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2489         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2490         .clksel         = omap343x_gpt_clksel,
2491         .flags          = CLOCK_IN_OMAP343X,
2492         .clkdm_name     = "per_clkdm",
2493         .recalc         = &omap2_clksel_recalc,
2494 };
2495
2496 static struct clk gpt8_fck = {
2497         .name           = "gpt8_fck",
2498         .init           = &omap2_init_clksel_parent,
2499         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2500         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2501         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2502         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2503         .clksel         = omap343x_gpt_clksel,
2504         .flags          = CLOCK_IN_OMAP343X,
2505         .clkdm_name     = "per_clkdm",
2506         .recalc         = &omap2_clksel_recalc,
2507 };
2508
2509 static struct clk gpt9_fck = {
2510         .name           = "gpt9_fck",
2511         .init           = &omap2_init_clksel_parent,
2512         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2513         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2514         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2515         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2516         .clksel         = omap343x_gpt_clksel,
2517         .flags          = CLOCK_IN_OMAP343X,
2518         .clkdm_name     = "per_clkdm",
2519         .recalc         = &omap2_clksel_recalc,
2520 };
2521
2522 static struct clk per_32k_alwon_fck = {
2523         .name           = "per_32k_alwon_fck",
2524         .ops            = &clkops_null,
2525         .parent         = &omap_32k_fck,
2526         .clkdm_name     = "per_clkdm",
2527         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2528         .recalc         = &followparent_recalc,
2529 };
2530
2531 static struct clk gpio6_dbck = {
2532         .name           = "gpio6_dbck",
2533         .parent         = &per_32k_alwon_fck,
2534         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2535         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2536         .flags          = CLOCK_IN_OMAP343X,
2537         .clkdm_name     = "per_clkdm",
2538         .recalc         = &followparent_recalc,
2539 };
2540
2541 static struct clk gpio5_dbck = {
2542         .name           = "gpio5_dbck",
2543         .parent         = &per_32k_alwon_fck,
2544         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2545         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2546         .flags          = CLOCK_IN_OMAP343X,
2547         .clkdm_name     = "per_clkdm",
2548         .recalc         = &followparent_recalc,
2549 };
2550
2551 static struct clk gpio4_dbck = {
2552         .name           = "gpio4_dbck",
2553         .parent         = &per_32k_alwon_fck,
2554         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2555         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2556         .flags          = CLOCK_IN_OMAP343X,
2557         .clkdm_name     = "per_clkdm",
2558         .recalc         = &followparent_recalc,
2559 };
2560
2561 static struct clk gpio3_dbck = {
2562         .name           = "gpio3_dbck",
2563         .parent         = &per_32k_alwon_fck,
2564         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2565         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2566         .flags          = CLOCK_IN_OMAP343X,
2567         .clkdm_name     = "per_clkdm",
2568         .recalc         = &followparent_recalc,
2569 };
2570
2571 static struct clk gpio2_dbck = {
2572         .name           = "gpio2_dbck",
2573         .parent         = &per_32k_alwon_fck,
2574         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2575         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2576         .flags          = CLOCK_IN_OMAP343X,
2577         .clkdm_name     = "per_clkdm",
2578         .recalc         = &followparent_recalc,
2579 };
2580
2581 static struct clk wdt3_fck = {
2582         .name           = "wdt3_fck",
2583         .parent         = &per_32k_alwon_fck,
2584         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2585         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2586         .flags          = CLOCK_IN_OMAP343X,
2587         .clkdm_name     = "per_clkdm",
2588         .recalc         = &followparent_recalc,
2589 };
2590
2591 static struct clk per_l4_ick = {
2592         .name           = "per_l4_ick",
2593         .parent         = &l4_ick,
2594         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2595                                 PARENT_CONTROLS_CLOCK,
2596         .clkdm_name     = "per_clkdm",
2597         .recalc         = &followparent_recalc,
2598 };
2599
2600 static struct clk gpio6_ick = {
2601         .name           = "gpio6_ick",
2602         .parent         = &per_l4_ick,
2603         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2604         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2605         .flags          = CLOCK_IN_OMAP343X,
2606         .clkdm_name     = "per_clkdm",
2607         .recalc         = &followparent_recalc,
2608 };
2609
2610 static struct clk gpio5_ick = {
2611         .name           = "gpio5_ick",
2612         .parent         = &per_l4_ick,
2613         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2614         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2615         .flags          = CLOCK_IN_OMAP343X,
2616         .clkdm_name     = "per_clkdm",
2617         .recalc         = &followparent_recalc,
2618 };
2619
2620 static struct clk gpio4_ick = {
2621         .name           = "gpio4_ick",
2622         .parent         = &per_l4_ick,
2623         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2624         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2625         .flags          = CLOCK_IN_OMAP343X,
2626         .clkdm_name     = "per_clkdm",
2627         .recalc         = &followparent_recalc,
2628 };
2629
2630 static struct clk gpio3_ick = {
2631         .name           = "gpio3_ick",
2632         .parent         = &per_l4_ick,
2633         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2634         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2635         .flags          = CLOCK_IN_OMAP343X,
2636         .clkdm_name     = "per_clkdm",
2637         .recalc         = &followparent_recalc,
2638 };
2639
2640 static struct clk gpio2_ick = {
2641         .name           = "gpio2_ick",
2642         .parent         = &per_l4_ick,
2643         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2644         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2645         .flags          = CLOCK_IN_OMAP343X,
2646         .clkdm_name     = "per_clkdm",
2647         .recalc         = &followparent_recalc,
2648 };
2649
2650 static struct clk wdt3_ick = {
2651         .name           = "wdt3_ick",
2652         .parent         = &per_l4_ick,
2653         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2654         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2655         .flags          = CLOCK_IN_OMAP343X,
2656         .clkdm_name     = "per_clkdm",
2657         .recalc         = &followparent_recalc,
2658 };
2659
2660 static struct clk uart3_ick = {
2661         .name           = "uart3_ick",
2662         .parent         = &per_l4_ick,
2663         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2664         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2665         .flags          = CLOCK_IN_OMAP343X,
2666         .clkdm_name     = "per_clkdm",
2667         .recalc         = &followparent_recalc,
2668 };
2669
2670 static struct clk gpt9_ick = {
2671         .name           = "gpt9_ick",
2672         .parent         = &per_l4_ick,
2673         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2674         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2675         .flags          = CLOCK_IN_OMAP343X,
2676         .clkdm_name     = "per_clkdm",
2677         .recalc         = &followparent_recalc,
2678 };
2679
2680 static struct clk gpt8_ick = {
2681         .name           = "gpt8_ick",
2682         .parent         = &per_l4_ick,
2683         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2684         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2685         .flags          = CLOCK_IN_OMAP343X,
2686         .clkdm_name     = "per_clkdm",
2687         .recalc         = &followparent_recalc,
2688 };
2689
2690 static struct clk gpt7_ick = {
2691         .name           = "gpt7_ick",
2692         .parent         = &per_l4_ick,
2693         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2694         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2695         .flags          = CLOCK_IN_OMAP343X,
2696         .clkdm_name     = "per_clkdm",
2697         .recalc         = &followparent_recalc,
2698 };
2699
2700 static struct clk gpt6_ick = {
2701         .name           = "gpt6_ick",
2702         .parent         = &per_l4_ick,
2703         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2704         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2705         .flags          = CLOCK_IN_OMAP343X,
2706         .clkdm_name     = "per_clkdm",
2707         .recalc         = &followparent_recalc,
2708 };
2709
2710 static struct clk gpt5_ick = {
2711         .name           = "gpt5_ick",
2712         .parent         = &per_l4_ick,
2713         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2714         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2715         .flags          = CLOCK_IN_OMAP343X,
2716         .clkdm_name     = "per_clkdm",
2717         .recalc         = &followparent_recalc,
2718 };
2719
2720 static struct clk gpt4_ick = {
2721         .name           = "gpt4_ick",
2722         .parent         = &per_l4_ick,
2723         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2724         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2725         .flags          = CLOCK_IN_OMAP343X,
2726         .clkdm_name     = "per_clkdm",
2727         .recalc         = &followparent_recalc,
2728 };
2729
2730 static struct clk gpt3_ick = {
2731         .name           = "gpt3_ick",
2732         .parent         = &per_l4_ick,
2733         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2734         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2735         .flags          = CLOCK_IN_OMAP343X,
2736         .clkdm_name     = "per_clkdm",
2737         .recalc         = &followparent_recalc,
2738 };
2739
2740 static struct clk gpt2_ick = {
2741         .name           = "gpt2_ick",
2742         .parent         = &per_l4_ick,
2743         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2744         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2745         .flags          = CLOCK_IN_OMAP343X,
2746         .clkdm_name     = "per_clkdm",
2747         .recalc         = &followparent_recalc,
2748 };
2749
2750 static struct clk mcbsp2_ick = {
2751         .name           = "mcbsp_ick",
2752         .id             = 2,
2753         .parent         = &per_l4_ick,
2754         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2755         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2756         .flags          = CLOCK_IN_OMAP343X,
2757         .clkdm_name     = "per_clkdm",
2758         .recalc         = &followparent_recalc,
2759 };
2760
2761 static struct clk mcbsp3_ick = {
2762         .name           = "mcbsp_ick",
2763         .id             = 3,
2764         .parent         = &per_l4_ick,
2765         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2766         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2767         .flags          = CLOCK_IN_OMAP343X,
2768         .clkdm_name     = "per_clkdm",
2769         .recalc         = &followparent_recalc,
2770 };
2771
2772 static struct clk mcbsp4_ick = {
2773         .name           = "mcbsp_ick",
2774         .id             = 4,
2775         .parent         = &per_l4_ick,
2776         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2777         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2778         .flags          = CLOCK_IN_OMAP343X,
2779         .clkdm_name     = "per_clkdm",
2780         .recalc         = &followparent_recalc,
2781 };
2782
2783 static const struct clksel mcbsp_234_clksel[] = {
2784         { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2785         { .parent = &mcbsp_clks,  .rates = common_mcbsp_mcbsp_rates },
2786         { .parent = NULL }
2787 };
2788
2789 static struct clk mcbsp2_fck = {
2790         .name           = "mcbsp_fck",
2791         .id             = 2,
2792         .init           = &omap2_init_clksel_parent,
2793         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2794         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2795         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2796         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2797         .clksel         = mcbsp_234_clksel,
2798         .flags          = CLOCK_IN_OMAP343X,
2799         .clkdm_name     = "per_clkdm",
2800         .recalc         = &omap2_clksel_recalc,
2801 };
2802
2803 static struct clk mcbsp3_fck = {
2804         .name           = "mcbsp_fck",
2805         .id             = 3,
2806         .init           = &omap2_init_clksel_parent,
2807         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2808         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2809         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2810         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2811         .clksel         = mcbsp_234_clksel,
2812         .flags          = CLOCK_IN_OMAP343X,
2813         .clkdm_name     = "per_clkdm",
2814         .recalc         = &omap2_clksel_recalc,
2815 };
2816
2817 static struct clk mcbsp4_fck = {
2818         .name           = "mcbsp_fck",
2819         .id             = 4,
2820         .init           = &omap2_init_clksel_parent,
2821         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2822         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2823         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2824         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2825         .clksel         = mcbsp_234_clksel,
2826         .flags          = CLOCK_IN_OMAP343X,
2827         .clkdm_name     = "per_clkdm",
2828         .recalc         = &omap2_clksel_recalc,
2829 };
2830
2831 /* EMU clocks */
2832
2833 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2834
2835 static const struct clksel_rate emu_src_sys_rates[] = {
2836         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2837         { .div = 0 },
2838 };
2839
2840 static const struct clksel_rate emu_src_core_rates[] = {
2841         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2842         { .div = 0 },
2843 };
2844
2845 static const struct clksel_rate emu_src_per_rates[] = {
2846         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2847         { .div = 0 },
2848 };
2849
2850 static const struct clksel_rate emu_src_mpu_rates[] = {
2851         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2852         { .div = 0 },
2853 };
2854
2855 static const struct clksel emu_src_clksel[] = {
2856         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2857         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2858         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2859         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2860         { .parent = NULL },
2861 };
2862
2863 /*
2864  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2865  * to switch the source of some of the EMU clocks.
2866  * XXX Are there CLKEN bits for these EMU clks?
2867  */
2868 static struct clk emu_src_ck = {
2869         .name           = "emu_src_ck",
2870         .ops            = &clkops_null,
2871         .init           = &omap2_init_clksel_parent,
2872         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2873         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2874         .clksel         = emu_src_clksel,
2875         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2876         .clkdm_name     = "emu_clkdm",
2877         .recalc         = &omap2_clksel_recalc,
2878 };
2879
2880 static const struct clksel_rate pclk_emu_rates[] = {
2881         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2882         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2883         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2884         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2885         { .div = 0 },
2886 };
2887
2888 static const struct clksel pclk_emu_clksel[] = {
2889         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2890         { .parent = NULL },
2891 };
2892
2893 static struct clk pclk_fck = {
2894         .name           = "pclk_fck",
2895         .ops            = &clkops_null,
2896         .init           = &omap2_init_clksel_parent,
2897         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2898         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2899         .clksel         = pclk_emu_clksel,
2900         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2901         .clkdm_name     = "emu_clkdm",
2902         .recalc         = &omap2_clksel_recalc,
2903 };
2904
2905 static const struct clksel_rate pclkx2_emu_rates[] = {
2906         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2907         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2908         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2909         { .div = 0 },
2910 };
2911
2912 static const struct clksel pclkx2_emu_clksel[] = {
2913         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2914         { .parent = NULL },
2915 };
2916
2917 static struct clk pclkx2_fck = {
2918         .name           = "pclkx2_fck",
2919         .ops            = &clkops_null,
2920         .init           = &omap2_init_clksel_parent,
2921         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2922         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2923         .clksel         = pclkx2_emu_clksel,
2924         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2925         .clkdm_name     = "emu_clkdm",
2926         .recalc         = &omap2_clksel_recalc,
2927 };
2928
2929 static const struct clksel atclk_emu_clksel[] = {
2930         { .parent = &emu_src_ck, .rates = div2_rates },
2931         { .parent = NULL },
2932 };
2933
2934 static struct clk atclk_fck = {
2935         .name           = "atclk_fck",
2936         .ops            = &clkops_null,
2937         .init           = &omap2_init_clksel_parent,
2938         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2939         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2940         .clksel         = atclk_emu_clksel,
2941         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2942         .clkdm_name     = "emu_clkdm",
2943         .recalc         = &omap2_clksel_recalc,
2944 };
2945
2946 static struct clk traceclk_src_fck = {
2947         .name           = "traceclk_src_fck",
2948         .ops            = &clkops_null,
2949         .init           = &omap2_init_clksel_parent,
2950         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2951         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2952         .clksel         = emu_src_clksel,
2953         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2954         .clkdm_name     = "emu_clkdm",
2955         .recalc         = &omap2_clksel_recalc,
2956 };
2957
2958 static const struct clksel_rate traceclk_rates[] = {
2959         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2960         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2961         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2962         { .div = 0 },
2963 };
2964
2965 static const struct clksel traceclk_clksel[] = {
2966         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2967         { .parent = NULL },
2968 };
2969
2970 static struct clk traceclk_fck = {
2971         .name           = "traceclk_fck",
2972         .ops            = &clkops_null,
2973         .init           = &omap2_init_clksel_parent,
2974         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2975         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
2976         .clksel         = traceclk_clksel,
2977         .flags          = CLOCK_IN_OMAP343X,
2978         .clkdm_name     = "emu_clkdm",
2979         .recalc         = &omap2_clksel_recalc,
2980 };
2981
2982 /* SR clocks */
2983
2984 /* SmartReflex fclk (VDD1) */
2985 static struct clk sr1_fck = {
2986         .name           = "sr1_fck",
2987         .parent         = &sys_ck,
2988         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2989         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
2990         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2991         .recalc         = &followparent_recalc,
2992 };
2993
2994 /* SmartReflex fclk (VDD2) */
2995 static struct clk sr2_fck = {
2996         .name           = "sr2_fck",
2997         .parent         = &sys_ck,
2998         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2999         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3000         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3001         .recalc         = &followparent_recalc,
3002 };
3003
3004 static struct clk sr_l4_ick = {
3005         .name           = "sr_l4_ick",
3006         .ops            = &clkops_null, /* RMK: missing? */
3007         .parent         = &l4_ick,
3008         .flags          = CLOCK_IN_OMAP343X,
3009         .clkdm_name     = "core_l4_clkdm",
3010         .recalc         = &followparent_recalc,
3011 };
3012
3013 /* SECURE_32K_FCK clocks */
3014
3015 /* XXX This clock no longer exists in 3430 TRM rev F */
3016 static struct clk gpt12_fck = {
3017         .name           = "gpt12_fck",
3018         .ops            = &clkops_null,
3019         .parent         = &secure_32k_fck,
3020         .flags          = CLOCK_IN_OMAP343X,
3021         .recalc         = &followparent_recalc,
3022 };
3023
3024 static struct clk wdt1_fck = {
3025         .name           = "wdt1_fck",
3026         .ops            = &clkops_null,
3027         .parent         = &secure_32k_fck,
3028         .flags          = CLOCK_IN_OMAP343X,
3029         .recalc         = &followparent_recalc,
3030 };
3031
3032 static struct clk *onchip_34xx_clks[] __initdata = {
3033         &omap_32k_fck,
3034         &virt_12m_ck,
3035         &virt_13m_ck,
3036         &virt_16_8m_ck,
3037         &virt_19_2m_ck,
3038         &virt_26m_ck,
3039         &virt_38_4m_ck,
3040         &osc_sys_ck,
3041         &sys_ck,
3042         &sys_altclk,
3043         &mcbsp_clks,
3044         &sys_clkout1,
3045         &dpll1_ck,
3046         &dpll1_x2_ck,
3047         &dpll1_x2m2_ck,
3048         &dpll2_ck,
3049         &dpll2_m2_ck,
3050         &dpll3_ck,
3051         &core_ck,
3052         &dpll3_x2_ck,
3053         &dpll3_m2_ck,
3054         &dpll3_m2x2_ck,
3055         &dpll3_m3_ck,
3056         &dpll3_m3x2_ck,
3057         &emu_core_alwon_ck,
3058         &dpll4_ck,
3059         &dpll4_x2_ck,
3060         &omap_96m_alwon_fck,
3061         &omap_96m_fck,
3062         &cm_96m_fck,
3063         &virt_omap_54m_fck,
3064         &omap_54m_fck,
3065         &omap_48m_fck,
3066         &omap_12m_fck,
3067         &dpll4_m2_ck,
3068         &dpll4_m2x2_ck,
3069         &dpll4_m3_ck,
3070         &dpll4_m3x2_ck,
3071         &dpll4_m4_ck,
3072         &dpll4_m4x2_ck,
3073         &dpll4_m5_ck,
3074         &dpll4_m5x2_ck,
3075         &dpll4_m6_ck,
3076         &dpll4_m6x2_ck,
3077         &emu_per_alwon_ck,
3078         &dpll5_ck,
3079         &dpll5_m2_ck,
3080         &omap_120m_fck,
3081         &clkout2_src_ck,
3082         &sys_clkout2,
3083         &corex2_fck,
3084         &dpll1_fck,
3085         &mpu_ck,
3086         &arm_fck,
3087         &emu_mpu_alwon_ck,
3088         &dpll2_fck,
3089         &iva2_ck,
3090         &l3_ick,
3091         &l4_ick,
3092         &rm_ick,
3093         &gfx_l3_ck,
3094         &gfx_l3_fck,
3095         &gfx_l3_ick,
3096         &gfx_cg1_ck,
3097         &gfx_cg2_ck,
3098         &sgx_fck,
3099         &sgx_ick,
3100         &d2d_26m_fck,
3101         &gpt10_fck,
3102         &gpt11_fck,
3103         &cpefuse_fck,
3104         &ts_fck,
3105         &usbtll_fck,
3106         &core_96m_fck,
3107         &mmchs3_fck,
3108         &mmchs2_fck,
3109         &mspro_fck,
3110         &mmchs1_fck,
3111         &i2c3_fck,
3112         &i2c2_fck,
3113         &i2c1_fck,
3114         &mcbsp5_fck,
3115         &mcbsp1_fck,
3116         &core_48m_fck,
3117         &mcspi4_fck,
3118         &mcspi3_fck,
3119         &mcspi2_fck,
3120         &mcspi1_fck,
3121         &uart2_fck,
3122         &uart1_fck,
3123         &fshostusb_fck,
3124         &core_12m_fck,
3125         &hdq_fck,
3126         &ssi_ssr_fck,
3127         &ssi_sst_fck,
3128         &core_l3_ick,
3129         &hsotgusb_ick,
3130         &sdrc_ick,
3131         &gpmc_fck,
3132         &security_l3_ick,
3133         &pka_ick,
3134         &core_l4_ick,
3135         &usbtll_ick,
3136         &mmchs3_ick,
3137         &icr_ick,
3138         &aes2_ick,
3139         &sha12_ick,
3140         &des2_ick,
3141         &mmchs2_ick,
3142         &mmchs1_ick,
3143         &mspro_ick,
3144         &hdq_ick,
3145         &mcspi4_ick,
3146         &mcspi3_ick,
3147         &mcspi2_ick,
3148         &mcspi1_ick,
3149         &i2c3_ick,
3150         &i2c2_ick,
3151         &i2c1_ick,
3152         &uart2_ick,
3153         &uart1_ick,
3154         &gpt11_ick,
3155         &gpt10_ick,
3156         &mcbsp5_ick,
3157         &mcbsp1_ick,
3158         &fac_ick,
3159         &mailboxes_ick,
3160         &omapctrl_ick,
3161         &ssi_l4_ick,
3162         &ssi_ick,
3163         &usb_l4_ick,
3164         &security_l4_ick2,
3165         &aes1_ick,
3166         &rng_ick,
3167         &sha11_ick,
3168         &des1_ick,
3169         &dss1_alwon_fck,
3170         &dss_tv_fck,
3171         &dss_96m_fck,
3172         &dss2_alwon_fck,
3173         &dss_ick,
3174         &cam_mclk,
3175         &cam_ick,
3176         &usbhost_120m_fck,
3177         &usbhost_48m_fck,
3178         &usbhost_ick,
3179         &usbhost_sar_fck,
3180         &usim_fck,
3181         &gpt1_fck,
3182         &wkup_32k_fck,
3183         &gpio1_dbck,
3184         &wdt2_fck,
3185         &wkup_l4_ick,
3186         &usim_ick,
3187         &wdt2_ick,
3188         &wdt1_ick,
3189         &gpio1_ick,
3190         &omap_32ksync_ick,
3191         &gpt12_ick,
3192         &gpt1_ick,
3193         &per_96m_fck,
3194         &per_48m_fck,
3195         &uart3_fck,
3196         &gpt2_fck,
3197         &gpt3_fck,
3198         &gpt4_fck,
3199         &gpt5_fck,
3200         &gpt6_fck,
3201         &gpt7_fck,
3202         &gpt8_fck,
3203         &gpt9_fck,
3204         &per_32k_alwon_fck,
3205         &gpio6_dbck,
3206         &gpio5_dbck,
3207         &gpio4_dbck,
3208         &gpio3_dbck,
3209         &gpio2_dbck,
3210         &wdt3_fck,
3211         &per_l4_ick,
3212         &gpio6_ick,
3213         &gpio5_ick,
3214         &gpio4_ick,
3215         &gpio3_ick,
3216         &gpio2_ick,
3217         &wdt3_ick,
3218         &uart3_ick,
3219         &gpt9_ick,
3220         &gpt8_ick,
3221         &gpt7_ick,
3222         &gpt6_ick,
3223         &gpt5_ick,
3224         &gpt4_ick,
3225         &gpt3_ick,
3226         &gpt2_ick,
3227         &mcbsp2_ick,
3228         &mcbsp3_ick,
3229         &mcbsp4_ick,
3230         &mcbsp2_fck,
3231         &mcbsp3_fck,
3232         &mcbsp4_fck,
3233         &emu_src_ck,
3234         &pclk_fck,
3235         &pclkx2_fck,
3236         &atclk_fck,
3237         &traceclk_src_fck,
3238         &traceclk_fck,
3239         &sr1_fck,
3240         &sr2_fck,
3241         &sr_l4_ick,
3242         &secure_32k_fck,
3243         &gpt12_fck,
3244         &wdt1_fck,
3245 };
3246
3247 #endif