arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  36 static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
  37
  38 /* Maximum DPLL multiplier, divider values for OMAP3 */
  39 #define OMAP3_MAX_DPLL_MULT             2048
  40 #define OMAP3_MAX_DPLL_DIV              128
  41
  42 /*
  43  * DPLL1 supplies clock to the MPU.
  44  * DPLL2 supplies clock to the IVA2.
  45  * DPLL3 supplies CORE domain clocks.
  46  * DPLL4 supplies peripheral clocks.
  47  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  48  */
  49
  50 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  51 #define DPLL_LOW_POWER_STOP             0x1
  52 #define DPLL_LOW_POWER_BYPASS           0x5
  53 #define DPLL_LOCKED                     0x7
  54
  55 /* PRM CLOCKS */
  56
  57 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  58 static struct clk omap_32k_fck = {
  59         .name           = "omap_32k_fck",
  60         .ops            = &clkops_null,
  61         .rate           = 32768,
  62         .flags          = RATE_FIXED | RATE_PROPAGATES,
  63 };
  64
  65 static struct clk secure_32k_fck = {
  66         .name           = "secure_32k_fck",
  67         .ops            = &clkops_null,
  68         .rate           = 32768,
  69         .flags          = RATE_FIXED | RATE_PROPAGATES,
  70 };
  71
  72 /* Virtual source clocks for osc_sys_ck */
  73 static struct clk virt_12m_ck = {
  74         .name           = "virt_12m_ck",
  75         .ops            = &clkops_null,
  76         .rate           = 12000000,
  77         .flags          = RATE_FIXED | RATE_PROPAGATES,
  78 };
  79
  80 static struct clk virt_13m_ck = {
  81         .name           = "virt_13m_ck",
  82         .ops            = &clkops_null,
  83         .rate           = 13000000,
  84         .flags          = RATE_FIXED | RATE_PROPAGATES,
  85 };
  86
  87 static struct clk virt_16_8m_ck = {
  88         .name           = "virt_16_8m_ck",
  89         .ops            = &clkops_null,
  90         .rate           = 16800000,
  91         .flags          = RATE_FIXED | RATE_PROPAGATES,
  92 };
  93
  94 static struct clk virt_19_2m_ck = {
  95         .name           = "virt_19_2m_ck",
  96         .ops            = &clkops_null,
  97         .rate           = 19200000,
  98         .flags          = RATE_FIXED | RATE_PROPAGATES,
  99 };
 100
 101 static struct clk virt_26m_ck = {
 102         .name           = "virt_26m_ck",
 103         .ops            = &clkops_null,
 104         .rate           = 26000000,
 105         .flags          = RATE_FIXED | RATE_PROPAGATES,
 106 };
 107
 108 static struct clk virt_38_4m_ck = {
 109         .name           = "virt_38_4m_ck",
 110         .ops            = &clkops_null,
 111         .rate           = 38400000,
 112         .flags          = RATE_FIXED | RATE_PROPAGATES,
 113 };
 114
 115 static const struct clksel_rate osc_sys_12m_rates[] = {
 116         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 117         { .div = 0 }
 118 };
 119
 120 static const struct clksel_rate osc_sys_13m_rates[] = {
 121         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 122         { .div = 0 }
 123 };
 124
 125 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 126         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 127         { .div = 0 }
 128 };
 129
 130 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 131         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 132         { .div = 0 }
 133 };
 134
 135 static const struct clksel_rate osc_sys_26m_rates[] = {
 136         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 137         { .div = 0 }
 138 };
 139
 140 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 141         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 142         { .div = 0 }
 143 };
 144
 145 static const struct clksel osc_sys_clksel[] = {
 146         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 147         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 148         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 149         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 150         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 151         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 152         { .parent = NULL },
 153 };
 154
 155 /* Oscillator clock */
 156 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 157 static struct clk osc_sys_ck = {
 158         .name           = "osc_sys_ck",
 159         .ops            = &clkops_null,
 160         .init           = &omap2_init_clksel_parent,
 161         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 162         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 163         .clksel         = osc_sys_clksel,
 164         /* REVISIT: deal with autoextclkmode? */
 165         .flags          = RATE_FIXED | RATE_PROPAGATES,
 166         .recalc         = &omap2_clksel_recalc,
 167 };
 168
 169 static const struct clksel_rate div2_rates[] = {
 170         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 171         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 172         { .div = 0 }
 173 };
 174
 175 static const struct clksel sys_clksel[] = {
 176         { .parent = &osc_sys_ck, .rates = div2_rates },
 177         { .parent = NULL }
 178 };
 179
 180 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 181 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 182 static struct clk sys_ck = {
 183         .name           = "sys_ck",
 184         .ops            = &clkops_null,
 185         .parent         = &osc_sys_ck,
 186         .init           = &omap2_init_clksel_parent,
 187         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 188         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 189         .clksel         = sys_clksel,
 190         .flags          = RATE_PROPAGATES,
 191         .recalc         = &omap2_clksel_recalc,
 192 };
 193
 194 static struct clk sys_altclk = {
 195         .name           = "sys_altclk",
 196         .ops            = &clkops_null,
 197         .flags          = RATE_PROPAGATES,
 198 };
 199
 200 /* Optional external clock input for some McBSPs */
 201 static struct clk mcbsp_clks = {
 202         .name           = "mcbsp_clks",
 203         .ops            = &clkops_null,
 204         .flags          = RATE_PROPAGATES,
 205 };
 206
 207 /* PRM EXTERNAL CLOCK OUTPUT */
 208
 209 static struct clk sys_clkout1 = {
 210         .name           = "sys_clkout1",
 211         .ops            = &clkops_omap2_dflt,
 212         .parent         = &osc_sys_ck,
 213         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 214         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 215         .recalc         = &followparent_recalc,
 216 };
 217
 218 /* DPLLS */
 219
 220 /* CM CLOCKS */
 221
 222 static const struct clksel_rate dpll_bypass_rates[] = {
 223         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 224         { .div = 0 }
 225 };
 226
 227 static const struct clksel_rate dpll_locked_rates[] = {
 228         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 229         { .div = 0 }
 230 };
 231
 232 static const struct clksel_rate div16_dpll_rates[] = {
 233         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 234         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 235         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 236         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 237         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 238         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 239         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 240         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 241         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 242         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 243         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 244         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 245         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 246         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 247         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 248         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 249         { .div = 0 }
 250 };
 251
 252 /* DPLL1 */
 253 /* MPU clock source */
 254 /* Type: DPLL */
 255 static struct dpll_data dpll1_dd = {
 256         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 257         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 258         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 259         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 260         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 261         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 262         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 263         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 264         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 265         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 266         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 267         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 268         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 269         .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
 270         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 271         .max_divider    = OMAP3_MAX_DPLL_DIV,
 272         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 273 };
 274
 275 static struct clk dpll1_ck = {
 276         .name           = "dpll1_ck",
 277         .ops            = &clkops_null,
 278         .parent         = &sys_ck,
 279         .dpll_data      = &dpll1_dd,
 280         .flags          = RATE_PROPAGATES,
 281         .round_rate     = &omap2_dpll_round_rate,
 282         .set_rate       = &omap3_noncore_dpll_set_rate,
 283         .recalc         = &omap3_dpll_recalc,
 284 };
 285
 286 /*
 287  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 288  * DPLL isn't bypassed.
 289  */
 290 static struct clk dpll1_x2_ck = {
 291         .name           = "dpll1_x2_ck",
 292         .ops            = &clkops_null,
 293         .parent         = &dpll1_ck,
 294         .flags          = RATE_PROPAGATES,
 295         .recalc         = &omap3_clkoutx2_recalc,
 296 };
 297
 298 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 299 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 300         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 301         { .parent = NULL }
 302 };
 303
 304 /*
 305  * Does not exist in the TRM - needed to separate the M2 divider from
 306  * bypass selection in mpu_ck
 307  */
 308 static struct clk dpll1_x2m2_ck = {
 309         .name           = "dpll1_x2m2_ck",
 310         .ops            = &clkops_null,
 311         .parent         = &dpll1_x2_ck,
 312         .init           = &omap2_init_clksel_parent,
 313         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 314         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 315         .clksel         = div16_dpll1_x2m2_clksel,
 316         .flags          = RATE_PROPAGATES,
 317         .recalc         = &omap2_clksel_recalc,
 318 };
 319
 320 /* DPLL2 */
 321 /* IVA2 clock source */
 322 /* Type: DPLL */
 323
 324 static struct dpll_data dpll2_dd = {
 325         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 326         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 327         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 328         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 329         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 330         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 331         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 332                                 (1 << DPLL_LOW_POWER_BYPASS),
 333         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 334         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 335         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 336         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 337         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 338         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 339         .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
 340         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 341         .max_divider    = OMAP3_MAX_DPLL_DIV,
 342         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 343 };
 344
 345 static struct clk dpll2_ck = {
 346         .name           = "dpll2_ck",
 347         .ops            = &clkops_noncore_dpll_ops,
 348         .parent         = &sys_ck,
 349         .dpll_data      = &dpll2_dd,
 350         .flags          = RATE_PROPAGATES,
 351         .round_rate     = &omap2_dpll_round_rate,
 352         .set_rate       = &omap3_noncore_dpll_set_rate,
 353         .recalc         = &omap3_dpll_recalc,
 354 };
 355
 356 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 357         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 358         { .parent = NULL }
 359 };
 360
 361 /*
 362  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 363  * or CLKOUTX2. CLKOUT seems most plausible.
 364  */
 365 static struct clk dpll2_m2_ck = {
 366         .name           = "dpll2_m2_ck",
 367         .ops            = &clkops_null,
 368         .parent         = &dpll2_ck,
 369         .init           = &omap2_init_clksel_parent,
 370         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 371                                           OMAP3430_CM_CLKSEL2_PLL),
 372         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 373         .clksel         = div16_dpll2_m2x2_clksel,
 374         .flags          = RATE_PROPAGATES,
 375         .recalc         = &omap2_clksel_recalc,
 376 };
 377
 378 /*
 379  * DPLL3
 380  * Source clock for all interfaces and for some device fclks
 381  * REVISIT: Also supports fast relock bypass - not included below
 382  */
 383 static struct dpll_data dpll3_dd = {
 384         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 385         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 386         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 387         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 388         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 389         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 390         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 391         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 392         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 393         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 394         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 395         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 396         .max_divider    = OMAP3_MAX_DPLL_DIV,
 397         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 398 };
 399
 400 static struct clk dpll3_ck = {
 401         .name           = "dpll3_ck",
 402         .ops            = &clkops_null,
 403         .parent         = &sys_ck,
 404         .dpll_data      = &dpll3_dd,
 405         .flags          = RATE_PROPAGATES,
 406         .round_rate     = &omap2_dpll_round_rate,
 407         .recalc         = &omap3_dpll_recalc,
 408 };
 409
 410 /*
 411  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 412  * DPLL isn't bypassed
 413  */
 414 static struct clk dpll3_x2_ck = {
 415         .name           = "dpll3_x2_ck",
 416         .ops            = &clkops_null,
 417         .parent         = &dpll3_ck,
 418         .flags          = RATE_PROPAGATES,
 419         .recalc         = &omap3_clkoutx2_recalc,
 420 };
 421
 422 static const struct clksel_rate div31_dpll3_rates[] = {
 423         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 424         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 425         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 426         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 427         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 428         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 429         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 430         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 431         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 432         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 433         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 434         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 435         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 436         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 437         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 438         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 439         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 440         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 441         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 442         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 443         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 444         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 445         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 446         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 447         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 448         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 449         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 450         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 451         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 452         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 453         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 454         { .div = 0 },
 455 };
 456
 457 static const struct clksel div31_dpll3m2_clksel[] = {
 458         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 459         { .parent = NULL }
 460 };
 461
 462 /*
 463  * DPLL3 output M2
 464  * REVISIT: This DPLL output divider must be changed in SRAM, so until
 465  * that code is ready, this should remain a 'read-only' clksel clock.
 466  */
 467 static struct clk dpll3_m2_ck = {
 468         .name           = "dpll3_m2_ck",
 469         .ops            = &clkops_null,
 470         .parent         = &dpll3_ck,
 471         .init           = &omap2_init_clksel_parent,
 472         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 473         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 474         .clksel         = div31_dpll3m2_clksel,
 475         .flags          = RATE_PROPAGATES,
 476         .recalc         = &omap2_clksel_recalc,
 477 };
 478
 479 static const struct clksel core_ck_clksel[] = {
 480         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 481         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 482         { .parent = NULL }
 483 };
 484
 485 static struct clk core_ck = {
 486         .name           = "core_ck",
 487         .ops            = &clkops_null,
 488         .init           = &omap2_init_clksel_parent,
 489         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 490         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 491         .clksel         = core_ck_clksel,
 492         .flags          = RATE_PROPAGATES,
 493         .recalc         = &omap2_clksel_recalc,
 494 };
 495
 496 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 497         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 498         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 499         { .parent = NULL }
 500 };
 501
 502 static struct clk dpll3_m2x2_ck = {
 503         .name           = "dpll3_m2x2_ck",
 504         .ops            = &clkops_null,
 505         .init           = &omap2_init_clksel_parent,
 506         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 507         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 508         .clksel         = dpll3_m2x2_ck_clksel,
 509         .flags          = RATE_PROPAGATES,
 510         .recalc         = &omap2_clksel_recalc,
 511 };
 512
 513 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 514 static const struct clksel div16_dpll3_clksel[] = {
 515         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 516         { .parent = NULL }
 517 };
 518
 519 /* This virtual clock is the source for dpll3_m3x2_ck */
 520 static struct clk dpll3_m3_ck = {
 521         .name           = "dpll3_m3_ck",
 522         .ops            = &clkops_null,
 523         .parent         = &dpll3_ck,
 524         .init           = &omap2_init_clksel_parent,
 525         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 526         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 527         .clksel         = div16_dpll3_clksel,
 528         .flags          = RATE_PROPAGATES,
 529         .recalc         = &omap2_clksel_recalc,
 530 };
 531
 532 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 533 static struct clk dpll3_m3x2_ck = {
 534         .name           = "dpll3_m3x2_ck",
 535         .ops            = &clkops_omap2_dflt_wait,
 536         .parent         = &dpll3_m3_ck,
 537         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 538         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 539         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 540         .recalc         = &omap3_clkoutx2_recalc,
 541 };
 542
 543 static const struct clksel emu_core_alwon_ck_clksel[] = {
 544         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 545         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 546         { .parent = NULL }
 547 };
 548
 549 static struct clk emu_core_alwon_ck = {
 550         .name           = "emu_core_alwon_ck",
 551         .ops            = &clkops_null,
 552         .parent         = &dpll3_m3x2_ck,
 553         .init           = &omap2_init_clksel_parent,
 554         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 555         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 556         .clksel         = emu_core_alwon_ck_clksel,
 557         .flags          = RATE_PROPAGATES,
 558         .recalc         = &omap2_clksel_recalc,
 559 };
 560
 561 /* DPLL4 */
 562 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 563 /* Type: DPLL */
 564 static struct dpll_data dpll4_dd = {
 565         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 566         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 567         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 568         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 569         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 570         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 571         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 572         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 573         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 574         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 575         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 576         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 577         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 578         .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
 579         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 580         .max_divider    = OMAP3_MAX_DPLL_DIV,
 581         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 582 };
 583
 584 static struct clk dpll4_ck = {
 585         .name           = "dpll4_ck",
 586         .ops            = &clkops_noncore_dpll_ops,
 587         .parent         = &sys_ck,
 588         .dpll_data      = &dpll4_dd,
 589         .flags          = RATE_PROPAGATES,
 590         .round_rate     = &omap2_dpll_round_rate,
 591         .set_rate       = &omap3_dpll4_set_rate,
 592         .recalc         = &omap3_dpll_recalc,
 593 };
 594
 595 /*
 596  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 597  * DPLL isn't bypassed --
 598  * XXX does this serve any downstream clocks?
 599  */
 600 static struct clk dpll4_x2_ck = {
 601         .name           = "dpll4_x2_ck",
 602         .ops            = &clkops_null,
 603         .parent         = &dpll4_ck,
 604         .flags          = RATE_PROPAGATES,
 605         .recalc         = &omap3_clkoutx2_recalc,
 606 };
 607
 608 static const struct clksel div16_dpll4_clksel[] = {
 609         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 610         { .parent = NULL }
 611 };
 612
 613 /* This virtual clock is the source for dpll4_m2x2_ck */
 614 static struct clk dpll4_m2_ck = {
 615         .name           = "dpll4_m2_ck",
 616         .ops            = &clkops_null,
 617         .parent         = &dpll4_ck,
 618         .init           = &omap2_init_clksel_parent,
 619         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 620         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 621         .clksel         = div16_dpll4_clksel,
 622         .flags          = RATE_PROPAGATES,
 623         .recalc         = &omap2_clksel_recalc,
 624 };
 625
 626 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 627 static struct clk dpll4_m2x2_ck = {
 628         .name           = "dpll4_m2x2_ck",
 629         .ops            = &clkops_omap2_dflt_wait,
 630         .parent         = &dpll4_m2_ck,
 631         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 632         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 633         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 634         .recalc         = &omap3_clkoutx2_recalc,
 635 };
 636
 637 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 638         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 639         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 640         { .parent = NULL }
 641 };
 642
 643 static struct clk omap_96m_alwon_fck = {
 644         .name           = "omap_96m_alwon_fck",
 645         .ops            = &clkops_null,
 646         .parent         = &dpll4_m2x2_ck,
 647         .init           = &omap2_init_clksel_parent,
 648         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 649         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 650         .clksel         = omap_96m_alwon_fck_clksel,
 651         .flags          = RATE_PROPAGATES,
 652         .recalc         = &omap2_clksel_recalc,
 653 };
 654
 655 static struct clk omap_96m_fck = {
 656         .name           = "omap_96m_fck",
 657         .ops            = &clkops_null,
 658         .parent         = &omap_96m_alwon_fck,
 659         .flags          = RATE_PROPAGATES,
 660         .recalc         = &followparent_recalc,
 661 };
 662
 663 static const struct clksel cm_96m_fck_clksel[] = {
 664         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 665         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 666         { .parent = NULL }
 667 };
 668
 669 static struct clk cm_96m_fck = {
 670         .name           = "cm_96m_fck",
 671         .ops            = &clkops_null,
 672         .parent         = &dpll4_m2x2_ck,
 673         .init           = &omap2_init_clksel_parent,
 674         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 675         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 676         .clksel         = cm_96m_fck_clksel,
 677         .flags          = RATE_PROPAGATES,
 678         .recalc         = &omap2_clksel_recalc,
 679 };
 680
 681 /* This virtual clock is the source for dpll4_m3x2_ck */
 682 static struct clk dpll4_m3_ck = {
 683         .name           = "dpll4_m3_ck",
 684         .ops            = &clkops_null,
 685         .parent         = &dpll4_ck,
 686         .init           = &omap2_init_clksel_parent,
 687         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 688         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 689         .clksel         = div16_dpll4_clksel,
 690         .flags          = RATE_PROPAGATES,
 691         .recalc         = &omap2_clksel_recalc,
 692 };
 693
 694 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 695 static struct clk dpll4_m3x2_ck = {
 696         .name           = "dpll4_m3x2_ck",
 697         .ops            = &clkops_omap2_dflt_wait,
 698         .parent         = &dpll4_m3_ck,
 699         .init           = &omap2_init_clksel_parent,
 700         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 701         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 702         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 703         .recalc         = &omap3_clkoutx2_recalc,
 704 };
 705
 706 static const struct clksel virt_omap_54m_fck_clksel[] = {
 707         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 708         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 709         { .parent = NULL }
 710 };
 711
 712 static struct clk virt_omap_54m_fck = {
 713         .name           = "virt_omap_54m_fck",
 714         .ops            = &clkops_null,
 715         .parent         = &dpll4_m3x2_ck,
 716         .init           = &omap2_init_clksel_parent,
 717         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 718         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 719         .clksel         = virt_omap_54m_fck_clksel,
 720         .flags          = RATE_PROPAGATES,
 721         .recalc         = &omap2_clksel_recalc,
 722 };
 723
 724 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 725         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 726         { .div = 0 }
 727 };
 728
 729 static const struct clksel_rate omap_54m_alt_rates[] = {
 730         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 731         { .div = 0 }
 732 };
 733
 734 static const struct clksel omap_54m_clksel[] = {
 735         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 736         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 737         { .parent = NULL }
 738 };
 739
 740 static struct clk omap_54m_fck = {
 741         .name           = "omap_54m_fck",
 742         .ops            = &clkops_null,
 743         .init           = &omap2_init_clksel_parent,
 744         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 745         .clksel_mask    = OMAP3430_SOURCE_54M,
 746         .clksel         = omap_54m_clksel,
 747         .flags          = RATE_PROPAGATES,
 748         .recalc         = &omap2_clksel_recalc,
 749 };
 750
 751 static const struct clksel_rate omap_48m_96md2_rates[] = {
 752         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 753         { .div = 0 }
 754 };
 755
 756 static const struct clksel_rate omap_48m_alt_rates[] = {
 757         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 758         { .div = 0 }
 759 };
 760
 761 static const struct clksel omap_48m_clksel[] = {
 762         { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
 763         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 764         { .parent = NULL }
 765 };
 766
 767 static struct clk omap_48m_fck = {
 768         .name           = "omap_48m_fck",
 769         .ops            = &clkops_null,
 770         .init           = &omap2_init_clksel_parent,
 771         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 772         .clksel_mask    = OMAP3430_SOURCE_48M,
 773         .clksel         = omap_48m_clksel,
 774         .flags          = RATE_PROPAGATES,
 775         .recalc         = &omap2_clksel_recalc,
 776 };
 777
 778 static struct clk omap_12m_fck = {
 779         .name           = "omap_12m_fck",
 780         .ops            = &clkops_null,
 781         .parent         = &omap_48m_fck,
 782         .fixed_div      = 4,
 783         .flags          = RATE_PROPAGATES,
 784         .recalc         = &omap2_fixed_divisor_recalc,
 785 };
 786
 787 /* This virstual clock is the source for dpll4_m4x2_ck */
 788 static struct clk dpll4_m4_ck = {
 789         .name           = "dpll4_m4_ck",
 790         .ops            = &clkops_null,
 791         .parent         = &dpll4_ck,
 792         .init           = &omap2_init_clksel_parent,
 793         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 794         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 795         .clksel         = div16_dpll4_clksel,
 796         .flags          = RATE_PROPAGATES,
 797         .recalc         = &omap2_clksel_recalc,
 798 };
 799
 800 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 801 static struct clk dpll4_m4x2_ck = {
 802         .name           = "dpll4_m4x2_ck",
 803         .ops            = &clkops_omap2_dflt_wait,
 804         .parent         = &dpll4_m4_ck,
 805         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 806         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 807         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 808         .recalc         = &omap3_clkoutx2_recalc,
 809 };
 810
 811 /* This virtual clock is the source for dpll4_m5x2_ck */
 812 static struct clk dpll4_m5_ck = {
 813         .name           = "dpll4_m5_ck",
 814         .ops            = &clkops_null,
 815         .parent         = &dpll4_ck,
 816         .init           = &omap2_init_clksel_parent,
 817         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 818         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 819         .clksel         = div16_dpll4_clksel,
 820         .flags          = RATE_PROPAGATES,
 821         .recalc         = &omap2_clksel_recalc,
 822 };
 823
 824 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 825 static struct clk dpll4_m5x2_ck = {
 826         .name           = "dpll4_m5x2_ck",
 827         .ops            = &clkops_omap2_dflt_wait,
 828         .parent         = &dpll4_m5_ck,
 829         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 830         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 831         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 832         .recalc         = &omap3_clkoutx2_recalc,
 833 };
 834
 835 /* This virtual clock is the source for dpll4_m6x2_ck */
 836 static struct clk dpll4_m6_ck = {
 837         .name           = "dpll4_m6_ck",
 838         .ops            = &clkops_null,
 839         .parent         = &dpll4_ck,
 840         .init           = &omap2_init_clksel_parent,
 841         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 842         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 843         .clksel         = div16_dpll4_clksel,
 844         .flags          = RATE_PROPAGATES,
 845         .recalc         = &omap2_clksel_recalc,
 846 };
 847
 848 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 849 static struct clk dpll4_m6x2_ck = {
 850         .name           = "dpll4_m6x2_ck",
 851         .ops            = &clkops_omap2_dflt_wait,
 852         .parent         = &dpll4_m6_ck,
 853         .init           = &omap2_init_clksel_parent,
 854         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 855         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 856         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 857         .recalc         = &omap3_clkoutx2_recalc,
 858 };
 859
 860 static struct clk emu_per_alwon_ck = {
 861         .name           = "emu_per_alwon_ck",
 862         .ops            = &clkops_null,
 863         .parent         = &dpll4_m6x2_ck,
 864         .flags          = RATE_PROPAGATES,
 865         .recalc         = &followparent_recalc,
 866 };
 867
 868 /* DPLL5 */
 869 /* Supplies 120MHz clock, USIM source clock */
 870 /* Type: DPLL */
 871 /* 3430ES2 only */
 872 static struct dpll_data dpll5_dd = {
 873         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 874         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 875         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 876         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 877         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 878         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 879         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 880         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 881         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 882         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 883         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 884         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 885         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 886         .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
 887         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 888         .max_divider    = OMAP3_MAX_DPLL_DIV,
 889         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 890 };
 891
 892 static struct clk dpll5_ck = {
 893         .name           = "dpll5_ck",
 894         .ops            = &clkops_noncore_dpll_ops,
 895         .parent         = &sys_ck,
 896         .dpll_data      = &dpll5_dd,
 897         .flags          = RATE_PROPAGATES,
 898         .round_rate     = &omap2_dpll_round_rate,
 899         .set_rate       = &omap3_noncore_dpll_set_rate,
 900         .recalc         = &omap3_dpll_recalc,
 901 };
 902
 903 static const struct clksel div16_dpll5_clksel[] = {
 904         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 905         { .parent = NULL }
 906 };
 907
 908 static struct clk dpll5_m2_ck = {
 909         .name           = "dpll5_m2_ck",
 910         .ops            = &clkops_null,
 911         .parent         = &dpll5_ck,
 912         .init           = &omap2_init_clksel_parent,
 913         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 914         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 915         .clksel         = div16_dpll5_clksel,
 916         .flags          = RATE_PROPAGATES,
 917         .recalc         = &omap2_clksel_recalc,
 918 };
 919
 920 static const struct clksel omap_120m_fck_clksel[] = {
 921         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 922         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
 923         { .parent = NULL }
 924 };
 925
 926 static struct clk omap_120m_fck = {
 927         .name           = "omap_120m_fck",
 928         .ops            = &clkops_null,
 929         .parent         = &dpll5_m2_ck,
 930         .init           = &omap2_init_clksel_parent,
 931         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 932         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 933         .clksel         = omap_120m_fck_clksel,
 934         .flags          = RATE_PROPAGATES,
 935         .recalc         = &omap2_clksel_recalc,
 936 };
 937
 938 /* CM EXTERNAL CLOCK OUTPUTS */
 939
 940 static const struct clksel_rate clkout2_src_core_rates[] = {
 941         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 942         { .div = 0 }
 943 };
 944
 945 static const struct clksel_rate clkout2_src_sys_rates[] = {
 946         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 947         { .div = 0 }
 948 };
 949
 950 static const struct clksel_rate clkout2_src_96m_rates[] = {
 951         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 952         { .div = 0 }
 953 };
 954
 955 static const struct clksel_rate clkout2_src_54m_rates[] = {
 956         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 957         { .div = 0 }
 958 };
 959
 960 static const struct clksel clkout2_src_clksel[] = {
 961         { .parent = &core_ck,             .rates = clkout2_src_core_rates },
 962         { .parent = &sys_ck,              .rates = clkout2_src_sys_rates },
 963         { .parent = &omap_96m_alwon_fck,  .rates = clkout2_src_96m_rates },
 964         { .parent = &omap_54m_fck,        .rates = clkout2_src_54m_rates },
 965         { .parent = NULL }
 966 };
 967
 968 static struct clk clkout2_src_ck = {
 969         .name           = "clkout2_src_ck",
 970         .ops            = &clkops_omap2_dflt,
 971         .init           = &omap2_init_clksel_parent,
 972         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
 973         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 974         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 975         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 976         .clksel         = clkout2_src_clksel,
 977         .flags          = RATE_PROPAGATES,
 978         .recalc         = &omap2_clksel_recalc,
 979 };
 980
 981 static const struct clksel_rate sys_clkout2_rates[] = {
 982         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 983         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 984         { .div = 4, .val = 2, .flags = RATE_IN_343X },
 985         { .div = 8, .val = 3, .flags = RATE_IN_343X },
 986         { .div = 16, .val = 4, .flags = RATE_IN_343X },
 987         { .div = 0 },
 988 };
 989
 990 static const struct clksel sys_clkout2_clksel[] = {
 991         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
 992         { .parent = NULL },
 993 };
 994
 995 static struct clk sys_clkout2 = {
 996         .name           = "sys_clkout2",
 997         .ops            = &clkops_null,
 998         .init           = &omap2_init_clksel_parent,
 999         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
1000         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1001         .clksel         = sys_clkout2_clksel,
1002         .recalc         = &omap2_clksel_recalc,
1003 };
1004
1005 /* CM OUTPUT CLOCKS */
1006
1007 static struct clk corex2_fck = {
1008         .name           = "corex2_fck",
1009         .ops            = &clkops_null,
1010         .parent         = &dpll3_m2x2_ck,
1011         .flags          = RATE_PROPAGATES,
1012         .recalc         = &followparent_recalc,
1013 };
1014
1015 /* DPLL power domain clock controls */
1016
1017 static const struct clksel div2_core_clksel[] = {
1018         { .parent = &core_ck, .rates = div2_rates },
1019         { .parent = NULL }
1020 };
1021
1022 /*
1023  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1024  * may be inconsistent here?
1025  */
1026 static struct clk dpll1_fck = {
1027         .name           = "dpll1_fck",
1028         .ops            = &clkops_null,
1029         .parent         = &core_ck,
1030         .init           = &omap2_init_clksel_parent,
1031         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1032         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1033         .clksel         = div2_core_clksel,
1034         .flags          = RATE_PROPAGATES,
1035         .recalc         = &omap2_clksel_recalc,
1036 };
1037
1038 /*
1039  * MPU clksel:
1040  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1041  * derives from the high-frequency bypass clock originating from DPLL3,
1042  * called 'dpll1_fck'
1043  */
1044 static const struct clksel mpu_clksel[] = {
1045         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1046         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1047         { .parent = NULL }
1048 };
1049
1050 static struct clk mpu_ck = {
1051         .name           = "mpu_ck",
1052         .ops            = &clkops_null,
1053         .parent         = &dpll1_x2m2_ck,
1054         .init           = &omap2_init_clksel_parent,
1055         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1056         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1057         .clksel         = mpu_clksel,
1058         .flags          = RATE_PROPAGATES,
1059         .clkdm_name     = "mpu_clkdm",
1060         .recalc         = &omap2_clksel_recalc,
1061 };
1062
1063 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1064 static const struct clksel_rate arm_fck_rates[] = {
1065         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1066         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1067         { .div = 0 },
1068 };
1069
1070 static const struct clksel arm_fck_clksel[] = {
1071         { .parent = &mpu_ck, .rates = arm_fck_rates },
1072         { .parent = NULL }
1073 };
1074
1075 static struct clk arm_fck = {
1076         .name           = "arm_fck",
1077         .ops            = &clkops_null,
1078         .parent         = &mpu_ck,
1079         .init           = &omap2_init_clksel_parent,
1080         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1081         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1082         .clksel         = arm_fck_clksel,
1083         .flags          = RATE_PROPAGATES,
1084         .recalc         = &omap2_clksel_recalc,
1085 };
1086
1087 /* XXX What about neon_clkdm ? */
1088
1089 /*
1090  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1091  * although it is referenced - so this is a guess
1092  */
1093 static struct clk emu_mpu_alwon_ck = {
1094         .name           = "emu_mpu_alwon_ck",
1095         .ops            = &clkops_null,
1096         .parent         = &mpu_ck,
1097         .flags          = RATE_PROPAGATES,
1098         .recalc         = &followparent_recalc,
1099 };
1100
1101 static struct clk dpll2_fck = {
1102         .name           = "dpll2_fck",
1103         .ops            = &clkops_null,
1104         .parent         = &core_ck,
1105         .init           = &omap2_init_clksel_parent,
1106         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1107         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1108         .clksel         = div2_core_clksel,
1109         .flags          = RATE_PROPAGATES,
1110         .recalc         = &omap2_clksel_recalc,
1111 };
1112
1113 /*
1114  * IVA2 clksel:
1115  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1116  * derives from the high-frequency bypass clock originating from DPLL3,
1117  * called 'dpll2_fck'
1118  */
1119
1120 static const struct clksel iva2_clksel[] = {
1121         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1122         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1123         { .parent = NULL }
1124 };
1125
1126 static struct clk iva2_ck = {
1127         .name           = "iva2_ck",
1128         .ops            = &clkops_omap2_dflt_wait,
1129         .parent         = &dpll2_m2_ck,
1130         .init           = &omap2_init_clksel_parent,
1131         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1132         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1133         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1134                                           OMAP3430_CM_IDLEST_PLL),
1135         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1136         .clksel         = iva2_clksel,
1137         .flags          = RATE_PROPAGATES,
1138         .clkdm_name     = "iva2_clkdm",
1139         .recalc         = &omap2_clksel_recalc,
1140 };
1141
1142 /* Common interface clocks */
1143
1144 static struct clk l3_ick = {
1145         .name           = "l3_ick",
1146         .ops            = &clkops_null,
1147         .parent         = &core_ck,
1148         .init           = &omap2_init_clksel_parent,
1149         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1150         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1151         .clksel         = div2_core_clksel,
1152         .flags          = RATE_PROPAGATES,
1153         .clkdm_name     = "core_l3_clkdm",
1154         .recalc         = &omap2_clksel_recalc,
1155 };
1156
1157 static const struct clksel div2_l3_clksel[] = {
1158         { .parent = &l3_ick, .rates = div2_rates },
1159         { .parent = NULL }
1160 };
1161
1162 static struct clk l4_ick = {
1163         .name           = "l4_ick",
1164         .ops            = &clkops_null,
1165         .parent         = &l3_ick,
1166         .init           = &omap2_init_clksel_parent,
1167         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1168         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1169         .clksel         = div2_l3_clksel,
1170         .flags          = RATE_PROPAGATES,
1171         .clkdm_name     = "core_l4_clkdm",
1172         .recalc         = &omap2_clksel_recalc,
1173
1174 };
1175
1176 static const struct clksel div2_l4_clksel[] = {
1177         { .parent = &l4_ick, .rates = div2_rates },
1178         { .parent = NULL }
1179 };
1180
1181 static struct clk rm_ick = {
1182         .name           = "rm_ick",
1183         .ops            = &clkops_null,
1184         .parent         = &l4_ick,
1185         .init           = &omap2_init_clksel_parent,
1186         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1187         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1188         .clksel         = div2_l4_clksel,
1189         .recalc         = &omap2_clksel_recalc,
1190 };
1191
1192 /* GFX power domain */
1193
1194 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1195
1196 static const struct clksel gfx_l3_clksel[] = {
1197         { .parent = &l3_ick, .rates = gfx_l3_rates },
1198         { .parent = NULL }
1199 };
1200
1201 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1202 static struct clk gfx_l3_ck = {
1203         .name           = "gfx_l3_ck",
1204         .ops            = &clkops_omap2_dflt_wait,
1205         .parent         = &l3_ick,
1206         .init           = &omap2_init_clksel_parent,
1207         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1208         .enable_bit     = OMAP_EN_GFX_SHIFT,
1209         .recalc         = &followparent_recalc,
1210 };
1211
1212 static struct clk gfx_l3_fck = {
1213         .name           = "gfx_l3_fck",
1214         .ops            = &clkops_null,
1215         .parent         = &gfx_l3_ck,
1216         .init           = &omap2_init_clksel_parent,
1217         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1218         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1219         .clksel         = gfx_l3_clksel,
1220         .flags          = RATE_PROPAGATES,
1221         .clkdm_name     = "gfx_3430es1_clkdm",
1222         .recalc         = &omap2_clksel_recalc,
1223 };
1224
1225 static struct clk gfx_l3_ick = {
1226         .name           = "gfx_l3_ick",
1227         .ops            = &clkops_null,
1228         .parent         = &gfx_l3_ck,
1229         .clkdm_name     = "gfx_3430es1_clkdm",
1230         .recalc         = &followparent_recalc,
1231 };
1232
1233 static struct clk gfx_cg1_ck = {
1234         .name           = "gfx_cg1_ck",
1235         .ops            = &clkops_omap2_dflt_wait,
1236         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1237         .init           = &omap2_init_clk_clkdm,
1238         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1239         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1240         .clkdm_name     = "gfx_3430es1_clkdm",
1241         .recalc         = &followparent_recalc,
1242 };
1243
1244 static struct clk gfx_cg2_ck = {
1245         .name           = "gfx_cg2_ck",
1246         .ops            = &clkops_omap2_dflt_wait,
1247         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1248         .init           = &omap2_init_clk_clkdm,
1249         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1250         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1251         .clkdm_name     = "gfx_3430es1_clkdm",
1252         .recalc         = &followparent_recalc,
1253 };
1254
1255 /* SGX power domain - 3430ES2 only */
1256
1257 static const struct clksel_rate sgx_core_rates[] = {
1258         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1259         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1260         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1261         { .div = 0 },
1262 };
1263
1264 static const struct clksel_rate sgx_96m_rates[] = {
1265         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1266         { .div = 0 },
1267 };
1268
1269 static const struct clksel sgx_clksel[] = {
1270         { .parent = &core_ck,    .rates = sgx_core_rates },
1271         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1272         { .parent = NULL },
1273 };
1274
1275 static struct clk sgx_fck = {
1276         .name           = "sgx_fck",
1277         .ops            = &clkops_omap2_dflt_wait,
1278         .init           = &omap2_init_clksel_parent,
1279         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1280         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1281         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1282         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1283         .clksel         = sgx_clksel,
1284         .clkdm_name     = "sgx_clkdm",
1285         .recalc         = &omap2_clksel_recalc,
1286 };
1287
1288 static struct clk sgx_ick = {
1289         .name           = "sgx_ick",
1290         .ops            = &clkops_omap2_dflt_wait,
1291         .parent         = &l3_ick,
1292         .init           = &omap2_init_clk_clkdm,
1293         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1294         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1295         .clkdm_name     = "sgx_clkdm",
1296         .recalc         = &followparent_recalc,
1297 };
1298
1299 /* CORE power domain */
1300
1301 static struct clk d2d_26m_fck = {
1302         .name           = "d2d_26m_fck",
1303         .ops            = &clkops_omap2_dflt_wait,
1304         .parent         = &sys_ck,
1305         .init           = &omap2_init_clk_clkdm,
1306         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1307         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1308         .clkdm_name     = "d2d_clkdm",
1309         .recalc         = &followparent_recalc,
1310 };
1311
1312 static const struct clksel omap343x_gpt_clksel[] = {
1313         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1314         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1315         { .parent = NULL}
1316 };
1317
1318 static struct clk gpt10_fck = {
1319         .name           = "gpt10_fck",
1320         .ops            = &clkops_omap2_dflt_wait,
1321         .parent         = &sys_ck,
1322         .init           = &omap2_init_clksel_parent,
1323         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1324         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1325         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1326         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1327         .clksel         = omap343x_gpt_clksel,
1328         .clkdm_name     = "core_l4_clkdm",
1329         .recalc         = &omap2_clksel_recalc,
1330 };
1331
1332 static struct clk gpt11_fck = {
1333         .name           = "gpt11_fck",
1334         .ops            = &clkops_omap2_dflt_wait,
1335         .parent         = &sys_ck,
1336         .init           = &omap2_init_clksel_parent,
1337         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1338         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1339         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1340         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1341         .clksel         = omap343x_gpt_clksel,
1342         .clkdm_name     = "core_l4_clkdm",
1343         .recalc         = &omap2_clksel_recalc,
1344 };
1345
1346 static struct clk cpefuse_fck = {
1347         .name           = "cpefuse_fck",
1348         .ops            = &clkops_omap2_dflt,
1349         .parent         = &sys_ck,
1350         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1351         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1352         .recalc         = &followparent_recalc,
1353 };
1354
1355 static struct clk ts_fck = {
1356         .name           = "ts_fck",
1357         .ops            = &clkops_omap2_dflt,
1358         .parent         = &omap_32k_fck,
1359         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1360         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1361         .recalc         = &followparent_recalc,
1362 };
1363
1364 static struct clk usbtll_fck = {
1365         .name           = "usbtll_fck",
1366         .ops            = &clkops_omap2_dflt,
1367         .parent         = &omap_120m_fck,
1368         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1369         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1370         .recalc         = &followparent_recalc,
1371 };
1372
1373 /* CORE 96M FCLK-derived clocks */
1374
1375 static struct clk core_96m_fck = {
1376         .name           = "core_96m_fck",
1377         .ops            = &clkops_null,
1378         .parent         = &omap_96m_fck,
1379         .flags          = RATE_PROPAGATES,
1380         .clkdm_name     = "core_l4_clkdm",
1381         .recalc         = &followparent_recalc,
1382 };
1383
1384 static struct clk mmchs3_fck = {
1385         .name           = "mmchs_fck",
1386         .ops            = &clkops_omap2_dflt_wait,
1387         .id             = 2,
1388         .parent         = &core_96m_fck,
1389         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1390         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1391         .clkdm_name     = "core_l4_clkdm",
1392         .recalc         = &followparent_recalc,
1393 };
1394
1395 static struct clk mmchs2_fck = {
1396         .name           = "mmchs_fck",
1397         .ops            = &clkops_omap2_dflt_wait,
1398         .id             = 1,
1399         .parent         = &core_96m_fck,
1400         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1401         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1402         .clkdm_name     = "core_l4_clkdm",
1403         .recalc         = &followparent_recalc,
1404 };
1405
1406 static struct clk mspro_fck = {
1407         .name           = "mspro_fck",
1408         .ops            = &clkops_omap2_dflt_wait,
1409         .parent         = &core_96m_fck,
1410         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1411         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1412         .clkdm_name     = "core_l4_clkdm",
1413         .recalc         = &followparent_recalc,
1414 };
1415
1416 static struct clk mmchs1_fck = {
1417         .name           = "mmchs_fck",
1418         .ops            = &clkops_omap2_dflt_wait,
1419         .parent         = &core_96m_fck,
1420         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1421         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1422         .clkdm_name     = "core_l4_clkdm",
1423         .recalc         = &followparent_recalc,
1424 };
1425
1426 static struct clk i2c3_fck = {
1427         .name           = "i2c_fck",
1428         .ops            = &clkops_omap2_dflt_wait,
1429         .id             = 3,
1430         .parent         = &core_96m_fck,
1431         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1432         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1433         .clkdm_name     = "core_l4_clkdm",
1434         .recalc         = &followparent_recalc,
1435 };
1436
1437 static struct clk i2c2_fck = {
1438         .name           = "i2c_fck",
1439         .ops            = &clkops_omap2_dflt_wait,
1440         .id             = 2,
1441         .parent         = &core_96m_fck,
1442         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1443         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1444         .clkdm_name     = "core_l4_clkdm",
1445         .recalc         = &followparent_recalc,
1446 };
1447
1448 static struct clk i2c1_fck = {
1449         .name           = "i2c_fck",
1450         .ops            = &clkops_omap2_dflt_wait,
1451         .id             = 1,
1452         .parent         = &core_96m_fck,
1453         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1454         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1455         .clkdm_name     = "core_l4_clkdm",
1456         .recalc         = &followparent_recalc,
1457 };
1458
1459 /*
1460  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1461  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1462  */
1463 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1464         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1465         { .div = 0 }
1466 };
1467
1468 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1469         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1470         { .div = 0 }
1471 };
1472
1473 static const struct clksel mcbsp_15_clksel[] = {
1474         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1475         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1476         { .parent = NULL }
1477 };
1478
1479 static struct clk mcbsp5_fck = {
1480         .name           = "mcbsp_fck",
1481         .ops            = &clkops_omap2_dflt_wait,
1482         .id             = 5,
1483         .init           = &omap2_init_clksel_parent,
1484         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1485         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1486         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1487         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1488         .clksel         = mcbsp_15_clksel,
1489         .clkdm_name     = "core_l4_clkdm",
1490         .recalc         = &omap2_clksel_recalc,
1491 };
1492
1493 static struct clk mcbsp1_fck = {
1494         .name           = "mcbsp_fck",
1495         .ops            = &clkops_omap2_dflt_wait,
1496         .id             = 1,
1497         .init           = &omap2_init_clksel_parent,
1498         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1499         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1500         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1501         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1502         .clksel         = mcbsp_15_clksel,
1503         .clkdm_name     = "core_l4_clkdm",
1504         .recalc         = &omap2_clksel_recalc,
1505 };
1506
1507 /* CORE_48M_FCK-derived clocks */
1508
1509 static struct clk core_48m_fck = {
1510         .name           = "core_48m_fck",
1511         .ops            = &clkops_null,
1512         .parent         = &omap_48m_fck,
1513         .flags          = RATE_PROPAGATES,
1514         .clkdm_name     = "core_l4_clkdm",
1515         .recalc         = &followparent_recalc,
1516 };
1517
1518 static struct clk mcspi4_fck = {
1519         .name           = "mcspi_fck",
1520         .ops            = &clkops_omap2_dflt_wait,
1521         .id             = 4,
1522         .parent         = &core_48m_fck,
1523         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1524         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1525         .recalc         = &followparent_recalc,
1526 };
1527
1528 static struct clk mcspi3_fck = {
1529         .name           = "mcspi_fck",
1530         .ops            = &clkops_omap2_dflt_wait,
1531         .id             = 3,
1532         .parent         = &core_48m_fck,
1533         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1534         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1535         .recalc         = &followparent_recalc,
1536 };
1537
1538 static struct clk mcspi2_fck = {
1539         .name           = "mcspi_fck",
1540         .ops            = &clkops_omap2_dflt_wait,
1541         .id             = 2,
1542         .parent         = &core_48m_fck,
1543         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1544         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1545         .recalc         = &followparent_recalc,
1546 };
1547
1548 static struct clk mcspi1_fck = {
1549         .name           = "mcspi_fck",
1550         .ops            = &clkops_omap2_dflt_wait,
1551         .id             = 1,
1552         .parent         = &core_48m_fck,
1553         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1554         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1555         .recalc         = &followparent_recalc,
1556 };
1557
1558 static struct clk uart2_fck = {
1559         .name           = "uart2_fck",
1560         .ops            = &clkops_omap2_dflt_wait,
1561         .parent         = &core_48m_fck,
1562         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1563         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1564         .recalc         = &followparent_recalc,
1565 };
1566
1567 static struct clk uart1_fck = {
1568         .name           = "uart1_fck",
1569         .ops            = &clkops_omap2_dflt_wait,
1570         .parent         = &core_48m_fck,
1571         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1572         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1573         .recalc         = &followparent_recalc,
1574 };
1575
1576 static struct clk fshostusb_fck = {
1577         .name           = "fshostusb_fck",
1578         .ops            = &clkops_omap2_dflt_wait,
1579         .parent         = &core_48m_fck,
1580         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1581         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1582         .recalc         = &followparent_recalc,
1583 };
1584
1585 /* CORE_12M_FCK based clocks */
1586
1587 static struct clk core_12m_fck = {
1588         .name           = "core_12m_fck",
1589         .ops            = &clkops_null,
1590         .parent         = &omap_12m_fck,
1591         .flags          = RATE_PROPAGATES,
1592         .clkdm_name     = "core_l4_clkdm",
1593         .recalc         = &followparent_recalc,
1594 };
1595
1596 static struct clk hdq_fck = {
1597         .name           = "hdq_fck",
1598         .ops            = &clkops_omap2_dflt_wait,
1599         .parent         = &core_12m_fck,
1600         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1601         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1602         .recalc         = &followparent_recalc,
1603 };
1604
1605 /* DPLL3-derived clock */
1606
1607 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1608         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1609         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1610         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1611         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1612         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1613         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1614         { .div = 0 }
1615 };
1616
1617 static const struct clksel ssi_ssr_clksel[] = {
1618         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1619         { .parent = NULL }
1620 };
1621
1622 static struct clk ssi_ssr_fck = {
1623         .name           = "ssi_ssr_fck",
1624         .ops            = &clkops_omap2_dflt,
1625         .init           = &omap2_init_clksel_parent,
1626         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1627         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1628         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1629         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1630         .clksel         = ssi_ssr_clksel,
1631         .flags          = RATE_PROPAGATES,
1632         .clkdm_name     = "core_l4_clkdm",
1633         .recalc         = &omap2_clksel_recalc,
1634 };
1635
1636 static struct clk ssi_sst_fck = {
1637         .name           = "ssi_sst_fck",
1638         .ops            = &clkops_null,
1639         .parent         = &ssi_ssr_fck,
1640         .fixed_div      = 2,
1641         .recalc         = &omap2_fixed_divisor_recalc,
1642 };
1643
1644
1645
1646 /* CORE_L3_ICK based clocks */
1647
1648 /*
1649  * XXX must add clk_enable/clk_disable for these if standard code won't
1650  * handle it
1651  */
1652 static struct clk core_l3_ick = {
1653         .name           = "core_l3_ick",
1654         .ops            = &clkops_null,
1655         .parent         = &l3_ick,
1656         .init           = &omap2_init_clk_clkdm,
1657         .flags          = RATE_PROPAGATES,
1658         .clkdm_name     = "core_l3_clkdm",
1659         .recalc         = &followparent_recalc,
1660 };
1661
1662 static struct clk hsotgusb_ick = {
1663         .name           = "hsotgusb_ick",
1664         .ops            = &clkops_omap2_dflt_wait,
1665         .parent         = &core_l3_ick,
1666         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1667         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1668         .clkdm_name     = "core_l3_clkdm",
1669         .recalc         = &followparent_recalc,
1670 };
1671
1672 static struct clk sdrc_ick = {
1673         .name           = "sdrc_ick",
1674         .ops            = &clkops_omap2_dflt_wait,
1675         .parent         = &core_l3_ick,
1676         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1677         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1678         .flags          = ENABLE_ON_INIT,
1679         .clkdm_name     = "core_l3_clkdm",
1680         .recalc         = &followparent_recalc,
1681 };
1682
1683 static struct clk gpmc_fck = {
1684         .name           = "gpmc_fck",
1685         .ops            = &clkops_null,
1686         .parent         = &core_l3_ick,
1687         .flags          = ENABLE_ON_INIT, /* huh? */
1688         .clkdm_name     = "core_l3_clkdm",
1689         .recalc         = &followparent_recalc,
1690 };
1691
1692 /* SECURITY_L3_ICK based clocks */
1693
1694 static struct clk security_l3_ick = {
1695         .name           = "security_l3_ick",
1696         .ops            = &clkops_null,
1697         .parent         = &l3_ick,
1698         .flags          = RATE_PROPAGATES,
1699         .recalc         = &followparent_recalc,
1700 };
1701
1702 static struct clk pka_ick = {
1703         .name           = "pka_ick",
1704         .ops            = &clkops_omap2_dflt_wait,
1705         .parent         = &security_l3_ick,
1706         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1707         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1708         .recalc         = &followparent_recalc,
1709 };
1710
1711 /* CORE_L4_ICK based clocks */
1712
1713 static struct clk core_l4_ick = {
1714         .name           = "core_l4_ick",
1715         .ops            = &clkops_null,
1716         .parent         = &l4_ick,
1717         .init           = &omap2_init_clk_clkdm,
1718         .flags          = RATE_PROPAGATES,
1719         .clkdm_name     = "core_l4_clkdm",
1720         .recalc         = &followparent_recalc,
1721 };
1722
1723 static struct clk usbtll_ick = {
1724         .name           = "usbtll_ick",
1725         .ops            = &clkops_omap2_dflt_wait,
1726         .parent         = &core_l4_ick,
1727         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1728         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1729         .clkdm_name     = "core_l4_clkdm",
1730         .recalc         = &followparent_recalc,
1731 };
1732
1733 static struct clk mmchs3_ick = {
1734         .name           = "mmchs_ick",
1735         .ops            = &clkops_omap2_dflt_wait,
1736         .id             = 2,
1737         .parent         = &core_l4_ick,
1738         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1739         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1740         .clkdm_name     = "core_l4_clkdm",
1741         .recalc         = &followparent_recalc,
1742 };
1743
1744 /* Intersystem Communication Registers - chassis mode only */
1745 static struct clk icr_ick = {
1746         .name           = "icr_ick",
1747         .ops            = &clkops_omap2_dflt_wait,
1748         .parent         = &core_l4_ick,
1749         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1750         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1751         .clkdm_name     = "core_l4_clkdm",
1752         .recalc         = &followparent_recalc,
1753 };
1754
1755 static struct clk aes2_ick = {
1756         .name           = "aes2_ick",
1757         .ops            = &clkops_omap2_dflt_wait,
1758         .parent         = &core_l4_ick,
1759         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1760         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1761         .clkdm_name     = "core_l4_clkdm",
1762         .recalc         = &followparent_recalc,
1763 };
1764
1765 static struct clk sha12_ick = {
1766         .name           = "sha12_ick",
1767         .ops            = &clkops_omap2_dflt_wait,
1768         .parent         = &core_l4_ick,
1769         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1770         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1771         .clkdm_name     = "core_l4_clkdm",
1772         .recalc         = &followparent_recalc,
1773 };
1774
1775 static struct clk des2_ick = {
1776         .name           = "des2_ick",
1777         .ops            = &clkops_omap2_dflt_wait,
1778         .parent         = &core_l4_ick,
1779         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1780         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1781         .clkdm_name     = "core_l4_clkdm",
1782         .recalc         = &followparent_recalc,
1783 };
1784
1785 static struct clk mmchs2_ick = {
1786         .name           = "mmchs_ick",
1787         .ops            = &clkops_omap2_dflt_wait,
1788         .id             = 1,
1789         .parent         = &core_l4_ick,
1790         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1791         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1792         .clkdm_name     = "core_l4_clkdm",
1793         .recalc         = &followparent_recalc,
1794 };
1795
1796 static struct clk mmchs1_ick = {
1797         .name           = "mmchs_ick",
1798         .ops            = &clkops_omap2_dflt_wait,
1799         .parent         = &core_l4_ick,
1800         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1801         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1802         .clkdm_name     = "core_l4_clkdm",
1803         .recalc         = &followparent_recalc,
1804 };
1805
1806 static struct clk mspro_ick = {
1807         .name           = "mspro_ick",
1808         .ops            = &clkops_omap2_dflt_wait,
1809         .parent         = &core_l4_ick,
1810         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1811         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1812         .clkdm_name     = "core_l4_clkdm",
1813         .recalc         = &followparent_recalc,
1814 };
1815
1816 static struct clk hdq_ick = {
1817         .name           = "hdq_ick",
1818         .ops            = &clkops_omap2_dflt_wait,
1819         .parent         = &core_l4_ick,
1820         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1821         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1822         .clkdm_name     = "core_l4_clkdm",
1823         .recalc         = &followparent_recalc,
1824 };
1825
1826 static struct clk mcspi4_ick = {
1827         .name           = "mcspi_ick",
1828         .ops            = &clkops_omap2_dflt_wait,
1829         .id             = 4,
1830         .parent         = &core_l4_ick,
1831         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1832         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1833         .clkdm_name     = "core_l4_clkdm",
1834         .recalc         = &followparent_recalc,
1835 };
1836
1837 static struct clk mcspi3_ick = {
1838         .name           = "mcspi_ick",
1839         .ops            = &clkops_omap2_dflt_wait,
1840         .id             = 3,
1841         .parent         = &core_l4_ick,
1842         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1843         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1844         .clkdm_name     = "core_l4_clkdm",
1845         .recalc         = &followparent_recalc,
1846 };
1847
1848 static struct clk mcspi2_ick = {
1849         .name           = "mcspi_ick",
1850         .ops            = &clkops_omap2_dflt_wait,
1851         .id             = 2,
1852         .parent         = &core_l4_ick,
1853         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1854         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1855         .clkdm_name     = "core_l4_clkdm",
1856         .recalc         = &followparent_recalc,
1857 };
1858
1859 static struct clk mcspi1_ick = {
1860         .name           = "mcspi_ick",
1861         .ops            = &clkops_omap2_dflt_wait,
1862         .id             = 1,
1863         .parent         = &core_l4_ick,
1864         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1865         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1866         .clkdm_name     = "core_l4_clkdm",
1867         .recalc         = &followparent_recalc,
1868 };
1869
1870 static struct clk i2c3_ick = {
1871         .name           = "i2c_ick",
1872         .ops            = &clkops_omap2_dflt_wait,
1873         .id             = 3,
1874         .parent         = &core_l4_ick,
1875         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1876         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1877         .clkdm_name     = "core_l4_clkdm",
1878         .recalc         = &followparent_recalc,
1879 };
1880
1881 static struct clk i2c2_ick = {
1882         .name           = "i2c_ick",
1883         .ops            = &clkops_omap2_dflt_wait,
1884         .id             = 2,
1885         .parent         = &core_l4_ick,
1886         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1887         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1888         .clkdm_name     = "core_l4_clkdm",
1889         .recalc         = &followparent_recalc,
1890 };
1891
1892 static struct clk i2c1_ick = {
1893         .name           = "i2c_ick",
1894         .ops            = &clkops_omap2_dflt_wait,
1895         .id             = 1,
1896         .parent         = &core_l4_ick,
1897         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1898         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1899         .clkdm_name     = "core_l4_clkdm",
1900         .recalc         = &followparent_recalc,
1901 };
1902
1903 static struct clk uart2_ick = {
1904         .name           = "uart2_ick",
1905         .ops            = &clkops_omap2_dflt_wait,
1906         .parent         = &core_l4_ick,
1907         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1908         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1909         .clkdm_name     = "core_l4_clkdm",
1910         .recalc         = &followparent_recalc,
1911 };
1912
1913 static struct clk uart1_ick = {
1914         .name           = "uart1_ick",
1915         .ops            = &clkops_omap2_dflt_wait,
1916         .parent         = &core_l4_ick,
1917         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1918         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1919         .clkdm_name     = "core_l4_clkdm",
1920         .recalc         = &followparent_recalc,
1921 };
1922
1923 static struct clk gpt11_ick = {
1924         .name           = "gpt11_ick",
1925         .ops            = &clkops_omap2_dflt_wait,
1926         .parent         = &core_l4_ick,
1927         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1928         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1929         .clkdm_name     = "core_l4_clkdm",
1930         .recalc         = &followparent_recalc,
1931 };
1932
1933 static struct clk gpt10_ick = {
1934         .name           = "gpt10_ick",
1935         .ops            = &clkops_omap2_dflt_wait,
1936         .parent         = &core_l4_ick,
1937         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1938         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1939         .clkdm_name     = "core_l4_clkdm",
1940         .recalc         = &followparent_recalc,
1941 };
1942
1943 static struct clk mcbsp5_ick = {
1944         .name           = "mcbsp_ick",
1945         .ops            = &clkops_omap2_dflt_wait,
1946         .id             = 5,
1947         .parent         = &core_l4_ick,
1948         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1949         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1950         .clkdm_name     = "core_l4_clkdm",
1951         .recalc         = &followparent_recalc,
1952 };
1953
1954 static struct clk mcbsp1_ick = {
1955         .name           = "mcbsp_ick",
1956         .ops            = &clkops_omap2_dflt_wait,
1957         .id             = 1,
1958         .parent         = &core_l4_ick,
1959         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1960         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1961         .clkdm_name     = "core_l4_clkdm",
1962         .recalc         = &followparent_recalc,
1963 };
1964
1965 static struct clk fac_ick = {
1966         .name           = "fac_ick",
1967         .ops            = &clkops_omap2_dflt_wait,
1968         .parent         = &core_l4_ick,
1969         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1970         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1971         .clkdm_name     = "core_l4_clkdm",
1972         .recalc         = &followparent_recalc,
1973 };
1974
1975 static struct clk mailboxes_ick = {
1976         .name           = "mailboxes_ick",
1977         .ops            = &clkops_omap2_dflt_wait,
1978         .parent         = &core_l4_ick,
1979         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1980         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
1981         .clkdm_name     = "core_l4_clkdm",
1982         .recalc         = &followparent_recalc,
1983 };
1984
1985 static struct clk omapctrl_ick = {
1986         .name           = "omapctrl_ick",
1987         .ops            = &clkops_omap2_dflt_wait,
1988         .parent         = &core_l4_ick,
1989         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1990         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
1991         .flags          = ENABLE_ON_INIT,
1992         .recalc         = &followparent_recalc,
1993 };
1994
1995 /* SSI_L4_ICK based clocks */
1996
1997 static struct clk ssi_l4_ick = {
1998         .name           = "ssi_l4_ick",
1999         .ops            = &clkops_null,
2000         .parent         = &l4_ick,
2001         .flags          = RATE_PROPAGATES,
2002         .clkdm_name     = "core_l4_clkdm",
2003         .recalc         = &followparent_recalc,
2004 };
2005
2006 static struct clk ssi_ick = {
2007         .name           = "ssi_ick",
2008         .ops            = &clkops_omap2_dflt,
2009         .parent         = &ssi_l4_ick,
2010         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2011         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2012         .clkdm_name     = "core_l4_clkdm",
2013         .recalc         = &followparent_recalc,
2014 };
2015
2016 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2017  * but l4_ick makes more sense to me */
2018
2019 static const struct clksel usb_l4_clksel[] = {
2020         { .parent = &l4_ick, .rates = div2_rates },
2021         { .parent = NULL },
2022 };
2023
2024 static struct clk usb_l4_ick = {
2025         .name           = "usb_l4_ick",
2026         .ops            = &clkops_omap2_dflt_wait,
2027         .parent         = &l4_ick,
2028         .init           = &omap2_init_clksel_parent,
2029         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2030         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2031         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2032         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2033         .clksel         = usb_l4_clksel,
2034         .recalc         = &omap2_clksel_recalc,
2035 };
2036
2037 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2038
2039 /* SECURITY_L4_ICK2 based clocks */
2040
2041 static struct clk security_l4_ick2 = {
2042         .name           = "security_l4_ick2",
2043         .ops            = &clkops_null,
2044         .parent         = &l4_ick,
2045         .flags          = RATE_PROPAGATES,
2046         .recalc         = &followparent_recalc,
2047 };
2048
2049 static struct clk aes1_ick = {
2050         .name           = "aes1_ick",
2051         .ops            = &clkops_omap2_dflt_wait,
2052         .parent         = &security_l4_ick2,
2053         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2054         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2055         .recalc         = &followparent_recalc,
2056 };
2057
2058 static struct clk rng_ick = {
2059         .name           = "rng_ick",
2060         .ops            = &clkops_omap2_dflt_wait,
2061         .parent         = &security_l4_ick2,
2062         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2063         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2064         .recalc         = &followparent_recalc,
2065 };
2066
2067 static struct clk sha11_ick = {
2068         .name           = "sha11_ick",
2069         .ops            = &clkops_omap2_dflt_wait,
2070         .parent         = &security_l4_ick2,
2071         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2072         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2073         .recalc         = &followparent_recalc,
2074 };
2075
2076 static struct clk des1_ick = {
2077         .name           = "des1_ick",
2078         .ops            = &clkops_omap2_dflt_wait,
2079         .parent         = &security_l4_ick2,
2080         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2081         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2082         .recalc         = &followparent_recalc,
2083 };
2084
2085 /* DSS */
2086 static const struct clksel dss1_alwon_fck_clksel[] = {
2087         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2088         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2089         { .parent = NULL }
2090 };
2091
2092 static struct clk dss1_alwon_fck = {
2093         .name           = "dss1_alwon_fck",
2094         .ops            = &clkops_omap2_dflt,
2095         .parent         = &dpll4_m4x2_ck,
2096         .init           = &omap2_init_clksel_parent,
2097         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2098         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2099         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2100         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2101         .clksel         = dss1_alwon_fck_clksel,
2102         .clkdm_name     = "dss_clkdm",
2103         .recalc         = &omap2_clksel_recalc,
2104 };
2105
2106 static struct clk dss_tv_fck = {
2107         .name           = "dss_tv_fck",
2108         .ops            = &clkops_omap2_dflt,
2109         .parent         = &omap_54m_fck,
2110         .init           = &omap2_init_clk_clkdm,
2111         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2112         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2113         .clkdm_name     = "dss_clkdm",
2114         .recalc         = &followparent_recalc,
2115 };
2116
2117 static struct clk dss_96m_fck = {
2118         .name           = "dss_96m_fck",
2119         .ops            = &clkops_omap2_dflt,
2120         .parent         = &omap_96m_fck,
2121         .init           = &omap2_init_clk_clkdm,
2122         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2123         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2124         .clkdm_name     = "dss_clkdm",
2125         .recalc         = &followparent_recalc,
2126 };
2127
2128 static struct clk dss2_alwon_fck = {
2129         .name           = "dss2_alwon_fck",
2130         .ops            = &clkops_omap2_dflt,
2131         .parent         = &sys_ck,
2132         .init           = &omap2_init_clk_clkdm,
2133         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2134         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2135         .clkdm_name     = "dss_clkdm",
2136         .recalc         = &followparent_recalc,
2137 };
2138
2139 static struct clk dss_ick = {
2140         /* Handles both L3 and L4 clocks */
2141         .name           = "dss_ick",
2142         .ops            = &clkops_omap2_dflt,
2143         .parent         = &l4_ick,
2144         .init           = &omap2_init_clk_clkdm,
2145         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2146         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2147         .clkdm_name     = "dss_clkdm",
2148         .recalc         = &followparent_recalc,
2149 };
2150
2151 /* CAM */
2152
2153 static const struct clksel cam_mclk_clksel[] = {
2154         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2155         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2156         { .parent = NULL }
2157 };
2158
2159 static struct clk cam_mclk = {
2160         .name           = "cam_mclk",
2161         .ops            = &clkops_omap2_dflt_wait,
2162         .parent         = &dpll4_m5x2_ck,
2163         .init           = &omap2_init_clksel_parent,
2164         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2165         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2166         .clksel         = cam_mclk_clksel,
2167         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2168         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2169         .clkdm_name     = "cam_clkdm",
2170         .recalc         = &omap2_clksel_recalc,
2171 };
2172
2173 static struct clk cam_ick = {
2174         /* Handles both L3 and L4 clocks */
2175         .name           = "cam_ick",
2176         .ops            = &clkops_omap2_dflt_wait,
2177         .parent         = &l4_ick,
2178         .init           = &omap2_init_clk_clkdm,
2179         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2180         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2181         .clkdm_name     = "cam_clkdm",
2182         .recalc         = &followparent_recalc,
2183 };
2184
2185 /* USBHOST - 3430ES2 only */
2186
2187 static struct clk usbhost_120m_fck = {
2188         .name           = "usbhost_120m_fck",
2189         .ops            = &clkops_omap2_dflt_wait,
2190         .parent         = &omap_120m_fck,
2191         .init           = &omap2_init_clk_clkdm,
2192         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2193         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2194         .clkdm_name     = "usbhost_clkdm",
2195         .recalc         = &followparent_recalc,
2196 };
2197
2198 static struct clk usbhost_48m_fck = {
2199         .name           = "usbhost_48m_fck",
2200         .ops            = &clkops_omap2_dflt_wait,
2201         .parent         = &omap_48m_fck,
2202         .init           = &omap2_init_clk_clkdm,
2203         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2204         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2205         .clkdm_name     = "usbhost_clkdm",
2206         .recalc         = &followparent_recalc,
2207 };
2208
2209 static struct clk usbhost_ick = {
2210         /* Handles both L3 and L4 clocks */
2211         .name           = "usbhost_ick",
2212         .ops            = &clkops_omap2_dflt_wait,
2213         .parent         = &l4_ick,
2214         .init           = &omap2_init_clk_clkdm,
2215         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2216         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2217         .clkdm_name     = "usbhost_clkdm",
2218         .recalc         = &followparent_recalc,
2219 };
2220
2221 static struct clk usbhost_sar_fck = {
2222         .name           = "usbhost_sar_fck",
2223         .ops            = &clkops_omap2_dflt,
2224         .parent         = &osc_sys_ck,
2225         .init           = &omap2_init_clk_clkdm,
2226         .enable_reg     = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
2227         .enable_bit     = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
2228         .clkdm_name     = "usbhost_clkdm",
2229         .recalc         = &followparent_recalc,
2230 };
2231
2232 /* WKUP */
2233
2234 static const struct clksel_rate usim_96m_rates[] = {
2235         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2236         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2237         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2238         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2239         { .div = 0 },
2240 };
2241
2242 static const struct clksel_rate usim_120m_rates[] = {
2243         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2244         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2245         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2246         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2247         { .div = 0 },
2248 };
2249
2250 static const struct clksel usim_clksel[] = {
2251         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2252         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2253         { .parent = &sys_ck,            .rates = div2_rates },
2254         { .parent = NULL },
2255 };
2256
2257 /* 3430ES2 only */
2258 static struct clk usim_fck = {
2259         .name           = "usim_fck",
2260         .ops            = &clkops_omap2_dflt_wait,
2261         .init           = &omap2_init_clksel_parent,
2262         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2263         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2264         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2265         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2266         .clksel         = usim_clksel,
2267         .recalc         = &omap2_clksel_recalc,
2268 };
2269
2270 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2271 static struct clk gpt1_fck = {
2272         .name           = "gpt1_fck",
2273         .ops            = &clkops_omap2_dflt_wait,
2274         .init           = &omap2_init_clksel_parent,
2275         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2276         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2277         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2278         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2279         .clksel         = omap343x_gpt_clksel,
2280         .clkdm_name     = "wkup_clkdm",
2281         .recalc         = &omap2_clksel_recalc,
2282 };
2283
2284 static struct clk wkup_32k_fck = {
2285         .name           = "wkup_32k_fck",
2286         .ops            = &clkops_null,
2287         .init           = &omap2_init_clk_clkdm,
2288         .parent         = &omap_32k_fck,
2289         .flags          = RATE_PROPAGATES,
2290         .clkdm_name     = "wkup_clkdm",
2291         .recalc         = &followparent_recalc,
2292 };
2293
2294 static struct clk gpio1_dbck = {
2295         .name           = "gpio1_dbck",
2296         .ops            = &clkops_omap2_dflt_wait,
2297         .parent         = &wkup_32k_fck,
2298         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2299         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2300         .clkdm_name     = "wkup_clkdm",
2301         .recalc         = &followparent_recalc,
2302 };
2303
2304 static struct clk wdt2_fck = {
2305         .name           = "wdt2_fck",
2306         .ops            = &clkops_omap2_dflt_wait,
2307         .parent         = &wkup_32k_fck,
2308         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2309         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2310         .clkdm_name     = "wkup_clkdm",
2311         .recalc         = &followparent_recalc,
2312 };
2313
2314 static struct clk wkup_l4_ick = {
2315         .name           = "wkup_l4_ick",
2316         .ops            = &clkops_null,
2317         .parent         = &sys_ck,
2318         .flags          = RATE_PROPAGATES,
2319         .clkdm_name     = "wkup_clkdm",
2320         .recalc         = &followparent_recalc,
2321 };
2322
2323 /* 3430ES2 only */
2324 /* Never specifically named in the TRM, so we have to infer a likely name */
2325 static struct clk usim_ick = {
2326         .name           = "usim_ick",
2327         .ops            = &clkops_omap2_dflt_wait,
2328         .parent         = &wkup_l4_ick,
2329         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2330         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2331         .clkdm_name     = "wkup_clkdm",
2332         .recalc         = &followparent_recalc,
2333 };
2334
2335 static struct clk wdt2_ick = {
2336         .name           = "wdt2_ick",
2337         .ops            = &clkops_omap2_dflt_wait,
2338         .parent         = &wkup_l4_ick,
2339         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2340         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2341         .clkdm_name     = "wkup_clkdm",
2342         .recalc         = &followparent_recalc,
2343 };
2344
2345 static struct clk wdt1_ick = {
2346         .name           = "wdt1_ick",
2347         .ops            = &clkops_omap2_dflt_wait,
2348         .parent         = &wkup_l4_ick,
2349         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2350         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2351         .clkdm_name     = "wkup_clkdm",
2352         .recalc         = &followparent_recalc,
2353 };
2354
2355 static struct clk gpio1_ick = {
2356         .name           = "gpio1_ick",
2357         .ops            = &clkops_omap2_dflt_wait,
2358         .parent         = &wkup_l4_ick,
2359         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2360         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2361         .clkdm_name     = "wkup_clkdm",
2362         .recalc         = &followparent_recalc,
2363 };
2364
2365 static struct clk omap_32ksync_ick = {
2366         .name           = "omap_32ksync_ick",
2367         .ops            = &clkops_omap2_dflt_wait,
2368         .parent         = &wkup_l4_ick,
2369         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2370         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2371         .clkdm_name     = "wkup_clkdm",
2372         .recalc         = &followparent_recalc,
2373 };
2374
2375 /* XXX This clock no longer exists in 3430 TRM rev F */
2376 static struct clk gpt12_ick = {
2377         .name           = "gpt12_ick",
2378         .ops            = &clkops_omap2_dflt_wait,
2379         .parent         = &wkup_l4_ick,
2380         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2381         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2382         .clkdm_name     = "wkup_clkdm",
2383         .recalc         = &followparent_recalc,
2384 };
2385
2386 static struct clk gpt1_ick = {
2387         .name           = "gpt1_ick",
2388         .ops            = &clkops_omap2_dflt_wait,
2389         .parent         = &wkup_l4_ick,
2390         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2391         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2392         .clkdm_name     = "wkup_clkdm",
2393         .recalc         = &followparent_recalc,
2394 };
2395
2396
2397
2398 /* PER clock domain */
2399
2400 static struct clk per_96m_fck = {
2401         .name           = "per_96m_fck",
2402         .ops            = &clkops_null,
2403         .parent         = &omap_96m_alwon_fck,
2404         .init           = &omap2_init_clk_clkdm,
2405         .flags          = RATE_PROPAGATES,
2406         .clkdm_name     = "per_clkdm",
2407         .recalc         = &followparent_recalc,
2408 };
2409
2410 static struct clk per_48m_fck = {
2411         .name           = "per_48m_fck",
2412         .ops            = &clkops_null,
2413         .parent         = &omap_48m_fck,
2414         .init           = &omap2_init_clk_clkdm,
2415         .flags          = RATE_PROPAGATES,
2416         .clkdm_name     = "per_clkdm",
2417         .recalc         = &followparent_recalc,
2418 };
2419
2420 static struct clk uart3_fck = {
2421         .name           = "uart3_fck",
2422         .ops            = &clkops_omap2_dflt_wait,
2423         .parent         = &per_48m_fck,
2424         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2425         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2426         .clkdm_name     = "per_clkdm",
2427         .recalc         = &followparent_recalc,
2428 };
2429
2430 static struct clk gpt2_fck = {
2431         .name           = "gpt2_fck",
2432         .ops            = &clkops_omap2_dflt_wait,
2433         .init           = &omap2_init_clksel_parent,
2434         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2435         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2436         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2437         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2438         .clksel         = omap343x_gpt_clksel,
2439         .clkdm_name     = "per_clkdm",
2440         .recalc         = &omap2_clksel_recalc,
2441 };
2442
2443 static struct clk gpt3_fck = {
2444         .name           = "gpt3_fck",
2445         .ops            = &clkops_omap2_dflt_wait,
2446         .init           = &omap2_init_clksel_parent,
2447         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2448         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2449         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2450         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2451         .clksel         = omap343x_gpt_clksel,
2452         .clkdm_name     = "per_clkdm",
2453         .recalc         = &omap2_clksel_recalc,
2454 };
2455
2456 static struct clk gpt4_fck = {
2457         .name           = "gpt4_fck",
2458         .ops            = &clkops_omap2_dflt_wait,
2459         .init           = &omap2_init_clksel_parent,
2460         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2461         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2462         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2463         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2464         .clksel         = omap343x_gpt_clksel,
2465         .clkdm_name     = "per_clkdm",
2466         .recalc         = &omap2_clksel_recalc,
2467 };
2468
2469 static struct clk gpt5_fck = {
2470         .name           = "gpt5_fck",
2471         .ops            = &clkops_omap2_dflt_wait,
2472         .init           = &omap2_init_clksel_parent,
2473         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2474         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2475         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2476         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2477         .clksel         = omap343x_gpt_clksel,
2478         .clkdm_name     = "per_clkdm",
2479         .recalc         = &omap2_clksel_recalc,
2480 };
2481
2482 static struct clk gpt6_fck = {
2483         .name           = "gpt6_fck",
2484         .ops            = &clkops_omap2_dflt_wait,
2485         .init           = &omap2_init_clksel_parent,
2486         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2487         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2488         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2489         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2490         .clksel         = omap343x_gpt_clksel,
2491         .clkdm_name     = "per_clkdm",
2492         .recalc         = &omap2_clksel_recalc,
2493 };
2494
2495 static struct clk gpt7_fck = {
2496         .name           = "gpt7_fck",
2497         .ops            = &clkops_omap2_dflt_wait,
2498         .init           = &omap2_init_clksel_parent,
2499         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2500         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2501         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2502         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2503         .clksel         = omap343x_gpt_clksel,
2504         .clkdm_name     = "per_clkdm",
2505         .recalc         = &omap2_clksel_recalc,
2506 };
2507
2508 static struct clk gpt8_fck = {
2509         .name           = "gpt8_fck",
2510         .ops            = &clkops_omap2_dflt_wait,
2511         .init           = &omap2_init_clksel_parent,
2512         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2513         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2514         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2515         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2516         .clksel         = omap343x_gpt_clksel,
2517         .clkdm_name     = "per_clkdm",
2518         .recalc         = &omap2_clksel_recalc,
2519 };
2520
2521 static struct clk gpt9_fck = {
2522         .name           = "gpt9_fck",
2523         .ops            = &clkops_omap2_dflt_wait,
2524         .init           = &omap2_init_clksel_parent,
2525         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2526         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2527         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2528         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2529         .clksel         = omap343x_gpt_clksel,
2530         .clkdm_name     = "per_clkdm",
2531         .recalc         = &omap2_clksel_recalc,
2532 };
2533
2534 static struct clk per_32k_alwon_fck = {
2535         .name           = "per_32k_alwon_fck",
2536         .ops            = &clkops_null,
2537         .parent         = &omap_32k_fck,
2538         .clkdm_name     = "per_clkdm",
2539         .flags          = RATE_PROPAGATES,
2540         .recalc         = &followparent_recalc,
2541 };
2542
2543 static struct clk gpio6_dbck = {
2544         .name           = "gpio6_dbck",
2545         .ops            = &clkops_omap2_dflt_wait,
2546         .parent         = &per_32k_alwon_fck,
2547         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2548         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2549         .clkdm_name     = "per_clkdm",
2550         .recalc         = &followparent_recalc,
2551 };
2552
2553 static struct clk gpio5_dbck = {
2554         .name           = "gpio5_dbck",
2555         .ops            = &clkops_omap2_dflt_wait,
2556         .parent         = &per_32k_alwon_fck,
2557         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2558         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2559         .clkdm_name     = "per_clkdm",
2560         .recalc         = &followparent_recalc,
2561 };
2562
2563 static struct clk gpio4_dbck = {
2564         .name           = "gpio4_dbck",
2565         .ops            = &clkops_omap2_dflt_wait,
2566         .parent         = &per_32k_alwon_fck,
2567         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2568         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2569         .clkdm_name     = "per_clkdm",
2570         .recalc         = &followparent_recalc,
2571 };
2572
2573 static struct clk gpio3_dbck = {
2574         .name           = "gpio3_dbck",
2575         .ops            = &clkops_omap2_dflt_wait,
2576         .parent         = &per_32k_alwon_fck,
2577         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2578         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2579         .clkdm_name     = "per_clkdm",
2580         .recalc         = &followparent_recalc,
2581 };
2582
2583 static struct clk gpio2_dbck = {
2584         .name           = "gpio2_dbck",
2585         .ops            = &clkops_omap2_dflt_wait,
2586         .parent         = &per_32k_alwon_fck,
2587         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2588         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2589         .clkdm_name     = "per_clkdm",
2590         .recalc         = &followparent_recalc,
2591 };
2592
2593 static struct clk wdt3_fck = {
2594         .name           = "wdt3_fck",
2595         .ops            = &clkops_omap2_dflt_wait,
2596         .parent         = &per_32k_alwon_fck,
2597         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2598         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2599         .clkdm_name     = "per_clkdm",
2600         .recalc         = &followparent_recalc,
2601 };
2602
2603 static struct clk per_l4_ick = {
2604         .name           = "per_l4_ick",
2605         .ops            = &clkops_null,
2606         .parent         = &l4_ick,
2607         .flags          = RATE_PROPAGATES,
2608         .clkdm_name     = "per_clkdm",
2609         .recalc         = &followparent_recalc,
2610 };
2611
2612 static struct clk gpio6_ick = {
2613         .name           = "gpio6_ick",
2614         .ops            = &clkops_omap2_dflt_wait,
2615         .parent         = &per_l4_ick,
2616         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2617         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2618         .clkdm_name     = "per_clkdm",
2619         .recalc         = &followparent_recalc,
2620 };
2621
2622 static struct clk gpio5_ick = {
2623         .name           = "gpio5_ick",
2624         .ops            = &clkops_omap2_dflt_wait,
2625         .parent         = &per_l4_ick,
2626         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2627         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2628         .clkdm_name     = "per_clkdm",
2629         .recalc         = &followparent_recalc,
2630 };
2631
2632 static struct clk gpio4_ick = {
2633         .name           = "gpio4_ick",
2634         .ops            = &clkops_omap2_dflt_wait,
2635         .parent         = &per_l4_ick,
2636         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2637         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2638         .clkdm_name     = "per_clkdm",
2639         .recalc         = &followparent_recalc,
2640 };
2641
2642 static struct clk gpio3_ick = {
2643         .name           = "gpio3_ick",
2644         .ops            = &clkops_omap2_dflt_wait,
2645         .parent         = &per_l4_ick,
2646         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2647         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2648         .clkdm_name     = "per_clkdm",
2649         .recalc         = &followparent_recalc,
2650 };
2651
2652 static struct clk gpio2_ick = {
2653         .name           = "gpio2_ick",
2654         .ops            = &clkops_omap2_dflt_wait,
2655         .parent         = &per_l4_ick,
2656         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2657         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2658         .clkdm_name     = "per_clkdm",
2659         .recalc         = &followparent_recalc,
2660 };
2661
2662 static struct clk wdt3_ick = {
2663         .name           = "wdt3_ick",
2664         .ops            = &clkops_omap2_dflt_wait,
2665         .parent         = &per_l4_ick,
2666         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2667         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2668         .clkdm_name     = "per_clkdm",
2669         .recalc         = &followparent_recalc,
2670 };
2671
2672 static struct clk uart3_ick = {
2673         .name           = "uart3_ick",
2674         .ops            = &clkops_omap2_dflt_wait,
2675         .parent         = &per_l4_ick,
2676         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2677         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2678         .clkdm_name     = "per_clkdm",
2679         .recalc         = &followparent_recalc,
2680 };
2681
2682 static struct clk gpt9_ick = {
2683         .name           = "gpt9_ick",
2684         .ops            = &clkops_omap2_dflt_wait,
2685         .parent         = &per_l4_ick,
2686         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2687         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2688         .clkdm_name     = "per_clkdm",
2689         .recalc         = &followparent_recalc,
2690 };
2691
2692 static struct clk gpt8_ick = {
2693         .name           = "gpt8_ick",
2694         .ops            = &clkops_omap2_dflt_wait,
2695         .parent         = &per_l4_ick,
2696         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2697         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2698         .clkdm_name     = "per_clkdm",
2699         .recalc         = &followparent_recalc,
2700 };
2701
2702 static struct clk gpt7_ick = {
2703         .name           = "gpt7_ick",
2704         .ops            = &clkops_omap2_dflt_wait,
2705         .parent         = &per_l4_ick,
2706         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2707         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2708         .clkdm_name     = "per_clkdm",
2709         .recalc         = &followparent_recalc,
2710 };
2711
2712 static struct clk gpt6_ick = {
2713         .name           = "gpt6_ick",
2714         .ops            = &clkops_omap2_dflt_wait,
2715         .parent         = &per_l4_ick,
2716         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2717         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2718         .clkdm_name     = "per_clkdm",
2719         .recalc         = &followparent_recalc,
2720 };
2721
2722 static struct clk gpt5_ick = {
2723         .name           = "gpt5_ick",
2724         .ops            = &clkops_omap2_dflt_wait,
2725         .parent         = &per_l4_ick,
2726         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2727         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2728         .clkdm_name     = "per_clkdm",
2729         .recalc         = &followparent_recalc,
2730 };
2731
2732 static struct clk gpt4_ick = {
2733         .name           = "gpt4_ick",
2734         .ops            = &clkops_omap2_dflt_wait,
2735         .parent         = &per_l4_ick,
2736         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2737         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2738         .clkdm_name     = "per_clkdm",
2739         .recalc         = &followparent_recalc,
2740 };
2741
2742 static struct clk gpt3_ick = {
2743         .name           = "gpt3_ick",
2744         .ops            = &clkops_omap2_dflt_wait,
2745         .parent         = &per_l4_ick,
2746         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2747         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2748         .clkdm_name     = "per_clkdm",
2749         .recalc         = &followparent_recalc,
2750 };
2751
2752 static struct clk gpt2_ick = {
2753         .name           = "gpt2_ick",
2754         .ops            = &clkops_omap2_dflt_wait,
2755         .parent         = &per_l4_ick,
2756         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2757         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2758         .clkdm_name     = "per_clkdm",
2759         .recalc         = &followparent_recalc,
2760 };
2761
2762 static struct clk mcbsp2_ick = {
2763         .name           = "mcbsp_ick",
2764         .ops            = &clkops_omap2_dflt_wait,
2765         .id             = 2,
2766         .parent         = &per_l4_ick,
2767         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2768         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2769         .clkdm_name     = "per_clkdm",
2770         .recalc         = &followparent_recalc,
2771 };
2772
2773 static struct clk mcbsp3_ick = {
2774         .name           = "mcbsp_ick",
2775         .ops            = &clkops_omap2_dflt_wait,
2776         .id             = 3,
2777         .parent         = &per_l4_ick,
2778         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2779         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2780         .clkdm_name     = "per_clkdm",
2781         .recalc         = &followparent_recalc,
2782 };
2783
2784 static struct clk mcbsp4_ick = {
2785         .name           = "mcbsp_ick",
2786         .ops            = &clkops_omap2_dflt_wait,
2787         .id             = 4,
2788         .parent         = &per_l4_ick,
2789         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2790         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2791         .clkdm_name     = "per_clkdm",
2792         .recalc         = &followparent_recalc,
2793 };
2794
2795 static const struct clksel mcbsp_234_clksel[] = {
2796         { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2797         { .parent = &mcbsp_clks,  .rates = common_mcbsp_mcbsp_rates },
2798         { .parent = NULL }
2799 };
2800
2801 static struct clk mcbsp2_fck = {
2802         .name           = "mcbsp_fck",
2803         .ops            = &clkops_omap2_dflt_wait,
2804         .id             = 2,
2805         .init           = &omap2_init_clksel_parent,
2806         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2807         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2808         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2809         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2810         .clksel         = mcbsp_234_clksel,
2811         .clkdm_name     = "per_clkdm",
2812         .recalc         = &omap2_clksel_recalc,
2813 };
2814
2815 static struct clk mcbsp3_fck = {
2816         .name           = "mcbsp_fck",
2817         .ops            = &clkops_omap2_dflt_wait,
2818         .id             = 3,
2819         .init           = &omap2_init_clksel_parent,
2820         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2821         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2822         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2823         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2824         .clksel         = mcbsp_234_clksel,
2825         .clkdm_name     = "per_clkdm",
2826         .recalc         = &omap2_clksel_recalc,
2827 };
2828
2829 static struct clk mcbsp4_fck = {
2830         .name           = "mcbsp_fck",
2831         .ops            = &clkops_omap2_dflt_wait,
2832         .id             = 4,
2833         .init           = &omap2_init_clksel_parent,
2834         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2835         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2836         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2837         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2838         .clksel         = mcbsp_234_clksel,
2839         .clkdm_name     = "per_clkdm",
2840         .recalc         = &omap2_clksel_recalc,
2841 };
2842
2843 /* EMU clocks */
2844
2845 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2846
2847 static const struct clksel_rate emu_src_sys_rates[] = {
2848         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2849         { .div = 0 },
2850 };
2851
2852 static const struct clksel_rate emu_src_core_rates[] = {
2853         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2854         { .div = 0 },
2855 };
2856
2857 static const struct clksel_rate emu_src_per_rates[] = {
2858         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2859         { .div = 0 },
2860 };
2861
2862 static const struct clksel_rate emu_src_mpu_rates[] = {
2863         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2864         { .div = 0 },
2865 };
2866
2867 static const struct clksel emu_src_clksel[] = {
2868         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2869         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2870         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2871         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2872         { .parent = NULL },
2873 };
2874
2875 /*
2876  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2877  * to switch the source of some of the EMU clocks.
2878  * XXX Are there CLKEN bits for these EMU clks?
2879  */
2880 static struct clk emu_src_ck = {
2881         .name           = "emu_src_ck",
2882         .ops            = &clkops_null,
2883         .init           = &omap2_init_clksel_parent,
2884         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2885         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2886         .clksel         = emu_src_clksel,
2887         .flags          = RATE_PROPAGATES,
2888         .clkdm_name     = "emu_clkdm",
2889         .recalc         = &omap2_clksel_recalc,
2890 };
2891
2892 static const struct clksel_rate pclk_emu_rates[] = {
2893         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2894         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2895         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2896         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2897         { .div = 0 },
2898 };
2899
2900 static const struct clksel pclk_emu_clksel[] = {
2901         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2902         { .parent = NULL },
2903 };
2904
2905 static struct clk pclk_fck = {
2906         .name           = "pclk_fck",
2907         .ops            = &clkops_null,
2908         .init           = &omap2_init_clksel_parent,
2909         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2910         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2911         .clksel         = pclk_emu_clksel,
2912         .flags          = RATE_PROPAGATES,
2913         .clkdm_name     = "emu_clkdm",
2914         .recalc         = &omap2_clksel_recalc,
2915 };
2916
2917 static const struct clksel_rate pclkx2_emu_rates[] = {
2918         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2919         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2920         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2921         { .div = 0 },
2922 };
2923
2924 static const struct clksel pclkx2_emu_clksel[] = {
2925         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2926         { .parent = NULL },
2927 };
2928
2929 static struct clk pclkx2_fck = {
2930         .name           = "pclkx2_fck",
2931         .ops            = &clkops_null,
2932         .init           = &omap2_init_clksel_parent,
2933         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2934         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2935         .clksel         = pclkx2_emu_clksel,
2936         .flags          = RATE_PROPAGATES,
2937         .clkdm_name     = "emu_clkdm",
2938         .recalc         = &omap2_clksel_recalc,
2939 };
2940
2941 static const struct clksel atclk_emu_clksel[] = {
2942         { .parent = &emu_src_ck, .rates = div2_rates },
2943         { .parent = NULL },
2944 };
2945
2946 static struct clk atclk_fck = {
2947         .name           = "atclk_fck",
2948         .ops            = &clkops_null,
2949         .init           = &omap2_init_clksel_parent,
2950         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2951         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2952         .clksel         = atclk_emu_clksel,
2953         .flags          = RATE_PROPAGATES,
2954         .clkdm_name     = "emu_clkdm",
2955         .recalc         = &omap2_clksel_recalc,
2956 };
2957
2958 static struct clk traceclk_src_fck = {
2959         .name           = "traceclk_src_fck",
2960         .ops            = &clkops_null,
2961         .init           = &omap2_init_clksel_parent,
2962         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2963         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2964         .clksel         = emu_src_clksel,
2965         .flags          = RATE_PROPAGATES,
2966         .clkdm_name     = "emu_clkdm",
2967         .recalc         = &omap2_clksel_recalc,
2968 };
2969
2970 static const struct clksel_rate traceclk_rates[] = {
2971         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2972         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2973         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2974         { .div = 0 },
2975 };
2976
2977 static const struct clksel traceclk_clksel[] = {
2978         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2979         { .parent = NULL },
2980 };
2981
2982 static struct clk traceclk_fck = {
2983         .name           = "traceclk_fck",
2984         .ops            = &clkops_null,
2985         .init           = &omap2_init_clksel_parent,
2986         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2987         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
2988         .clksel         = traceclk_clksel,
2989         .clkdm_name     = "emu_clkdm",
2990         .recalc         = &omap2_clksel_recalc,
2991 };
2992
2993 /* SR clocks */
2994
2995 /* SmartReflex fclk (VDD1) */
2996 static struct clk sr1_fck = {
2997         .name           = "sr1_fck",
2998         .ops            = &clkops_omap2_dflt_wait,
2999         .parent         = &sys_ck,
3000         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3001         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3002         .flags          = RATE_PROPAGATES,
3003         .recalc         = &followparent_recalc,
3004 };
3005
3006 /* SmartReflex fclk (VDD2) */
3007 static struct clk sr2_fck = {
3008         .name           = "sr2_fck",
3009         .ops            = &clkops_omap2_dflt_wait,
3010         .parent         = &sys_ck,
3011         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3012         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3013         .flags          = RATE_PROPAGATES,
3014         .recalc         = &followparent_recalc,
3015 };
3016
3017 static struct clk sr_l4_ick = {
3018         .name           = "sr_l4_ick",
3019         .ops            = &clkops_null, /* RMK: missing? */
3020         .parent         = &l4_ick,
3021         .clkdm_name     = "core_l4_clkdm",
3022         .recalc         = &followparent_recalc,
3023 };
3024
3025 /* SECURE_32K_FCK clocks */
3026
3027 /* XXX This clock no longer exists in 3430 TRM rev F */
3028 static struct clk gpt12_fck = {
3029         .name           = "gpt12_fck",
3030         .ops            = &clkops_null,
3031         .parent         = &secure_32k_fck,
3032         .recalc         = &followparent_recalc,
3033 };
3034
3035 static struct clk wdt1_fck = {
3036         .name           = "wdt1_fck",
3037         .ops            = &clkops_null,
3038         .parent         = &secure_32k_fck,
3039         .recalc         = &followparent_recalc,
3040 };
3041
3042 #endif