arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  36 static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
  37 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
  38
  39 /* Maximum DPLL multiplier, divider values for OMAP3 */
  40 #define OMAP3_MAX_DPLL_MULT             2048
  41 #define OMAP3_MAX_DPLL_DIV              128
  42
  43 /*
  44  * DPLL1 supplies clock to the MPU.
  45  * DPLL2 supplies clock to the IVA2.
  46  * DPLL3 supplies CORE domain clocks.
  47  * DPLL4 supplies peripheral clocks.
  48  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  49  */
  50
  51 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  52 #define DPLL_LOW_POWER_STOP             0x1
  53 #define DPLL_LOW_POWER_BYPASS           0x5
  54 #define DPLL_LOCKED                     0x7
  55
  56 /* PRM CLOCKS */
  57
  58 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  59 static struct clk omap_32k_fck = {
  60         .name           = "omap_32k_fck",
  61         .ops            = &clkops_null,
  62         .rate           = 32768,
  63         .flags          = RATE_FIXED | RATE_PROPAGATES,
  64 };
  65
  66 static struct clk secure_32k_fck = {
  67         .name           = "secure_32k_fck",
  68         .ops            = &clkops_null,
  69         .rate           = 32768,
  70         .flags          = RATE_FIXED | RATE_PROPAGATES,
  71 };
  72
  73 /* Virtual source clocks for osc_sys_ck */
  74 static struct clk virt_12m_ck = {
  75         .name           = "virt_12m_ck",
  76         .ops            = &clkops_null,
  77         .rate           = 12000000,
  78         .flags          = RATE_FIXED | RATE_PROPAGATES,
  79 };
  80
  81 static struct clk virt_13m_ck = {
  82         .name           = "virt_13m_ck",
  83         .ops            = &clkops_null,
  84         .rate           = 13000000,
  85         .flags          = RATE_FIXED | RATE_PROPAGATES,
  86 };
  87
  88 static struct clk virt_16_8m_ck = {
  89         .name           = "virt_16_8m_ck",
  90         .ops            = &clkops_null,
  91         .rate           = 16800000,
  92         .flags          = RATE_FIXED | RATE_PROPAGATES,
  93 };
  94
  95 static struct clk virt_19_2m_ck = {
  96         .name           = "virt_19_2m_ck",
  97         .ops            = &clkops_null,
  98         .rate           = 19200000,
  99         .flags          = RATE_FIXED | RATE_PROPAGATES,
 100 };
 101
 102 static struct clk virt_26m_ck = {
 103         .name           = "virt_26m_ck",
 104         .ops            = &clkops_null,
 105         .rate           = 26000000,
 106         .flags          = RATE_FIXED | RATE_PROPAGATES,
 107 };
 108
 109 static struct clk virt_38_4m_ck = {
 110         .name           = "virt_38_4m_ck",
 111         .ops            = &clkops_null,
 112         .rate           = 38400000,
 113         .flags          = RATE_FIXED | RATE_PROPAGATES,
 114 };
 115
 116 static const struct clksel_rate osc_sys_12m_rates[] = {
 117         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 118         { .div = 0 }
 119 };
 120
 121 static const struct clksel_rate osc_sys_13m_rates[] = {
 122         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 123         { .div = 0 }
 124 };
 125
 126 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 127         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 128         { .div = 0 }
 129 };
 130
 131 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 132         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 133         { .div = 0 }
 134 };
 135
 136 static const struct clksel_rate osc_sys_26m_rates[] = {
 137         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 138         { .div = 0 }
 139 };
 140
 141 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 142         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 143         { .div = 0 }
 144 };
 145
 146 static const struct clksel osc_sys_clksel[] = {
 147         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 148         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 149         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 150         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 151         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 152         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 153         { .parent = NULL },
 154 };
 155
 156 /* Oscillator clock */
 157 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 158 static struct clk osc_sys_ck = {
 159         .name           = "osc_sys_ck",
 160         .ops            = &clkops_null,
 161         .init           = &omap2_init_clksel_parent,
 162         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 163         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 164         .clksel         = osc_sys_clksel,
 165         /* REVISIT: deal with autoextclkmode? */
 166         .flags          = RATE_FIXED | RATE_PROPAGATES,
 167         .recalc         = &omap2_clksel_recalc,
 168 };
 169
 170 static const struct clksel_rate div2_rates[] = {
 171         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 172         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 173         { .div = 0 }
 174 };
 175
 176 static const struct clksel sys_clksel[] = {
 177         { .parent = &osc_sys_ck, .rates = div2_rates },
 178         { .parent = NULL }
 179 };
 180
 181 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 182 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 183 static struct clk sys_ck = {
 184         .name           = "sys_ck",
 185         .ops            = &clkops_null,
 186         .parent         = &osc_sys_ck,
 187         .init           = &omap2_init_clksel_parent,
 188         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 189         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 190         .clksel         = sys_clksel,
 191         .flags          = RATE_PROPAGATES,
 192         .recalc         = &omap2_clksel_recalc,
 193 };
 194
 195 static struct clk sys_altclk = {
 196         .name           = "sys_altclk",
 197         .ops            = &clkops_null,
 198         .flags          = RATE_PROPAGATES,
 199 };
 200
 201 /* Optional external clock input for some McBSPs */
 202 static struct clk mcbsp_clks = {
 203         .name           = "mcbsp_clks",
 204         .ops            = &clkops_null,
 205         .flags          = RATE_PROPAGATES,
 206 };
 207
 208 /* PRM EXTERNAL CLOCK OUTPUT */
 209
 210 static struct clk sys_clkout1 = {
 211         .name           = "sys_clkout1",
 212         .ops            = &clkops_omap2_dflt,
 213         .parent         = &osc_sys_ck,
 214         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 215         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 216         .recalc         = &followparent_recalc,
 217 };
 218
 219 /* DPLLS */
 220
 221 /* CM CLOCKS */
 222
 223 static const struct clksel_rate dpll_bypass_rates[] = {
 224         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 225         { .div = 0 }
 226 };
 227
 228 static const struct clksel_rate dpll_locked_rates[] = {
 229         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 230         { .div = 0 }
 231 };
 232
 233 static const struct clksel_rate div16_dpll_rates[] = {
 234         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 235         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 236         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 237         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 238         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 239         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 240         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 241         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 242         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 243         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 244         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 245         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 246         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 247         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 248         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 249         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 250         { .div = 0 }
 251 };
 252
 253 /* DPLL1 */
 254 /* MPU clock source */
 255 /* Type: DPLL */
 256 static struct dpll_data dpll1_dd = {
 257         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 258         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 259         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 260         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 261         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 262         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 263         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 264         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 265         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 266         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 267         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 268         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 269         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 270         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
 271         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 272         .min_divider    = 1,
 273         .max_divider    = OMAP3_MAX_DPLL_DIV,
 274         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 275 };
 276
 277 static struct clk dpll1_ck = {
 278         .name           = "dpll1_ck",
 279         .ops            = &clkops_null,
 280         .parent         = &sys_ck,
 281         .dpll_data      = &dpll1_dd,
 282         .flags          = RATE_PROPAGATES,
 283         .round_rate     = &omap2_dpll_round_rate,
 284         .set_rate       = &omap3_noncore_dpll_set_rate,
 285         .clkdm_name     = "dpll1_clkdm",
 286         .recalc         = &omap3_dpll_recalc,
 287 };
 288
 289 /*
 290  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 291  * DPLL isn't bypassed.
 292  */
 293 static struct clk dpll1_x2_ck = {
 294         .name           = "dpll1_x2_ck",
 295         .ops            = &clkops_null,
 296         .parent         = &dpll1_ck,
 297         .flags          = RATE_PROPAGATES,
 298         .clkdm_name     = "dpll1_clkdm",
 299         .recalc         = &omap3_clkoutx2_recalc,
 300 };
 301
 302 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 303 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 304         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 305         { .parent = NULL }
 306 };
 307
 308 /*
 309  * Does not exist in the TRM - needed to separate the M2 divider from
 310  * bypass selection in mpu_ck
 311  */
 312 static struct clk dpll1_x2m2_ck = {
 313         .name           = "dpll1_x2m2_ck",
 314         .ops            = &clkops_null,
 315         .parent         = &dpll1_x2_ck,
 316         .init           = &omap2_init_clksel_parent,
 317         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 318         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 319         .clksel         = div16_dpll1_x2m2_clksel,
 320         .flags          = RATE_PROPAGATES,
 321         .clkdm_name     = "dpll1_clkdm",
 322         .recalc         = &omap2_clksel_recalc,
 323 };
 324
 325 /* DPLL2 */
 326 /* IVA2 clock source */
 327 /* Type: DPLL */
 328
 329 static struct dpll_data dpll2_dd = {
 330         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 331         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 332         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 333         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 334         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 335         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 336         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 337                                 (1 << DPLL_LOW_POWER_BYPASS),
 338         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 339         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 340         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 341         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 342         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 343         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 344         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
 345         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 346         .min_divider    = 1,
 347         .max_divider    = OMAP3_MAX_DPLL_DIV,
 348         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 349 };
 350
 351 static struct clk dpll2_ck = {
 352         .name           = "dpll2_ck",
 353         .ops            = &clkops_noncore_dpll_ops,
 354         .parent         = &sys_ck,
 355         .dpll_data      = &dpll2_dd,
 356         .flags          = RATE_PROPAGATES,
 357         .round_rate     = &omap2_dpll_round_rate,
 358         .set_rate       = &omap3_noncore_dpll_set_rate,
 359         .clkdm_name     = "dpll2_clkdm",
 360         .recalc         = &omap3_dpll_recalc,
 361 };
 362
 363 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 364         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 365         { .parent = NULL }
 366 };
 367
 368 /*
 369  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 370  * or CLKOUTX2. CLKOUT seems most plausible.
 371  */
 372 static struct clk dpll2_m2_ck = {
 373         .name           = "dpll2_m2_ck",
 374         .ops            = &clkops_null,
 375         .parent         = &dpll2_ck,
 376         .init           = &omap2_init_clksel_parent,
 377         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 378                                           OMAP3430_CM_CLKSEL2_PLL),
 379         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 380         .clksel         = div16_dpll2_m2x2_clksel,
 381         .flags          = RATE_PROPAGATES,
 382         .clkdm_name     = "dpll2_clkdm",
 383         .recalc         = &omap2_clksel_recalc,
 384 };
 385
 386 /*
 387  * DPLL3
 388  * Source clock for all interfaces and for some device fclks
 389  * REVISIT: Also supports fast relock bypass - not included below
 390  */
 391 static struct dpll_data dpll3_dd = {
 392         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 393         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 394         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 395         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 396         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 397         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 398         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 399         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 400         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 401         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 402         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 403         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 404         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
 405         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 406         .min_divider    = 1,
 407         .max_divider    = OMAP3_MAX_DPLL_DIV,
 408         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 409 };
 410
 411 static struct clk dpll3_ck = {
 412         .name           = "dpll3_ck",
 413         .ops            = &clkops_null,
 414         .parent         = &sys_ck,
 415         .dpll_data      = &dpll3_dd,
 416         .flags          = RATE_PROPAGATES,
 417         .round_rate     = &omap2_dpll_round_rate,
 418         .clkdm_name     = "dpll3_clkdm",
 419         .recalc         = &omap3_dpll_recalc,
 420 };
 421
 422 /*
 423  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 424  * DPLL isn't bypassed
 425  */
 426 static struct clk dpll3_x2_ck = {
 427         .name           = "dpll3_x2_ck",
 428         .ops            = &clkops_null,
 429         .parent         = &dpll3_ck,
 430         .flags          = RATE_PROPAGATES,
 431         .clkdm_name     = "dpll3_clkdm",
 432         .recalc         = &omap3_clkoutx2_recalc,
 433 };
 434
 435 static const struct clksel_rate div31_dpll3_rates[] = {
 436         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 437         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 438         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 439         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 440         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 441         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 442         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 443         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 444         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 445         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 446         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 447         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 448         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 449         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 450         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 451         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 452         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 453         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 454         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 455         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 456         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 457         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 458         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 459         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 460         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 461         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 462         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 463         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 464         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 465         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 466         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 467         { .div = 0 },
 468 };
 469
 470 static const struct clksel div31_dpll3m2_clksel[] = {
 471         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 472         { .parent = NULL }
 473 };
 474
 475 /* DPLL3 output M2 - primary control point for CORE speed */
 476 static struct clk dpll3_m2_ck = {
 477         .name           = "dpll3_m2_ck",
 478         .ops            = &clkops_null,
 479         .parent         = &dpll3_ck,
 480         .init           = &omap2_init_clksel_parent,
 481         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 482         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 483         .clksel         = div31_dpll3m2_clksel,
 484         .flags          = RATE_PROPAGATES,
 485         .clkdm_name     = "dpll3_clkdm",
 486         .round_rate     = &omap2_clksel_round_rate,
 487         .set_rate       = &omap3_core_dpll_m2_set_rate,
 488         .recalc         = &omap2_clksel_recalc,
 489 };
 490
 491 static const struct clksel core_ck_clksel[] = {
 492         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 493         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 494         { .parent = NULL }
 495 };
 496
 497 static struct clk core_ck = {
 498         .name           = "core_ck",
 499         .ops            = &clkops_null,
 500         .init           = &omap2_init_clksel_parent,
 501         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 502         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 503         .clksel         = core_ck_clksel,
 504         .flags          = RATE_PROPAGATES,
 505         .recalc         = &omap2_clksel_recalc,
 506 };
 507
 508 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 509         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 510         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 511         { .parent = NULL }
 512 };
 513
 514 static struct clk dpll3_m2x2_ck = {
 515         .name           = "dpll3_m2x2_ck",
 516         .ops            = &clkops_null,
 517         .init           = &omap2_init_clksel_parent,
 518         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 519         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 520         .clksel         = dpll3_m2x2_ck_clksel,
 521         .flags          = RATE_PROPAGATES,
 522         .clkdm_name     = "dpll3_clkdm",
 523         .recalc         = &omap2_clksel_recalc,
 524 };
 525
 526 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 527 static const struct clksel div16_dpll3_clksel[] = {
 528         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 529         { .parent = NULL }
 530 };
 531
 532 /* This virtual clock is the source for dpll3_m3x2_ck */
 533 static struct clk dpll3_m3_ck = {
 534         .name           = "dpll3_m3_ck",
 535         .ops            = &clkops_null,
 536         .parent         = &dpll3_ck,
 537         .init           = &omap2_init_clksel_parent,
 538         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 539         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 540         .clksel         = div16_dpll3_clksel,
 541         .flags          = RATE_PROPAGATES,
 542         .clkdm_name     = "dpll3_clkdm",
 543         .recalc         = &omap2_clksel_recalc,
 544 };
 545
 546 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 547 static struct clk dpll3_m3x2_ck = {
 548         .name           = "dpll3_m3x2_ck",
 549         .ops            = &clkops_omap2_dflt_wait,
 550         .parent         = &dpll3_m3_ck,
 551         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 552         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 553         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 554         .clkdm_name     = "dpll3_clkdm",
 555         .recalc         = &omap3_clkoutx2_recalc,
 556 };
 557
 558 static const struct clksel emu_core_alwon_ck_clksel[] = {
 559         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 560         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 561         { .parent = NULL }
 562 };
 563
 564 static struct clk emu_core_alwon_ck = {
 565         .name           = "emu_core_alwon_ck",
 566         .ops            = &clkops_null,
 567         .parent         = &dpll3_m3x2_ck,
 568         .init           = &omap2_init_clksel_parent,
 569         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 570         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 571         .clksel         = emu_core_alwon_ck_clksel,
 572         .flags          = RATE_PROPAGATES,
 573         .clkdm_name     = "dpll3_clkdm",
 574         .recalc         = &omap2_clksel_recalc,
 575 };
 576
 577 /* DPLL4 */
 578 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 579 /* Type: DPLL */
 580 static struct dpll_data dpll4_dd = {
 581         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 582         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 583         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 584         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 585         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 586         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 587         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 588         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 589         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 590         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 591         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 592         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 593         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 594         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 595         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 596         .min_divider    = 1,
 597         .max_divider    = OMAP3_MAX_DPLL_DIV,
 598         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 599 };
 600
 601 static struct clk dpll4_ck = {
 602         .name           = "dpll4_ck",
 603         .ops            = &clkops_noncore_dpll_ops,
 604         .parent         = &sys_ck,
 605         .dpll_data      = &dpll4_dd,
 606         .flags          = RATE_PROPAGATES,
 607         .round_rate     = &omap2_dpll_round_rate,
 608         .set_rate       = &omap3_dpll4_set_rate,
 609         .clkdm_name     = "dpll4_clkdm",
 610         .recalc         = &omap3_dpll_recalc,
 611 };
 612
 613 /*
 614  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 615  * DPLL isn't bypassed --
 616  * XXX does this serve any downstream clocks?
 617  */
 618 static struct clk dpll4_x2_ck = {
 619         .name           = "dpll4_x2_ck",
 620         .ops            = &clkops_null,
 621         .parent         = &dpll4_ck,
 622         .flags          = RATE_PROPAGATES,
 623         .clkdm_name     = "dpll4_clkdm",
 624         .recalc         = &omap3_clkoutx2_recalc,
 625 };
 626
 627 static const struct clksel div16_dpll4_clksel[] = {
 628         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 629         { .parent = NULL }
 630 };
 631
 632 /* This virtual clock is the source for dpll4_m2x2_ck */
 633 static struct clk dpll4_m2_ck = {
 634         .name           = "dpll4_m2_ck",
 635         .ops            = &clkops_null,
 636         .parent         = &dpll4_ck,
 637         .init           = &omap2_init_clksel_parent,
 638         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 639         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 640         .clksel         = div16_dpll4_clksel,
 641         .flags          = RATE_PROPAGATES,
 642         .clkdm_name     = "dpll4_clkdm",
 643         .recalc         = &omap2_clksel_recalc,
 644 };
 645
 646 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 647 static struct clk dpll4_m2x2_ck = {
 648         .name           = "dpll4_m2x2_ck",
 649         .ops            = &clkops_omap2_dflt_wait,
 650         .parent         = &dpll4_m2_ck,
 651         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 652         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 653         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 654         .clkdm_name     = "dpll4_clkdm",
 655         .recalc         = &omap3_clkoutx2_recalc,
 656 };
 657
 658 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 659         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 660         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 661         { .parent = NULL }
 662 };
 663
 664 /*
 665  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 666  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 667  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 668  * CM_96K_(F)CLK.
 669  */
 670 static struct clk omap_96m_alwon_fck = {
 671         .name           = "omap_96m_alwon_fck",
 672         .ops            = &clkops_null,
 673         .parent         = &dpll4_m2x2_ck,
 674         .init           = &omap2_init_clksel_parent,
 675         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 676         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 677         .clksel         = omap_96m_alwon_fck_clksel,
 678         .flags          = RATE_PROPAGATES,
 679         .recalc         = &omap2_clksel_recalc,
 680 };
 681
 682 static struct clk cm_96m_fck = {
 683         .name           = "cm_96m_fck",
 684         .ops            = &clkops_null,
 685         .parent         = &omap_96m_alwon_fck,
 686         .flags          = RATE_PROPAGATES,
 687         .recalc         = &followparent_recalc,
 688 };
 689
 690 static const struct clksel_rate omap_96m_dpll_rates[] = {
 691         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 692         { .div = 0 }
 693 };
 694
 695 static const struct clksel_rate omap_96m_sys_rates[] = {
 696         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 697         { .div = 0 }
 698 };
 699
 700 static const struct clksel omap_96m_fck_clksel[] = {
 701         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 702         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 703         { .parent = NULL }
 704 };
 705
 706 static struct clk omap_96m_fck = {
 707         .name           = "omap_96m_fck",
 708         .ops            = &clkops_null,
 709         .parent         = &sys_ck,
 710         .init           = &omap2_init_clksel_parent,
 711         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 712         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 713         .clksel         = omap_96m_fck_clksel,
 714         .flags          = RATE_PROPAGATES,
 715         .recalc         = &omap2_clksel_recalc,
 716 };
 717
 718 /* This virtual clock is the source for dpll4_m3x2_ck */
 719 static struct clk dpll4_m3_ck = {
 720         .name           = "dpll4_m3_ck",
 721         .ops            = &clkops_null,
 722         .parent         = &dpll4_ck,
 723         .init           = &omap2_init_clksel_parent,
 724         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 725         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 726         .clksel         = div16_dpll4_clksel,
 727         .flags          = RATE_PROPAGATES,
 728         .clkdm_name     = "dpll4_clkdm",
 729         .recalc         = &omap2_clksel_recalc,
 730 };
 731
 732 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 733 static struct clk dpll4_m3x2_ck = {
 734         .name           = "dpll4_m3x2_ck",
 735         .ops            = &clkops_omap2_dflt_wait,
 736         .parent         = &dpll4_m3_ck,
 737         .init           = &omap2_init_clksel_parent,
 738         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 739         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 740         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 741         .clkdm_name     = "dpll4_clkdm",
 742         .recalc         = &omap3_clkoutx2_recalc,
 743 };
 744
 745 static const struct clksel virt_omap_54m_fck_clksel[] = {
 746         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 747         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 748         { .parent = NULL }
 749 };
 750
 751 static struct clk virt_omap_54m_fck = {
 752         .name           = "virt_omap_54m_fck",
 753         .ops            = &clkops_null,
 754         .parent         = &dpll4_m3x2_ck,
 755         .init           = &omap2_init_clksel_parent,
 756         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 757         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 758         .clksel         = virt_omap_54m_fck_clksel,
 759         .flags          = RATE_PROPAGATES,
 760         .recalc         = &omap2_clksel_recalc,
 761 };
 762
 763 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 764         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 765         { .div = 0 }
 766 };
 767
 768 static const struct clksel_rate omap_54m_alt_rates[] = {
 769         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 770         { .div = 0 }
 771 };
 772
 773 static const struct clksel omap_54m_clksel[] = {
 774         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 775         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 776         { .parent = NULL }
 777 };
 778
 779 static struct clk omap_54m_fck = {
 780         .name           = "omap_54m_fck",
 781         .ops            = &clkops_null,
 782         .init           = &omap2_init_clksel_parent,
 783         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 784         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 785         .clksel         = omap_54m_clksel,
 786         .flags          = RATE_PROPAGATES,
 787         .recalc         = &omap2_clksel_recalc,
 788 };
 789
 790 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 791         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 792         { .div = 0 }
 793 };
 794
 795 static const struct clksel_rate omap_48m_alt_rates[] = {
 796         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 797         { .div = 0 }
 798 };
 799
 800 static const struct clksel omap_48m_clksel[] = {
 801         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 802         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 803         { .parent = NULL }
 804 };
 805
 806 static struct clk omap_48m_fck = {
 807         .name           = "omap_48m_fck",
 808         .ops            = &clkops_null,
 809         .init           = &omap2_init_clksel_parent,
 810         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 811         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 812         .clksel         = omap_48m_clksel,
 813         .flags          = RATE_PROPAGATES,
 814         .recalc         = &omap2_clksel_recalc,
 815 };
 816
 817 static struct clk omap_12m_fck = {
 818         .name           = "omap_12m_fck",
 819         .ops            = &clkops_null,
 820         .parent         = &omap_48m_fck,
 821         .fixed_div      = 4,
 822         .flags          = RATE_PROPAGATES,
 823         .recalc         = &omap2_fixed_divisor_recalc,
 824 };
 825
 826 /* This virstual clock is the source for dpll4_m4x2_ck */
 827 static struct clk dpll4_m4_ck = {
 828         .name           = "dpll4_m4_ck",
 829         .ops            = &clkops_null,
 830         .parent         = &dpll4_ck,
 831         .init           = &omap2_init_clksel_parent,
 832         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 833         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 834         .clksel         = div16_dpll4_clksel,
 835         .flags          = RATE_PROPAGATES,
 836         .clkdm_name     = "dpll4_clkdm",
 837         .recalc         = &omap2_clksel_recalc,
 838         .set_rate       = &omap2_clksel_set_rate,
 839         .round_rate     = &omap2_clksel_round_rate,
 840 };
 841
 842 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 843 static struct clk dpll4_m4x2_ck = {
 844         .name           = "dpll4_m4x2_ck",
 845         .ops            = &clkops_omap2_dflt_wait,
 846         .parent         = &dpll4_m4_ck,
 847         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 848         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 849         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 850         .clkdm_name     = "dpll4_clkdm",
 851         .recalc         = &omap3_clkoutx2_recalc,
 852 };
 853
 854 /* This virtual clock is the source for dpll4_m5x2_ck */
 855 static struct clk dpll4_m5_ck = {
 856         .name           = "dpll4_m5_ck",
 857         .ops            = &clkops_null,
 858         .parent         = &dpll4_ck,
 859         .init           = &omap2_init_clksel_parent,
 860         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 861         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 862         .clksel         = div16_dpll4_clksel,
 863         .flags          = RATE_PROPAGATES,
 864         .clkdm_name     = "dpll4_clkdm",
 865         .recalc         = &omap2_clksel_recalc,
 866 };
 867
 868 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 869 static struct clk dpll4_m5x2_ck = {
 870         .name           = "dpll4_m5x2_ck",
 871         .ops            = &clkops_omap2_dflt_wait,
 872         .parent         = &dpll4_m5_ck,
 873         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 874         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 875         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 876         .clkdm_name     = "dpll4_clkdm",
 877         .recalc         = &omap3_clkoutx2_recalc,
 878 };
 879
 880 /* This virtual clock is the source for dpll4_m6x2_ck */
 881 static struct clk dpll4_m6_ck = {
 882         .name           = "dpll4_m6_ck",
 883         .ops            = &clkops_null,
 884         .parent         = &dpll4_ck,
 885         .init           = &omap2_init_clksel_parent,
 886         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 887         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 888         .clksel         = div16_dpll4_clksel,
 889         .flags          = RATE_PROPAGATES,
 890         .clkdm_name     = "dpll4_clkdm",
 891         .recalc         = &omap2_clksel_recalc,
 892 };
 893
 894 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 895 static struct clk dpll4_m6x2_ck = {
 896         .name           = "dpll4_m6x2_ck",
 897         .ops            = &clkops_omap2_dflt_wait,
 898         .parent         = &dpll4_m6_ck,
 899         .init           = &omap2_init_clksel_parent,
 900         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 901         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 902         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 903         .clkdm_name     = "dpll4_clkdm",
 904         .recalc         = &omap3_clkoutx2_recalc,
 905 };
 906
 907 static struct clk emu_per_alwon_ck = {
 908         .name           = "emu_per_alwon_ck",
 909         .ops            = &clkops_null,
 910         .parent         = &dpll4_m6x2_ck,
 911         .flags          = RATE_PROPAGATES,
 912         .clkdm_name     = "dpll4_clkdm",
 913         .recalc         = &followparent_recalc,
 914 };
 915
 916 /* DPLL5 */
 917 /* Supplies 120MHz clock, USIM source clock */
 918 /* Type: DPLL */
 919 /* 3430ES2 only */
 920 static struct dpll_data dpll5_dd = {
 921         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 922         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 923         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 924         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 925         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 926         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 927         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 928         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 929         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 930         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 931         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 932         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 933         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 934         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 935         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 936         .min_divider    = 1,
 937         .max_divider    = OMAP3_MAX_DPLL_DIV,
 938         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 939 };
 940
 941 static struct clk dpll5_ck = {
 942         .name           = "dpll5_ck",
 943         .ops            = &clkops_noncore_dpll_ops,
 944         .parent         = &sys_ck,
 945         .dpll_data      = &dpll5_dd,
 946         .flags          = RATE_PROPAGATES,
 947         .round_rate     = &omap2_dpll_round_rate,
 948         .set_rate       = &omap3_noncore_dpll_set_rate,
 949         .clkdm_name     = "dpll5_clkdm",
 950         .recalc         = &omap3_dpll_recalc,
 951 };
 952
 953 static const struct clksel div16_dpll5_clksel[] = {
 954         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 955         { .parent = NULL }
 956 };
 957
 958 static struct clk dpll5_m2_ck = {
 959         .name           = "dpll5_m2_ck",
 960         .ops            = &clkops_null,
 961         .parent         = &dpll5_ck,
 962         .init           = &omap2_init_clksel_parent,
 963         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 964         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 965         .clksel         = div16_dpll5_clksel,
 966         .flags          = RATE_PROPAGATES,
 967         .clkdm_name     = "dpll5_clkdm",
 968         .recalc         = &omap2_clksel_recalc,
 969 };
 970
 971 static const struct clksel omap_120m_fck_clksel[] = {
 972         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 973         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
 974         { .parent = NULL }
 975 };
 976
 977 static struct clk omap_120m_fck = {
 978         .name           = "omap_120m_fck",
 979         .ops            = &clkops_null,
 980         .parent         = &dpll5_m2_ck,
 981         .init           = &omap2_init_clksel_parent,
 982         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 983         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 984         .clksel         = omap_120m_fck_clksel,
 985         .flags          = RATE_PROPAGATES,
 986         .recalc         = &omap2_clksel_recalc,
 987 };
 988
 989 /* CM EXTERNAL CLOCK OUTPUTS */
 990
 991 static const struct clksel_rate clkout2_src_core_rates[] = {
 992         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 993         { .div = 0 }
 994 };
 995
 996 static const struct clksel_rate clkout2_src_sys_rates[] = {
 997         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 998         { .div = 0 }
 999 };
1000
1001 static const struct clksel_rate clkout2_src_96m_rates[] = {
1002         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
1003         { .div = 0 }
1004 };
1005
1006 static const struct clksel_rate clkout2_src_54m_rates[] = {
1007         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1008         { .div = 0 }
1009 };
1010
1011 static const struct clksel clkout2_src_clksel[] = {
1012         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
1013         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
1014         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
1015         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
1016         { .parent = NULL }
1017 };
1018
1019 static struct clk clkout2_src_ck = {
1020         .name           = "clkout2_src_ck",
1021         .ops            = &clkops_omap2_dflt,
1022         .init           = &omap2_init_clksel_parent,
1023         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
1024         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
1025         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
1026         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
1027         .clksel         = clkout2_src_clksel,
1028         .flags          = RATE_PROPAGATES,
1029         .clkdm_name     = "core_clkdm",
1030         .recalc         = &omap2_clksel_recalc,
1031 };
1032
1033 static const struct clksel_rate sys_clkout2_rates[] = {
1034         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1035         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1036         { .div = 4, .val = 2, .flags = RATE_IN_343X },
1037         { .div = 8, .val = 3, .flags = RATE_IN_343X },
1038         { .div = 16, .val = 4, .flags = RATE_IN_343X },
1039         { .div = 0 },
1040 };
1041
1042 static const struct clksel sys_clkout2_clksel[] = {
1043         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1044         { .parent = NULL },
1045 };
1046
1047 static struct clk sys_clkout2 = {
1048         .name           = "sys_clkout2",
1049         .ops            = &clkops_null,
1050         .init           = &omap2_init_clksel_parent,
1051         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
1052         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1053         .clksel         = sys_clkout2_clksel,
1054         .recalc         = &omap2_clksel_recalc,
1055 };
1056
1057 /* CM OUTPUT CLOCKS */
1058
1059 static struct clk corex2_fck = {
1060         .name           = "corex2_fck",
1061         .ops            = &clkops_null,
1062         .parent         = &dpll3_m2x2_ck,
1063         .flags          = RATE_PROPAGATES,
1064         .recalc         = &followparent_recalc,
1065 };
1066
1067 /* DPLL power domain clock controls */
1068
1069 static const struct clksel_rate div4_rates[] = {
1070         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1071         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1072         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1073         { .div = 0 }
1074 };
1075
1076 static const struct clksel div4_core_clksel[] = {
1077         { .parent = &core_ck, .rates = div4_rates },
1078         { .parent = NULL }
1079 };
1080
1081 /*
1082  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1083  * may be inconsistent here?
1084  */
1085 static struct clk dpll1_fck = {
1086         .name           = "dpll1_fck",
1087         .ops            = &clkops_null,
1088         .parent         = &core_ck,
1089         .init           = &omap2_init_clksel_parent,
1090         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1091         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1092         .clksel         = div4_core_clksel,
1093         .flags          = RATE_PROPAGATES,
1094         .recalc         = &omap2_clksel_recalc,
1095 };
1096
1097 /*
1098  * MPU clksel:
1099  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1100  * derives from the high-frequency bypass clock originating from DPLL3,
1101  * called 'dpll1_fck'
1102  */
1103 static const struct clksel mpu_clksel[] = {
1104         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1105         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1106         { .parent = NULL }
1107 };
1108
1109 static struct clk mpu_ck = {
1110         .name           = "mpu_ck",
1111         .ops            = &clkops_null,
1112         .parent         = &dpll1_x2m2_ck,
1113         .init           = &omap2_init_clksel_parent,
1114         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1115         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1116         .clksel         = mpu_clksel,
1117         .flags          = RATE_PROPAGATES,
1118         .clkdm_name     = "mpu_clkdm",
1119         .recalc         = &omap2_clksel_recalc,
1120 };
1121
1122 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1123 static const struct clksel_rate arm_fck_rates[] = {
1124         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1125         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1126         { .div = 0 },
1127 };
1128
1129 static const struct clksel arm_fck_clksel[] = {
1130         { .parent = &mpu_ck, .rates = arm_fck_rates },
1131         { .parent = NULL }
1132 };
1133
1134 static struct clk arm_fck = {
1135         .name           = "arm_fck",
1136         .ops            = &clkops_null,
1137         .parent         = &mpu_ck,
1138         .init           = &omap2_init_clksel_parent,
1139         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1140         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1141         .clksel         = arm_fck_clksel,
1142         .flags          = RATE_PROPAGATES,
1143         .recalc         = &omap2_clksel_recalc,
1144 };
1145
1146 /* XXX What about neon_clkdm ? */
1147
1148 /*
1149  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1150  * although it is referenced - so this is a guess
1151  */
1152 static struct clk emu_mpu_alwon_ck = {
1153         .name           = "emu_mpu_alwon_ck",
1154         .ops            = &clkops_null,
1155         .parent         = &mpu_ck,
1156         .flags          = RATE_PROPAGATES,
1157         .recalc         = &followparent_recalc,
1158 };
1159
1160 static struct clk dpll2_fck = {
1161         .name           = "dpll2_fck",
1162         .ops            = &clkops_null,
1163         .parent         = &core_ck,
1164         .init           = &omap2_init_clksel_parent,
1165         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1166         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1167         .clksel         = div4_core_clksel,
1168         .flags          = RATE_PROPAGATES,
1169         .recalc         = &omap2_clksel_recalc,
1170 };
1171
1172 /*
1173  * IVA2 clksel:
1174  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1175  * derives from the high-frequency bypass clock originating from DPLL3,
1176  * called 'dpll2_fck'
1177  */
1178
1179 static const struct clksel iva2_clksel[] = {
1180         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1181         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1182         { .parent = NULL }
1183 };
1184
1185 static struct clk iva2_ck = {
1186         .name           = "iva2_ck",
1187         .ops            = &clkops_omap2_dflt_wait,
1188         .parent         = &dpll2_m2_ck,
1189         .init           = &omap2_init_clksel_parent,
1190         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1191         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1192         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1193                                           OMAP3430_CM_IDLEST_PLL),
1194         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1195         .clksel         = iva2_clksel,
1196         .flags          = RATE_PROPAGATES,
1197         .clkdm_name     = "iva2_clkdm",
1198         .recalc         = &omap2_clksel_recalc,
1199 };
1200
1201 /* Common interface clocks */
1202
1203 static const struct clksel div2_core_clksel[] = {
1204         { .parent = &core_ck, .rates = div2_rates },
1205         { .parent = NULL }
1206 };
1207
1208 static struct clk l3_ick = {
1209         .name           = "l3_ick",
1210         .ops            = &clkops_null,
1211         .parent         = &core_ck,
1212         .init           = &omap2_init_clksel_parent,
1213         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1214         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1215         .clksel         = div2_core_clksel,
1216         .flags          = RATE_PROPAGATES,
1217         .clkdm_name     = "core_l3_clkdm",
1218         .recalc         = &omap2_clksel_recalc,
1219 };
1220
1221 static const struct clksel div2_l3_clksel[] = {
1222         { .parent = &l3_ick, .rates = div2_rates },
1223         { .parent = NULL }
1224 };
1225
1226 static struct clk l4_ick = {
1227         .name           = "l4_ick",
1228         .ops            = &clkops_null,
1229         .parent         = &l3_ick,
1230         .init           = &omap2_init_clksel_parent,
1231         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1232         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1233         .clksel         = div2_l3_clksel,
1234         .flags          = RATE_PROPAGATES,
1235         .clkdm_name     = "core_l4_clkdm",
1236         .recalc         = &omap2_clksel_recalc,
1237
1238 };
1239
1240 static const struct clksel div2_l4_clksel[] = {
1241         { .parent = &l4_ick, .rates = div2_rates },
1242         { .parent = NULL }
1243 };
1244
1245 static struct clk rm_ick = {
1246         .name           = "rm_ick",
1247         .ops            = &clkops_null,
1248         .parent         = &l4_ick,
1249         .init           = &omap2_init_clksel_parent,
1250         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1251         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1252         .clksel         = div2_l4_clksel,
1253         .recalc         = &omap2_clksel_recalc,
1254 };
1255
1256 /* GFX power domain */
1257
1258 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1259
1260 static const struct clksel gfx_l3_clksel[] = {
1261         { .parent = &l3_ick, .rates = gfx_l3_rates },
1262         { .parent = NULL }
1263 };
1264
1265 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1266 static struct clk gfx_l3_ck = {
1267         .name           = "gfx_l3_ck",
1268         .ops            = &clkops_omap2_dflt_wait,
1269         .parent         = &l3_ick,
1270         .init           = &omap2_init_clksel_parent,
1271         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1272         .enable_bit     = OMAP_EN_GFX_SHIFT,
1273         .recalc         = &followparent_recalc,
1274 };
1275
1276 static struct clk gfx_l3_fck = {
1277         .name           = "gfx_l3_fck",
1278         .ops            = &clkops_null,
1279         .parent         = &gfx_l3_ck,
1280         .init           = &omap2_init_clksel_parent,
1281         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1282         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1283         .clksel         = gfx_l3_clksel,
1284         .flags          = RATE_PROPAGATES,
1285         .clkdm_name     = "gfx_3430es1_clkdm",
1286         .recalc         = &omap2_clksel_recalc,
1287 };
1288
1289 static struct clk gfx_l3_ick = {
1290         .name           = "gfx_l3_ick",
1291         .ops            = &clkops_null,
1292         .parent         = &gfx_l3_ck,
1293         .clkdm_name     = "gfx_3430es1_clkdm",
1294         .recalc         = &followparent_recalc,
1295 };
1296
1297 static struct clk gfx_cg1_ck = {
1298         .name           = "gfx_cg1_ck",
1299         .ops            = &clkops_omap2_dflt_wait,
1300         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1301         .init           = &omap2_init_clk_clkdm,
1302         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1303         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1304         .clkdm_name     = "gfx_3430es1_clkdm",
1305         .recalc         = &followparent_recalc,
1306 };
1307
1308 static struct clk gfx_cg2_ck = {
1309         .name           = "gfx_cg2_ck",
1310         .ops            = &clkops_omap2_dflt_wait,
1311         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1312         .init           = &omap2_init_clk_clkdm,
1313         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1314         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1315         .clkdm_name     = "gfx_3430es1_clkdm",
1316         .recalc         = &followparent_recalc,
1317 };
1318
1319 /* SGX power domain - 3430ES2 only */
1320
1321 static const struct clksel_rate sgx_core_rates[] = {
1322         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1323         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1324         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1325         { .div = 0 },
1326 };
1327
1328 static const struct clksel_rate sgx_96m_rates[] = {
1329         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1330         { .div = 0 },
1331 };
1332
1333 static const struct clksel sgx_clksel[] = {
1334         { .parent = &core_ck,    .rates = sgx_core_rates },
1335         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1336         { .parent = NULL },
1337 };
1338
1339 static struct clk sgx_fck = {
1340         .name           = "sgx_fck",
1341         .ops            = &clkops_omap2_dflt_wait,
1342         .init           = &omap2_init_clksel_parent,
1343         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1344         .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1345         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1346         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1347         .clksel         = sgx_clksel,
1348         .clkdm_name     = "sgx_clkdm",
1349         .recalc         = &omap2_clksel_recalc,
1350 };
1351
1352 static struct clk sgx_ick = {
1353         .name           = "sgx_ick",
1354         .ops            = &clkops_omap2_dflt_wait,
1355         .parent         = &l3_ick,
1356         .init           = &omap2_init_clk_clkdm,
1357         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1358         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1359         .clkdm_name     = "sgx_clkdm",
1360         .recalc         = &followparent_recalc,
1361 };
1362
1363 /* CORE power domain */
1364
1365 static struct clk d2d_26m_fck = {
1366         .name           = "d2d_26m_fck",
1367         .ops            = &clkops_omap2_dflt_wait,
1368         .parent         = &sys_ck,
1369         .init           = &omap2_init_clk_clkdm,
1370         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1371         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1372         .clkdm_name     = "d2d_clkdm",
1373         .recalc         = &followparent_recalc,
1374 };
1375
1376 static const struct clksel omap343x_gpt_clksel[] = {
1377         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1378         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1379         { .parent = NULL}
1380 };
1381
1382 static struct clk gpt10_fck = {
1383         .name           = "gpt10_fck",
1384         .ops            = &clkops_omap2_dflt_wait,
1385         .parent         = &sys_ck,
1386         .init           = &omap2_init_clksel_parent,
1387         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1388         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1389         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1390         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1391         .clksel         = omap343x_gpt_clksel,
1392         .clkdm_name     = "core_l4_clkdm",
1393         .recalc         = &omap2_clksel_recalc,
1394 };
1395
1396 static struct clk gpt11_fck = {
1397         .name           = "gpt11_fck",
1398         .ops            = &clkops_omap2_dflt_wait,
1399         .parent         = &sys_ck,
1400         .init           = &omap2_init_clksel_parent,
1401         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1402         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1403         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1404         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1405         .clksel         = omap343x_gpt_clksel,
1406         .clkdm_name     = "core_l4_clkdm",
1407         .recalc         = &omap2_clksel_recalc,
1408 };
1409
1410 static struct clk cpefuse_fck = {
1411         .name           = "cpefuse_fck",
1412         .ops            = &clkops_omap2_dflt,
1413         .parent         = &sys_ck,
1414         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1415         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1416         .recalc         = &followparent_recalc,
1417 };
1418
1419 static struct clk ts_fck = {
1420         .name           = "ts_fck",
1421         .ops            = &clkops_omap2_dflt,
1422         .parent         = &omap_32k_fck,
1423         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1424         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1425         .recalc         = &followparent_recalc,
1426 };
1427
1428 static struct clk usbtll_fck = {
1429         .name           = "usbtll_fck",
1430         .ops            = &clkops_omap2_dflt,
1431         .parent         = &omap_120m_fck,
1432         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1433         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1434         .recalc         = &followparent_recalc,
1435 };
1436
1437 /* CORE 96M FCLK-derived clocks */
1438
1439 static struct clk core_96m_fck = {
1440         .name           = "core_96m_fck",
1441         .ops            = &clkops_null,
1442         .parent         = &omap_96m_fck,
1443         .flags          = RATE_PROPAGATES,
1444         .clkdm_name     = "core_l4_clkdm",
1445         .recalc         = &followparent_recalc,
1446 };
1447
1448 static struct clk mmchs3_fck = {
1449         .name           = "mmchs_fck",
1450         .ops            = &clkops_omap2_dflt_wait,
1451         .id             = 2,
1452         .parent         = &core_96m_fck,
1453         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1454         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1455         .clkdm_name     = "core_l4_clkdm",
1456         .recalc         = &followparent_recalc,
1457 };
1458
1459 static struct clk mmchs2_fck = {
1460         .name           = "mmchs_fck",
1461         .ops            = &clkops_omap2_dflt_wait,
1462         .id             = 1,
1463         .parent         = &core_96m_fck,
1464         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1465         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1466         .clkdm_name     = "core_l4_clkdm",
1467         .recalc         = &followparent_recalc,
1468 };
1469
1470 static struct clk mspro_fck = {
1471         .name           = "mspro_fck",
1472         .ops            = &clkops_omap2_dflt_wait,
1473         .parent         = &core_96m_fck,
1474         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1475         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1476         .clkdm_name     = "core_l4_clkdm",
1477         .recalc         = &followparent_recalc,
1478 };
1479
1480 static struct clk mmchs1_fck = {
1481         .name           = "mmchs_fck",
1482         .ops            = &clkops_omap2_dflt_wait,
1483         .parent         = &core_96m_fck,
1484         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1485         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1486         .clkdm_name     = "core_l4_clkdm",
1487         .recalc         = &followparent_recalc,
1488 };
1489
1490 static struct clk i2c3_fck = {
1491         .name           = "i2c_fck",
1492         .ops            = &clkops_omap2_dflt_wait,
1493         .id             = 3,
1494         .parent         = &core_96m_fck,
1495         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1496         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1497         .clkdm_name     = "core_l4_clkdm",
1498         .recalc         = &followparent_recalc,
1499 };
1500
1501 static struct clk i2c2_fck = {
1502         .name           = "i2c_fck",
1503         .ops            = &clkops_omap2_dflt_wait,
1504         .id             = 2,
1505         .parent         = &core_96m_fck,
1506         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1507         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1508         .clkdm_name     = "core_l4_clkdm",
1509         .recalc         = &followparent_recalc,
1510 };
1511
1512 static struct clk i2c1_fck = {
1513         .name           = "i2c_fck",
1514         .ops            = &clkops_omap2_dflt_wait,
1515         .id             = 1,
1516         .parent         = &core_96m_fck,
1517         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1518         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1519         .clkdm_name     = "core_l4_clkdm",
1520         .recalc         = &followparent_recalc,
1521 };
1522
1523 /*
1524  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1525  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1526  */
1527 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1528         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1529         { .div = 0 }
1530 };
1531
1532 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1533         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1534         { .div = 0 }
1535 };
1536
1537 static const struct clksel mcbsp_15_clksel[] = {
1538         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1539         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1540         { .parent = NULL }
1541 };
1542
1543 static struct clk mcbsp5_fck = {
1544         .name           = "mcbsp_fck",
1545         .ops            = &clkops_omap2_dflt_wait,
1546         .id             = 5,
1547         .init           = &omap2_init_clksel_parent,
1548         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1549         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1550         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1551         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1552         .clksel         = mcbsp_15_clksel,
1553         .clkdm_name     = "core_l4_clkdm",
1554         .recalc         = &omap2_clksel_recalc,
1555 };
1556
1557 static struct clk mcbsp1_fck = {
1558         .name           = "mcbsp_fck",
1559         .ops            = &clkops_omap2_dflt_wait,
1560         .id             = 1,
1561         .init           = &omap2_init_clksel_parent,
1562         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1563         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1564         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1565         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1566         .clksel         = mcbsp_15_clksel,
1567         .clkdm_name     = "core_l4_clkdm",
1568         .recalc         = &omap2_clksel_recalc,
1569 };
1570
1571 /* CORE_48M_FCK-derived clocks */
1572
1573 static struct clk core_48m_fck = {
1574         .name           = "core_48m_fck",
1575         .ops            = &clkops_null,
1576         .parent         = &omap_48m_fck,
1577         .flags          = RATE_PROPAGATES,
1578         .clkdm_name     = "core_l4_clkdm",
1579         .recalc         = &followparent_recalc,
1580 };
1581
1582 static struct clk mcspi4_fck = {
1583         .name           = "mcspi_fck",
1584         .ops            = &clkops_omap2_dflt_wait,
1585         .id             = 4,
1586         .parent         = &core_48m_fck,
1587         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1588         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1589         .recalc         = &followparent_recalc,
1590 };
1591
1592 static struct clk mcspi3_fck = {
1593         .name           = "mcspi_fck",
1594         .ops            = &clkops_omap2_dflt_wait,
1595         .id             = 3,
1596         .parent         = &core_48m_fck,
1597         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1598         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1599         .recalc         = &followparent_recalc,
1600 };
1601
1602 static struct clk mcspi2_fck = {
1603         .name           = "mcspi_fck",
1604         .ops            = &clkops_omap2_dflt_wait,
1605         .id             = 2,
1606         .parent         = &core_48m_fck,
1607         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1608         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1609         .recalc         = &followparent_recalc,
1610 };
1611
1612 static struct clk mcspi1_fck = {
1613         .name           = "mcspi_fck",
1614         .ops            = &clkops_omap2_dflt_wait,
1615         .id             = 1,
1616         .parent         = &core_48m_fck,
1617         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1618         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1619         .recalc         = &followparent_recalc,
1620 };
1621
1622 static struct clk uart2_fck = {
1623         .name           = "uart2_fck",
1624         .ops            = &clkops_omap2_dflt_wait,
1625         .parent         = &core_48m_fck,
1626         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1627         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1628         .recalc         = &followparent_recalc,
1629 };
1630
1631 static struct clk uart1_fck = {
1632         .name           = "uart1_fck",
1633         .ops            = &clkops_omap2_dflt_wait,
1634         .parent         = &core_48m_fck,
1635         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1636         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1637         .recalc         = &followparent_recalc,
1638 };
1639
1640 static struct clk fshostusb_fck = {
1641         .name           = "fshostusb_fck",
1642         .ops            = &clkops_omap2_dflt_wait,
1643         .parent         = &core_48m_fck,
1644         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1645         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1646         .recalc         = &followparent_recalc,
1647 };
1648
1649 /* CORE_12M_FCK based clocks */
1650
1651 static struct clk core_12m_fck = {
1652         .name           = "core_12m_fck",
1653         .ops            = &clkops_null,
1654         .parent         = &omap_12m_fck,
1655         .flags          = RATE_PROPAGATES,
1656         .clkdm_name     = "core_l4_clkdm",
1657         .recalc         = &followparent_recalc,
1658 };
1659
1660 static struct clk hdq_fck = {
1661         .name           = "hdq_fck",
1662         .ops            = &clkops_omap2_dflt_wait,
1663         .parent         = &core_12m_fck,
1664         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1665         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1666         .recalc         = &followparent_recalc,
1667 };
1668
1669 /* DPLL3-derived clock */
1670
1671 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1672         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1673         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1674         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1675         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1676         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1677         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1678         { .div = 0 }
1679 };
1680
1681 static const struct clksel ssi_ssr_clksel[] = {
1682         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1683         { .parent = NULL }
1684 };
1685
1686 static struct clk ssi_ssr_fck = {
1687         .name           = "ssi_ssr_fck",
1688         .ops            = &clkops_omap2_dflt,
1689         .init           = &omap2_init_clksel_parent,
1690         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1691         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1692         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1693         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1694         .clksel         = ssi_ssr_clksel,
1695         .flags          = RATE_PROPAGATES,
1696         .clkdm_name     = "core_l4_clkdm",
1697         .recalc         = &omap2_clksel_recalc,
1698 };
1699
1700 static struct clk ssi_sst_fck = {
1701         .name           = "ssi_sst_fck",
1702         .ops            = &clkops_null,
1703         .parent         = &ssi_ssr_fck,
1704         .fixed_div      = 2,
1705         .recalc         = &omap2_fixed_divisor_recalc,
1706 };
1707
1708
1709
1710 /* CORE_L3_ICK based clocks */
1711
1712 /*
1713  * XXX must add clk_enable/clk_disable for these if standard code won't
1714  * handle it
1715  */
1716 static struct clk core_l3_ick = {
1717         .name           = "core_l3_ick",
1718         .ops            = &clkops_null,
1719         .parent         = &l3_ick,
1720         .init           = &omap2_init_clk_clkdm,
1721         .flags          = RATE_PROPAGATES,
1722         .clkdm_name     = "core_l3_clkdm",
1723         .recalc         = &followparent_recalc,
1724 };
1725
1726 static struct clk hsotgusb_ick = {
1727         .name           = "hsotgusb_ick",
1728         .ops            = &clkops_omap2_dflt_wait,
1729         .parent         = &core_l3_ick,
1730         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1731         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1732         .clkdm_name     = "core_l3_clkdm",
1733         .recalc         = &followparent_recalc,
1734 };
1735
1736 static struct clk sdrc_ick = {
1737         .name           = "sdrc_ick",
1738         .ops            = &clkops_omap2_dflt_wait,
1739         .parent         = &core_l3_ick,
1740         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1741         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1742         .flags          = ENABLE_ON_INIT,
1743         .clkdm_name     = "core_l3_clkdm",
1744         .recalc         = &followparent_recalc,
1745 };
1746
1747 static struct clk gpmc_fck = {
1748         .name           = "gpmc_fck",
1749         .ops            = &clkops_null,
1750         .parent         = &core_l3_ick,
1751         .flags          = ENABLE_ON_INIT, /* huh? */
1752         .clkdm_name     = "core_l3_clkdm",
1753         .recalc         = &followparent_recalc,
1754 };
1755
1756 /* SECURITY_L3_ICK based clocks */
1757
1758 static struct clk security_l3_ick = {
1759         .name           = "security_l3_ick",
1760         .ops            = &clkops_null,
1761         .parent         = &l3_ick,
1762         .flags          = RATE_PROPAGATES,
1763         .recalc         = &followparent_recalc,
1764 };
1765
1766 static struct clk pka_ick = {
1767         .name           = "pka_ick",
1768         .ops            = &clkops_omap2_dflt_wait,
1769         .parent         = &security_l3_ick,
1770         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1771         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1772         .recalc         = &followparent_recalc,
1773 };
1774
1775 /* CORE_L4_ICK based clocks */
1776
1777 static struct clk core_l4_ick = {
1778         .name           = "core_l4_ick",
1779         .ops            = &clkops_null,
1780         .parent         = &l4_ick,
1781         .init           = &omap2_init_clk_clkdm,
1782         .flags          = RATE_PROPAGATES,
1783         .clkdm_name     = "core_l4_clkdm",
1784         .recalc         = &followparent_recalc,
1785 };
1786
1787 static struct clk usbtll_ick = {
1788         .name           = "usbtll_ick",
1789         .ops            = &clkops_omap2_dflt_wait,
1790         .parent         = &core_l4_ick,
1791         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1792         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1793         .clkdm_name     = "core_l4_clkdm",
1794         .recalc         = &followparent_recalc,
1795 };
1796
1797 static struct clk mmchs3_ick = {
1798         .name           = "mmchs_ick",
1799         .ops            = &clkops_omap2_dflt_wait,
1800         .id             = 2,
1801         .parent         = &core_l4_ick,
1802         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1803         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1804         .clkdm_name     = "core_l4_clkdm",
1805         .recalc         = &followparent_recalc,
1806 };
1807
1808 /* Intersystem Communication Registers - chassis mode only */
1809 static struct clk icr_ick = {
1810         .name           = "icr_ick",
1811         .ops            = &clkops_omap2_dflt_wait,
1812         .parent         = &core_l4_ick,
1813         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1814         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1815         .clkdm_name     = "core_l4_clkdm",
1816         .recalc         = &followparent_recalc,
1817 };
1818
1819 static struct clk aes2_ick = {
1820         .name           = "aes2_ick",
1821         .ops            = &clkops_omap2_dflt_wait,
1822         .parent         = &core_l4_ick,
1823         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1824         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1825         .clkdm_name     = "core_l4_clkdm",
1826         .recalc         = &followparent_recalc,
1827 };
1828
1829 static struct clk sha12_ick = {
1830         .name           = "sha12_ick",
1831         .ops            = &clkops_omap2_dflt_wait,
1832         .parent         = &core_l4_ick,
1833         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1834         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1835         .clkdm_name     = "core_l4_clkdm",
1836         .recalc         = &followparent_recalc,
1837 };
1838
1839 static struct clk des2_ick = {
1840         .name           = "des2_ick",
1841         .ops            = &clkops_omap2_dflt_wait,
1842         .parent         = &core_l4_ick,
1843         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1844         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1845         .clkdm_name     = "core_l4_clkdm",
1846         .recalc         = &followparent_recalc,
1847 };
1848
1849 static struct clk mmchs2_ick = {
1850         .name           = "mmchs_ick",
1851         .ops            = &clkops_omap2_dflt_wait,
1852         .id             = 1,
1853         .parent         = &core_l4_ick,
1854         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1855         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1856         .clkdm_name     = "core_l4_clkdm",
1857         .recalc         = &followparent_recalc,
1858 };
1859
1860 static struct clk mmchs1_ick = {
1861         .name           = "mmchs_ick",
1862         .ops            = &clkops_omap2_dflt_wait,
1863         .parent         = &core_l4_ick,
1864         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1865         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1866         .clkdm_name     = "core_l4_clkdm",
1867         .recalc         = &followparent_recalc,
1868 };
1869
1870 static struct clk mspro_ick = {
1871         .name           = "mspro_ick",
1872         .ops            = &clkops_omap2_dflt_wait,
1873         .parent         = &core_l4_ick,
1874         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1875         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1876         .clkdm_name     = "core_l4_clkdm",
1877         .recalc         = &followparent_recalc,
1878 };
1879
1880 static struct clk hdq_ick = {
1881         .name           = "hdq_ick",
1882         .ops            = &clkops_omap2_dflt_wait,
1883         .parent         = &core_l4_ick,
1884         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1885         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1886         .clkdm_name     = "core_l4_clkdm",
1887         .recalc         = &followparent_recalc,
1888 };
1889
1890 static struct clk mcspi4_ick = {
1891         .name           = "mcspi_ick",
1892         .ops            = &clkops_omap2_dflt_wait,
1893         .id             = 4,
1894         .parent         = &core_l4_ick,
1895         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1896         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1897         .clkdm_name     = "core_l4_clkdm",
1898         .recalc         = &followparent_recalc,
1899 };
1900
1901 static struct clk mcspi3_ick = {
1902         .name           = "mcspi_ick",
1903         .ops            = &clkops_omap2_dflt_wait,
1904         .id             = 3,
1905         .parent         = &core_l4_ick,
1906         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1907         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1908         .clkdm_name     = "core_l4_clkdm",
1909         .recalc         = &followparent_recalc,
1910 };
1911
1912 static struct clk mcspi2_ick = {
1913         .name           = "mcspi_ick",
1914         .ops            = &clkops_omap2_dflt_wait,
1915         .id             = 2,
1916         .parent         = &core_l4_ick,
1917         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1918         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1919         .clkdm_name     = "core_l4_clkdm",
1920         .recalc         = &followparent_recalc,
1921 };
1922
1923 static struct clk mcspi1_ick = {
1924         .name           = "mcspi_ick",
1925         .ops            = &clkops_omap2_dflt_wait,
1926         .id             = 1,
1927         .parent         = &core_l4_ick,
1928         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1929         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1930         .clkdm_name     = "core_l4_clkdm",
1931         .recalc         = &followparent_recalc,
1932 };
1933
1934 static struct clk i2c3_ick = {
1935         .name           = "i2c_ick",
1936         .ops            = &clkops_omap2_dflt_wait,
1937         .id             = 3,
1938         .parent         = &core_l4_ick,
1939         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1940         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1941         .clkdm_name     = "core_l4_clkdm",
1942         .recalc         = &followparent_recalc,
1943 };
1944
1945 static struct clk i2c2_ick = {
1946         .name           = "i2c_ick",
1947         .ops            = &clkops_omap2_dflt_wait,
1948         .id             = 2,
1949         .parent         = &core_l4_ick,
1950         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1951         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1952         .clkdm_name     = "core_l4_clkdm",
1953         .recalc         = &followparent_recalc,
1954 };
1955
1956 static struct clk i2c1_ick = {
1957         .name           = "i2c_ick",
1958         .ops            = &clkops_omap2_dflt_wait,
1959         .id             = 1,
1960         .parent         = &core_l4_ick,
1961         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1962         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1963         .clkdm_name     = "core_l4_clkdm",
1964         .recalc         = &followparent_recalc,
1965 };
1966
1967 static struct clk uart2_ick = {
1968         .name           = "uart2_ick",
1969         .ops            = &clkops_omap2_dflt_wait,
1970         .parent         = &core_l4_ick,
1971         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1972         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1973         .clkdm_name     = "core_l4_clkdm",
1974         .recalc         = &followparent_recalc,
1975 };
1976
1977 static struct clk uart1_ick = {
1978         .name           = "uart1_ick",
1979         .ops            = &clkops_omap2_dflt_wait,
1980         .parent         = &core_l4_ick,
1981         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1982         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1983         .clkdm_name     = "core_l4_clkdm",
1984         .recalc         = &followparent_recalc,
1985 };
1986
1987 static struct clk gpt11_ick = {
1988         .name           = "gpt11_ick",
1989         .ops            = &clkops_omap2_dflt_wait,
1990         .parent         = &core_l4_ick,
1991         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1992         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1993         .clkdm_name     = "core_l4_clkdm",
1994         .recalc         = &followparent_recalc,
1995 };
1996
1997 static struct clk gpt10_ick = {
1998         .name           = "gpt10_ick",
1999         .ops            = &clkops_omap2_dflt_wait,
2000         .parent         = &core_l4_ick,
2001         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2002         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
2003         .clkdm_name     = "core_l4_clkdm",
2004         .recalc         = &followparent_recalc,
2005 };
2006
2007 static struct clk mcbsp5_ick = {
2008         .name           = "mcbsp_ick",
2009         .ops            = &clkops_omap2_dflt_wait,
2010         .id             = 5,
2011         .parent         = &core_l4_ick,
2012         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2013         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
2014         .clkdm_name     = "core_l4_clkdm",
2015         .recalc         = &followparent_recalc,
2016 };
2017
2018 static struct clk mcbsp1_ick = {
2019         .name           = "mcbsp_ick",
2020         .ops            = &clkops_omap2_dflt_wait,
2021         .id             = 1,
2022         .parent         = &core_l4_ick,
2023         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2024         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2025         .clkdm_name     = "core_l4_clkdm",
2026         .recalc         = &followparent_recalc,
2027 };
2028
2029 static struct clk fac_ick = {
2030         .name           = "fac_ick",
2031         .ops            = &clkops_omap2_dflt_wait,
2032         .parent         = &core_l4_ick,
2033         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2034         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
2035         .clkdm_name     = "core_l4_clkdm",
2036         .recalc         = &followparent_recalc,
2037 };
2038
2039 static struct clk mailboxes_ick = {
2040         .name           = "mailboxes_ick",
2041         .ops            = &clkops_omap2_dflt_wait,
2042         .parent         = &core_l4_ick,
2043         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2044         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2045         .clkdm_name     = "core_l4_clkdm",
2046         .recalc         = &followparent_recalc,
2047 };
2048
2049 static struct clk omapctrl_ick = {
2050         .name           = "omapctrl_ick",
2051         .ops            = &clkops_omap2_dflt_wait,
2052         .parent         = &core_l4_ick,
2053         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2054         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2055         .flags          = ENABLE_ON_INIT,
2056         .recalc         = &followparent_recalc,
2057 };
2058
2059 /* SSI_L4_ICK based clocks */
2060
2061 static struct clk ssi_l4_ick = {
2062         .name           = "ssi_l4_ick",
2063         .ops            = &clkops_null,
2064         .parent         = &l4_ick,
2065         .flags          = RATE_PROPAGATES,
2066         .clkdm_name     = "core_l4_clkdm",
2067         .recalc         = &followparent_recalc,
2068 };
2069
2070 static struct clk ssi_ick = {
2071         .name           = "ssi_ick",
2072         .ops            = &clkops_omap2_dflt,
2073         .parent         = &ssi_l4_ick,
2074         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2075         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2076         .clkdm_name     = "core_l4_clkdm",
2077         .recalc         = &followparent_recalc,
2078 };
2079
2080 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2081  * but l4_ick makes more sense to me */
2082
2083 static const struct clksel usb_l4_clksel[] = {
2084         { .parent = &l4_ick, .rates = div2_rates },
2085         { .parent = NULL },
2086 };
2087
2088 static struct clk usb_l4_ick = {
2089         .name           = "usb_l4_ick",
2090         .ops            = &clkops_omap2_dflt_wait,
2091         .parent         = &l4_ick,
2092         .init           = &omap2_init_clksel_parent,
2093         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2094         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2095         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2096         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2097         .clksel         = usb_l4_clksel,
2098         .recalc         = &omap2_clksel_recalc,
2099 };
2100
2101 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2102
2103 /* SECURITY_L4_ICK2 based clocks */
2104
2105 static struct clk security_l4_ick2 = {
2106         .name           = "security_l4_ick2",
2107         .ops            = &clkops_null,
2108         .parent         = &l4_ick,
2109         .flags          = RATE_PROPAGATES,
2110         .recalc         = &followparent_recalc,
2111 };
2112
2113 static struct clk aes1_ick = {
2114         .name           = "aes1_ick",
2115         .ops            = &clkops_omap2_dflt_wait,
2116         .parent         = &security_l4_ick2,
2117         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2118         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2119         .recalc         = &followparent_recalc,
2120 };
2121
2122 static struct clk rng_ick = {
2123         .name           = "rng_ick",
2124         .ops            = &clkops_omap2_dflt_wait,
2125         .parent         = &security_l4_ick2,
2126         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2127         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2128         .recalc         = &followparent_recalc,
2129 };
2130
2131 static struct clk sha11_ick = {
2132         .name           = "sha11_ick",
2133         .ops            = &clkops_omap2_dflt_wait,
2134         .parent         = &security_l4_ick2,
2135         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2136         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2137         .recalc         = &followparent_recalc,
2138 };
2139
2140 static struct clk des1_ick = {
2141         .name           = "des1_ick",
2142         .ops            = &clkops_omap2_dflt_wait,
2143         .parent         = &security_l4_ick2,
2144         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2145         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2146         .recalc         = &followparent_recalc,
2147 };
2148
2149 /* DSS */
2150 static const struct clksel dss1_alwon_fck_clksel[] = {
2151         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2152         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2153         { .parent = NULL }
2154 };
2155
2156 static struct clk dss1_alwon_fck = {
2157         .name           = "dss1_alwon_fck",
2158         .ops            = &clkops_omap2_dflt,
2159         .parent         = &dpll4_m4x2_ck,
2160         .init           = &omap2_init_clksel_parent,
2161         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2162         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2163         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2164         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2165         .clksel         = dss1_alwon_fck_clksel,
2166         .clkdm_name     = "dss_clkdm",
2167         .recalc         = &omap2_clksel_recalc,
2168 };
2169
2170 static struct clk dss_tv_fck = {
2171         .name           = "dss_tv_fck",
2172         .ops            = &clkops_omap2_dflt,
2173         .parent         = &omap_54m_fck,
2174         .init           = &omap2_init_clk_clkdm,
2175         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2176         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2177         .clkdm_name     = "dss_clkdm",
2178         .recalc         = &followparent_recalc,
2179 };
2180
2181 static struct clk dss_96m_fck = {
2182         .name           = "dss_96m_fck",
2183         .ops            = &clkops_omap2_dflt,
2184         .parent         = &omap_96m_fck,
2185         .init           = &omap2_init_clk_clkdm,
2186         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2187         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2188         .clkdm_name     = "dss_clkdm",
2189         .recalc         = &followparent_recalc,
2190 };
2191
2192 static struct clk dss2_alwon_fck = {
2193         .name           = "dss2_alwon_fck",
2194         .ops            = &clkops_omap2_dflt,
2195         .parent         = &sys_ck,
2196         .init           = &omap2_init_clk_clkdm,
2197         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2198         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2199         .clkdm_name     = "dss_clkdm",
2200         .recalc         = &followparent_recalc,
2201 };
2202
2203 static struct clk dss_ick = {
2204         /* Handles both L3 and L4 clocks */
2205         .name           = "dss_ick",
2206         .ops            = &clkops_omap2_dflt,
2207         .parent         = &l4_ick,
2208         .init           = &omap2_init_clk_clkdm,
2209         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2210         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2211         .clkdm_name     = "dss_clkdm",
2212         .recalc         = &followparent_recalc,
2213 };
2214
2215 /* CAM */
2216
2217 static const struct clksel cam_mclk_clksel[] = {
2218         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2219         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2220         { .parent = NULL }
2221 };
2222
2223 static struct clk cam_mclk = {
2224         .name           = "cam_mclk",
2225         .ops            = &clkops_omap2_dflt_wait,
2226         .parent         = &dpll4_m5x2_ck,
2227         .init           = &omap2_init_clksel_parent,
2228         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2229         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2230         .clksel         = cam_mclk_clksel,
2231         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2232         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2233         .clkdm_name     = "cam_clkdm",
2234         .recalc         = &omap2_clksel_recalc,
2235 };
2236
2237 static struct clk cam_ick = {
2238         /* Handles both L3 and L4 clocks */
2239         .name           = "cam_ick",
2240         .ops            = &clkops_omap2_dflt_wait,
2241         .parent         = &l4_ick,
2242         .init           = &omap2_init_clk_clkdm,
2243         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2244         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2245         .clkdm_name     = "cam_clkdm",
2246         .recalc         = &followparent_recalc,
2247 };
2248
2249 static struct clk csi2_96m_fck = {
2250         .name           = "csi2_96m_fck",
2251         .ops            = &clkops_omap2_dflt_wait,
2252         .parent         = &core_96m_fck,
2253         .init           = &omap2_init_clk_clkdm,
2254         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2255         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2256         .clkdm_name     = "cam_clkdm",
2257         .recalc         = &followparent_recalc,
2258 };
2259
2260 /* USBHOST - 3430ES2 only */
2261
2262 static struct clk usbhost_120m_fck = {
2263         .name           = "usbhost_120m_fck",
2264         .ops            = &clkops_omap2_dflt_wait,
2265         .parent         = &omap_120m_fck,
2266         .init           = &omap2_init_clk_clkdm,
2267         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2268         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2269         .clkdm_name     = "usbhost_clkdm",
2270         .recalc         = &followparent_recalc,
2271 };
2272
2273 static struct clk usbhost_48m_fck = {
2274         .name           = "usbhost_48m_fck",
2275         .ops            = &clkops_omap2_dflt_wait,
2276         .parent         = &omap_48m_fck,
2277         .init           = &omap2_init_clk_clkdm,
2278         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2279         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2280         .clkdm_name     = "usbhost_clkdm",
2281         .recalc         = &followparent_recalc,
2282 };
2283
2284 static struct clk usbhost_ick = {
2285         /* Handles both L3 and L4 clocks */
2286         .name           = "usbhost_ick",
2287         .ops            = &clkops_omap2_dflt_wait,
2288         .parent         = &l4_ick,
2289         .init           = &omap2_init_clk_clkdm,
2290         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2291         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2292         .clkdm_name     = "usbhost_clkdm",
2293         .recalc         = &followparent_recalc,
2294 };
2295
2296 /* WKUP */
2297
2298 static const struct clksel_rate usim_96m_rates[] = {
2299         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2300         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2301         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2302         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2303         { .div = 0 },
2304 };
2305
2306 static const struct clksel_rate usim_120m_rates[] = {
2307         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2308         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2309         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2310         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2311         { .div = 0 },
2312 };
2313
2314 static const struct clksel usim_clksel[] = {
2315         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2316         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2317         { .parent = &sys_ck,            .rates = div2_rates },
2318         { .parent = NULL },
2319 };
2320
2321 /* 3430ES2 only */
2322 static struct clk usim_fck = {
2323         .name           = "usim_fck",
2324         .ops            = &clkops_omap2_dflt_wait,
2325         .init           = &omap2_init_clksel_parent,
2326         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2327         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2328         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2329         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2330         .clksel         = usim_clksel,
2331         .recalc         = &omap2_clksel_recalc,
2332 };
2333
2334 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2335 static struct clk gpt1_fck = {
2336         .name           = "gpt1_fck",
2337         .ops            = &clkops_omap2_dflt_wait,
2338         .init           = &omap2_init_clksel_parent,
2339         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2340         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2341         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2342         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2343         .clksel         = omap343x_gpt_clksel,
2344         .clkdm_name     = "wkup_clkdm",
2345         .recalc         = &omap2_clksel_recalc,
2346 };
2347
2348 static struct clk wkup_32k_fck = {
2349         .name           = "wkup_32k_fck",
2350         .ops            = &clkops_null,
2351         .init           = &omap2_init_clk_clkdm,
2352         .parent         = &omap_32k_fck,
2353         .flags          = RATE_PROPAGATES,
2354         .clkdm_name     = "wkup_clkdm",
2355         .recalc         = &followparent_recalc,
2356 };
2357
2358 static struct clk gpio1_dbck = {
2359         .name           = "gpio1_dbck",
2360         .ops            = &clkops_omap2_dflt_wait,
2361         .parent         = &wkup_32k_fck,
2362         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2363         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2364         .clkdm_name     = "wkup_clkdm",
2365         .recalc         = &followparent_recalc,
2366 };
2367
2368 static struct clk wdt2_fck = {
2369         .name           = "wdt2_fck",
2370         .ops            = &clkops_omap2_dflt_wait,
2371         .parent         = &wkup_32k_fck,
2372         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2373         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2374         .clkdm_name     = "wkup_clkdm",
2375         .recalc         = &followparent_recalc,
2376 };
2377
2378 static struct clk wkup_l4_ick = {
2379         .name           = "wkup_l4_ick",
2380         .ops            = &clkops_null,
2381         .parent         = &sys_ck,
2382         .flags          = RATE_PROPAGATES,
2383         .clkdm_name     = "wkup_clkdm",
2384         .recalc         = &followparent_recalc,
2385 };
2386
2387 /* 3430ES2 only */
2388 /* Never specifically named in the TRM, so we have to infer a likely name */
2389 static struct clk usim_ick = {
2390         .name           = "usim_ick",
2391         .ops            = &clkops_omap2_dflt_wait,
2392         .parent         = &wkup_l4_ick,
2393         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2394         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2395         .clkdm_name     = "wkup_clkdm",
2396         .recalc         = &followparent_recalc,
2397 };
2398
2399 static struct clk wdt2_ick = {
2400         .name           = "wdt2_ick",
2401         .ops            = &clkops_omap2_dflt_wait,
2402         .parent         = &wkup_l4_ick,
2403         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2404         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2405         .clkdm_name     = "wkup_clkdm",
2406         .recalc         = &followparent_recalc,
2407 };
2408
2409 static struct clk wdt1_ick = {
2410         .name           = "wdt1_ick",
2411         .ops            = &clkops_omap2_dflt_wait,
2412         .parent         = &wkup_l4_ick,
2413         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2414         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2415         .clkdm_name     = "wkup_clkdm",
2416         .recalc         = &followparent_recalc,
2417 };
2418
2419 static struct clk gpio1_ick = {
2420         .name           = "gpio1_ick",
2421         .ops            = &clkops_omap2_dflt_wait,
2422         .parent         = &wkup_l4_ick,
2423         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2424         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2425         .clkdm_name     = "wkup_clkdm",
2426         .recalc         = &followparent_recalc,
2427 };
2428
2429 static struct clk omap_32ksync_ick = {
2430         .name           = "omap_32ksync_ick",
2431         .ops            = &clkops_omap2_dflt_wait,
2432         .parent         = &wkup_l4_ick,
2433         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2434         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2435         .clkdm_name     = "wkup_clkdm",
2436         .recalc         = &followparent_recalc,
2437 };
2438
2439 /* XXX This clock no longer exists in 3430 TRM rev F */
2440 static struct clk gpt12_ick = {
2441         .name           = "gpt12_ick",
2442         .ops            = &clkops_omap2_dflt_wait,
2443         .parent         = &wkup_l4_ick,
2444         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2445         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2446         .clkdm_name     = "wkup_clkdm",
2447         .recalc         = &followparent_recalc,
2448 };
2449
2450 static struct clk gpt1_ick = {
2451         .name           = "gpt1_ick",
2452         .ops            = &clkops_omap2_dflt_wait,
2453         .parent         = &wkup_l4_ick,
2454         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2455         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2456         .clkdm_name     = "wkup_clkdm",
2457         .recalc         = &followparent_recalc,
2458 };
2459
2460
2461
2462 /* PER clock domain */
2463
2464 static struct clk per_96m_fck = {
2465         .name           = "per_96m_fck",
2466         .ops            = &clkops_null,
2467         .parent         = &omap_96m_alwon_fck,
2468         .init           = &omap2_init_clk_clkdm,
2469         .flags          = RATE_PROPAGATES,
2470         .clkdm_name     = "per_clkdm",
2471         .recalc         = &followparent_recalc,
2472 };
2473
2474 static struct clk per_48m_fck = {
2475         .name           = "per_48m_fck",
2476         .ops            = &clkops_null,
2477         .parent         = &omap_48m_fck,
2478         .init           = &omap2_init_clk_clkdm,
2479         .flags          = RATE_PROPAGATES,
2480         .clkdm_name     = "per_clkdm",
2481         .recalc         = &followparent_recalc,
2482 };
2483
2484 static struct clk uart3_fck = {
2485         .name           = "uart3_fck",
2486         .ops            = &clkops_omap2_dflt_wait,
2487         .parent         = &per_48m_fck,
2488         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2489         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2490         .clkdm_name     = "per_clkdm",
2491         .recalc         = &followparent_recalc,
2492 };
2493
2494 static struct clk gpt2_fck = {
2495         .name           = "gpt2_fck",
2496         .ops            = &clkops_omap2_dflt_wait,
2497         .init           = &omap2_init_clksel_parent,
2498         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2499         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2500         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2501         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2502         .clksel         = omap343x_gpt_clksel,
2503         .clkdm_name     = "per_clkdm",
2504         .recalc         = &omap2_clksel_recalc,
2505 };
2506
2507 static struct clk gpt3_fck = {
2508         .name           = "gpt3_fck",
2509         .ops            = &clkops_omap2_dflt_wait,
2510         .init           = &omap2_init_clksel_parent,
2511         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2512         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2513         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2514         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2515         .clksel         = omap343x_gpt_clksel,
2516         .clkdm_name     = "per_clkdm",
2517         .recalc         = &omap2_clksel_recalc,
2518 };
2519
2520 static struct clk gpt4_fck = {
2521         .name           = "gpt4_fck",
2522         .ops            = &clkops_omap2_dflt_wait,
2523         .init           = &omap2_init_clksel_parent,
2524         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2525         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2526         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2527         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2528         .clksel         = omap343x_gpt_clksel,
2529         .clkdm_name     = "per_clkdm",
2530         .recalc         = &omap2_clksel_recalc,
2531 };
2532
2533 static struct clk gpt5_fck = {
2534         .name           = "gpt5_fck",
2535         .ops            = &clkops_omap2_dflt_wait,
2536         .init           = &omap2_init_clksel_parent,
2537         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2538         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2539         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2540         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2541         .clksel         = omap343x_gpt_clksel,
2542         .clkdm_name     = "per_clkdm",
2543         .recalc         = &omap2_clksel_recalc,
2544 };
2545
2546 static struct clk gpt6_fck = {
2547         .name           = "gpt6_fck",
2548         .ops            = &clkops_omap2_dflt_wait,
2549         .init           = &omap2_init_clksel_parent,
2550         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2551         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2552         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2553         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2554         .clksel         = omap343x_gpt_clksel,
2555         .clkdm_name     = "per_clkdm",
2556         .recalc         = &omap2_clksel_recalc,
2557 };
2558
2559 static struct clk gpt7_fck = {
2560         .name           = "gpt7_fck",
2561         .ops            = &clkops_omap2_dflt_wait,
2562         .init           = &omap2_init_clksel_parent,
2563         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2564         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2565         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2566         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2567         .clksel         = omap343x_gpt_clksel,
2568         .clkdm_name     = "per_clkdm",
2569         .recalc         = &omap2_clksel_recalc,
2570 };
2571
2572 static struct clk gpt8_fck = {
2573         .name           = "gpt8_fck",
2574         .ops            = &clkops_omap2_dflt_wait,
2575         .init           = &omap2_init_clksel_parent,
2576         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2577         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2578         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2579         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2580         .clksel         = omap343x_gpt_clksel,
2581         .clkdm_name     = "per_clkdm",
2582         .recalc         = &omap2_clksel_recalc,
2583 };
2584
2585 static struct clk gpt9_fck = {
2586         .name           = "gpt9_fck",
2587         .ops            = &clkops_omap2_dflt_wait,
2588         .init           = &omap2_init_clksel_parent,
2589         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2590         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2591         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2592         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2593         .clksel         = omap343x_gpt_clksel,
2594         .clkdm_name     = "per_clkdm",
2595         .recalc         = &omap2_clksel_recalc,
2596 };
2597
2598 static struct clk per_32k_alwon_fck = {
2599         .name           = "per_32k_alwon_fck",
2600         .ops            = &clkops_null,
2601         .parent         = &omap_32k_fck,
2602         .clkdm_name     = "per_clkdm",
2603         .flags          = RATE_PROPAGATES,
2604         .recalc         = &followparent_recalc,
2605 };
2606
2607 static struct clk gpio6_dbck = {
2608         .name           = "gpio6_dbck",
2609         .ops            = &clkops_omap2_dflt_wait,
2610         .parent         = &per_32k_alwon_fck,
2611         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2612         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2613         .clkdm_name     = "per_clkdm",
2614         .recalc         = &followparent_recalc,
2615 };
2616
2617 static struct clk gpio5_dbck = {
2618         .name           = "gpio5_dbck",
2619         .ops            = &clkops_omap2_dflt_wait,
2620         .parent         = &per_32k_alwon_fck,
2621         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2622         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2623         .clkdm_name     = "per_clkdm",
2624         .recalc         = &followparent_recalc,
2625 };
2626
2627 static struct clk gpio4_dbck = {
2628         .name           = "gpio4_dbck",
2629         .ops            = &clkops_omap2_dflt_wait,
2630         .parent         = &per_32k_alwon_fck,
2631         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2632         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2633         .clkdm_name     = "per_clkdm",
2634         .recalc         = &followparent_recalc,
2635 };
2636
2637 static struct clk gpio3_dbck = {
2638         .name           = "gpio3_dbck",
2639         .ops            = &clkops_omap2_dflt_wait,
2640         .parent         = &per_32k_alwon_fck,
2641         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2642         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2643         .clkdm_name     = "per_clkdm",
2644         .recalc         = &followparent_recalc,
2645 };
2646
2647 static struct clk gpio2_dbck = {
2648         .name           = "gpio2_dbck",
2649         .ops            = &clkops_omap2_dflt_wait,
2650         .parent         = &per_32k_alwon_fck,
2651         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2652         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2653         .clkdm_name     = "per_clkdm",
2654         .recalc         = &followparent_recalc,
2655 };
2656
2657 static struct clk wdt3_fck = {
2658         .name           = "wdt3_fck",
2659         .ops            = &clkops_omap2_dflt_wait,
2660         .parent         = &per_32k_alwon_fck,
2661         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2662         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2663         .clkdm_name     = "per_clkdm",
2664         .recalc         = &followparent_recalc,
2665 };
2666
2667 static struct clk per_l4_ick = {
2668         .name           = "per_l4_ick",
2669         .ops            = &clkops_null,
2670         .parent         = &l4_ick,
2671         .flags          = RATE_PROPAGATES,
2672         .clkdm_name     = "per_clkdm",
2673         .recalc         = &followparent_recalc,
2674 };
2675
2676 static struct clk gpio6_ick = {
2677         .name           = "gpio6_ick",
2678         .ops            = &clkops_omap2_dflt_wait,
2679         .parent         = &per_l4_ick,
2680         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2681         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2682         .clkdm_name     = "per_clkdm",
2683         .recalc         = &followparent_recalc,
2684 };
2685
2686 static struct clk gpio5_ick = {
2687         .name           = "gpio5_ick",
2688         .ops            = &clkops_omap2_dflt_wait,
2689         .parent         = &per_l4_ick,
2690         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2691         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2692         .clkdm_name     = "per_clkdm",
2693         .recalc         = &followparent_recalc,
2694 };
2695
2696 static struct clk gpio4_ick = {
2697         .name           = "gpio4_ick",
2698         .ops            = &clkops_omap2_dflt_wait,
2699         .parent         = &per_l4_ick,
2700         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2701         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2702         .clkdm_name     = "per_clkdm",
2703         .recalc         = &followparent_recalc,
2704 };
2705
2706 static struct clk gpio3_ick = {
2707         .name           = "gpio3_ick",
2708         .ops            = &clkops_omap2_dflt_wait,
2709         .parent         = &per_l4_ick,
2710         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2711         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2712         .clkdm_name     = "per_clkdm",
2713         .recalc         = &followparent_recalc,
2714 };
2715
2716 static struct clk gpio2_ick = {
2717         .name           = "gpio2_ick",
2718         .ops            = &clkops_omap2_dflt_wait,
2719         .parent         = &per_l4_ick,
2720         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2721         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2722         .clkdm_name     = "per_clkdm",
2723         .recalc         = &followparent_recalc,
2724 };
2725
2726 static struct clk wdt3_ick = {
2727         .name           = "wdt3_ick",
2728         .ops            = &clkops_omap2_dflt_wait,
2729         .parent         = &per_l4_ick,
2730         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2731         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2732         .clkdm_name     = "per_clkdm",
2733         .recalc         = &followparent_recalc,
2734 };
2735
2736 static struct clk uart3_ick = {
2737         .name           = "uart3_ick",
2738         .ops            = &clkops_omap2_dflt_wait,
2739         .parent         = &per_l4_ick,
2740         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2741         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2742         .clkdm_name     = "per_clkdm",
2743         .recalc         = &followparent_recalc,
2744 };
2745
2746 static struct clk gpt9_ick = {
2747         .name           = "gpt9_ick",
2748         .ops            = &clkops_omap2_dflt_wait,
2749         .parent         = &per_l4_ick,
2750         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2751         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2752         .clkdm_name     = "per_clkdm",
2753         .recalc         = &followparent_recalc,
2754 };
2755
2756 static struct clk gpt8_ick = {
2757         .name           = "gpt8_ick",
2758         .ops            = &clkops_omap2_dflt_wait,
2759         .parent         = &per_l4_ick,
2760         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2761         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2762         .clkdm_name     = "per_clkdm",
2763         .recalc         = &followparent_recalc,
2764 };
2765
2766 static struct clk gpt7_ick = {
2767         .name           = "gpt7_ick",
2768         .ops            = &clkops_omap2_dflt_wait,
2769         .parent         = &per_l4_ick,
2770         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2771         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2772         .clkdm_name     = "per_clkdm",
2773         .recalc         = &followparent_recalc,
2774 };
2775
2776 static struct clk gpt6_ick = {
2777         .name           = "gpt6_ick",
2778         .ops            = &clkops_omap2_dflt_wait,
2779         .parent         = &per_l4_ick,
2780         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2781         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2782         .clkdm_name     = "per_clkdm",
2783         .recalc         = &followparent_recalc,
2784 };
2785
2786 static struct clk gpt5_ick = {
2787         .name           = "gpt5_ick",
2788         .ops            = &clkops_omap2_dflt_wait,
2789         .parent         = &per_l4_ick,
2790         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2791         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2792         .clkdm_name     = "per_clkdm",
2793         .recalc         = &followparent_recalc,
2794 };
2795
2796 static struct clk gpt4_ick = {
2797         .name           = "gpt4_ick",
2798         .ops            = &clkops_omap2_dflt_wait,
2799         .parent         = &per_l4_ick,
2800         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2801         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2802         .clkdm_name     = "per_clkdm",
2803         .recalc         = &followparent_recalc,
2804 };
2805
2806 static struct clk gpt3_ick = {
2807         .name           = "gpt3_ick",
2808         .ops            = &clkops_omap2_dflt_wait,
2809         .parent         = &per_l4_ick,
2810         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2811         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2812         .clkdm_name     = "per_clkdm",
2813         .recalc         = &followparent_recalc,
2814 };
2815
2816 static struct clk gpt2_ick = {
2817         .name           = "gpt2_ick",
2818         .ops            = &clkops_omap2_dflt_wait,
2819         .parent         = &per_l4_ick,
2820         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2821         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2822         .clkdm_name     = "per_clkdm",
2823         .recalc         = &followparent_recalc,
2824 };
2825
2826 static struct clk mcbsp2_ick = {
2827         .name           = "mcbsp_ick",
2828         .ops            = &clkops_omap2_dflt_wait,
2829         .id             = 2,
2830         .parent         = &per_l4_ick,
2831         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2832         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2833         .clkdm_name     = "per_clkdm",
2834         .recalc         = &followparent_recalc,
2835 };
2836
2837 static struct clk mcbsp3_ick = {
2838         .name           = "mcbsp_ick",
2839         .ops            = &clkops_omap2_dflt_wait,
2840         .id             = 3,
2841         .parent         = &per_l4_ick,
2842         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2843         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2844         .clkdm_name     = "per_clkdm",
2845         .recalc         = &followparent_recalc,
2846 };
2847
2848 static struct clk mcbsp4_ick = {
2849         .name           = "mcbsp_ick",
2850         .ops            = &clkops_omap2_dflt_wait,
2851         .id             = 4,
2852         .parent         = &per_l4_ick,
2853         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2854         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2855         .clkdm_name     = "per_clkdm",
2856         .recalc         = &followparent_recalc,
2857 };
2858
2859 static const struct clksel mcbsp_234_clksel[] = {
2860         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2861         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2862         { .parent = NULL }
2863 };
2864
2865 static struct clk mcbsp2_fck = {
2866         .name           = "mcbsp_fck",
2867         .ops            = &clkops_omap2_dflt_wait,
2868         .id             = 2,
2869         .init           = &omap2_init_clksel_parent,
2870         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2871         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2872         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2873         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2874         .clksel         = mcbsp_234_clksel,
2875         .clkdm_name     = "per_clkdm",
2876         .recalc         = &omap2_clksel_recalc,
2877 };
2878
2879 static struct clk mcbsp3_fck = {
2880         .name           = "mcbsp_fck",
2881         .ops            = &clkops_omap2_dflt_wait,
2882         .id             = 3,
2883         .init           = &omap2_init_clksel_parent,
2884         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2885         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2886         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2887         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2888         .clksel         = mcbsp_234_clksel,
2889         .clkdm_name     = "per_clkdm",
2890         .recalc         = &omap2_clksel_recalc,
2891 };
2892
2893 static struct clk mcbsp4_fck = {
2894         .name           = "mcbsp_fck",
2895         .ops            = &clkops_omap2_dflt_wait,
2896         .id             = 4,
2897         .init           = &omap2_init_clksel_parent,
2898         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2899         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2900         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2901         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2902         .clksel         = mcbsp_234_clksel,
2903         .clkdm_name     = "per_clkdm",
2904         .recalc         = &omap2_clksel_recalc,
2905 };
2906
2907 /* EMU clocks */
2908
2909 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2910
2911 static const struct clksel_rate emu_src_sys_rates[] = {
2912         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2913         { .div = 0 },
2914 };
2915
2916 static const struct clksel_rate emu_src_core_rates[] = {
2917         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2918         { .div = 0 },
2919 };
2920
2921 static const struct clksel_rate emu_src_per_rates[] = {
2922         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2923         { .div = 0 },
2924 };
2925
2926 static const struct clksel_rate emu_src_mpu_rates[] = {
2927         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2928         { .div = 0 },
2929 };
2930
2931 static const struct clksel emu_src_clksel[] = {
2932         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2933         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2934         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2935         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2936         { .parent = NULL },
2937 };
2938
2939 /*
2940  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2941  * to switch the source of some of the EMU clocks.
2942  * XXX Are there CLKEN bits for these EMU clks?
2943  */
2944 static struct clk emu_src_ck = {
2945         .name           = "emu_src_ck",
2946         .ops            = &clkops_null,
2947         .init           = &omap2_init_clksel_parent,
2948         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2949         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2950         .clksel         = emu_src_clksel,
2951         .flags          = RATE_PROPAGATES,
2952         .clkdm_name     = "emu_clkdm",
2953         .recalc         = &omap2_clksel_recalc,
2954 };
2955
2956 static const struct clksel_rate pclk_emu_rates[] = {
2957         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2958         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2959         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2960         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2961         { .div = 0 },
2962 };
2963
2964 static const struct clksel pclk_emu_clksel[] = {
2965         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2966         { .parent = NULL },
2967 };
2968
2969 static struct clk pclk_fck = {
2970         .name           = "pclk_fck",
2971         .ops            = &clkops_null,
2972         .init           = &omap2_init_clksel_parent,
2973         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2974         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2975         .clksel         = pclk_emu_clksel,
2976         .flags          = RATE_PROPAGATES,
2977         .clkdm_name     = "emu_clkdm",
2978         .recalc         = &omap2_clksel_recalc,
2979 };
2980
2981 static const struct clksel_rate pclkx2_emu_rates[] = {
2982         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2983         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2984         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2985         { .div = 0 },
2986 };
2987
2988 static const struct clksel pclkx2_emu_clksel[] = {
2989         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2990         { .parent = NULL },
2991 };
2992
2993 static struct clk pclkx2_fck = {
2994         .name           = "pclkx2_fck",
2995         .ops            = &clkops_null,
2996         .init           = &omap2_init_clksel_parent,
2997         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2998         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2999         .clksel         = pclkx2_emu_clksel,
3000         .flags          = RATE_PROPAGATES,
3001         .clkdm_name     = "emu_clkdm",
3002         .recalc         = &omap2_clksel_recalc,
3003 };
3004
3005 static const struct clksel atclk_emu_clksel[] = {
3006         { .parent = &emu_src_ck, .rates = div2_rates },
3007         { .parent = NULL },
3008 };
3009
3010 static struct clk atclk_fck = {
3011         .name           = "atclk_fck",
3012         .ops            = &clkops_null,
3013         .init           = &omap2_init_clksel_parent,
3014         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3015         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
3016         .clksel         = atclk_emu_clksel,
3017         .flags          = RATE_PROPAGATES,
3018         .clkdm_name     = "emu_clkdm",
3019         .recalc         = &omap2_clksel_recalc,
3020 };
3021
3022 static struct clk traceclk_src_fck = {
3023         .name           = "traceclk_src_fck",
3024         .ops            = &clkops_null,
3025         .init           = &omap2_init_clksel_parent,
3026         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3027         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
3028         .clksel         = emu_src_clksel,
3029         .flags          = RATE_PROPAGATES,
3030         .clkdm_name     = "emu_clkdm",
3031         .recalc         = &omap2_clksel_recalc,
3032 };
3033
3034 static const struct clksel_rate traceclk_rates[] = {
3035         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3036         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3037         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3038         { .div = 0 },
3039 };
3040
3041 static const struct clksel traceclk_clksel[] = {
3042         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3043         { .parent = NULL },
3044 };
3045
3046 static struct clk traceclk_fck = {
3047         .name           = "traceclk_fck",
3048         .ops            = &clkops_null,
3049         .init           = &omap2_init_clksel_parent,
3050         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3051         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3052         .clksel         = traceclk_clksel,
3053         .clkdm_name     = "emu_clkdm",
3054         .recalc         = &omap2_clksel_recalc,
3055 };
3056
3057 /* SR clocks */
3058
3059 /* SmartReflex fclk (VDD1) */
3060 static struct clk sr1_fck = {
3061         .name           = "sr1_fck",
3062         .ops            = &clkops_omap2_dflt_wait,
3063         .parent         = &sys_ck,
3064         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3065         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3066         .flags          = RATE_PROPAGATES,
3067         .recalc         = &followparent_recalc,
3068 };
3069
3070 /* SmartReflex fclk (VDD2) */
3071 static struct clk sr2_fck = {
3072         .name           = "sr2_fck",
3073         .ops            = &clkops_omap2_dflt_wait,
3074         .parent         = &sys_ck,
3075         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3076         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3077         .flags          = RATE_PROPAGATES,
3078         .recalc         = &followparent_recalc,
3079 };
3080
3081 static struct clk sr_l4_ick = {
3082         .name           = "sr_l4_ick",
3083         .ops            = &clkops_null, /* RMK: missing? */
3084         .parent         = &l4_ick,
3085         .clkdm_name     = "core_l4_clkdm",
3086         .recalc         = &followparent_recalc,
3087 };
3088
3089 /* SECURE_32K_FCK clocks */
3090
3091 /* XXX This clock no longer exists in 3430 TRM rev F */
3092 static struct clk gpt12_fck = {
3093         .name           = "gpt12_fck",
3094         .ops            = &clkops_null,
3095         .parent         = &secure_32k_fck,
3096         .recalc         = &followparent_recalc,
3097 };
3098
3099 static struct clk wdt1_fck = {
3100         .name           = "wdt1_fck",
3101         .ops            = &clkops_null,
3102         .parent         = &secure_32k_fck,
3103         .recalc         = &followparent_recalc,
3104 };
3105
3106 #endif