2 * OMAP3 clock framework
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
22 #include <mach/control.h>
26 #include "cm-regbits-34xx.h"
28 #include "prm-regbits-34xx.h"
30 static void omap3_dpll_recalc(struct clk *clk);
31 static void omap3_clkoutx2_recalc(struct clk *clk);
32 static void omap3_dpll_allow_idle(struct clk *clk);
33 static void omap3_dpll_deny_idle(struct clk *clk);
34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
35 static int omap3_noncore_dpll_enable(struct clk *clk);
36 static void omap3_noncore_dpll_disable(struct clk *clk);
37 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
38 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
40 /* Maximum DPLL multiplier, divider values for OMAP3 */
41 #define OMAP3_MAX_DPLL_MULT 2048
42 #define OMAP3_MAX_DPLL_DIV 128
45 * DPLL1 supplies clock to the MPU.
46 * DPLL2 supplies clock to the IVA2.
47 * DPLL3 supplies CORE domain clocks.
48 * DPLL4 supplies peripheral clocks.
49 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
52 /* Forward declarations for DPLL bypass clocks */
53 static struct clk dpll1_fck;
54 static struct clk dpll2_fck;
56 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
57 #define DPLL_LOW_POWER_STOP 0x1
58 #define DPLL_LOW_POWER_BYPASS 0x5
59 #define DPLL_LOCKED 0x7
63 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
64 static struct clk omap_32k_fck = {
65 .name = "omap_32k_fck",
67 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
69 .clkdm = { .name = "prm_clkdm" },
70 .recalc = &propagate_rate,
73 static struct clk secure_32k_fck = {
74 .name = "secure_32k_fck",
76 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
78 .clkdm = { .name = "prm_clkdm" },
79 .recalc = &propagate_rate,
82 /* Virtual source clocks for osc_sys_ck */
83 static struct clk virt_12m_ck = {
84 .name = "virt_12m_ck",
86 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
88 .clkdm = { .name = "prm_clkdm" },
89 .recalc = &propagate_rate,
92 static struct clk virt_13m_ck = {
93 .name = "virt_13m_ck",
95 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
97 .clkdm = { .name = "prm_clkdm" },
98 .recalc = &propagate_rate,
101 static struct clk virt_16_8m_ck = {
102 .name = "virt_16_8m_ck",
104 .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
106 .clkdm = { .name = "prm_clkdm" },
107 .recalc = &propagate_rate,
110 static struct clk virt_19_2m_ck = {
111 .name = "virt_19_2m_ck",
113 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
115 .clkdm = { .name = "prm_clkdm" },
116 .recalc = &propagate_rate,
119 static struct clk virt_26m_ck = {
120 .name = "virt_26m_ck",
122 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
124 .clkdm = { .name = "prm_clkdm" },
125 .recalc = &propagate_rate,
128 static struct clk virt_38_4m_ck = {
129 .name = "virt_38_4m_ck",
131 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
133 .clkdm = { .name = "prm_clkdm" },
134 .recalc = &propagate_rate,
137 static const struct clksel_rate osc_sys_12m_rates[] = {
138 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
142 static const struct clksel_rate osc_sys_13m_rates[] = {
143 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
147 static const struct clksel_rate osc_sys_16_8m_rates[] = {
148 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
152 static const struct clksel_rate osc_sys_19_2m_rates[] = {
153 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
157 static const struct clksel_rate osc_sys_26m_rates[] = {
158 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
162 static const struct clksel_rate osc_sys_38_4m_rates[] = {
163 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
167 static const struct clksel osc_sys_clksel[] = {
168 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
169 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
170 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
171 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
172 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
173 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
177 /* Oscillator clock */
178 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
179 static struct clk osc_sys_ck = {
180 .name = "osc_sys_ck",
181 .prcm_mod = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
182 .init = &omap2_init_clksel_parent,
183 .clksel_reg = OMAP3_PRM_CLKSEL_OFFSET,
184 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
185 .clksel = osc_sys_clksel,
186 /* REVISIT: deal with autoextclkmode? */
187 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
189 .clkdm = { .name = "prm_clkdm" },
190 .recalc = &omap2_clksel_recalc,
193 static const struct clksel_rate div2_rates[] = {
194 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
195 { .div = 2, .val = 2, .flags = RATE_IN_343X },
199 static const struct clksel sys_clksel[] = {
200 { .parent = &osc_sys_ck, .rates = div2_rates },
204 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
205 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
206 static struct clk sys_ck = {
208 .parent = &osc_sys_ck,
209 .prcm_mod = OMAP3430_GR_MOD | CLK_REG_IN_PRM,
210 .init = &omap2_init_clksel_parent,
211 .clksel_reg = OMAP3_PRM_CLKSRC_CTRL_OFFSET,
212 .clksel_mask = OMAP_SYSCLKDIV_MASK,
213 .clksel = sys_clksel,
214 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
215 .clkdm = { .name = "prm_clkdm" },
216 .recalc = &omap2_clksel_recalc,
219 static struct clk sys_altclk = {
220 .name = "sys_altclk",
221 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
222 .clkdm = { .name = "cm_clkdm" },
223 .recalc = &propagate_rate,
227 * Optional external clock input for some McBSPs
228 * Apparently this is not really in prm_clkdm, but rather is fed into
229 * both CORE and PER separately.
231 static struct clk mcbsp_clks = {
232 .name = "mcbsp_clks",
233 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
234 .clkdm = { .name = "prm_clkdm" },
235 .recalc = &propagate_rate,
238 /* PRM EXTERNAL CLOCK OUTPUT */
240 static struct clk sys_clkout1 = {
241 .name = "sys_clkout1",
242 .parent = &osc_sys_ck,
243 .prcm_mod = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
244 .enable_reg = OMAP3_PRM_CLKOUT_CTRL_OFFSET,
245 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
246 .flags = CLOCK_IN_OMAP343X,
247 .clkdm = { .name = "prm_clkdm" },
248 .recalc = &followparent_recalc,
255 static const struct clksel_rate div16_dpll_rates[] = {
256 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
257 { .div = 2, .val = 2, .flags = RATE_IN_343X },
258 { .div = 3, .val = 3, .flags = RATE_IN_343X },
259 { .div = 4, .val = 4, .flags = RATE_IN_343X },
260 { .div = 5, .val = 5, .flags = RATE_IN_343X },
261 { .div = 6, .val = 6, .flags = RATE_IN_343X },
262 { .div = 7, .val = 7, .flags = RATE_IN_343X },
263 { .div = 8, .val = 8, .flags = RATE_IN_343X },
264 { .div = 9, .val = 9, .flags = RATE_IN_343X },
265 { .div = 10, .val = 10, .flags = RATE_IN_343X },
266 { .div = 11, .val = 11, .flags = RATE_IN_343X },
267 { .div = 12, .val = 12, .flags = RATE_IN_343X },
268 { .div = 13, .val = 13, .flags = RATE_IN_343X },
269 { .div = 14, .val = 14, .flags = RATE_IN_343X },
270 { .div = 15, .val = 15, .flags = RATE_IN_343X },
271 { .div = 16, .val = 16, .flags = RATE_IN_343X },
276 /* MPU clock source */
278 static struct dpll_data dpll1_dd = {
279 .mult_div1_reg = OMAP3430_CM_CLKSEL1_PLL,
280 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
281 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
282 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
283 .control_reg = OMAP3430_CM_CLKEN_PLL,
284 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
285 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
286 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
287 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
288 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
289 .autoidle_reg = OMAP3430_CM_AUTOIDLE_PLL,
290 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
291 .idlest_reg = OMAP3430_CM_IDLEST_PLL,
292 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
293 .bypass_clk = &dpll1_fck,
294 .max_multiplier = OMAP3_MAX_DPLL_MULT,
295 .max_divider = OMAP3_MAX_DPLL_DIV,
296 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
299 static struct clk dpll1_ck = {
303 .dpll_data = &dpll1_dd,
304 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
305 .round_rate = &omap2_dpll_round_rate,
306 .set_rate = &omap3_noncore_dpll_set_rate,
307 .clkdm = { .name = "dpll1_clkdm" },
308 .recalc = &omap3_dpll_recalc,
312 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
313 * DPLL isn't bypassed.
315 static struct clk dpll1_x2_ck = {
316 .name = "dpll1_x2_ck",
318 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
319 PARENT_CONTROLS_CLOCK,
320 .clkdm = { .name = "dpll1_clkdm" },
321 .recalc = &omap3_clkoutx2_recalc,
324 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
325 static const struct clksel div16_dpll1_x2m2_clksel[] = {
326 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
331 * Does not exist in the TRM - needed to separate the M2 divider from
332 * bypass selection in mpu_ck
334 static struct clk dpll1_x2m2_ck = {
335 .name = "dpll1_x2m2_ck",
336 .parent = &dpll1_x2_ck,
338 .init = &omap2_init_clksel_parent,
339 .clksel_reg = OMAP3430_CM_CLKSEL2_PLL,
340 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
341 .clksel = div16_dpll1_x2m2_clksel,
342 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
343 PARENT_CONTROLS_CLOCK,
344 .clkdm = { .name = "dpll1_clkdm" },
345 .recalc = &omap2_clksel_recalc,
349 /* IVA2 clock source */
352 static struct dpll_data dpll2_dd = {
353 .mult_div1_reg = OMAP3430_CM_CLKSEL1_PLL,
354 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
355 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
356 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
357 .control_reg = OMAP3430_CM_CLKEN_PLL,
358 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
359 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
360 (1 << DPLL_LOW_POWER_BYPASS),
361 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
362 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
363 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
364 .autoidle_reg = OMAP3430_CM_AUTOIDLE_PLL,
365 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
366 .idlest_reg = OMAP3430_CM_IDLEST_PLL,
367 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
368 .bypass_clk = &dpll2_fck,
369 .max_multiplier = OMAP3_MAX_DPLL_MULT,
370 .max_divider = OMAP3_MAX_DPLL_DIV,
371 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
374 static struct clk dpll2_ck = {
377 .prcm_mod = OMAP3430_IVA2_MOD,
378 .dpll_data = &dpll2_dd,
379 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
380 .enable = &omap3_noncore_dpll_enable,
381 .disable = &omap3_noncore_dpll_disable,
382 .round_rate = &omap2_dpll_round_rate,
383 .set_rate = &omap3_noncore_dpll_set_rate,
384 .clkdm = { .name = "dpll2_clkdm" },
385 .recalc = &omap3_dpll_recalc,
388 static const struct clksel div16_dpll2_m2x2_clksel[] = {
389 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
394 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
395 * or CLKOUTX2. CLKOUT seems most plausible.
397 static struct clk dpll2_m2_ck = {
398 .name = "dpll2_m2_ck",
400 .prcm_mod = OMAP3430_IVA2_MOD,
401 .init = &omap2_init_clksel_parent,
402 .clksel_reg = OMAP3430_CM_CLKSEL2_PLL,
403 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
404 .clksel = div16_dpll2_m2x2_clksel,
405 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
406 PARENT_CONTROLS_CLOCK,
407 .clkdm = { .name = "dpll2_clkdm" },
408 .recalc = &omap2_clksel_recalc,
413 * Source clock for all interfaces and for some device fclks
414 * REVISIT: Also supports fast relock bypass - not included below
416 static struct dpll_data dpll3_dd = {
417 .mult_div1_reg = CM_CLKSEL1,
418 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
419 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
420 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
421 .control_reg = CM_CLKEN,
422 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
423 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
424 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
425 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
426 .autoidle_reg = CM_AUTOIDLE,
427 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
428 .idlest_reg = CM_IDLEST,
429 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
430 .bypass_clk = &sys_ck,
431 .max_multiplier = OMAP3_MAX_DPLL_MULT,
432 .max_divider = OMAP3_MAX_DPLL_DIV,
433 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
436 static struct clk dpll3_ck = {
440 .dpll_data = &dpll3_dd,
441 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
442 .round_rate = &omap2_dpll_round_rate,
443 .clkdm = { .name = "dpll3_clkdm" },
444 .recalc = &omap3_dpll_recalc,
448 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
449 * DPLL isn't bypassed
451 static struct clk dpll3_x2_ck = {
452 .name = "dpll3_x2_ck",
454 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
455 PARENT_CONTROLS_CLOCK,
456 .clkdm = { .name = "dpll3_clkdm" },
457 .recalc = &omap3_clkoutx2_recalc,
460 static const struct clksel_rate div31_dpll3_rates[] = {
461 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
462 { .div = 2, .val = 2, .flags = RATE_IN_343X },
463 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
464 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
465 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
466 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
467 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
468 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
469 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
470 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
471 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
472 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
473 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
474 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
475 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
476 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
477 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
478 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
479 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
480 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
481 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
482 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
483 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
484 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
485 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
486 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
487 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
488 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
489 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
490 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
491 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
495 static const struct clksel div31_dpll3m2_clksel[] = {
496 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
500 /* DPLL3 output M2 - primary control point for CORE speed */
501 static struct clk dpll3_m2_ck = {
502 .name = "dpll3_m2_ck",
505 .init = &omap2_init_clksel_parent,
506 .clksel_reg = CM_CLKSEL1,
507 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
508 .clksel = div31_dpll3m2_clksel,
509 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
510 PARENT_CONTROLS_CLOCK,
511 .clkdm = { .name = "dpll3_clkdm" },
512 .round_rate = &omap2_clksel_round_rate,
513 .set_rate = &omap3_core_dpll_m2_set_rate,
514 .recalc = &omap2_clksel_recalc,
517 static struct clk core_ck = {
519 .parent = &dpll3_m2_ck,
520 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
521 PARENT_CONTROLS_CLOCK,
522 .clkdm = { .name = "cm_clkdm" },
523 .recalc = &followparent_recalc,
526 static struct clk dpll3_m2x2_ck = {
527 .name = "dpll3_m2x2_ck",
528 .parent = &dpll3_x2_ck,
529 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
530 PARENT_CONTROLS_CLOCK,
531 .clkdm = { .name = "dpll3_clkdm" },
532 .recalc = &followparent_recalc,
535 /* The PWRDN bit is apparently only available on 3430ES2 and above */
536 static const struct clksel div16_dpll3_clksel[] = {
537 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
541 /* This virtual clock is the source for dpll3_m3x2_ck */
542 static struct clk dpll3_m3_ck = {
543 .name = "dpll3_m3_ck",
545 .prcm_mod = OMAP3430_EMU_MOD,
546 .init = &omap2_init_clksel_parent,
547 .clksel_reg = CM_CLKSEL1,
548 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
549 .clksel = div16_dpll3_clksel,
550 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
551 PARENT_CONTROLS_CLOCK,
552 .clkdm = { .name = "dpll3_clkdm" },
553 .recalc = &omap2_clksel_recalc,
556 /* The PWRDN bit is apparently only available on 3430ES2 and above */
557 static struct clk dpll3_m3x2_ck = {
558 .name = "dpll3_m3x2_ck",
559 .parent = &dpll3_m3_ck,
561 .enable_reg = CM_CLKEN,
562 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
563 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
564 .clkdm = { .name = "dpll3_clkdm" },
565 .recalc = &omap3_clkoutx2_recalc,
568 static struct clk emu_core_alwon_ck = {
569 .name = "emu_core_alwon_ck",
570 .parent = &dpll3_m3x2_ck,
571 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
572 PARENT_CONTROLS_CLOCK,
573 .clkdm = { .name = "dpll3_clkdm" },
574 .recalc = &followparent_recalc,
578 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
580 static struct dpll_data dpll4_dd = {
581 .mult_div1_reg = CM_CLKSEL2,
582 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
583 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
584 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
585 .control_reg = CM_CLKEN,
586 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
587 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
588 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
589 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
590 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
591 .autoidle_reg = CM_AUTOIDLE,
592 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
593 .idlest_reg = CM_IDLEST,
594 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
595 .bypass_clk = &sys_ck,
596 .max_multiplier = OMAP3_MAX_DPLL_MULT,
597 .max_divider = OMAP3_MAX_DPLL_DIV,
598 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
601 static struct clk dpll4_ck = {
605 .dpll_data = &dpll4_dd,
606 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
607 .enable = &omap3_noncore_dpll_enable,
608 .disable = &omap3_noncore_dpll_disable,
609 .round_rate = &omap2_dpll_round_rate,
610 .set_rate = &omap3_noncore_dpll_set_rate,
611 .clkdm = { .name = "dpll4_clkdm" },
612 .recalc = &omap3_dpll_recalc,
616 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
617 * DPLL isn't bypassed --
618 * XXX does this serve any downstream clocks?
620 static struct clk dpll4_x2_ck = {
621 .name = "dpll4_x2_ck",
623 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
624 PARENT_CONTROLS_CLOCK,
625 .clkdm = { .name = "dpll4_clkdm" },
626 .recalc = &omap3_clkoutx2_recalc,
629 static const struct clksel div16_dpll4_clksel[] = {
630 { .parent = &dpll4_ck, .rates = div16_dpll_rates },
634 /* This virtual clock is the source for dpll4_m2x2_ck */
635 static struct clk dpll4_m2_ck = {
636 .name = "dpll4_m2_ck",
639 .init = &omap2_init_clksel_parent,
640 .clksel_reg = OMAP3430_CM_CLKSEL3,
641 .clksel_mask = OMAP3430_DIV_96M_MASK,
642 .clksel = div16_dpll4_clksel,
643 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
644 PARENT_CONTROLS_CLOCK,
645 .clkdm = { .name = "dpll4_clkdm" },
646 .recalc = &omap2_clksel_recalc,
649 /* The PWRDN bit is apparently only available on 3430ES2 and above */
650 static struct clk dpll4_m2x2_ck = {
651 .name = "dpll4_m2x2_ck",
652 .parent = &dpll4_m2_ck,
654 .enable_reg = CM_CLKEN,
655 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
656 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
657 .clkdm = { .name = "dpll4_clkdm" },
658 .recalc = &omap3_clkoutx2_recalc,
662 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
663 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
664 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
667 static struct clk omap_96m_alwon_fck = {
668 .name = "omap_96m_alwon_fck",
669 .parent = &dpll4_m2x2_ck,
670 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
671 PARENT_CONTROLS_CLOCK,
672 .clkdm = { .name = "prm_clkdm" },
673 .recalc = &followparent_recalc,
676 static struct clk cm_96m_fck = {
677 .name = "cm_96m_fck",
678 .parent = &omap_96m_alwon_fck,
679 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
680 PARENT_CONTROLS_CLOCK,
681 .clkdm = { .name = "cm_clkdm" },
682 .recalc = &followparent_recalc,
685 static const struct clksel_rate omap_96m_dpll_rates[] = {
686 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
690 static const struct clksel_rate omap_96m_sys_rates[] = {
691 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
695 static const struct clksel omap_96m_fck_clksel[] = {
696 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
697 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
701 static struct clk omap_96m_fck = {
702 .name = "omap_96m_fck",
705 .init = &omap2_init_clksel_parent,
706 .clksel_reg = CM_CLKSEL1,
707 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
708 .clksel = omap_96m_fck_clksel,
709 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
710 PARENT_CONTROLS_CLOCK,
711 .clkdm = { .name = "cm_clkdm" },
712 .recalc = &omap2_clksel_recalc,
715 /* This virtual clock is the source for dpll4_m3x2_ck */
716 static struct clk dpll4_m3_ck = {
717 .name = "dpll4_m3_ck",
719 .prcm_mod = OMAP3430_DSS_MOD,
720 .init = &omap2_init_clksel_parent,
721 .clksel_reg = CM_CLKSEL,
722 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
723 .clksel = div16_dpll4_clksel,
724 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
725 PARENT_CONTROLS_CLOCK,
726 .clkdm = { .name = "dpll4_clkdm" },
727 .recalc = &omap2_clksel_recalc,
730 /* The PWRDN bit is apparently only available on 3430ES2 and above */
731 static struct clk dpll4_m3x2_ck = {
732 .name = "dpll4_m3x2_ck",
733 .parent = &dpll4_m3_ck,
735 .init = &omap2_init_clksel_parent,
736 .enable_reg = CM_CLKEN,
737 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
738 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
739 .clkdm = { .name = "dpll4_clkdm" },
740 .recalc = &omap3_clkoutx2_recalc,
743 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
744 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
748 static const struct clksel_rate omap_54m_alt_rates[] = {
749 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
753 static const struct clksel omap_54m_clksel[] = {
754 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
755 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
759 static struct clk omap_54m_fck = {
760 .name = "omap_54m_fck",
762 .init = &omap2_init_clksel_parent,
763 .clksel_reg = CM_CLKSEL1,
764 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
765 .clksel = omap_54m_clksel,
766 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
767 PARENT_CONTROLS_CLOCK,
768 .clkdm = { .name = "cm_clkdm" },
769 .recalc = &omap2_clksel_recalc,
772 static const struct clksel_rate omap_48m_cm96m_rates[] = {
773 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
777 static const struct clksel_rate omap_48m_alt_rates[] = {
778 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
782 static const struct clksel omap_48m_clksel[] = {
783 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
784 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
788 static struct clk omap_48m_fck = {
789 .name = "omap_48m_fck",
791 .init = &omap2_init_clksel_parent,
792 .clksel_reg = CM_CLKSEL1,
793 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
794 .clksel = omap_48m_clksel,
795 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
796 PARENT_CONTROLS_CLOCK,
797 .clkdm = { .name = "cm_clkdm" },
798 .recalc = &omap2_clksel_recalc,
801 static struct clk omap_12m_fck = {
802 .name = "omap_12m_fck",
803 .parent = &omap_48m_fck,
805 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
806 PARENT_CONTROLS_CLOCK,
807 .clkdm = { .name = "cm_clkdm" },
808 .recalc = &omap2_fixed_divisor_recalc,
811 /* This virstual clock is the source for dpll4_m4x2_ck */
812 static struct clk dpll4_m4_ck = {
813 .name = "dpll4_m4_ck",
815 .prcm_mod = OMAP3430_DSS_MOD,
816 .init = &omap2_init_clksel_parent,
817 .clksel_reg = CM_CLKSEL,
818 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
819 .clksel = div16_dpll4_clksel,
820 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
821 PARENT_CONTROLS_CLOCK,
822 .clkdm = { .name = "dpll4_clkdm" },
823 .recalc = &omap2_clksel_recalc,
826 /* The PWRDN bit is apparently only available on 3430ES2 and above */
827 static struct clk dpll4_m4x2_ck = {
828 .name = "dpll4_m4x2_ck",
829 .parent = &dpll4_m4_ck,
831 .enable_reg = CM_CLKEN,
832 .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
833 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
834 .clkdm = { .name = "dpll4_clkdm" },
835 .recalc = &omap3_clkoutx2_recalc,
838 /* This virtual clock is the source for dpll4_m5x2_ck */
839 static struct clk dpll4_m5_ck = {
840 .name = "dpll4_m5_ck",
842 .prcm_mod = OMAP3430_CAM_MOD,
843 .init = &omap2_init_clksel_parent,
844 .clksel_reg = CM_CLKSEL,
845 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
846 .clksel = div16_dpll4_clksel,
847 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
848 PARENT_CONTROLS_CLOCK,
849 .clkdm = { .name = "dpll4_clkdm" },
850 .recalc = &omap2_clksel_recalc,
853 /* The PWRDN bit is apparently only available on 3430ES2 and above */
854 static struct clk dpll4_m5x2_ck = {
855 .name = "dpll4_m5x2_ck",
856 .parent = &dpll4_m5_ck,
858 .enable_reg = CM_CLKEN,
859 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
860 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
861 .clkdm = { .name = "dpll4_clkdm" },
862 .recalc = &omap3_clkoutx2_recalc,
865 /* This virtual clock is the source for dpll4_m6x2_ck */
866 static struct clk dpll4_m6_ck = {
867 .name = "dpll4_m6_ck",
869 .prcm_mod = OMAP3430_EMU_MOD,
870 .init = &omap2_init_clksel_parent,
871 .clksel_reg = CM_CLKSEL1,
872 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
873 .clksel = div16_dpll4_clksel,
874 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
875 PARENT_CONTROLS_CLOCK,
876 .clkdm = { .name = "dpll4_clkdm" },
877 .recalc = &omap2_clksel_recalc,
880 /* The PWRDN bit is apparently only available on 3430ES2 and above */
881 static struct clk dpll4_m6x2_ck = {
882 .name = "dpll4_m6x2_ck",
883 .parent = &dpll4_m6_ck,
885 .init = &omap2_init_clksel_parent,
886 .enable_reg = CM_CLKEN,
887 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
888 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
889 .clkdm = { .name = "dpll4_clkdm" },
890 .recalc = &omap3_clkoutx2_recalc,
893 static struct clk emu_per_alwon_ck = {
894 .name = "emu_per_alwon_ck",
895 .parent = &dpll4_m6x2_ck,
896 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
897 PARENT_CONTROLS_CLOCK,
898 .clkdm = { .name = "dpll4_clkdm" },
899 .recalc = &followparent_recalc,
903 /* Supplies 120MHz clock, USIM source clock */
906 static struct dpll_data dpll5_dd = {
907 .mult_div1_reg = OMAP3430ES2_CM_CLKSEL4,
908 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
909 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
910 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
911 .control_reg = OMAP3430ES2_CM_CLKEN2,
912 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
913 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
914 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
915 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
916 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
917 .autoidle_reg = OMAP3430ES2_CM_AUTOIDLE2_PLL,
918 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
919 .idlest_reg = CM_IDLEST2,
920 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
921 .bypass_clk = &sys_ck,
922 .max_multiplier = OMAP3_MAX_DPLL_MULT,
923 .max_divider = OMAP3_MAX_DPLL_DIV,
924 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
927 static struct clk dpll5_ck = {
931 .dpll_data = &dpll5_dd,
932 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
933 .enable = &omap3_noncore_dpll_enable,
934 .disable = &omap3_noncore_dpll_disable,
935 .round_rate = &omap2_dpll_round_rate,
936 .set_rate = &omap3_noncore_dpll_set_rate,
937 .clkdm = { .name = "dpll5_clkdm" },
938 .recalc = &omap3_dpll_recalc,
941 static const struct clksel div16_dpll5_clksel[] = {
942 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
946 static struct clk dpll5_m2_ck = {
947 .name = "dpll5_m2_ck",
950 .init = &omap2_init_clksel_parent,
951 .clksel_reg = OMAP3430ES2_CM_CLKSEL5,
952 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
953 .clksel = div16_dpll5_clksel,
954 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
955 PARENT_CONTROLS_CLOCK,
956 .clkdm = { .name = "dpll5_clkdm" },
957 .recalc = &omap2_clksel_recalc,
960 /* CM EXTERNAL CLOCK OUTPUTS */
962 static const struct clksel_rate clkout2_src_core_rates[] = {
963 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
967 static const struct clksel_rate clkout2_src_sys_rates[] = {
968 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
972 static const struct clksel_rate clkout2_src_96m_rates[] = {
973 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
977 static const struct clksel_rate clkout2_src_54m_rates[] = {
978 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
982 static const struct clksel clkout2_src_clksel[] = {
983 { .parent = &core_ck, .rates = clkout2_src_core_rates },
984 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
985 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
986 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
990 static struct clk clkout2_src_ck = {
991 .name = "clkout2_src_ck",
992 .prcm_mod = OMAP3430_CCR_MOD,
993 .init = &omap2_init_clksel_parent,
994 .enable_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
995 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
996 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
997 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
998 .clksel = clkout2_src_clksel,
999 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1000 .clkdm = { .name = "cm_clkdm" },
1001 .recalc = &omap2_clksel_recalc,
1004 static const struct clksel_rate sys_clkout2_rates[] = {
1005 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1006 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1007 { .div = 4, .val = 2, .flags = RATE_IN_343X },
1008 { .div = 8, .val = 3, .flags = RATE_IN_343X },
1009 { .div = 16, .val = 4, .flags = RATE_IN_343X },
1013 static const struct clksel sys_clkout2_clksel[] = {
1014 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1018 static struct clk sys_clkout2 = {
1019 .name = "sys_clkout2",
1020 .prcm_mod = OMAP3430_CCR_MOD,
1021 .init = &omap2_init_clksel_parent,
1022 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
1023 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
1024 .clksel = sys_clkout2_clksel,
1025 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1026 .clkdm = { .name = "cm_clkdm" },
1027 .recalc = &omap2_clksel_recalc,
1030 /* CM OUTPUT CLOCKS */
1032 static struct clk corex2_fck = {
1033 .name = "corex2_fck",
1034 .parent = &dpll3_m2x2_ck,
1035 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1036 PARENT_CONTROLS_CLOCK,
1037 .clkdm = { .name = "cm_clkdm" },
1038 .recalc = &followparent_recalc,
1041 /* DPLL power domain clock controls */
1043 static const struct clksel_rate div4_rates[] = {
1044 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1045 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1046 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1050 static const struct clksel div4_core_clksel[] = {
1051 { .parent = &core_ck, .rates = div4_rates },
1055 static struct clk dpll1_fck = {
1056 .name = "dpll1_fck",
1058 .prcm_mod = MPU_MOD,
1059 .init = &omap2_init_clksel_parent,
1060 .clksel_reg = OMAP3430_CM_CLKSEL1_PLL,
1061 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1062 .clksel = div4_core_clksel,
1063 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1064 PARENT_CONTROLS_CLOCK,
1065 .clkdm = { .name = "cm_clkdm" },
1066 .recalc = &omap2_clksel_recalc,
1069 static struct clk mpu_ck = {
1071 .parent = &dpll1_x2m2_ck,
1072 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1073 PARENT_CONTROLS_CLOCK,
1074 .clkdm = { .name = "mpu_clkdm" },
1075 .recalc = &followparent_recalc,
1078 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1079 static const struct clksel_rate arm_fck_rates[] = {
1080 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1081 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1085 static const struct clksel arm_fck_clksel[] = {
1086 { .parent = &mpu_ck, .rates = arm_fck_rates },
1090 static struct clk arm_fck = {
1093 .prcm_mod = MPU_MOD,
1094 .init = &omap2_init_clksel_parent,
1095 .clksel_reg = OMAP3430_CM_IDLEST_PLL,
1096 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1097 .clksel = arm_fck_clksel,
1098 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1099 PARENT_CONTROLS_CLOCK,
1100 .clkdm = { .name = "mpu_clkdm" },
1101 .recalc = &omap2_clksel_recalc,
1104 /* XXX What about neon_clkdm ? */
1107 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1108 * although it is referenced - so this is a guess
1110 static struct clk emu_mpu_alwon_ck = {
1111 .name = "emu_mpu_alwon_ck",
1113 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1114 PARENT_CONTROLS_CLOCK,
1115 .clkdm = { .name = "mpu_clkdm" },
1116 .recalc = &followparent_recalc,
1119 static struct clk dpll2_fck = {
1120 .name = "dpll2_fck",
1122 .prcm_mod = OMAP3430_IVA2_MOD,
1123 .init = &omap2_init_clksel_parent,
1124 .clksel_reg = OMAP3430_CM_CLKSEL1_PLL,
1125 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1126 .clksel = div4_core_clksel,
1127 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1128 PARENT_CONTROLS_CLOCK,
1129 .clkdm = { .name = "cm_clkdm" },
1130 .recalc = &omap2_clksel_recalc,
1133 static struct clk iva2_ck = {
1135 .parent = &dpll2_m2_ck,
1136 .prcm_mod = OMAP3430_IVA2_MOD,
1137 .init = &omap2_init_clksel_parent,
1138 .enable_reg = CM_FCLKEN,
1139 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1140 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1141 .clkdm = { .name = "iva2_clkdm" },
1142 .recalc = &followparent_recalc,
1145 /* Common interface clocks */
1147 static const struct clksel div2_core_clksel[] = {
1148 { .parent = &core_ck, .rates = div2_rates },
1152 static struct clk l3_ick = {
1155 .prcm_mod = CORE_MOD,
1156 .init = &omap2_init_clksel_parent,
1157 .clksel_reg = CM_CLKSEL,
1158 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1159 .clksel = div2_core_clksel,
1160 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1161 PARENT_CONTROLS_CLOCK,
1162 .clkdm = { .name = "core_l3_clkdm" },
1163 .recalc = &omap2_clksel_recalc,
1166 static const struct clksel div2_l3_clksel[] = {
1167 { .parent = &l3_ick, .rates = div2_rates },
1171 static struct clk l4_ick = {
1174 .prcm_mod = CORE_MOD,
1175 .init = &omap2_init_clksel_parent,
1176 .clksel_reg = CM_CLKSEL,
1177 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1178 .clksel = div2_l3_clksel,
1179 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1180 PARENT_CONTROLS_CLOCK,
1181 .clkdm = { .name = "core_l4_clkdm" },
1182 .recalc = &omap2_clksel_recalc,
1186 static const struct clksel div2_l4_clksel[] = {
1187 { .parent = &l4_ick, .rates = div2_rates },
1191 static struct clk rm_ick = {
1194 .prcm_mod = WKUP_MOD,
1195 .init = &omap2_init_clksel_parent,
1196 .clksel_reg = CM_CLKSEL,
1197 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1198 .clksel = div2_l4_clksel,
1199 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1200 .clkdm = { .name = "cm_clkdm" },
1201 .recalc = &omap2_clksel_recalc,
1204 /* GFX power domain */
1206 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1208 static const struct clksel gfx_l3_clksel[] = {
1209 { .parent = &l3_ick, .rates = gfx_l3_rates },
1213 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1214 static struct clk gfx_l3_ck = {
1215 .name = "gfx_l3_ck",
1217 .prcm_mod = GFX_MOD,
1218 .init = &omap2_init_clksel_parent,
1219 .enable_reg = CM_ICLKEN,
1220 .enable_bit = OMAP_EN_GFX_SHIFT,
1221 .flags = CLOCK_IN_OMAP3430ES1,
1222 .clkdm = { .name = "gfx_3430es1_clkdm" },
1223 .recalc = &followparent_recalc,
1226 static struct clk gfx_l3_fck = {
1227 .name = "gfx_l3_fck",
1228 .parent = &gfx_l3_ck,
1229 .prcm_mod = GFX_MOD,
1230 .init = &omap2_init_clksel_parent,
1231 .clksel_reg = CM_CLKSEL,
1232 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1233 .clksel = gfx_l3_clksel,
1234 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1235 PARENT_CONTROLS_CLOCK,
1236 .clkdm = { .name = "gfx_3430es1_clkdm" },
1237 .recalc = &omap2_clksel_recalc,
1240 static struct clk gfx_l3_ick = {
1241 .name = "gfx_l3_ick",
1242 .parent = &gfx_l3_ck,
1243 .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1244 .clkdm = { .name = "gfx_3430es1_clkdm" },
1245 .recalc = &followparent_recalc,
1248 static struct clk gfx_cg1_ck = {
1249 .name = "gfx_cg1_ck",
1250 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1251 .prcm_mod = GFX_MOD,
1252 .enable_reg = CM_FCLKEN,
1253 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1254 .flags = CLOCK_IN_OMAP3430ES1,
1255 .clkdm = { .name = "gfx_3430es1_clkdm" },
1256 .recalc = &followparent_recalc,
1259 static struct clk gfx_cg2_ck = {
1260 .name = "gfx_cg2_ck",
1261 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1262 .prcm_mod = GFX_MOD,
1263 .enable_reg = CM_FCLKEN,
1264 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1265 .flags = CLOCK_IN_OMAP3430ES1,
1266 .clkdm = { .name = "gfx_3430es1_clkdm" },
1267 .recalc = &followparent_recalc,
1270 /* SGX power domain - 3430ES2 only */
1272 static const struct clksel_rate sgx_core_rates[] = {
1273 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1274 { .div = 4, .val = 1, .flags = RATE_IN_343X },
1275 { .div = 6, .val = 2, .flags = RATE_IN_343X },
1279 static const struct clksel_rate sgx_96m_rates[] = {
1280 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1284 static const struct clksel sgx_clksel[] = {
1285 { .parent = &core_ck, .rates = sgx_core_rates },
1286 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1290 static struct clk sgx_fck = {
1292 .init = &omap2_init_clksel_parent,
1293 .prcm_mod = OMAP3430ES2_SGX_MOD,
1294 .enable_reg = CM_FCLKEN,
1295 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1296 .clksel_reg = CM_CLKSEL,
1297 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1298 .clksel = sgx_clksel,
1299 .flags = CLOCK_IN_OMAP3430ES2,
1300 .clkdm = { .name = "sgx_clkdm" },
1301 .recalc = &omap2_clksel_recalc,
1304 static struct clk sgx_ick = {
1307 .prcm_mod = OMAP3430ES2_SGX_MOD,
1308 .enable_reg = CM_ICLKEN,
1309 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1310 .flags = CLOCK_IN_OMAP3430ES2,
1311 .clkdm = { .name = "sgx_clkdm" },
1312 .recalc = &followparent_recalc,
1315 /* CORE power domain */
1317 static struct clk d2d_26m_fck = {
1318 .name = "d2d_26m_fck",
1320 .prcm_mod = CORE_MOD,
1321 .enable_reg = CM_FCLKEN1,
1322 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1323 .flags = CLOCK_IN_OMAP3430ES1,
1324 .clkdm = { .name = "d2d_clkdm" },
1325 .recalc = &followparent_recalc,
1328 static const struct clksel omap343x_gpt_clksel[] = {
1329 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1330 { .parent = &sys_ck, .rates = gpt_sys_rates },
1334 static struct clk gpt10_fck = {
1335 .name = "gpt10_fck",
1337 .prcm_mod = CORE_MOD,
1338 .init = &omap2_init_clksel_parent,
1339 .enable_reg = CM_FCLKEN1,
1340 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1341 .clksel_reg = CM_CLKSEL,
1342 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1343 .clksel = omap343x_gpt_clksel,
1344 .flags = CLOCK_IN_OMAP343X,
1345 .clkdm = { .name = "core_l4_clkdm" },
1346 .recalc = &omap2_clksel_recalc,
1349 static struct clk gpt11_fck = {
1350 .name = "gpt11_fck",
1352 .prcm_mod = CORE_MOD,
1353 .init = &omap2_init_clksel_parent,
1354 .enable_reg = CM_FCLKEN1,
1355 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1356 .clksel_reg = CM_CLKSEL,
1357 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1358 .clksel = omap343x_gpt_clksel,
1359 .flags = CLOCK_IN_OMAP343X,
1360 .clkdm = { .name = "core_l4_clkdm" },
1361 .recalc = &omap2_clksel_recalc,
1364 static struct clk cpefuse_fck = {
1365 .name = "cpefuse_fck",
1367 .prcm_mod = CORE_MOD,
1368 .enable_reg = OMAP3430ES2_CM_FCLKEN3,
1369 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1370 .flags = CLOCK_IN_OMAP3430ES2,
1371 .clkdm = { .name = "cm_clkdm" },
1372 .recalc = &followparent_recalc,
1375 static struct clk ts_fck = {
1377 .parent = &omap_32k_fck,
1378 .prcm_mod = CORE_MOD,
1379 .enable_reg = OMAP3430ES2_CM_FCLKEN3,
1380 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1381 .flags = CLOCK_IN_OMAP3430ES2,
1382 .clkdm = { .name = "core_l4_clkdm" },
1383 .recalc = &followparent_recalc,
1386 static struct clk usbtll_fck = {
1387 .name = "usbtll_fck",
1388 .parent = &dpll5_m2_ck,
1389 .prcm_mod = CORE_MOD,
1390 .enable_reg = OMAP3430ES2_CM_FCLKEN3,
1391 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1392 .flags = CLOCK_IN_OMAP3430ES2,
1393 .clkdm = { .name = "core_l4_clkdm" },
1394 .recalc = &followparent_recalc,
1397 /* CORE 96M FCLK-derived clocks */
1399 static struct clk core_96m_fck = {
1400 .name = "core_96m_fck",
1401 .parent = &omap_96m_fck,
1402 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1403 PARENT_CONTROLS_CLOCK,
1404 .clkdm = { .name = "core_l4_clkdm" },
1405 .recalc = &followparent_recalc,
1408 static struct clk mmchs3_fck = {
1409 .name = "mmchs_fck",
1411 .parent = &core_96m_fck,
1412 .prcm_mod = CORE_MOD,
1413 .enable_reg = CM_FCLKEN1,
1414 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1415 .flags = CLOCK_IN_OMAP3430ES2,
1416 .clkdm = { .name = "core_l4_clkdm" },
1417 .recalc = &followparent_recalc,
1420 static struct clk mmchs2_fck = {
1421 .name = "mmchs_fck",
1423 .parent = &core_96m_fck,
1424 .prcm_mod = CORE_MOD,
1425 .enable_reg = CM_FCLKEN1,
1426 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1427 .flags = CLOCK_IN_OMAP343X,
1428 .clkdm = { .name = "core_l4_clkdm" },
1429 .recalc = &followparent_recalc,
1432 static struct clk mspro_fck = {
1433 .name = "mspro_fck",
1434 .parent = &core_96m_fck,
1435 .prcm_mod = CORE_MOD,
1436 .enable_reg = CM_FCLKEN1,
1437 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1438 .flags = CLOCK_IN_OMAP343X,
1439 .clkdm = { .name = "core_l4_clkdm" },
1440 .recalc = &followparent_recalc,
1443 static struct clk mmchs1_fck = {
1444 .name = "mmchs_fck",
1446 .parent = &core_96m_fck,
1447 .prcm_mod = CORE_MOD,
1448 .enable_reg = CM_FCLKEN1,
1449 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1450 .flags = CLOCK_IN_OMAP343X,
1451 .clkdm = { .name = "core_l4_clkdm" },
1452 .recalc = &followparent_recalc,
1455 static struct clk i2c3_fck = {
1458 .parent = &core_96m_fck,
1459 .prcm_mod = CORE_MOD,
1460 .enable_reg = CM_FCLKEN1,
1461 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1462 .flags = CLOCK_IN_OMAP343X,
1463 .clkdm = { .name = "core_l4_clkdm" },
1464 .recalc = &followparent_recalc,
1467 static struct clk i2c2_fck = {
1470 .parent = &core_96m_fck,
1471 .prcm_mod = CORE_MOD,
1472 .enable_reg = CM_FCLKEN1,
1473 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1474 .flags = CLOCK_IN_OMAP343X,
1475 .clkdm = { .name = "core_l4_clkdm" },
1476 .recalc = &followparent_recalc,
1479 static struct clk i2c1_fck = {
1482 .parent = &core_96m_fck,
1483 .prcm_mod = CORE_MOD,
1484 .enable_reg = CM_FCLKEN1,
1485 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1486 .flags = CLOCK_IN_OMAP343X,
1487 .clkdm = { .name = "core_l4_clkdm" },
1488 .recalc = &followparent_recalc,
1492 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1493 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1495 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1496 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1500 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1501 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1505 static const struct clksel mcbsp_15_clksel[] = {
1506 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1507 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1511 static struct clk mcbsp5_src_fck = {
1512 .name = "mcbsp_src_fck",
1514 .prcm_mod = CLK_REG_IN_SCM,
1515 .init = &omap2_init_clksel_parent,
1516 .clksel_reg = OMAP343X_CONTROL_DEVCONF1,
1517 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1518 .clksel = mcbsp_15_clksel,
1519 .flags = CLOCK_IN_OMAP343X,
1520 .clkdm = { .name = "core_l4_clkdm" },
1521 .recalc = &omap2_clksel_recalc,
1524 static struct clk mcbsp5_fck = {
1525 .name = "mcbsp_fck",
1527 .parent = &mcbsp5_src_fck,
1528 .prcm_mod = CORE_MOD,
1529 .enable_reg = CM_FCLKEN1,
1530 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1531 .flags = CLOCK_IN_OMAP343X,
1532 .clkdm = { .name = "core_l4_clkdm" },
1533 .recalc = &followparent_recalc,
1536 static struct clk mcbsp1_src_fck = {
1537 .name = "mcbsp_src_fck",
1539 .prcm_mod = CLK_REG_IN_SCM,
1540 .init = &omap2_init_clksel_parent,
1541 .clksel_reg = OMAP2_CONTROL_DEVCONF0,
1542 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1543 .clksel = mcbsp_15_clksel,
1544 .flags = CLOCK_IN_OMAP343X,
1545 .clkdm = { .name = "core_l4_clkdm" },
1546 .recalc = &omap2_clksel_recalc,
1549 static struct clk mcbsp1_fck = {
1550 .name = "mcbsp_fck",
1552 .parent = &mcbsp1_src_fck,
1553 .prcm_mod = CORE_MOD,
1554 .enable_reg = CM_FCLKEN1,
1555 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1556 .flags = CLOCK_IN_OMAP343X,
1557 .clkdm = { .name = "core_l4_clkdm" },
1558 .recalc = &followparent_recalc,
1561 /* CORE_48M_FCK-derived clocks */
1563 static struct clk core_48m_fck = {
1564 .name = "core_48m_fck",
1565 .parent = &omap_48m_fck,
1566 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1567 PARENT_CONTROLS_CLOCK,
1568 .clkdm = { .name = "core_l4_clkdm" },
1569 .recalc = &followparent_recalc,
1572 static struct clk mcspi4_fck = {
1573 .name = "mcspi_fck",
1575 .parent = &core_48m_fck,
1576 .prcm_mod = CORE_MOD,
1577 .enable_reg = CM_FCLKEN1,
1578 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1579 .flags = CLOCK_IN_OMAP343X,
1580 .clkdm = { .name = "core_l4_clkdm" },
1581 .recalc = &followparent_recalc,
1584 static struct clk mcspi3_fck = {
1585 .name = "mcspi_fck",
1587 .parent = &core_48m_fck,
1588 .prcm_mod = CORE_MOD,
1589 .enable_reg = CM_FCLKEN1,
1590 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1591 .flags = CLOCK_IN_OMAP343X,
1592 .clkdm = { .name = "core_l4_clkdm" },
1593 .recalc = &followparent_recalc,
1596 static struct clk mcspi2_fck = {
1597 .name = "mcspi_fck",
1599 .parent = &core_48m_fck,
1600 .prcm_mod = CORE_MOD,
1601 .enable_reg = CM_FCLKEN1,
1602 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1603 .flags = CLOCK_IN_OMAP343X,
1604 .clkdm = { .name = "core_l4_clkdm" },
1605 .recalc = &followparent_recalc,
1608 static struct clk mcspi1_fck = {
1609 .name = "mcspi_fck",
1611 .parent = &core_48m_fck,
1612 .prcm_mod = CORE_MOD,
1613 .enable_reg = CM_FCLKEN1,
1614 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1615 .flags = CLOCK_IN_OMAP343X,
1616 .clkdm = { .name = "core_l4_clkdm" },
1617 .recalc = &followparent_recalc,
1620 static struct clk uart2_fck = {
1621 .name = "uart2_fck",
1622 .parent = &core_48m_fck,
1623 .prcm_mod = CORE_MOD,
1624 .enable_reg = CM_FCLKEN1,
1625 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1626 .flags = CLOCK_IN_OMAP343X,
1627 .clkdm = { .name = "core_l4_clkdm" },
1628 .recalc = &followparent_recalc,
1631 static struct clk uart1_fck = {
1632 .name = "uart1_fck",
1633 .parent = &core_48m_fck,
1634 .prcm_mod = CORE_MOD,
1635 .enable_reg = CM_FCLKEN1,
1636 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1637 .flags = CLOCK_IN_OMAP343X,
1638 .clkdm = { .name = "core_l4_clkdm" },
1639 .recalc = &followparent_recalc,
1642 static struct clk fshostusb_fck = {
1643 .name = "fshostusb_fck",
1644 .parent = &core_48m_fck,
1645 .prcm_mod = CORE_MOD,
1646 .enable_reg = CM_FCLKEN1,
1647 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1648 .flags = CLOCK_IN_OMAP3430ES1,
1649 .clkdm = { .name = "core_l4_clkdm" },
1650 .recalc = &followparent_recalc,
1653 /* CORE_12M_FCK based clocks */
1655 static struct clk core_12m_fck = {
1656 .name = "core_12m_fck",
1657 .parent = &omap_12m_fck,
1658 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1659 PARENT_CONTROLS_CLOCK,
1660 .clkdm = { .name = "core_l4_clkdm" },
1661 .recalc = &followparent_recalc,
1664 static struct clk hdq_fck = {
1666 .parent = &core_12m_fck,
1667 .prcm_mod = CORE_MOD,
1668 .enable_reg = CM_FCLKEN1,
1669 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1670 .flags = CLOCK_IN_OMAP343X,
1671 .clkdm = { .name = "core_l4_clkdm" },
1672 .recalc = &followparent_recalc,
1675 /* DPLL3-derived clock */
1677 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1678 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1679 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1680 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1681 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1682 { .div = 6, .val = 6, .flags = RATE_IN_343X },
1683 { .div = 8, .val = 8, .flags = RATE_IN_343X },
1687 static const struct clksel ssi_ssr_clksel[] = {
1688 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1692 static struct clk ssi_ssr_fck = {
1693 .name = "ssi_ssr_fck",
1694 .init = &omap2_init_clksel_parent,
1695 .prcm_mod = CORE_MOD,
1696 .enable_reg = CM_FCLKEN1,
1697 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1698 .clksel_reg = CM_CLKSEL,
1699 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1700 .clksel = ssi_ssr_clksel,
1701 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1702 .clkdm = { .name = "core_l4_clkdm" },
1703 .recalc = &omap2_clksel_recalc,
1706 static struct clk ssi_sst_fck = {
1707 .name = "ssi_sst_fck",
1708 .parent = &ssi_ssr_fck,
1710 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1711 .clkdm = { .name = "core_l4_clkdm" },
1712 .recalc = &omap2_fixed_divisor_recalc,
1717 /* CORE_L3_ICK based clocks */
1720 * XXX must add clk_enable/clk_disable for these if standard code won't
1723 static struct clk core_l3_ick = {
1724 .name = "core_l3_ick",
1726 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1727 PARENT_CONTROLS_CLOCK,
1728 .clkdm = { .name = "core_l3_clkdm" },
1729 .recalc = &followparent_recalc,
1732 static struct clk hsotgusb_ick = {
1733 .name = "hsotgusb_ick",
1734 .parent = &core_l3_ick,
1735 .prcm_mod = CORE_MOD,
1736 .enable_reg = CM_ICLKEN1,
1737 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1738 .flags = CLOCK_IN_OMAP343X,
1739 .clkdm = { .name = "core_l3_clkdm" },
1740 .recalc = &followparent_recalc,
1743 static struct clk sdrc_ick = {
1745 .parent = &core_l3_ick,
1746 .prcm_mod = CORE_MOD,
1747 .enable_reg = CM_ICLKEN1,
1748 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1749 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1750 .clkdm = { .name = "core_l3_clkdm" },
1751 .recalc = &followparent_recalc,
1754 static struct clk gpmc_fck = {
1756 .parent = &core_l3_ick,
1757 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1759 .clkdm = { .name = "core_l3_clkdm" },
1760 .recalc = &followparent_recalc,
1763 /* SECURITY_L3_ICK based clocks */
1765 static struct clk security_l3_ick = {
1766 .name = "security_l3_ick",
1768 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1769 PARENT_CONTROLS_CLOCK,
1770 .clkdm = { .name = "core_l3_clkdm" },
1771 .recalc = &followparent_recalc,
1774 static struct clk pka_ick = {
1776 .parent = &security_l3_ick,
1777 .prcm_mod = CORE_MOD,
1778 .enable_reg = CM_ICLKEN2,
1779 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1780 .flags = CLOCK_IN_OMAP343X,
1781 .clkdm = { .name = "core_l3_clkdm" },
1782 .recalc = &followparent_recalc,
1785 /* CORE_L4_ICK based clocks */
1787 static struct clk core_l4_ick = {
1788 .name = "core_l4_ick",
1790 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1791 PARENT_CONTROLS_CLOCK,
1792 .clkdm = { .name = "core_l4_clkdm" },
1793 .recalc = &followparent_recalc,
1796 static struct clk usbtll_ick = {
1797 .name = "usbtll_ick",
1798 .parent = &core_l4_ick,
1799 .prcm_mod = CORE_MOD,
1800 .enable_reg = CM_ICLKEN3,
1801 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1802 .flags = CLOCK_IN_OMAP3430ES2,
1803 .clkdm = { .name = "core_l4_clkdm" },
1804 .recalc = &followparent_recalc,
1807 static struct clk mmchs3_ick = {
1808 .name = "mmchs_ick",
1810 .parent = &core_l4_ick,
1811 .prcm_mod = CORE_MOD,
1812 .enable_reg = CM_ICLKEN1,
1813 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1814 .flags = CLOCK_IN_OMAP3430ES2,
1815 .clkdm = { .name = "core_l4_clkdm" },
1816 .recalc = &followparent_recalc,
1819 /* Intersystem Communication Registers - chassis mode only */
1820 static struct clk icr_ick = {
1822 .parent = &core_l4_ick,
1823 .prcm_mod = CORE_MOD,
1824 .enable_reg = CM_ICLKEN1,
1825 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1826 .flags = CLOCK_IN_OMAP343X,
1827 .clkdm = { .name = "core_l4_clkdm" },
1828 .recalc = &followparent_recalc,
1831 static struct clk aes2_ick = {
1833 .parent = &core_l4_ick,
1834 .prcm_mod = CORE_MOD,
1835 .enable_reg = CM_ICLKEN1,
1836 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1837 .flags = CLOCK_IN_OMAP343X,
1838 .clkdm = { .name = "core_l4_clkdm" },
1839 .recalc = &followparent_recalc,
1842 static struct clk sha12_ick = {
1843 .name = "sha12_ick",
1844 .parent = &core_l4_ick,
1845 .prcm_mod = CORE_MOD,
1846 .enable_reg = CM_ICLKEN1,
1847 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1848 .flags = CLOCK_IN_OMAP343X,
1849 .clkdm = { .name = "core_l4_clkdm" },
1850 .recalc = &followparent_recalc,
1853 static struct clk des2_ick = {
1855 .parent = &core_l4_ick,
1856 .prcm_mod = CORE_MOD,
1857 .enable_reg = CM_ICLKEN1,
1858 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1859 .flags = CLOCK_IN_OMAP343X,
1860 .clkdm = { .name = "core_l4_clkdm" },
1861 .recalc = &followparent_recalc,
1864 static struct clk mmchs2_ick = {
1865 .name = "mmchs_ick",
1867 .parent = &core_l4_ick,
1868 .prcm_mod = CORE_MOD,
1869 .enable_reg = CM_ICLKEN1,
1870 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1871 .flags = CLOCK_IN_OMAP343X,
1872 .clkdm = { .name = "core_l4_clkdm" },
1873 .recalc = &followparent_recalc,
1876 static struct clk mmchs1_ick = {
1877 .name = "mmchs_ick",
1879 .parent = &core_l4_ick,
1880 .prcm_mod = CORE_MOD,
1881 .enable_reg = CM_ICLKEN1,
1882 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1883 .flags = CLOCK_IN_OMAP343X,
1884 .clkdm = { .name = "core_l4_clkdm" },
1885 .recalc = &followparent_recalc,
1888 static struct clk mspro_ick = {
1889 .name = "mspro_ick",
1890 .parent = &core_l4_ick,
1891 .prcm_mod = CORE_MOD,
1892 .enable_reg = CM_ICLKEN1,
1893 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1894 .flags = CLOCK_IN_OMAP343X,
1895 .clkdm = { .name = "core_l4_clkdm" },
1896 .recalc = &followparent_recalc,
1899 static struct clk hdq_ick = {
1901 .parent = &core_l4_ick,
1902 .prcm_mod = CORE_MOD,
1903 .enable_reg = CM_ICLKEN1,
1904 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1905 .flags = CLOCK_IN_OMAP343X,
1906 .clkdm = { .name = "core_l4_clkdm" },
1907 .recalc = &followparent_recalc,
1910 static struct clk mcspi4_ick = {
1911 .name = "mcspi_ick",
1913 .parent = &core_l4_ick,
1914 .prcm_mod = CORE_MOD,
1915 .enable_reg = CM_ICLKEN1,
1916 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1917 .flags = CLOCK_IN_OMAP343X,
1918 .clkdm = { .name = "core_l4_clkdm" },
1919 .recalc = &followparent_recalc,
1922 static struct clk mcspi3_ick = {
1923 .name = "mcspi_ick",
1925 .parent = &core_l4_ick,
1926 .prcm_mod = CORE_MOD,
1927 .enable_reg = CM_ICLKEN1,
1928 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1929 .flags = CLOCK_IN_OMAP343X,
1930 .clkdm = { .name = "core_l4_clkdm" },
1931 .recalc = &followparent_recalc,
1934 static struct clk mcspi2_ick = {
1935 .name = "mcspi_ick",
1937 .parent = &core_l4_ick,
1938 .prcm_mod = CORE_MOD,
1939 .enable_reg = CM_ICLKEN1,
1940 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1941 .flags = CLOCK_IN_OMAP343X,
1942 .clkdm = { .name = "core_l4_clkdm" },
1943 .recalc = &followparent_recalc,
1946 static struct clk mcspi1_ick = {
1947 .name = "mcspi_ick",
1949 .parent = &core_l4_ick,
1950 .prcm_mod = CORE_MOD,
1951 .enable_reg = CM_ICLKEN1,
1952 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1953 .flags = CLOCK_IN_OMAP343X,
1954 .clkdm = { .name = "core_l4_clkdm" },
1955 .recalc = &followparent_recalc,
1958 static struct clk i2c3_ick = {
1961 .parent = &core_l4_ick,
1962 .prcm_mod = CORE_MOD,
1963 .enable_reg = CM_ICLKEN1,
1964 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1965 .flags = CLOCK_IN_OMAP343X,
1966 .clkdm = { .name = "core_l4_clkdm" },
1967 .recalc = &followparent_recalc,
1970 static struct clk i2c2_ick = {
1973 .parent = &core_l4_ick,
1974 .prcm_mod = CORE_MOD,
1975 .enable_reg = CM_ICLKEN1,
1976 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1977 .flags = CLOCK_IN_OMAP343X,
1978 .clkdm = { .name = "core_l4_clkdm" },
1979 .recalc = &followparent_recalc,
1982 static struct clk i2c1_ick = {
1985 .parent = &core_l4_ick,
1986 .prcm_mod = CORE_MOD,
1987 .enable_reg = CM_ICLKEN1,
1988 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1989 .flags = CLOCK_IN_OMAP343X,
1990 .clkdm = { .name = "core_l4_clkdm" },
1991 .recalc = &followparent_recalc,
1994 static struct clk uart2_ick = {
1995 .name = "uart2_ick",
1996 .parent = &core_l4_ick,
1997 .prcm_mod = CORE_MOD,
1998 .enable_reg = CM_ICLKEN1,
1999 .enable_bit = OMAP3430_EN_UART2_SHIFT,
2000 .flags = CLOCK_IN_OMAP343X,
2001 .clkdm = { .name = "core_l4_clkdm" },
2002 .recalc = &followparent_recalc,
2005 static struct clk uart1_ick = {
2006 .name = "uart1_ick",
2007 .parent = &core_l4_ick,
2008 .prcm_mod = CORE_MOD,
2009 .enable_reg = CM_ICLKEN1,
2010 .enable_bit = OMAP3430_EN_UART1_SHIFT,
2011 .flags = CLOCK_IN_OMAP343X,
2012 .clkdm = { .name = "core_l4_clkdm" },
2013 .recalc = &followparent_recalc,
2016 static struct clk gpt11_ick = {
2017 .name = "gpt11_ick",
2018 .parent = &core_l4_ick,
2019 .prcm_mod = CORE_MOD,
2020 .enable_reg = CM_ICLKEN1,
2021 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
2022 .flags = CLOCK_IN_OMAP343X,
2023 .clkdm = { .name = "core_l4_clkdm" },
2024 .recalc = &followparent_recalc,
2027 static struct clk gpt10_ick = {
2028 .name = "gpt10_ick",
2029 .parent = &core_l4_ick,
2030 .prcm_mod = CORE_MOD,
2031 .enable_reg = CM_ICLKEN1,
2032 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
2033 .flags = CLOCK_IN_OMAP343X,
2034 .clkdm = { .name = "core_l4_clkdm" },
2035 .recalc = &followparent_recalc,
2038 static struct clk mcbsp5_ick = {
2039 .name = "mcbsp_ick",
2041 .parent = &core_l4_ick,
2042 .prcm_mod = CORE_MOD,
2043 .enable_reg = CM_ICLKEN1,
2044 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
2045 .flags = CLOCK_IN_OMAP343X,
2046 .clkdm = { .name = "core_l4_clkdm" },
2047 .recalc = &followparent_recalc,
2050 static struct clk mcbsp1_ick = {
2051 .name = "mcbsp_ick",
2053 .parent = &core_l4_ick,
2054 .prcm_mod = CORE_MOD,
2055 .enable_reg = CM_ICLKEN1,
2056 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2057 .flags = CLOCK_IN_OMAP343X,
2058 .clkdm = { .name = "core_l4_clkdm" },
2059 .recalc = &followparent_recalc,
2062 static struct clk fac_ick = {
2064 .parent = &core_l4_ick,
2065 .prcm_mod = CORE_MOD,
2066 .enable_reg = CM_ICLKEN1,
2067 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
2068 .flags = CLOCK_IN_OMAP3430ES1,
2069 .clkdm = { .name = "core_l4_clkdm" },
2070 .recalc = &followparent_recalc,
2073 static struct clk mailboxes_ick = {
2074 .name = "mailboxes_ick",
2075 .parent = &core_l4_ick,
2076 .prcm_mod = CORE_MOD,
2077 .enable_reg = CM_ICLKEN1,
2078 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2079 .flags = CLOCK_IN_OMAP343X,
2080 .clkdm = { .name = "core_l4_clkdm" },
2081 .recalc = &followparent_recalc,
2084 static struct clk omapctrl_ick = {
2085 .name = "omapctrl_ick",
2086 .parent = &core_l4_ick,
2087 .prcm_mod = CORE_MOD,
2088 .enable_reg = CM_ICLKEN1,
2089 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2090 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
2091 .clkdm = { .name = "core_l4_clkdm" },
2092 .recalc = &followparent_recalc,
2095 /* SSI_L4_ICK based clocks */
2097 static struct clk ssi_l4_ick = {
2098 .name = "ssi_l4_ick",
2100 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2101 PARENT_CONTROLS_CLOCK,
2102 .clkdm = { .name = "core_l4_clkdm" },
2103 .recalc = &followparent_recalc,
2106 static struct clk ssi_ick = {
2108 .parent = &ssi_l4_ick,
2109 .prcm_mod = CORE_MOD,
2110 .enable_reg = CM_ICLKEN1,
2111 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2112 .flags = CLOCK_IN_OMAP343X,
2113 .clkdm = { .name = "core_l4_clkdm" },
2114 .recalc = &followparent_recalc,
2117 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2118 * but l4_ick makes more sense to me */
2120 static const struct clksel usb_l4_clksel[] = {
2121 { .parent = &l4_ick, .rates = div2_rates },
2125 static struct clk usb_l4_ick = {
2126 .name = "usb_l4_ick",
2128 .prcm_mod = CORE_MOD,
2129 .init = &omap2_init_clksel_parent,
2130 .enable_reg = CM_ICLKEN1,
2131 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2132 .clksel_reg = CM_CLKSEL,
2133 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2134 .clksel = usb_l4_clksel,
2135 .flags = CLOCK_IN_OMAP3430ES1,
2136 .clkdm = { .name = "core_l4_clkdm" },
2137 .recalc = &omap2_clksel_recalc,
2140 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2142 /* SECURITY_L4_ICK2 based clocks */
2144 static struct clk security_l4_ick2 = {
2145 .name = "security_l4_ick2",
2147 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2148 PARENT_CONTROLS_CLOCK,
2149 .clkdm = { .name = "core_l4_clkdm" },
2150 .recalc = &followparent_recalc,
2153 static struct clk aes1_ick = {
2155 .parent = &security_l4_ick2,
2156 .prcm_mod = CORE_MOD,
2157 .enable_reg = CM_ICLKEN2,
2158 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2159 .flags = CLOCK_IN_OMAP343X,
2160 .clkdm = { .name = "core_l4_clkdm" },
2161 .recalc = &followparent_recalc,
2164 static struct clk rng_ick = {
2166 .parent = &security_l4_ick2,
2167 .prcm_mod = CORE_MOD,
2168 .enable_reg = CM_ICLKEN2,
2169 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2170 .flags = CLOCK_IN_OMAP343X,
2171 .clkdm = { .name = "core_l4_clkdm" },
2172 .recalc = &followparent_recalc,
2175 static struct clk sha11_ick = {
2176 .name = "sha11_ick",
2177 .parent = &security_l4_ick2,
2178 .prcm_mod = CORE_MOD,
2179 .enable_reg = CM_ICLKEN2,
2180 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2181 .flags = CLOCK_IN_OMAP343X,
2182 .clkdm = { .name = "core_l4_clkdm" },
2183 .recalc = &followparent_recalc,
2186 static struct clk des1_ick = {
2188 .parent = &security_l4_ick2,
2189 .prcm_mod = CORE_MOD,
2190 .enable_reg = CM_ICLKEN2,
2191 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2192 .flags = CLOCK_IN_OMAP343X,
2193 .clkdm = { .name = "core_l4_clkdm" },
2194 .recalc = &followparent_recalc,
2198 static struct clk dss1_alwon_fck = {
2199 .name = "dss1_alwon_fck",
2200 .parent = &dpll4_m4x2_ck,
2201 .prcm_mod = OMAP3430_DSS_MOD,
2202 .enable_reg = CM_FCLKEN,
2203 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2204 .flags = CLOCK_IN_OMAP343X,
2205 .clkdm = { .name = "dss_clkdm" },
2206 .recalc = &followparent_recalc,
2209 static struct clk dss_tv_fck = {
2210 .name = "dss_tv_fck",
2211 .parent = &omap_54m_fck,
2212 .prcm_mod = OMAP3430_DSS_MOD,
2213 .enable_reg = CM_FCLKEN,
2214 .enable_bit = OMAP3430_EN_TV_SHIFT,
2215 .flags = CLOCK_IN_OMAP343X,
2216 .clkdm = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */
2217 .recalc = &followparent_recalc,
2220 static struct clk dss_96m_fck = {
2221 .name = "dss_96m_fck",
2222 .parent = &omap_96m_fck,
2223 .prcm_mod = OMAP3430_DSS_MOD,
2224 .enable_reg = CM_FCLKEN,
2225 .enable_bit = OMAP3430_EN_TV_SHIFT,
2226 .flags = CLOCK_IN_OMAP343X,
2227 .clkdm = { .name = "dss_clkdm" },
2228 .recalc = &followparent_recalc,
2231 static struct clk dss2_alwon_fck = {
2232 .name = "dss2_alwon_fck",
2234 .prcm_mod = OMAP3430_DSS_MOD,
2235 .enable_reg = CM_FCLKEN,
2236 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2237 .flags = CLOCK_IN_OMAP343X,
2238 .clkdm = { .name = "dss_clkdm" },
2239 .recalc = &followparent_recalc,
2242 static struct clk dss_ick = {
2243 /* Handles both L3 and L4 clocks */
2246 .prcm_mod = OMAP3430_DSS_MOD,
2247 .enable_reg = CM_ICLKEN,
2248 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2249 .flags = CLOCK_IN_OMAP343X,
2250 .clkdm = { .name = "dss_clkdm" },
2251 .recalc = &followparent_recalc,
2256 static struct clk cam_mclk = {
2258 .parent = &dpll4_m5x2_ck,
2259 .prcm_mod = OMAP3430_CAM_MOD,
2260 .enable_reg = CM_FCLKEN,
2261 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2262 .flags = CLOCK_IN_OMAP343X,
2263 .clkdm = { .name = "cam_clkdm" },
2264 .recalc = &followparent_recalc,
2267 static struct clk cam_ick = {
2268 /* Handles both L3 and L4 clocks */
2271 .prcm_mod = OMAP3430_CAM_MOD,
2272 .enable_reg = CM_ICLKEN,
2273 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2274 .flags = CLOCK_IN_OMAP343X,
2275 .clkdm = { .name = "cam_clkdm" },
2276 .recalc = &followparent_recalc,
2279 static struct clk csi2_96m_fck = {
2280 .name = "csi2_96m_fck",
2281 .parent = &core_96m_fck,
2282 .prcm_mod = OMAP3430_CAM_MOD,
2283 .enable_reg = CM_FCLKEN,
2284 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
2285 .flags = CLOCK_IN_OMAP343X,
2286 .clkdm = { .name = "cam_clkdm" },
2287 .recalc = &followparent_recalc,
2290 /* USBHOST - 3430ES2 only */
2292 static struct clk usbhost_120m_fck = {
2293 .name = "usbhost_120m_fck",
2294 .parent = &dpll5_m2_ck,
2295 .prcm_mod = OMAP3430ES2_USBHOST_MOD,
2296 .enable_reg = CM_FCLKEN,
2297 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2298 .flags = CLOCK_IN_OMAP3430ES2,
2299 .clkdm = { .name = "usbhost_clkdm" },
2300 .recalc = &followparent_recalc,
2303 static struct clk usbhost_48m_fck = {
2304 .name = "usbhost_48m_fck",
2305 .parent = &omap_48m_fck,
2306 .prcm_mod = OMAP3430ES2_USBHOST_MOD,
2307 .enable_reg = CM_FCLKEN,
2308 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2309 .flags = CLOCK_IN_OMAP3430ES2,
2310 .clkdm = { .name = "usbhost_clkdm" },
2311 .recalc = &followparent_recalc,
2314 static struct clk usbhost_ick = {
2315 /* Handles both L3 and L4 clocks */
2316 .name = "usbhost_ick",
2318 .prcm_mod = OMAP3430ES2_USBHOST_MOD,
2319 .enable_reg = CM_ICLKEN,
2320 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2321 .flags = CLOCK_IN_OMAP3430ES2,
2322 .clkdm = { .name = "usbhost_clkdm" },
2323 .recalc = &followparent_recalc,
2328 static const struct clksel_rate usim_96m_rates[] = {
2329 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2330 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2331 { .div = 8, .val = 5, .flags = RATE_IN_343X },
2332 { .div = 10, .val = 6, .flags = RATE_IN_343X },
2336 static const struct clksel_rate usim_120m_rates[] = {
2337 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
2338 { .div = 8, .val = 8, .flags = RATE_IN_343X },
2339 { .div = 16, .val = 9, .flags = RATE_IN_343X },
2340 { .div = 20, .val = 10, .flags = RATE_IN_343X },
2344 static const struct clksel usim_clksel[] = {
2345 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2346 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
2347 { .parent = &sys_ck, .rates = div2_rates },
2352 static struct clk usim_fck = {
2354 .prcm_mod = WKUP_MOD,
2355 .init = &omap2_init_clksel_parent,
2356 .enable_reg = CM_FCLKEN,
2357 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2358 .clksel_reg = CM_CLKSEL,
2359 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2360 .clksel = usim_clksel,
2361 .flags = CLOCK_IN_OMAP3430ES2,
2362 .clkdm = { .name = "prm_clkdm" },
2363 .recalc = &omap2_clksel_recalc,
2366 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2367 static struct clk gpt1_fck = {
2369 .prcm_mod = WKUP_MOD,
2370 .init = &omap2_init_clksel_parent,
2371 .enable_reg = CM_FCLKEN,
2372 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2373 .clksel_reg = CM_CLKSEL,
2374 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2375 .clksel = omap343x_gpt_clksel,
2376 .flags = CLOCK_IN_OMAP343X,
2377 .clkdm = { .name = "prm_clkdm" },
2378 .recalc = &omap2_clksel_recalc,
2381 static struct clk wkup_32k_fck = {
2382 .name = "wkup_32k_fck",
2383 .parent = &omap_32k_fck,
2384 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2385 .clkdm = { .name = "prm_clkdm" },
2386 .recalc = &followparent_recalc,
2389 static struct clk gpio1_fck = {
2390 .name = "gpio1_fck",
2391 .parent = &wkup_32k_fck,
2392 .prcm_mod = WKUP_MOD,
2393 .enable_reg = CM_FCLKEN,
2394 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2395 .flags = CLOCK_IN_OMAP343X,
2396 .clkdm = { .name = "prm_clkdm" },
2397 .recalc = &followparent_recalc,
2400 static struct clk wdt2_fck = {
2402 .parent = &wkup_32k_fck,
2403 .prcm_mod = WKUP_MOD,
2404 .enable_reg = CM_FCLKEN,
2405 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2406 .flags = CLOCK_IN_OMAP343X,
2407 .clkdm = { .name = "prm_clkdm" },
2408 .recalc = &followparent_recalc,
2411 static struct clk wkup_l4_ick = {
2412 .name = "wkup_l4_ick",
2414 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2415 .clkdm = { .name = "prm_clkdm" },
2416 .recalc = &followparent_recalc,
2420 /* Never specifically named in the TRM, so we have to infer a likely name */
2421 static struct clk usim_ick = {
2423 .parent = &wkup_l4_ick,
2424 .prcm_mod = WKUP_MOD,
2425 .enable_reg = CM_ICLKEN,
2426 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2427 .flags = CLOCK_IN_OMAP3430ES2,
2428 .clkdm = { .name = "prm_clkdm" },
2429 .recalc = &followparent_recalc,
2432 static struct clk wdt2_ick = {
2434 .parent = &wkup_l4_ick,
2435 .prcm_mod = WKUP_MOD,
2436 .enable_reg = CM_ICLKEN,
2437 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2438 .flags = CLOCK_IN_OMAP343X,
2439 .clkdm = { .name = "prm_clkdm" },
2440 .recalc = &followparent_recalc,
2443 static struct clk wdt1_ick = {
2445 .parent = &wkup_l4_ick,
2446 .prcm_mod = WKUP_MOD,
2447 .enable_reg = CM_ICLKEN,
2448 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2449 .flags = CLOCK_IN_OMAP343X,
2450 .clkdm = { .name = "prm_clkdm" },
2451 .recalc = &followparent_recalc,
2454 static struct clk gpio1_ick = {
2455 .name = "gpio1_ick",
2456 .parent = &wkup_l4_ick,
2457 .prcm_mod = WKUP_MOD,
2458 .enable_reg = CM_ICLKEN,
2459 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2460 .flags = CLOCK_IN_OMAP343X,
2461 .clkdm = { .name = "prm_clkdm" },
2462 .recalc = &followparent_recalc,
2465 static struct clk omap_32ksync_ick = {
2466 .name = "omap_32ksync_ick",
2467 .parent = &wkup_l4_ick,
2468 .prcm_mod = WKUP_MOD,
2469 .enable_reg = CM_ICLKEN,
2470 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2471 .flags = CLOCK_IN_OMAP343X,
2472 .clkdm = { .name = "prm_clkdm" },
2473 .recalc = &followparent_recalc,
2476 static struct clk gpt12_ick = {
2477 .name = "gpt12_ick",
2478 .parent = &wkup_l4_ick,
2479 .prcm_mod = WKUP_MOD,
2480 .enable_reg = CM_ICLKEN,
2481 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2482 .flags = CLOCK_IN_OMAP343X,
2483 .clkdm = { .name = "prm_clkdm" },
2484 .recalc = &followparent_recalc,
2487 static struct clk gpt1_ick = {
2489 .parent = &wkup_l4_ick,
2490 .prcm_mod = WKUP_MOD,
2491 .enable_reg = CM_ICLKEN,
2492 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2493 .flags = CLOCK_IN_OMAP343X,
2494 .clkdm = { .name = "prm_clkdm" },
2495 .recalc = &followparent_recalc,
2500 /* PER clock domain */
2502 static struct clk per_96m_fck = {
2503 .name = "per_96m_fck",
2504 .parent = &omap_96m_alwon_fck,
2505 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2506 PARENT_CONTROLS_CLOCK,
2507 .clkdm = { .name = "per_clkdm" },
2508 .recalc = &followparent_recalc,
2511 static struct clk per_48m_fck = {
2512 .name = "per_48m_fck",
2513 .parent = &omap_48m_fck,
2514 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2515 PARENT_CONTROLS_CLOCK,
2516 .clkdm = { .name = "per_clkdm" },
2517 .recalc = &followparent_recalc,
2520 static struct clk uart3_fck = {
2521 .name = "uart3_fck",
2522 .parent = &per_48m_fck,
2523 .prcm_mod = OMAP3430_PER_MOD,
2524 .enable_reg = CM_FCLKEN,
2525 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2526 .flags = CLOCK_IN_OMAP343X,
2527 .clkdm = { .name = "per_clkdm" },
2528 .recalc = &followparent_recalc,
2531 static struct clk gpt2_fck = {
2533 .prcm_mod = OMAP3430_PER_MOD,
2534 .init = &omap2_init_clksel_parent,
2535 .enable_reg = CM_FCLKEN,
2536 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2537 .clksel_reg = CM_CLKSEL,
2538 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2539 .clksel = omap343x_gpt_clksel,
2540 .flags = CLOCK_IN_OMAP343X,
2541 .clkdm = { .name = "per_clkdm" },
2542 .recalc = &omap2_clksel_recalc,
2545 static struct clk gpt3_fck = {
2547 .prcm_mod = OMAP3430_PER_MOD,
2548 .init = &omap2_init_clksel_parent,
2549 .enable_reg = CM_FCLKEN,
2550 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2551 .clksel_reg = CM_CLKSEL,
2552 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2553 .clksel = omap343x_gpt_clksel,
2554 .flags = CLOCK_IN_OMAP343X,
2555 .clkdm = { .name = "per_clkdm" },
2556 .recalc = &omap2_clksel_recalc,
2559 static struct clk gpt4_fck = {
2561 .prcm_mod = OMAP3430_PER_MOD,
2562 .init = &omap2_init_clksel_parent,
2563 .enable_reg = CM_FCLKEN,
2564 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2565 .clksel_reg = CM_CLKSEL,
2566 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2567 .clksel = omap343x_gpt_clksel,
2568 .flags = CLOCK_IN_OMAP343X,
2569 .clkdm = { .name = "per_clkdm" },
2570 .recalc = &omap2_clksel_recalc,
2573 static struct clk gpt5_fck = {
2575 .prcm_mod = OMAP3430_PER_MOD,
2576 .init = &omap2_init_clksel_parent,
2577 .enable_reg = CM_FCLKEN,
2578 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2579 .clksel_reg = CM_CLKSEL,
2580 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2581 .clksel = omap343x_gpt_clksel,
2582 .flags = CLOCK_IN_OMAP343X,
2583 .clkdm = { .name = "per_clkdm" },
2584 .recalc = &omap2_clksel_recalc,
2587 static struct clk gpt6_fck = {
2589 .prcm_mod = OMAP3430_PER_MOD,
2590 .init = &omap2_init_clksel_parent,
2591 .enable_reg = CM_FCLKEN,
2592 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2593 .clksel_reg = CM_CLKSEL,
2594 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2595 .clksel = omap343x_gpt_clksel,
2596 .flags = CLOCK_IN_OMAP343X,
2597 .clkdm = { .name = "per_clkdm" },
2598 .recalc = &omap2_clksel_recalc,
2601 static struct clk gpt7_fck = {
2603 .prcm_mod = OMAP3430_PER_MOD,
2604 .init = &omap2_init_clksel_parent,
2605 .enable_reg = CM_FCLKEN,
2606 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2607 .clksel_reg = CM_CLKSEL,
2608 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2609 .clksel = omap343x_gpt_clksel,
2610 .flags = CLOCK_IN_OMAP343X,
2611 .clkdm = { .name = "per_clkdm" },
2612 .recalc = &omap2_clksel_recalc,
2615 static struct clk gpt8_fck = {
2617 .prcm_mod = OMAP3430_PER_MOD,
2618 .init = &omap2_init_clksel_parent,
2619 .enable_reg = CM_FCLKEN,
2620 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2621 .clksel_reg = CM_CLKSEL,
2622 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2623 .clksel = omap343x_gpt_clksel,
2624 .flags = CLOCK_IN_OMAP343X,
2625 .clkdm = { .name = "per_clkdm" },
2626 .recalc = &omap2_clksel_recalc,
2629 static struct clk gpt9_fck = {
2631 .prcm_mod = OMAP3430_PER_MOD,
2632 .init = &omap2_init_clksel_parent,
2633 .enable_reg = CM_FCLKEN,
2634 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2635 .clksel_reg = CM_CLKSEL,
2636 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2637 .clksel = omap343x_gpt_clksel,
2638 .flags = CLOCK_IN_OMAP343X,
2639 .clkdm = { .name = "per_clkdm" },
2640 .recalc = &omap2_clksel_recalc,
2643 static struct clk per_32k_alwon_fck = {
2644 .name = "per_32k_alwon_fck",
2645 .parent = &omap_32k_fck,
2646 .clkdm = { .name = "per_clkdm" },
2647 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2648 .recalc = &followparent_recalc,
2651 static struct clk gpio6_fck = {
2652 .name = "gpio6_fck",
2653 .parent = &per_32k_alwon_fck,
2654 .prcm_mod = OMAP3430_PER_MOD,
2655 .enable_reg = CM_FCLKEN,
2656 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2657 .flags = CLOCK_IN_OMAP343X,
2658 .clkdm = { .name = "per_clkdm" },
2659 .recalc = &followparent_recalc,
2662 static struct clk gpio5_fck = {
2663 .name = "gpio5_fck",
2664 .parent = &per_32k_alwon_fck,
2665 .prcm_mod = OMAP3430_PER_MOD,
2666 .enable_reg = CM_FCLKEN,
2667 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2668 .flags = CLOCK_IN_OMAP343X,
2669 .clkdm = { .name = "per_clkdm" },
2670 .recalc = &followparent_recalc,
2673 static struct clk gpio4_fck = {
2674 .name = "gpio4_fck",
2675 .parent = &per_32k_alwon_fck,
2676 .prcm_mod = OMAP3430_PER_MOD,
2677 .enable_reg = CM_FCLKEN,
2678 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2679 .flags = CLOCK_IN_OMAP343X,
2680 .clkdm = { .name = "per_clkdm" },
2681 .recalc = &followparent_recalc,
2684 static struct clk gpio3_fck = {
2685 .name = "gpio3_fck",
2686 .parent = &per_32k_alwon_fck,
2687 .prcm_mod = OMAP3430_PER_MOD,
2688 .enable_reg = CM_FCLKEN,
2689 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2690 .flags = CLOCK_IN_OMAP343X,
2691 .clkdm = { .name = "per_clkdm" },
2692 .recalc = &followparent_recalc,
2695 static struct clk gpio2_fck = {
2696 .name = "gpio2_fck",
2697 .parent = &per_32k_alwon_fck,
2698 .prcm_mod = OMAP3430_PER_MOD,
2699 .enable_reg = CM_FCLKEN,
2700 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2701 .flags = CLOCK_IN_OMAP343X,
2702 .clkdm = { .name = "per_clkdm" },
2703 .recalc = &followparent_recalc,
2706 static struct clk wdt3_fck = {
2708 .parent = &per_32k_alwon_fck,
2709 .prcm_mod = OMAP3430_PER_MOD,
2710 .enable_reg = CM_FCLKEN,
2711 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2712 .flags = CLOCK_IN_OMAP343X,
2713 .clkdm = { .name = "per_clkdm" },
2714 .recalc = &followparent_recalc,
2717 static struct clk per_l4_ick = {
2718 .name = "per_l4_ick",
2720 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2721 PARENT_CONTROLS_CLOCK,
2722 .clkdm = { .name = "per_clkdm" },
2723 .recalc = &followparent_recalc,
2726 static struct clk gpio6_ick = {
2727 .name = "gpio6_ick",
2728 .parent = &per_l4_ick,
2729 .prcm_mod = OMAP3430_PER_MOD,
2730 .enable_reg = CM_ICLKEN,
2731 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2732 .flags = CLOCK_IN_OMAP343X,
2733 .clkdm = { .name = "per_clkdm" },
2734 .recalc = &followparent_recalc,
2737 static struct clk gpio5_ick = {
2738 .name = "gpio5_ick",
2739 .parent = &per_l4_ick,
2740 .prcm_mod = OMAP3430_PER_MOD,
2741 .enable_reg = CM_ICLKEN,
2742 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2743 .flags = CLOCK_IN_OMAP343X,
2744 .clkdm = { .name = "per_clkdm" },
2745 .recalc = &followparent_recalc,
2748 static struct clk gpio4_ick = {
2749 .name = "gpio4_ick",
2750 .parent = &per_l4_ick,
2751 .prcm_mod = OMAP3430_PER_MOD,
2752 .enable_reg = CM_ICLKEN,
2753 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2754 .flags = CLOCK_IN_OMAP343X,
2755 .clkdm = { .name = "per_clkdm" },
2756 .recalc = &followparent_recalc,
2759 static struct clk gpio3_ick = {
2760 .name = "gpio3_ick",
2761 .parent = &per_l4_ick,
2762 .prcm_mod = OMAP3430_PER_MOD,
2763 .enable_reg = CM_ICLKEN,
2764 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2765 .flags = CLOCK_IN_OMAP343X,
2766 .clkdm = { .name = "per_clkdm" },
2767 .recalc = &followparent_recalc,
2770 static struct clk gpio2_ick = {
2771 .name = "gpio2_ick",
2772 .parent = &per_l4_ick,
2773 .prcm_mod = OMAP3430_PER_MOD,
2774 .enable_reg = CM_ICLKEN,
2775 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2776 .flags = CLOCK_IN_OMAP343X,
2777 .clkdm = { .name = "per_clkdm" },
2778 .recalc = &followparent_recalc,
2781 static struct clk wdt3_ick = {
2783 .parent = &per_l4_ick,
2784 .prcm_mod = OMAP3430_PER_MOD,
2785 .enable_reg = CM_ICLKEN,
2786 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2787 .flags = CLOCK_IN_OMAP343X,
2788 .clkdm = { .name = "per_clkdm" },
2789 .recalc = &followparent_recalc,
2792 static struct clk uart3_ick = {
2793 .name = "uart3_ick",
2794 .parent = &per_l4_ick,
2795 .prcm_mod = OMAP3430_PER_MOD,
2796 .enable_reg = CM_ICLKEN,
2797 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2798 .flags = CLOCK_IN_OMAP343X,
2799 .clkdm = { .name = "per_clkdm" },
2800 .recalc = &followparent_recalc,
2803 static struct clk gpt9_ick = {
2805 .parent = &per_l4_ick,
2806 .prcm_mod = OMAP3430_PER_MOD,
2807 .enable_reg = CM_ICLKEN,
2808 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2809 .flags = CLOCK_IN_OMAP343X,
2810 .clkdm = { .name = "per_clkdm" },
2811 .recalc = &followparent_recalc,
2814 static struct clk gpt8_ick = {
2816 .parent = &per_l4_ick,
2817 .prcm_mod = OMAP3430_PER_MOD,
2818 .enable_reg = CM_ICLKEN,
2819 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2820 .flags = CLOCK_IN_OMAP343X,
2821 .clkdm = { .name = "per_clkdm" },
2822 .recalc = &followparent_recalc,
2825 static struct clk gpt7_ick = {
2827 .parent = &per_l4_ick,
2828 .prcm_mod = OMAP3430_PER_MOD,
2829 .enable_reg = CM_ICLKEN,
2830 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2831 .flags = CLOCK_IN_OMAP343X,
2832 .clkdm = { .name = "per_clkdm" },
2833 .recalc = &followparent_recalc,
2836 static struct clk gpt6_ick = {
2838 .parent = &per_l4_ick,
2839 .prcm_mod = OMAP3430_PER_MOD,
2840 .enable_reg = CM_ICLKEN,
2841 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2842 .flags = CLOCK_IN_OMAP343X,
2843 .clkdm = { .name = "per_clkdm" },
2844 .recalc = &followparent_recalc,
2847 static struct clk gpt5_ick = {
2849 .parent = &per_l4_ick,
2850 .prcm_mod = OMAP3430_PER_MOD,
2851 .enable_reg = CM_ICLKEN,
2852 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2853 .flags = CLOCK_IN_OMAP343X,
2854 .clkdm = { .name = "per_clkdm" },
2855 .recalc = &followparent_recalc,
2858 static struct clk gpt4_ick = {
2860 .parent = &per_l4_ick,
2861 .prcm_mod = OMAP3430_PER_MOD,
2862 .enable_reg = CM_ICLKEN,
2863 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2864 .flags = CLOCK_IN_OMAP343X,
2865 .clkdm = { .name = "per_clkdm" },
2866 .recalc = &followparent_recalc,
2869 static struct clk gpt3_ick = {
2871 .parent = &per_l4_ick,
2872 .prcm_mod = OMAP3430_PER_MOD,
2873 .enable_reg = CM_ICLKEN,
2874 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2875 .flags = CLOCK_IN_OMAP343X,
2876 .clkdm = { .name = "per_clkdm" },
2877 .recalc = &followparent_recalc,
2880 static struct clk gpt2_ick = {
2882 .parent = &per_l4_ick,
2883 .prcm_mod = OMAP3430_PER_MOD,
2884 .enable_reg = CM_ICLKEN,
2885 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2886 .flags = CLOCK_IN_OMAP343X,
2887 .clkdm = { .name = "per_clkdm" },
2888 .recalc = &followparent_recalc,
2891 static struct clk mcbsp2_ick = {
2892 .name = "mcbsp_ick",
2894 .parent = &per_l4_ick,
2895 .prcm_mod = OMAP3430_PER_MOD,
2896 .enable_reg = CM_ICLKEN,
2897 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2898 .flags = CLOCK_IN_OMAP343X,
2899 .clkdm = { .name = "per_clkdm" },
2900 .recalc = &followparent_recalc,
2903 static struct clk mcbsp3_ick = {
2904 .name = "mcbsp_ick",
2906 .parent = &per_l4_ick,
2907 .prcm_mod = OMAP3430_PER_MOD,
2908 .enable_reg = CM_ICLKEN,
2909 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2910 .flags = CLOCK_IN_OMAP343X,
2911 .clkdm = { .name = "per_clkdm" },
2912 .recalc = &followparent_recalc,
2915 static struct clk mcbsp4_ick = {
2916 .name = "mcbsp_ick",
2918 .parent = &per_l4_ick,
2919 .prcm_mod = OMAP3430_PER_MOD,
2920 .enable_reg = CM_ICLKEN,
2921 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2922 .flags = CLOCK_IN_OMAP343X,
2923 .clkdm = { .name = "per_clkdm" },
2924 .recalc = &followparent_recalc,
2927 static const struct clksel mcbsp_234_clksel[] = {
2928 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2929 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2933 static struct clk mcbsp2_src_fck = {
2934 .name = "mcbsp_src_fck",
2936 .prcm_mod = CLK_REG_IN_SCM,
2937 .init = &omap2_init_clksel_parent,
2938 .clksel_reg = OMAP2_CONTROL_DEVCONF0,
2939 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2940 .clksel = mcbsp_234_clksel,
2941 .flags = CLOCK_IN_OMAP343X,
2942 .clkdm = { .name = "per_clkdm" },
2943 .recalc = &omap2_clksel_recalc,
2946 static struct clk mcbsp2_fck = {
2947 .name = "mcbsp_fck",
2949 .parent = &mcbsp2_src_fck,
2950 .prcm_mod = OMAP3430_PER_MOD,
2951 .enable_reg = CM_FCLKEN,
2952 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2953 .flags = CLOCK_IN_OMAP343X,
2954 .clkdm = { .name = "per_clkdm" },
2955 .recalc = &omap2_clksel_recalc,
2958 static struct clk mcbsp3_src_fck = {
2959 .name = "mcbsp_src_fck",
2961 .prcm_mod = CLK_REG_IN_SCM,
2962 .init = &omap2_init_clksel_parent,
2963 .clksel_reg = OMAP343X_CONTROL_DEVCONF1,
2964 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2965 .clksel = mcbsp_234_clksel,
2966 .flags = CLOCK_IN_OMAP343X,
2967 .clkdm = { .name = "per_clkdm" },
2968 .recalc = &omap2_clksel_recalc,
2971 static struct clk mcbsp3_fck = {
2972 .name = "mcbsp_fck",
2974 .parent = &mcbsp3_src_fck,
2975 .prcm_mod = OMAP3430_PER_MOD,
2976 .enable_reg = CM_FCLKEN,
2977 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2978 .flags = CLOCK_IN_OMAP343X,
2979 .clkdm = { .name = "per_clkdm" },
2980 .recalc = &omap2_clksel_recalc,
2983 static struct clk mcbsp4_src_fck = {
2984 .name = "mcbsp_src_fck",
2986 .prcm_mod = CLK_REG_IN_SCM,
2987 .init = &omap2_init_clksel_parent,
2988 .clksel_reg = OMAP343X_CONTROL_DEVCONF1,
2989 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2990 .clksel = mcbsp_234_clksel,
2991 .flags = CLOCK_IN_OMAP343X,
2992 .clkdm = { .name = "per_clkdm" },
2993 .recalc = &omap2_clksel_recalc,
2996 static struct clk mcbsp4_fck = {
2997 .name = "mcbsp_fck",
2999 .parent = &mcbsp4_src_fck,
3000 .prcm_mod = OMAP3430_PER_MOD,
3001 .enable_reg = CM_FCLKEN,
3002 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
3003 .flags = CLOCK_IN_OMAP343X,
3004 .clkdm = { .name = "per_clkdm" },
3005 .recalc = &omap2_clksel_recalc,
3010 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
3012 static const struct clksel_rate emu_src_sys_rates[] = {
3013 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
3017 static const struct clksel_rate emu_src_core_rates[] = {
3018 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3022 static const struct clksel_rate emu_src_per_rates[] = {
3023 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3027 static const struct clksel_rate emu_src_mpu_rates[] = {
3028 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
3032 static const struct clksel emu_src_clksel[] = {
3033 { .parent = &sys_ck, .rates = emu_src_sys_rates },
3034 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
3035 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
3036 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
3041 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
3042 * to switch the source of some of the EMU clocks.
3043 * XXX Are there CLKEN bits for these EMU clks?
3045 static struct clk emu_src_ck = {
3046 .name = "emu_src_ck",
3047 .prcm_mod = OMAP3430_EMU_MOD,
3048 .init = &omap2_init_clksel_parent,
3049 .clksel_reg = CM_CLKSEL1,
3050 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
3051 .clksel = emu_src_clksel,
3052 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3053 .clkdm = { .name = "emu_clkdm" },
3054 .recalc = &omap2_clksel_recalc,
3057 static const struct clksel_rate pclk_emu_rates[] = {
3058 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3059 { .div = 3, .val = 3, .flags = RATE_IN_343X },
3060 { .div = 4, .val = 4, .flags = RATE_IN_343X },
3061 { .div = 6, .val = 6, .flags = RATE_IN_343X },
3065 static const struct clksel pclk_emu_clksel[] = {
3066 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
3070 static struct clk pclk_fck = {
3072 .prcm_mod = OMAP3430_EMU_MOD,
3073 .init = &omap2_init_clksel_parent,
3074 .clksel_reg = CM_CLKSEL1,
3075 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
3076 .clksel = pclk_emu_clksel,
3077 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3078 .clkdm = { .name = "emu_clkdm" },
3079 .recalc = &omap2_clksel_recalc,
3082 static const struct clksel_rate pclkx2_emu_rates[] = {
3083 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3084 { .div = 2, .val = 2, .flags = RATE_IN_343X },
3085 { .div = 3, .val = 3, .flags = RATE_IN_343X },
3089 static const struct clksel pclkx2_emu_clksel[] = {
3090 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
3094 static struct clk pclkx2_fck = {
3095 .name = "pclkx2_fck",
3096 .prcm_mod = OMAP3430_EMU_MOD,
3097 .init = &omap2_init_clksel_parent,
3098 .clksel_reg = CM_CLKSEL1,
3099 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
3100 .clksel = pclkx2_emu_clksel,
3101 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3102 .clkdm = { .name = "emu_clkdm" },
3103 .recalc = &omap2_clksel_recalc,
3106 static const struct clksel atclk_emu_clksel[] = {
3107 { .parent = &emu_src_ck, .rates = div2_rates },
3111 static struct clk atclk_fck = {
3112 .name = "atclk_fck",
3113 .prcm_mod = OMAP3430_EMU_MOD,
3114 .init = &omap2_init_clksel_parent,
3115 .clksel_reg = CM_CLKSEL1,
3116 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
3117 .clksel = atclk_emu_clksel,
3118 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3119 .clkdm = { .name = "emu_clkdm" },
3120 .recalc = &omap2_clksel_recalc,
3123 static struct clk traceclk_src_fck = {
3124 .name = "traceclk_src_fck",
3125 .prcm_mod = OMAP3430_EMU_MOD,
3126 .init = &omap2_init_clksel_parent,
3127 .clksel_reg = CM_CLKSEL1,
3128 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
3129 .clksel = emu_src_clksel,
3130 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3131 .clkdm = { .name = "emu_clkdm" },
3132 .recalc = &omap2_clksel_recalc,
3135 static const struct clksel_rate traceclk_rates[] = {
3136 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3137 { .div = 2, .val = 2, .flags = RATE_IN_343X },
3138 { .div = 4, .val = 4, .flags = RATE_IN_343X },
3142 static const struct clksel traceclk_clksel[] = {
3143 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3147 static struct clk traceclk_fck = {
3148 .name = "traceclk_fck",
3149 .prcm_mod = OMAP3430_EMU_MOD,
3150 .init = &omap2_init_clksel_parent,
3151 .clksel_reg = CM_CLKSEL1,
3152 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
3153 .clksel = traceclk_clksel,
3154 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3155 .clkdm = { .name = "emu_clkdm" },
3156 .recalc = &omap2_clksel_recalc,
3161 /* SmartReflex fclk (VDD1) */
3162 static struct clk sr1_fck = {
3165 .prcm_mod = WKUP_MOD,
3166 .enable_reg = CM_FCLKEN,
3167 .enable_bit = OMAP3430_EN_SR1_SHIFT,
3168 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3169 .clkdm = { .name = "prm_clkdm" },
3170 .recalc = &followparent_recalc,
3173 /* SmartReflex fclk (VDD2) */
3174 static struct clk sr2_fck = {
3177 .prcm_mod = WKUP_MOD,
3178 .enable_reg = CM_FCLKEN,
3179 .enable_bit = OMAP3430_EN_SR2_SHIFT,
3180 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3181 .clkdm = { .name = "prm_clkdm" },
3182 .recalc = &followparent_recalc,
3185 static struct clk sr_l4_ick = {
3186 .name = "sr_l4_ick",
3188 .flags = CLOCK_IN_OMAP343X,
3189 .clkdm = { .name = "core_l4_clkdm" },
3190 .recalc = &followparent_recalc,
3193 /* SECURE_32K_FCK clocks */
3195 /* XXX This clock no longer exists in 3430 TRM rev F */
3196 static struct clk gpt12_fck = {
3197 .name = "gpt12_fck",
3198 .parent = &secure_32k_fck,
3199 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3200 .clkdm = { .name = "prm_clkdm" },
3201 .recalc = &followparent_recalc,
3204 static struct clk wdt1_fck = {
3206 .parent = &secure_32k_fck,
3207 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3208 .clkdm = { .name = "prm_clkdm" },
3209 .recalc = &followparent_recalc,
3212 static struct clk *onchip_34xx_clks[] __initdata = {
3240 &omap_96m_alwon_fck,