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[ARM] OMAP: Add CSI2 clock struct for handling it with clock API
[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / clock34xx.h
1 /*
2  * OMAP3 clock framework
3  *
4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
5  * Copyright (C) 2007-2008 Nokia Corporation
6  *
7  * Written by Paul Walmsley
8  * With many device clock fixes by Kevin Hilman and Jouni Högander
9  * DPLL bypass clock support added by Roman Tereshonkov
10  *
11  */
12
13 /*
14  * Virtual clocks are introduced as convenient tools.
15  * They are sources for other clocks and not supposed
16  * to be requested from drivers directly.
17  */
18
19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
21
22 #include <mach/control.h>
23
24 #include "clock.h"
25 #include "cm.h"
26 #include "cm-regbits-34xx.h"
27 #include "prm.h"
28 #include "prm-regbits-34xx.h"
29
30 static void omap3_dpll_recalc(struct clk *clk);
31 static void omap3_clkoutx2_recalc(struct clk *clk);
32 static void omap3_dpll_allow_idle(struct clk *clk);
33 static void omap3_dpll_deny_idle(struct clk *clk);
34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
35 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
36 static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
37
38 /* Maximum DPLL multiplier, divider values for OMAP3 */
39 #define OMAP3_MAX_DPLL_MULT             2048
40 #define OMAP3_MAX_DPLL_DIV              128
41
42 /*
43  * DPLL1 supplies clock to the MPU.
44  * DPLL2 supplies clock to the IVA2.
45  * DPLL3 supplies CORE domain clocks.
46  * DPLL4 supplies peripheral clocks.
47  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
48  */
49
50 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
51 #define DPLL_LOW_POWER_STOP             0x1
52 #define DPLL_LOW_POWER_BYPASS           0x5
53 #define DPLL_LOCKED                     0x7
54
55 /* PRM CLOCKS */
56
57 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
58 static struct clk omap_32k_fck = {
59         .name           = "omap_32k_fck",
60         .ops            = &clkops_null,
61         .rate           = 32768,
62         .flags          = RATE_FIXED | RATE_PROPAGATES,
63 };
64
65 static struct clk secure_32k_fck = {
66         .name           = "secure_32k_fck",
67         .ops            = &clkops_null,
68         .rate           = 32768,
69         .flags          = RATE_FIXED | RATE_PROPAGATES,
70 };
71
72 /* Virtual source clocks for osc_sys_ck */
73 static struct clk virt_12m_ck = {
74         .name           = "virt_12m_ck",
75         .ops            = &clkops_null,
76         .rate           = 12000000,
77         .flags          = RATE_FIXED | RATE_PROPAGATES,
78 };
79
80 static struct clk virt_13m_ck = {
81         .name           = "virt_13m_ck",
82         .ops            = &clkops_null,
83         .rate           = 13000000,
84         .flags          = RATE_FIXED | RATE_PROPAGATES,
85 };
86
87 static struct clk virt_16_8m_ck = {
88         .name           = "virt_16_8m_ck",
89         .ops            = &clkops_null,
90         .rate           = 16800000,
91         .flags          = RATE_FIXED | RATE_PROPAGATES,
92 };
93
94 static struct clk virt_19_2m_ck = {
95         .name           = "virt_19_2m_ck",
96         .ops            = &clkops_null,
97         .rate           = 19200000,
98         .flags          = RATE_FIXED | RATE_PROPAGATES,
99 };
100
101 static struct clk virt_26m_ck = {
102         .name           = "virt_26m_ck",
103         .ops            = &clkops_null,
104         .rate           = 26000000,
105         .flags          = RATE_FIXED | RATE_PROPAGATES,
106 };
107
108 static struct clk virt_38_4m_ck = {
109         .name           = "virt_38_4m_ck",
110         .ops            = &clkops_null,
111         .rate           = 38400000,
112         .flags          = RATE_FIXED | RATE_PROPAGATES,
113 };
114
115 static const struct clksel_rate osc_sys_12m_rates[] = {
116         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
117         { .div = 0 }
118 };
119
120 static const struct clksel_rate osc_sys_13m_rates[] = {
121         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
122         { .div = 0 }
123 };
124
125 static const struct clksel_rate osc_sys_16_8m_rates[] = {
126         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
127         { .div = 0 }
128 };
129
130 static const struct clksel_rate osc_sys_19_2m_rates[] = {
131         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
132         { .div = 0 }
133 };
134
135 static const struct clksel_rate osc_sys_26m_rates[] = {
136         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
137         { .div = 0 }
138 };
139
140 static const struct clksel_rate osc_sys_38_4m_rates[] = {
141         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
142         { .div = 0 }
143 };
144
145 static const struct clksel osc_sys_clksel[] = {
146         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
147         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
148         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
149         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
150         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
151         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
152         { .parent = NULL },
153 };
154
155 /* Oscillator clock */
156 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
157 static struct clk osc_sys_ck = {
158         .name           = "osc_sys_ck",
159         .ops            = &clkops_null,
160         .init           = &omap2_init_clksel_parent,
161         .clksel_reg     = OMAP3430_PRM_CLKSEL,
162         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
163         .clksel         = osc_sys_clksel,
164         /* REVISIT: deal with autoextclkmode? */
165         .flags          = RATE_FIXED | RATE_PROPAGATES,
166         .recalc         = &omap2_clksel_recalc,
167 };
168
169 static const struct clksel_rate div2_rates[] = {
170         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
171         { .div = 2, .val = 2, .flags = RATE_IN_343X },
172         { .div = 0 }
173 };
174
175 static const struct clksel sys_clksel[] = {
176         { .parent = &osc_sys_ck, .rates = div2_rates },
177         { .parent = NULL }
178 };
179
180 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
181 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
182 static struct clk sys_ck = {
183         .name           = "sys_ck",
184         .ops            = &clkops_null,
185         .parent         = &osc_sys_ck,
186         .init           = &omap2_init_clksel_parent,
187         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
188         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
189         .clksel         = sys_clksel,
190         .flags          = RATE_PROPAGATES,
191         .recalc         = &omap2_clksel_recalc,
192 };
193
194 static struct clk sys_altclk = {
195         .name           = "sys_altclk",
196         .ops            = &clkops_null,
197         .flags          = RATE_PROPAGATES,
198 };
199
200 /* Optional external clock input for some McBSPs */
201 static struct clk mcbsp_clks = {
202         .name           = "mcbsp_clks",
203         .ops            = &clkops_null,
204         .flags          = RATE_PROPAGATES,
205 };
206
207 /* PRM EXTERNAL CLOCK OUTPUT */
208
209 static struct clk sys_clkout1 = {
210         .name           = "sys_clkout1",
211         .ops            = &clkops_omap2_dflt,
212         .parent         = &osc_sys_ck,
213         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
214         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
215         .recalc         = &followparent_recalc,
216 };
217
218 /* DPLLS */
219
220 /* CM CLOCKS */
221
222 static const struct clksel_rate dpll_bypass_rates[] = {
223         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
224         { .div = 0 }
225 };
226
227 static const struct clksel_rate dpll_locked_rates[] = {
228         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
229         { .div = 0 }
230 };
231
232 static const struct clksel_rate div16_dpll_rates[] = {
233         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
234         { .div = 2, .val = 2, .flags = RATE_IN_343X },
235         { .div = 3, .val = 3, .flags = RATE_IN_343X },
236         { .div = 4, .val = 4, .flags = RATE_IN_343X },
237         { .div = 5, .val = 5, .flags = RATE_IN_343X },
238         { .div = 6, .val = 6, .flags = RATE_IN_343X },
239         { .div = 7, .val = 7, .flags = RATE_IN_343X },
240         { .div = 8, .val = 8, .flags = RATE_IN_343X },
241         { .div = 9, .val = 9, .flags = RATE_IN_343X },
242         { .div = 10, .val = 10, .flags = RATE_IN_343X },
243         { .div = 11, .val = 11, .flags = RATE_IN_343X },
244         { .div = 12, .val = 12, .flags = RATE_IN_343X },
245         { .div = 13, .val = 13, .flags = RATE_IN_343X },
246         { .div = 14, .val = 14, .flags = RATE_IN_343X },
247         { .div = 15, .val = 15, .flags = RATE_IN_343X },
248         { .div = 16, .val = 16, .flags = RATE_IN_343X },
249         { .div = 0 }
250 };
251
252 /* DPLL1 */
253 /* MPU clock source */
254 /* Type: DPLL */
255 static struct dpll_data dpll1_dd = {
256         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
257         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
258         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
259         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
260         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
261         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
262         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
263         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
264         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
265         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
266         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
267         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
268         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
269         .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
270         .max_multiplier = OMAP3_MAX_DPLL_MULT,
271         .max_divider    = OMAP3_MAX_DPLL_DIV,
272         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
273 };
274
275 static struct clk dpll1_ck = {
276         .name           = "dpll1_ck",
277         .ops            = &clkops_null,
278         .parent         = &sys_ck,
279         .dpll_data      = &dpll1_dd,
280         .flags          = RATE_PROPAGATES,
281         .round_rate     = &omap2_dpll_round_rate,
282         .set_rate       = &omap3_noncore_dpll_set_rate,
283         .recalc         = &omap3_dpll_recalc,
284 };
285
286 /*
287  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
288  * DPLL isn't bypassed.
289  */
290 static struct clk dpll1_x2_ck = {
291         .name           = "dpll1_x2_ck",
292         .ops            = &clkops_null,
293         .parent         = &dpll1_ck,
294         .flags          = RATE_PROPAGATES,
295         .recalc         = &omap3_clkoutx2_recalc,
296 };
297
298 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
299 static const struct clksel div16_dpll1_x2m2_clksel[] = {
300         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
301         { .parent = NULL }
302 };
303
304 /*
305  * Does not exist in the TRM - needed to separate the M2 divider from
306  * bypass selection in mpu_ck
307  */
308 static struct clk dpll1_x2m2_ck = {
309         .name           = "dpll1_x2m2_ck",
310         .ops            = &clkops_null,
311         .parent         = &dpll1_x2_ck,
312         .init           = &omap2_init_clksel_parent,
313         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
314         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
315         .clksel         = div16_dpll1_x2m2_clksel,
316         .flags          = RATE_PROPAGATES,
317         .recalc         = &omap2_clksel_recalc,
318 };
319
320 /* DPLL2 */
321 /* IVA2 clock source */
322 /* Type: DPLL */
323
324 static struct dpll_data dpll2_dd = {
325         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
326         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
327         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
328         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
329         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
330         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
331         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
332                                 (1 << DPLL_LOW_POWER_BYPASS),
333         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
334         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
335         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
336         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
337         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
338         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
339         .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
340         .max_multiplier = OMAP3_MAX_DPLL_MULT,
341         .max_divider    = OMAP3_MAX_DPLL_DIV,
342         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
343 };
344
345 static struct clk dpll2_ck = {
346         .name           = "dpll2_ck",
347         .ops            = &clkops_noncore_dpll_ops,
348         .parent         = &sys_ck,
349         .dpll_data      = &dpll2_dd,
350         .flags          = RATE_PROPAGATES,
351         .round_rate     = &omap2_dpll_round_rate,
352         .set_rate       = &omap3_noncore_dpll_set_rate,
353         .recalc         = &omap3_dpll_recalc,
354 };
355
356 static const struct clksel div16_dpll2_m2x2_clksel[] = {
357         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
358         { .parent = NULL }
359 };
360
361 /*
362  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
363  * or CLKOUTX2. CLKOUT seems most plausible.
364  */
365 static struct clk dpll2_m2_ck = {
366         .name           = "dpll2_m2_ck",
367         .ops            = &clkops_null,
368         .parent         = &dpll2_ck,
369         .init           = &omap2_init_clksel_parent,
370         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
371                                           OMAP3430_CM_CLKSEL2_PLL),
372         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
373         .clksel         = div16_dpll2_m2x2_clksel,
374         .flags          = RATE_PROPAGATES,
375         .recalc         = &omap2_clksel_recalc,
376 };
377
378 /*
379  * DPLL3
380  * Source clock for all interfaces and for some device fclks
381  * REVISIT: Also supports fast relock bypass - not included below
382  */
383 static struct dpll_data dpll3_dd = {
384         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
385         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
386         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
387         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
388         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
389         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
390         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
391         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
392         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
393         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
394         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
395         .max_multiplier = OMAP3_MAX_DPLL_MULT,
396         .max_divider    = OMAP3_MAX_DPLL_DIV,
397         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
398 };
399
400 static struct clk dpll3_ck = {
401         .name           = "dpll3_ck",
402         .ops            = &clkops_null,
403         .parent         = &sys_ck,
404         .dpll_data      = &dpll3_dd,
405         .flags          = RATE_PROPAGATES,
406         .round_rate     = &omap2_dpll_round_rate,
407         .recalc         = &omap3_dpll_recalc,
408 };
409
410 /*
411  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
412  * DPLL isn't bypassed
413  */
414 static struct clk dpll3_x2_ck = {
415         .name           = "dpll3_x2_ck",
416         .ops            = &clkops_null,
417         .parent         = &dpll3_ck,
418         .flags          = RATE_PROPAGATES,
419         .recalc         = &omap3_clkoutx2_recalc,
420 };
421
422 static const struct clksel_rate div31_dpll3_rates[] = {
423         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
424         { .div = 2, .val = 2, .flags = RATE_IN_343X },
425         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
426         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
427         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
428         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
429         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
430         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
431         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
432         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
433         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
434         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
435         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
436         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
437         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
438         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
439         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
440         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
441         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
442         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
443         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
444         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
445         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
446         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
447         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
448         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
449         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
450         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
451         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
452         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
453         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
454         { .div = 0 },
455 };
456
457 static const struct clksel div31_dpll3m2_clksel[] = {
458         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
459         { .parent = NULL }
460 };
461
462 /*
463  * DPLL3 output M2
464  * REVISIT: This DPLL output divider must be changed in SRAM, so until
465  * that code is ready, this should remain a 'read-only' clksel clock.
466  */
467 static struct clk dpll3_m2_ck = {
468         .name           = "dpll3_m2_ck",
469         .ops            = &clkops_null,
470         .parent         = &dpll3_ck,
471         .init           = &omap2_init_clksel_parent,
472         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
473         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
474         .clksel         = div31_dpll3m2_clksel,
475         .flags          = RATE_PROPAGATES,
476         .recalc         = &omap2_clksel_recalc,
477 };
478
479 static const struct clksel core_ck_clksel[] = {
480         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
481         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
482         { .parent = NULL }
483 };
484
485 static struct clk core_ck = {
486         .name           = "core_ck",
487         .ops            = &clkops_null,
488         .init           = &omap2_init_clksel_parent,
489         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
490         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
491         .clksel         = core_ck_clksel,
492         .flags          = RATE_PROPAGATES,
493         .recalc         = &omap2_clksel_recalc,
494 };
495
496 static const struct clksel dpll3_m2x2_ck_clksel[] = {
497         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
498         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
499         { .parent = NULL }
500 };
501
502 static struct clk dpll3_m2x2_ck = {
503         .name           = "dpll3_m2x2_ck",
504         .ops            = &clkops_null,
505         .init           = &omap2_init_clksel_parent,
506         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
507         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
508         .clksel         = dpll3_m2x2_ck_clksel,
509         .flags          = RATE_PROPAGATES,
510         .recalc         = &omap2_clksel_recalc,
511 };
512
513 /* The PWRDN bit is apparently only available on 3430ES2 and above */
514 static const struct clksel div16_dpll3_clksel[] = {
515         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
516         { .parent = NULL }
517 };
518
519 /* This virtual clock is the source for dpll3_m3x2_ck */
520 static struct clk dpll3_m3_ck = {
521         .name           = "dpll3_m3_ck",
522         .ops            = &clkops_null,
523         .parent         = &dpll3_ck,
524         .init           = &omap2_init_clksel_parent,
525         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
526         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
527         .clksel         = div16_dpll3_clksel,
528         .flags          = RATE_PROPAGATES,
529         .recalc         = &omap2_clksel_recalc,
530 };
531
532 /* The PWRDN bit is apparently only available on 3430ES2 and above */
533 static struct clk dpll3_m3x2_ck = {
534         .name           = "dpll3_m3x2_ck",
535         .ops            = &clkops_omap2_dflt_wait,
536         .parent         = &dpll3_m3_ck,
537         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
538         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
539         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
540         .recalc         = &omap3_clkoutx2_recalc,
541 };
542
543 static const struct clksel emu_core_alwon_ck_clksel[] = {
544         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
545         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
546         { .parent = NULL }
547 };
548
549 static struct clk emu_core_alwon_ck = {
550         .name           = "emu_core_alwon_ck",
551         .ops            = &clkops_null,
552         .parent         = &dpll3_m3x2_ck,
553         .init           = &omap2_init_clksel_parent,
554         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
555         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
556         .clksel         = emu_core_alwon_ck_clksel,
557         .flags          = RATE_PROPAGATES,
558         .recalc         = &omap2_clksel_recalc,
559 };
560
561 /* DPLL4 */
562 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
563 /* Type: DPLL */
564 static struct dpll_data dpll4_dd = {
565         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
566         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
567         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
568         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
569         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
570         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
571         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
572         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
573         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
574         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
575         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
576         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
577         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
578         .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
579         .max_multiplier = OMAP3_MAX_DPLL_MULT,
580         .max_divider    = OMAP3_MAX_DPLL_DIV,
581         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
582 };
583
584 static struct clk dpll4_ck = {
585         .name           = "dpll4_ck",
586         .ops            = &clkops_noncore_dpll_ops,
587         .parent         = &sys_ck,
588         .dpll_data      = &dpll4_dd,
589         .flags          = RATE_PROPAGATES,
590         .round_rate     = &omap2_dpll_round_rate,
591         .set_rate       = &omap3_dpll4_set_rate,
592         .recalc         = &omap3_dpll_recalc,
593 };
594
595 /*
596  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
597  * DPLL isn't bypassed --
598  * XXX does this serve any downstream clocks?
599  */
600 static struct clk dpll4_x2_ck = {
601         .name           = "dpll4_x2_ck",
602         .ops            = &clkops_null,
603         .parent         = &dpll4_ck,
604         .flags          = RATE_PROPAGATES,
605         .recalc         = &omap3_clkoutx2_recalc,
606 };
607
608 static const struct clksel div16_dpll4_clksel[] = {
609         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
610         { .parent = NULL }
611 };
612
613 /* This virtual clock is the source for dpll4_m2x2_ck */
614 static struct clk dpll4_m2_ck = {
615         .name           = "dpll4_m2_ck",
616         .ops            = &clkops_null,
617         .parent         = &dpll4_ck,
618         .init           = &omap2_init_clksel_parent,
619         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
620         .clksel_mask    = OMAP3430_DIV_96M_MASK,
621         .clksel         = div16_dpll4_clksel,
622         .flags          = RATE_PROPAGATES,
623         .recalc         = &omap2_clksel_recalc,
624 };
625
626 /* The PWRDN bit is apparently only available on 3430ES2 and above */
627 static struct clk dpll4_m2x2_ck = {
628         .name           = "dpll4_m2x2_ck",
629         .ops            = &clkops_omap2_dflt_wait,
630         .parent         = &dpll4_m2_ck,
631         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
632         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
633         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
634         .recalc         = &omap3_clkoutx2_recalc,
635 };
636
637 static const struct clksel omap_96m_alwon_fck_clksel[] = {
638         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
639         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
640         { .parent = NULL }
641 };
642
643 /*
644  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
645  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
646  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
647  * CM_96K_(F)CLK.
648  */
649 static struct clk omap_96m_alwon_fck = {
650         .name           = "omap_96m_alwon_fck",
651         .ops            = &clkops_null,
652         .parent         = &dpll4_m2x2_ck,
653         .init           = &omap2_init_clksel_parent,
654         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
655         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
656         .clksel         = omap_96m_alwon_fck_clksel,
657         .flags          = RATE_PROPAGATES,
658         .recalc         = &omap2_clksel_recalc,
659 };
660
661 static struct clk cm_96m_fck = {
662         .name           = "cm_96m_fck",
663         .ops            = &clkops_null,
664         .parent         = &omap_96m_alwon_fck,
665         .flags          = RATE_PROPAGATES,
666         .recalc         = &followparent_recalc,
667 };
668
669 static const struct clksel_rate omap_96m_dpll_rates[] = {
670         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
671         { .div = 0 }
672 };
673
674 static const struct clksel_rate omap_96m_sys_rates[] = {
675         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
676         { .div = 0 }
677 };
678
679 static const struct clksel omap_96m_fck_clksel[] = {
680         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
681         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
682         { .parent = NULL }
683 };
684
685 static struct clk omap_96m_fck = {
686         .name           = "omap_96m_fck",
687         .ops            = &clkops_null,
688         .parent         = &sys_ck,
689         .init           = &omap2_init_clksel_parent,
690         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
691         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
692         .clksel         = omap_96m_fck_clksel,
693         .flags          = RATE_PROPAGATES,
694         .recalc         = &omap2_clksel_recalc,
695 };
696
697 /* This virtual clock is the source for dpll4_m3x2_ck */
698 static struct clk dpll4_m3_ck = {
699         .name           = "dpll4_m3_ck",
700         .ops            = &clkops_null,
701         .parent         = &dpll4_ck,
702         .init           = &omap2_init_clksel_parent,
703         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
704         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
705         .clksel         = div16_dpll4_clksel,
706         .flags          = RATE_PROPAGATES,
707         .recalc         = &omap2_clksel_recalc,
708 };
709
710 /* The PWRDN bit is apparently only available on 3430ES2 and above */
711 static struct clk dpll4_m3x2_ck = {
712         .name           = "dpll4_m3x2_ck",
713         .ops            = &clkops_omap2_dflt_wait,
714         .parent         = &dpll4_m3_ck,
715         .init           = &omap2_init_clksel_parent,
716         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
717         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
718         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
719         .recalc         = &omap3_clkoutx2_recalc,
720 };
721
722 static const struct clksel virt_omap_54m_fck_clksel[] = {
723         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
724         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
725         { .parent = NULL }
726 };
727
728 static struct clk virt_omap_54m_fck = {
729         .name           = "virt_omap_54m_fck",
730         .ops            = &clkops_null,
731         .parent         = &dpll4_m3x2_ck,
732         .init           = &omap2_init_clksel_parent,
733         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
734         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
735         .clksel         = virt_omap_54m_fck_clksel,
736         .flags          = RATE_PROPAGATES,
737         .recalc         = &omap2_clksel_recalc,
738 };
739
740 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
741         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
742         { .div = 0 }
743 };
744
745 static const struct clksel_rate omap_54m_alt_rates[] = {
746         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
747         { .div = 0 }
748 };
749
750 static const struct clksel omap_54m_clksel[] = {
751         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
752         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
753         { .parent = NULL }
754 };
755
756 static struct clk omap_54m_fck = {
757         .name           = "omap_54m_fck",
758         .ops            = &clkops_null,
759         .init           = &omap2_init_clksel_parent,
760         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
761         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
762         .clksel         = omap_54m_clksel,
763         .flags          = RATE_PROPAGATES,
764         .recalc         = &omap2_clksel_recalc,
765 };
766
767 static const struct clksel_rate omap_48m_cm96m_rates[] = {
768         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
769         { .div = 0 }
770 };
771
772 static const struct clksel_rate omap_48m_alt_rates[] = {
773         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
774         { .div = 0 }
775 };
776
777 static const struct clksel omap_48m_clksel[] = {
778         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
779         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
780         { .parent = NULL }
781 };
782
783 static struct clk omap_48m_fck = {
784         .name           = "omap_48m_fck",
785         .ops            = &clkops_null,
786         .init           = &omap2_init_clksel_parent,
787         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
788         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
789         .clksel         = omap_48m_clksel,
790         .flags          = RATE_PROPAGATES,
791         .recalc         = &omap2_clksel_recalc,
792 };
793
794 static struct clk omap_12m_fck = {
795         .name           = "omap_12m_fck",
796         .ops            = &clkops_null,
797         .parent         = &omap_48m_fck,
798         .fixed_div      = 4,
799         .flags          = RATE_PROPAGATES,
800         .recalc         = &omap2_fixed_divisor_recalc,
801 };
802
803 /* This virstual clock is the source for dpll4_m4x2_ck */
804 static struct clk dpll4_m4_ck = {
805         .name           = "dpll4_m4_ck",
806         .ops            = &clkops_null,
807         .parent         = &dpll4_ck,
808         .init           = &omap2_init_clksel_parent,
809         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
810         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
811         .clksel         = div16_dpll4_clksel,
812         .flags          = RATE_PROPAGATES,
813         .recalc         = &omap2_clksel_recalc,
814 };
815
816 /* The PWRDN bit is apparently only available on 3430ES2 and above */
817 static struct clk dpll4_m4x2_ck = {
818         .name           = "dpll4_m4x2_ck",
819         .ops            = &clkops_omap2_dflt_wait,
820         .parent         = &dpll4_m4_ck,
821         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
822         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
823         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
824         .recalc         = &omap3_clkoutx2_recalc,
825 };
826
827 /* This virtual clock is the source for dpll4_m5x2_ck */
828 static struct clk dpll4_m5_ck = {
829         .name           = "dpll4_m5_ck",
830         .ops            = &clkops_null,
831         .parent         = &dpll4_ck,
832         .init           = &omap2_init_clksel_parent,
833         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
834         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
835         .clksel         = div16_dpll4_clksel,
836         .flags          = RATE_PROPAGATES,
837         .recalc         = &omap2_clksel_recalc,
838 };
839
840 /* The PWRDN bit is apparently only available on 3430ES2 and above */
841 static struct clk dpll4_m5x2_ck = {
842         .name           = "dpll4_m5x2_ck",
843         .ops            = &clkops_omap2_dflt_wait,
844         .parent         = &dpll4_m5_ck,
845         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
846         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
847         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
848         .recalc         = &omap3_clkoutx2_recalc,
849 };
850
851 /* This virtual clock is the source for dpll4_m6x2_ck */
852 static struct clk dpll4_m6_ck = {
853         .name           = "dpll4_m6_ck",
854         .ops            = &clkops_null,
855         .parent         = &dpll4_ck,
856         .init           = &omap2_init_clksel_parent,
857         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
858         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
859         .clksel         = div16_dpll4_clksel,
860         .flags          = RATE_PROPAGATES,
861         .recalc         = &omap2_clksel_recalc,
862 };
863
864 /* The PWRDN bit is apparently only available on 3430ES2 and above */
865 static struct clk dpll4_m6x2_ck = {
866         .name           = "dpll4_m6x2_ck",
867         .ops            = &clkops_omap2_dflt_wait,
868         .parent         = &dpll4_m6_ck,
869         .init           = &omap2_init_clksel_parent,
870         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
871         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
872         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
873         .recalc         = &omap3_clkoutx2_recalc,
874 };
875
876 static struct clk emu_per_alwon_ck = {
877         .name           = "emu_per_alwon_ck",
878         .ops            = &clkops_null,
879         .parent         = &dpll4_m6x2_ck,
880         .flags          = RATE_PROPAGATES,
881         .recalc         = &followparent_recalc,
882 };
883
884 /* DPLL5 */
885 /* Supplies 120MHz clock, USIM source clock */
886 /* Type: DPLL */
887 /* 3430ES2 only */
888 static struct dpll_data dpll5_dd = {
889         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
890         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
891         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
892         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
893         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
894         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
895         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
896         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
897         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
898         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
899         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
900         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
901         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
902         .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
903         .max_multiplier = OMAP3_MAX_DPLL_MULT,
904         .max_divider    = OMAP3_MAX_DPLL_DIV,
905         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
906 };
907
908 static struct clk dpll5_ck = {
909         .name           = "dpll5_ck",
910         .ops            = &clkops_noncore_dpll_ops,
911         .parent         = &sys_ck,
912         .dpll_data      = &dpll5_dd,
913         .flags          = RATE_PROPAGATES,
914         .round_rate     = &omap2_dpll_round_rate,
915         .set_rate       = &omap3_noncore_dpll_set_rate,
916         .recalc         = &omap3_dpll_recalc,
917 };
918
919 static const struct clksel div16_dpll5_clksel[] = {
920         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
921         { .parent = NULL }
922 };
923
924 static struct clk dpll5_m2_ck = {
925         .name           = "dpll5_m2_ck",
926         .ops            = &clkops_null,
927         .parent         = &dpll5_ck,
928         .init           = &omap2_init_clksel_parent,
929         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
930         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
931         .clksel         = div16_dpll5_clksel,
932         .flags          = RATE_PROPAGATES,
933         .recalc         = &omap2_clksel_recalc,
934 };
935
936 static const struct clksel omap_120m_fck_clksel[] = {
937         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
938         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
939         { .parent = NULL }
940 };
941
942 static struct clk omap_120m_fck = {
943         .name           = "omap_120m_fck",
944         .ops            = &clkops_null,
945         .parent         = &dpll5_m2_ck,
946         .init           = &omap2_init_clksel_parent,
947         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
948         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
949         .clksel         = omap_120m_fck_clksel,
950         .flags          = RATE_PROPAGATES,
951         .recalc         = &omap2_clksel_recalc,
952 };
953
954 /* CM EXTERNAL CLOCK OUTPUTS */
955
956 static const struct clksel_rate clkout2_src_core_rates[] = {
957         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
958         { .div = 0 }
959 };
960
961 static const struct clksel_rate clkout2_src_sys_rates[] = {
962         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
963         { .div = 0 }
964 };
965
966 static const struct clksel_rate clkout2_src_96m_rates[] = {
967         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
968         { .div = 0 }
969 };
970
971 static const struct clksel_rate clkout2_src_54m_rates[] = {
972         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
973         { .div = 0 }
974 };
975
976 static const struct clksel clkout2_src_clksel[] = {
977         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
978         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
979         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
980         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
981         { .parent = NULL }
982 };
983
984 static struct clk clkout2_src_ck = {
985         .name           = "clkout2_src_ck",
986         .ops            = &clkops_omap2_dflt,
987         .init           = &omap2_init_clksel_parent,
988         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
989         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
990         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
991         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
992         .clksel         = clkout2_src_clksel,
993         .flags          = RATE_PROPAGATES,
994         .recalc         = &omap2_clksel_recalc,
995 };
996
997 static const struct clksel_rate sys_clkout2_rates[] = {
998         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
999         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1000         { .div = 4, .val = 2, .flags = RATE_IN_343X },
1001         { .div = 8, .val = 3, .flags = RATE_IN_343X },
1002         { .div = 16, .val = 4, .flags = RATE_IN_343X },
1003         { .div = 0 },
1004 };
1005
1006 static const struct clksel sys_clkout2_clksel[] = {
1007         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1008         { .parent = NULL },
1009 };
1010
1011 static struct clk sys_clkout2 = {
1012         .name           = "sys_clkout2",
1013         .ops            = &clkops_null,
1014         .init           = &omap2_init_clksel_parent,
1015         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
1016         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1017         .clksel         = sys_clkout2_clksel,
1018         .recalc         = &omap2_clksel_recalc,
1019 };
1020
1021 /* CM OUTPUT CLOCKS */
1022
1023 static struct clk corex2_fck = {
1024         .name           = "corex2_fck",
1025         .ops            = &clkops_null,
1026         .parent         = &dpll3_m2x2_ck,
1027         .flags          = RATE_PROPAGATES,
1028         .recalc         = &followparent_recalc,
1029 };
1030
1031 /* DPLL power domain clock controls */
1032
1033 static const struct clksel div2_core_clksel[] = {
1034         { .parent = &core_ck, .rates = div2_rates },
1035         { .parent = NULL }
1036 };
1037
1038 /*
1039  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1040  * may be inconsistent here?
1041  */
1042 static struct clk dpll1_fck = {
1043         .name           = "dpll1_fck",
1044         .ops            = &clkops_null,
1045         .parent         = &core_ck,
1046         .init           = &omap2_init_clksel_parent,
1047         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1048         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1049         .clksel         = div2_core_clksel,
1050         .flags          = RATE_PROPAGATES,
1051         .recalc         = &omap2_clksel_recalc,
1052 };
1053
1054 /*
1055  * MPU clksel:
1056  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1057  * derives from the high-frequency bypass clock originating from DPLL3,
1058  * called 'dpll1_fck'
1059  */
1060 static const struct clksel mpu_clksel[] = {
1061         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1062         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1063         { .parent = NULL }
1064 };
1065
1066 static struct clk mpu_ck = {
1067         .name           = "mpu_ck",
1068         .ops            = &clkops_null,
1069         .parent         = &dpll1_x2m2_ck,
1070         .init           = &omap2_init_clksel_parent,
1071         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1072         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1073         .clksel         = mpu_clksel,
1074         .flags          = RATE_PROPAGATES,
1075         .clkdm_name     = "mpu_clkdm",
1076         .recalc         = &omap2_clksel_recalc,
1077 };
1078
1079 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1080 static const struct clksel_rate arm_fck_rates[] = {
1081         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1082         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1083         { .div = 0 },
1084 };
1085
1086 static const struct clksel arm_fck_clksel[] = {
1087         { .parent = &mpu_ck, .rates = arm_fck_rates },
1088         { .parent = NULL }
1089 };
1090
1091 static struct clk arm_fck = {
1092         .name           = "arm_fck",
1093         .ops            = &clkops_null,
1094         .parent         = &mpu_ck,
1095         .init           = &omap2_init_clksel_parent,
1096         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1097         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1098         .clksel         = arm_fck_clksel,
1099         .flags          = RATE_PROPAGATES,
1100         .recalc         = &omap2_clksel_recalc,
1101 };
1102
1103 /* XXX What about neon_clkdm ? */
1104
1105 /*
1106  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1107  * although it is referenced - so this is a guess
1108  */
1109 static struct clk emu_mpu_alwon_ck = {
1110         .name           = "emu_mpu_alwon_ck",
1111         .ops            = &clkops_null,
1112         .parent         = &mpu_ck,
1113         .flags          = RATE_PROPAGATES,
1114         .recalc         = &followparent_recalc,
1115 };
1116
1117 static struct clk dpll2_fck = {
1118         .name           = "dpll2_fck",
1119         .ops            = &clkops_null,
1120         .parent         = &core_ck,
1121         .init           = &omap2_init_clksel_parent,
1122         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1123         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1124         .clksel         = div2_core_clksel,
1125         .flags          = RATE_PROPAGATES,
1126         .recalc         = &omap2_clksel_recalc,
1127 };
1128
1129 /*
1130  * IVA2 clksel:
1131  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1132  * derives from the high-frequency bypass clock originating from DPLL3,
1133  * called 'dpll2_fck'
1134  */
1135
1136 static const struct clksel iva2_clksel[] = {
1137         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1138         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1139         { .parent = NULL }
1140 };
1141
1142 static struct clk iva2_ck = {
1143         .name           = "iva2_ck",
1144         .ops            = &clkops_omap2_dflt_wait,
1145         .parent         = &dpll2_m2_ck,
1146         .init           = &omap2_init_clksel_parent,
1147         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1148         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1149         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1150                                           OMAP3430_CM_IDLEST_PLL),
1151         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1152         .clksel         = iva2_clksel,
1153         .flags          = RATE_PROPAGATES,
1154         .clkdm_name     = "iva2_clkdm",
1155         .recalc         = &omap2_clksel_recalc,
1156 };
1157
1158 /* Common interface clocks */
1159
1160 static struct clk l3_ick = {
1161         .name           = "l3_ick",
1162         .ops            = &clkops_null,
1163         .parent         = &core_ck,
1164         .init           = &omap2_init_clksel_parent,
1165         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1166         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1167         .clksel         = div2_core_clksel,
1168         .flags          = RATE_PROPAGATES,
1169         .clkdm_name     = "core_l3_clkdm",
1170         .recalc         = &omap2_clksel_recalc,
1171 };
1172
1173 static const struct clksel div2_l3_clksel[] = {
1174         { .parent = &l3_ick, .rates = div2_rates },
1175         { .parent = NULL }
1176 };
1177
1178 static struct clk l4_ick = {
1179         .name           = "l4_ick",
1180         .ops            = &clkops_null,
1181         .parent         = &l3_ick,
1182         .init           = &omap2_init_clksel_parent,
1183         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1184         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1185         .clksel         = div2_l3_clksel,
1186         .flags          = RATE_PROPAGATES,
1187         .clkdm_name     = "core_l4_clkdm",
1188         .recalc         = &omap2_clksel_recalc,
1189
1190 };
1191
1192 static const struct clksel div2_l4_clksel[] = {
1193         { .parent = &l4_ick, .rates = div2_rates },
1194         { .parent = NULL }
1195 };
1196
1197 static struct clk rm_ick = {
1198         .name           = "rm_ick",
1199         .ops            = &clkops_null,
1200         .parent         = &l4_ick,
1201         .init           = &omap2_init_clksel_parent,
1202         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1203         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1204         .clksel         = div2_l4_clksel,
1205         .recalc         = &omap2_clksel_recalc,
1206 };
1207
1208 /* GFX power domain */
1209
1210 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1211
1212 static const struct clksel gfx_l3_clksel[] = {
1213         { .parent = &l3_ick, .rates = gfx_l3_rates },
1214         { .parent = NULL }
1215 };
1216
1217 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1218 static struct clk gfx_l3_ck = {
1219         .name           = "gfx_l3_ck",
1220         .ops            = &clkops_omap2_dflt_wait,
1221         .parent         = &l3_ick,
1222         .init           = &omap2_init_clksel_parent,
1223         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1224         .enable_bit     = OMAP_EN_GFX_SHIFT,
1225         .recalc         = &followparent_recalc,
1226 };
1227
1228 static struct clk gfx_l3_fck = {
1229         .name           = "gfx_l3_fck",
1230         .ops            = &clkops_null,
1231         .parent         = &gfx_l3_ck,
1232         .init           = &omap2_init_clksel_parent,
1233         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1234         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1235         .clksel         = gfx_l3_clksel,
1236         .flags          = RATE_PROPAGATES,
1237         .clkdm_name     = "gfx_3430es1_clkdm",
1238         .recalc         = &omap2_clksel_recalc,
1239 };
1240
1241 static struct clk gfx_l3_ick = {
1242         .name           = "gfx_l3_ick",
1243         .ops            = &clkops_null,
1244         .parent         = &gfx_l3_ck,
1245         .clkdm_name     = "gfx_3430es1_clkdm",
1246         .recalc         = &followparent_recalc,
1247 };
1248
1249 static struct clk gfx_cg1_ck = {
1250         .name           = "gfx_cg1_ck",
1251         .ops            = &clkops_omap2_dflt_wait,
1252         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1253         .init           = &omap2_init_clk_clkdm,
1254         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1255         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1256         .clkdm_name     = "gfx_3430es1_clkdm",
1257         .recalc         = &followparent_recalc,
1258 };
1259
1260 static struct clk gfx_cg2_ck = {
1261         .name           = "gfx_cg2_ck",
1262         .ops            = &clkops_omap2_dflt_wait,
1263         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1264         .init           = &omap2_init_clk_clkdm,
1265         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1266         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1267         .clkdm_name     = "gfx_3430es1_clkdm",
1268         .recalc         = &followparent_recalc,
1269 };
1270
1271 /* SGX power domain - 3430ES2 only */
1272
1273 static const struct clksel_rate sgx_core_rates[] = {
1274         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1275         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1276         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1277         { .div = 0 },
1278 };
1279
1280 static const struct clksel_rate sgx_96m_rates[] = {
1281         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1282         { .div = 0 },
1283 };
1284
1285 static const struct clksel sgx_clksel[] = {
1286         { .parent = &core_ck,    .rates = sgx_core_rates },
1287         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1288         { .parent = NULL },
1289 };
1290
1291 static struct clk sgx_fck = {
1292         .name           = "sgx_fck",
1293         .ops            = &clkops_omap2_dflt_wait,
1294         .init           = &omap2_init_clksel_parent,
1295         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1296         .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1297         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1298         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1299         .clksel         = sgx_clksel,
1300         .clkdm_name     = "sgx_clkdm",
1301         .recalc         = &omap2_clksel_recalc,
1302 };
1303
1304 static struct clk sgx_ick = {
1305         .name           = "sgx_ick",
1306         .ops            = &clkops_omap2_dflt_wait,
1307         .parent         = &l3_ick,
1308         .init           = &omap2_init_clk_clkdm,
1309         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1310         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1311         .clkdm_name     = "sgx_clkdm",
1312         .recalc         = &followparent_recalc,
1313 };
1314
1315 /* CORE power domain */
1316
1317 static struct clk d2d_26m_fck = {
1318         .name           = "d2d_26m_fck",
1319         .ops            = &clkops_omap2_dflt_wait,
1320         .parent         = &sys_ck,
1321         .init           = &omap2_init_clk_clkdm,
1322         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1323         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1324         .clkdm_name     = "d2d_clkdm",
1325         .recalc         = &followparent_recalc,
1326 };
1327
1328 static const struct clksel omap343x_gpt_clksel[] = {
1329         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1330         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1331         { .parent = NULL}
1332 };
1333
1334 static struct clk gpt10_fck = {
1335         .name           = "gpt10_fck",
1336         .ops            = &clkops_omap2_dflt_wait,
1337         .parent         = &sys_ck,
1338         .init           = &omap2_init_clksel_parent,
1339         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1340         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1341         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1342         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1343         .clksel         = omap343x_gpt_clksel,
1344         .clkdm_name     = "core_l4_clkdm",
1345         .recalc         = &omap2_clksel_recalc,
1346 };
1347
1348 static struct clk gpt11_fck = {
1349         .name           = "gpt11_fck",
1350         .ops            = &clkops_omap2_dflt_wait,
1351         .parent         = &sys_ck,
1352         .init           = &omap2_init_clksel_parent,
1353         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1354         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1355         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1356         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1357         .clksel         = omap343x_gpt_clksel,
1358         .clkdm_name     = "core_l4_clkdm",
1359         .recalc         = &omap2_clksel_recalc,
1360 };
1361
1362 static struct clk cpefuse_fck = {
1363         .name           = "cpefuse_fck",
1364         .ops            = &clkops_omap2_dflt,
1365         .parent         = &sys_ck,
1366         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1367         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1368         .recalc         = &followparent_recalc,
1369 };
1370
1371 static struct clk ts_fck = {
1372         .name           = "ts_fck",
1373         .ops            = &clkops_omap2_dflt,
1374         .parent         = &omap_32k_fck,
1375         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1376         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1377         .recalc         = &followparent_recalc,
1378 };
1379
1380 static struct clk usbtll_fck = {
1381         .name           = "usbtll_fck",
1382         .ops            = &clkops_omap2_dflt,
1383         .parent         = &omap_120m_fck,
1384         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1385         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1386         .recalc         = &followparent_recalc,
1387 };
1388
1389 /* CORE 96M FCLK-derived clocks */
1390
1391 static struct clk core_96m_fck = {
1392         .name           = "core_96m_fck",
1393         .ops            = &clkops_null,
1394         .parent         = &omap_96m_fck,
1395         .flags          = RATE_PROPAGATES,
1396         .clkdm_name     = "core_l4_clkdm",
1397         .recalc         = &followparent_recalc,
1398 };
1399
1400 static struct clk mmchs3_fck = {
1401         .name           = "mmchs_fck",
1402         .ops            = &clkops_omap2_dflt_wait,
1403         .id             = 2,
1404         .parent         = &core_96m_fck,
1405         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1406         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1407         .clkdm_name     = "core_l4_clkdm",
1408         .recalc         = &followparent_recalc,
1409 };
1410
1411 static struct clk mmchs2_fck = {
1412         .name           = "mmchs_fck",
1413         .ops            = &clkops_omap2_dflt_wait,
1414         .id             = 1,
1415         .parent         = &core_96m_fck,
1416         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1417         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1418         .clkdm_name     = "core_l4_clkdm",
1419         .recalc         = &followparent_recalc,
1420 };
1421
1422 static struct clk mspro_fck = {
1423         .name           = "mspro_fck",
1424         .ops            = &clkops_omap2_dflt_wait,
1425         .parent         = &core_96m_fck,
1426         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1427         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1428         .clkdm_name     = "core_l4_clkdm",
1429         .recalc         = &followparent_recalc,
1430 };
1431
1432 static struct clk mmchs1_fck = {
1433         .name           = "mmchs_fck",
1434         .ops            = &clkops_omap2_dflt_wait,
1435         .parent         = &core_96m_fck,
1436         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1437         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1438         .clkdm_name     = "core_l4_clkdm",
1439         .recalc         = &followparent_recalc,
1440 };
1441
1442 static struct clk i2c3_fck = {
1443         .name           = "i2c_fck",
1444         .ops            = &clkops_omap2_dflt_wait,
1445         .id             = 3,
1446         .parent         = &core_96m_fck,
1447         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1448         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1449         .clkdm_name     = "core_l4_clkdm",
1450         .recalc         = &followparent_recalc,
1451 };
1452
1453 static struct clk i2c2_fck = {
1454         .name           = "i2c_fck",
1455         .ops            = &clkops_omap2_dflt_wait,
1456         .id             = 2,
1457         .parent         = &core_96m_fck,
1458         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1459         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1460         .clkdm_name     = "core_l4_clkdm",
1461         .recalc         = &followparent_recalc,
1462 };
1463
1464 static struct clk i2c1_fck = {
1465         .name           = "i2c_fck",
1466         .ops            = &clkops_omap2_dflt_wait,
1467         .id             = 1,
1468         .parent         = &core_96m_fck,
1469         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1470         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1471         .clkdm_name     = "core_l4_clkdm",
1472         .recalc         = &followparent_recalc,
1473 };
1474
1475 /*
1476  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1477  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1478  */
1479 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1480         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1481         { .div = 0 }
1482 };
1483
1484 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1485         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1486         { .div = 0 }
1487 };
1488
1489 static const struct clksel mcbsp_15_clksel[] = {
1490         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1491         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1492         { .parent = NULL }
1493 };
1494
1495 static struct clk mcbsp5_fck = {
1496         .name           = "mcbsp_fck",
1497         .ops            = &clkops_omap2_dflt_wait,
1498         .id             = 5,
1499         .init           = &omap2_init_clksel_parent,
1500         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1501         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1502         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1503         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1504         .clksel         = mcbsp_15_clksel,
1505         .clkdm_name     = "core_l4_clkdm",
1506         .recalc         = &omap2_clksel_recalc,
1507 };
1508
1509 static struct clk mcbsp1_fck = {
1510         .name           = "mcbsp_fck",
1511         .ops            = &clkops_omap2_dflt_wait,
1512         .id             = 1,
1513         .init           = &omap2_init_clksel_parent,
1514         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1515         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1516         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1517         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1518         .clksel         = mcbsp_15_clksel,
1519         .clkdm_name     = "core_l4_clkdm",
1520         .recalc         = &omap2_clksel_recalc,
1521 };
1522
1523 /* CORE_48M_FCK-derived clocks */
1524
1525 static struct clk core_48m_fck = {
1526         .name           = "core_48m_fck",
1527         .ops            = &clkops_null,
1528         .parent         = &omap_48m_fck,
1529         .flags          = RATE_PROPAGATES,
1530         .clkdm_name     = "core_l4_clkdm",
1531         .recalc         = &followparent_recalc,
1532 };
1533
1534 static struct clk mcspi4_fck = {
1535         .name           = "mcspi_fck",
1536         .ops            = &clkops_omap2_dflt_wait,
1537         .id             = 4,
1538         .parent         = &core_48m_fck,
1539         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1540         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1541         .recalc         = &followparent_recalc,
1542 };
1543
1544 static struct clk mcspi3_fck = {
1545         .name           = "mcspi_fck",
1546         .ops            = &clkops_omap2_dflt_wait,
1547         .id             = 3,
1548         .parent         = &core_48m_fck,
1549         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1550         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1551         .recalc         = &followparent_recalc,
1552 };
1553
1554 static struct clk mcspi2_fck = {
1555         .name           = "mcspi_fck",
1556         .ops            = &clkops_omap2_dflt_wait,
1557         .id             = 2,
1558         .parent         = &core_48m_fck,
1559         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1560         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1561         .recalc         = &followparent_recalc,
1562 };
1563
1564 static struct clk mcspi1_fck = {
1565         .name           = "mcspi_fck",
1566         .ops            = &clkops_omap2_dflt_wait,
1567         .id             = 1,
1568         .parent         = &core_48m_fck,
1569         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1570         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1571         .recalc         = &followparent_recalc,
1572 };
1573
1574 static struct clk uart2_fck = {
1575         .name           = "uart2_fck",
1576         .ops            = &clkops_omap2_dflt_wait,
1577         .parent         = &core_48m_fck,
1578         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1579         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1580         .recalc         = &followparent_recalc,
1581 };
1582
1583 static struct clk uart1_fck = {
1584         .name           = "uart1_fck",
1585         .ops            = &clkops_omap2_dflt_wait,
1586         .parent         = &core_48m_fck,
1587         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1588         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1589         .recalc         = &followparent_recalc,
1590 };
1591
1592 static struct clk fshostusb_fck = {
1593         .name           = "fshostusb_fck",
1594         .ops            = &clkops_omap2_dflt_wait,
1595         .parent         = &core_48m_fck,
1596         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1597         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1598         .recalc         = &followparent_recalc,
1599 };
1600
1601 /* CORE_12M_FCK based clocks */
1602
1603 static struct clk core_12m_fck = {
1604         .name           = "core_12m_fck",
1605         .ops            = &clkops_null,
1606         .parent         = &omap_12m_fck,
1607         .flags          = RATE_PROPAGATES,
1608         .clkdm_name     = "core_l4_clkdm",
1609         .recalc         = &followparent_recalc,
1610 };
1611
1612 static struct clk hdq_fck = {
1613         .name           = "hdq_fck",
1614         .ops            = &clkops_omap2_dflt_wait,
1615         .parent         = &core_12m_fck,
1616         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1617         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1618         .recalc         = &followparent_recalc,
1619 };
1620
1621 /* DPLL3-derived clock */
1622
1623 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1624         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1625         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1626         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1627         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1628         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1629         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1630         { .div = 0 }
1631 };
1632
1633 static const struct clksel ssi_ssr_clksel[] = {
1634         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1635         { .parent = NULL }
1636 };
1637
1638 static struct clk ssi_ssr_fck = {
1639         .name           = "ssi_ssr_fck",
1640         .ops            = &clkops_omap2_dflt,
1641         .init           = &omap2_init_clksel_parent,
1642         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1643         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1644         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1645         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1646         .clksel         = ssi_ssr_clksel,
1647         .flags          = RATE_PROPAGATES,
1648         .clkdm_name     = "core_l4_clkdm",
1649         .recalc         = &omap2_clksel_recalc,
1650 };
1651
1652 static struct clk ssi_sst_fck = {
1653         .name           = "ssi_sst_fck",
1654         .ops            = &clkops_null,
1655         .parent         = &ssi_ssr_fck,
1656         .fixed_div      = 2,
1657         .recalc         = &omap2_fixed_divisor_recalc,
1658 };
1659
1660
1661
1662 /* CORE_L3_ICK based clocks */
1663
1664 /*
1665  * XXX must add clk_enable/clk_disable for these if standard code won't
1666  * handle it
1667  */
1668 static struct clk core_l3_ick = {
1669         .name           = "core_l3_ick",
1670         .ops            = &clkops_null,
1671         .parent         = &l3_ick,
1672         .init           = &omap2_init_clk_clkdm,
1673         .flags          = RATE_PROPAGATES,
1674         .clkdm_name     = "core_l3_clkdm",
1675         .recalc         = &followparent_recalc,
1676 };
1677
1678 static struct clk hsotgusb_ick = {
1679         .name           = "hsotgusb_ick",
1680         .ops            = &clkops_omap2_dflt_wait,
1681         .parent         = &core_l3_ick,
1682         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1683         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1684         .clkdm_name     = "core_l3_clkdm",
1685         .recalc         = &followparent_recalc,
1686 };
1687
1688 static struct clk sdrc_ick = {
1689         .name           = "sdrc_ick",
1690         .ops            = &clkops_omap2_dflt_wait,
1691         .parent         = &core_l3_ick,
1692         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1693         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1694         .flags          = ENABLE_ON_INIT,
1695         .clkdm_name     = "core_l3_clkdm",
1696         .recalc         = &followparent_recalc,
1697 };
1698
1699 static struct clk gpmc_fck = {
1700         .name           = "gpmc_fck",
1701         .ops            = &clkops_null,
1702         .parent         = &core_l3_ick,
1703         .flags          = ENABLE_ON_INIT, /* huh? */
1704         .clkdm_name     = "core_l3_clkdm",
1705         .recalc         = &followparent_recalc,
1706 };
1707
1708 /* SECURITY_L3_ICK based clocks */
1709
1710 static struct clk security_l3_ick = {
1711         .name           = "security_l3_ick",
1712         .ops            = &clkops_null,
1713         .parent         = &l3_ick,
1714         .flags          = RATE_PROPAGATES,
1715         .recalc         = &followparent_recalc,
1716 };
1717
1718 static struct clk pka_ick = {
1719         .name           = "pka_ick",
1720         .ops            = &clkops_omap2_dflt_wait,
1721         .parent         = &security_l3_ick,
1722         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1723         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1724         .recalc         = &followparent_recalc,
1725 };
1726
1727 /* CORE_L4_ICK based clocks */
1728
1729 static struct clk core_l4_ick = {
1730         .name           = "core_l4_ick",
1731         .ops            = &clkops_null,
1732         .parent         = &l4_ick,
1733         .init           = &omap2_init_clk_clkdm,
1734         .flags          = RATE_PROPAGATES,
1735         .clkdm_name     = "core_l4_clkdm",
1736         .recalc         = &followparent_recalc,
1737 };
1738
1739 static struct clk usbtll_ick = {
1740         .name           = "usbtll_ick",
1741         .ops            = &clkops_omap2_dflt_wait,
1742         .parent         = &core_l4_ick,
1743         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1744         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1745         .clkdm_name     = "core_l4_clkdm",
1746         .recalc         = &followparent_recalc,
1747 };
1748
1749 static struct clk mmchs3_ick = {
1750         .name           = "mmchs_ick",
1751         .ops            = &clkops_omap2_dflt_wait,
1752         .id             = 2,
1753         .parent         = &core_l4_ick,
1754         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1755         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1756         .clkdm_name     = "core_l4_clkdm",
1757         .recalc         = &followparent_recalc,
1758 };
1759
1760 /* Intersystem Communication Registers - chassis mode only */
1761 static struct clk icr_ick = {
1762         .name           = "icr_ick",
1763         .ops            = &clkops_omap2_dflt_wait,
1764         .parent         = &core_l4_ick,
1765         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1766         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1767         .clkdm_name     = "core_l4_clkdm",
1768         .recalc         = &followparent_recalc,
1769 };
1770
1771 static struct clk aes2_ick = {
1772         .name           = "aes2_ick",
1773         .ops            = &clkops_omap2_dflt_wait,
1774         .parent         = &core_l4_ick,
1775         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1776         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1777         .clkdm_name     = "core_l4_clkdm",
1778         .recalc         = &followparent_recalc,
1779 };
1780
1781 static struct clk sha12_ick = {
1782         .name           = "sha12_ick",
1783         .ops            = &clkops_omap2_dflt_wait,
1784         .parent         = &core_l4_ick,
1785         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1786         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1787         .clkdm_name     = "core_l4_clkdm",
1788         .recalc         = &followparent_recalc,
1789 };
1790
1791 static struct clk des2_ick = {
1792         .name           = "des2_ick",
1793         .ops            = &clkops_omap2_dflt_wait,
1794         .parent         = &core_l4_ick,
1795         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1796         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1797         .clkdm_name     = "core_l4_clkdm",
1798         .recalc         = &followparent_recalc,
1799 };
1800
1801 static struct clk mmchs2_ick = {
1802         .name           = "mmchs_ick",
1803         .ops            = &clkops_omap2_dflt_wait,
1804         .id             = 1,
1805         .parent         = &core_l4_ick,
1806         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1807         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1808         .clkdm_name     = "core_l4_clkdm",
1809         .recalc         = &followparent_recalc,
1810 };
1811
1812 static struct clk mmchs1_ick = {
1813         .name           = "mmchs_ick",
1814         .ops            = &clkops_omap2_dflt_wait,
1815         .parent         = &core_l4_ick,
1816         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1817         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1818         .clkdm_name     = "core_l4_clkdm",
1819         .recalc         = &followparent_recalc,
1820 };
1821
1822 static struct clk mspro_ick = {
1823         .name           = "mspro_ick",
1824         .ops            = &clkops_omap2_dflt_wait,
1825         .parent         = &core_l4_ick,
1826         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1827         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1828         .clkdm_name     = "core_l4_clkdm",
1829         .recalc         = &followparent_recalc,
1830 };
1831
1832 static struct clk hdq_ick = {
1833         .name           = "hdq_ick",
1834         .ops            = &clkops_omap2_dflt_wait,
1835         .parent         = &core_l4_ick,
1836         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1837         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1838         .clkdm_name     = "core_l4_clkdm",
1839         .recalc         = &followparent_recalc,
1840 };
1841
1842 static struct clk mcspi4_ick = {
1843         .name           = "mcspi_ick",
1844         .ops            = &clkops_omap2_dflt_wait,
1845         .id             = 4,
1846         .parent         = &core_l4_ick,
1847         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1848         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1849         .clkdm_name     = "core_l4_clkdm",
1850         .recalc         = &followparent_recalc,
1851 };
1852
1853 static struct clk mcspi3_ick = {
1854         .name           = "mcspi_ick",
1855         .ops            = &clkops_omap2_dflt_wait,
1856         .id             = 3,
1857         .parent         = &core_l4_ick,
1858         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1859         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1860         .clkdm_name     = "core_l4_clkdm",
1861         .recalc         = &followparent_recalc,
1862 };
1863
1864 static struct clk mcspi2_ick = {
1865         .name           = "mcspi_ick",
1866         .ops            = &clkops_omap2_dflt_wait,
1867         .id             = 2,
1868         .parent         = &core_l4_ick,
1869         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1870         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1871         .clkdm_name     = "core_l4_clkdm",
1872         .recalc         = &followparent_recalc,
1873 };
1874
1875 static struct clk mcspi1_ick = {
1876         .name           = "mcspi_ick",
1877         .ops            = &clkops_omap2_dflt_wait,
1878         .id             = 1,
1879         .parent         = &core_l4_ick,
1880         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1881         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1882         .clkdm_name     = "core_l4_clkdm",
1883         .recalc         = &followparent_recalc,
1884 };
1885
1886 static struct clk i2c3_ick = {
1887         .name           = "i2c_ick",
1888         .ops            = &clkops_omap2_dflt_wait,
1889         .id             = 3,
1890         .parent         = &core_l4_ick,
1891         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1892         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1893         .clkdm_name     = "core_l4_clkdm",
1894         .recalc         = &followparent_recalc,
1895 };
1896
1897 static struct clk i2c2_ick = {
1898         .name           = "i2c_ick",
1899         .ops            = &clkops_omap2_dflt_wait,
1900         .id             = 2,
1901         .parent         = &core_l4_ick,
1902         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1903         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1904         .clkdm_name     = "core_l4_clkdm",
1905         .recalc         = &followparent_recalc,
1906 };
1907
1908 static struct clk i2c1_ick = {
1909         .name           = "i2c_ick",
1910         .ops            = &clkops_omap2_dflt_wait,
1911         .id             = 1,
1912         .parent         = &core_l4_ick,
1913         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1914         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1915         .clkdm_name     = "core_l4_clkdm",
1916         .recalc         = &followparent_recalc,
1917 };
1918
1919 static struct clk uart2_ick = {
1920         .name           = "uart2_ick",
1921         .ops            = &clkops_omap2_dflt_wait,
1922         .parent         = &core_l4_ick,
1923         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1924         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1925         .clkdm_name     = "core_l4_clkdm",
1926         .recalc         = &followparent_recalc,
1927 };
1928
1929 static struct clk uart1_ick = {
1930         .name           = "uart1_ick",
1931         .ops            = &clkops_omap2_dflt_wait,
1932         .parent         = &core_l4_ick,
1933         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1934         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1935         .clkdm_name     = "core_l4_clkdm",
1936         .recalc         = &followparent_recalc,
1937 };
1938
1939 static struct clk gpt11_ick = {
1940         .name           = "gpt11_ick",
1941         .ops            = &clkops_omap2_dflt_wait,
1942         .parent         = &core_l4_ick,
1943         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1944         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1945         .clkdm_name     = "core_l4_clkdm",
1946         .recalc         = &followparent_recalc,
1947 };
1948
1949 static struct clk gpt10_ick = {
1950         .name           = "gpt10_ick",
1951         .ops            = &clkops_omap2_dflt_wait,
1952         .parent         = &core_l4_ick,
1953         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1954         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1955         .clkdm_name     = "core_l4_clkdm",
1956         .recalc         = &followparent_recalc,
1957 };
1958
1959 static struct clk mcbsp5_ick = {
1960         .name           = "mcbsp_ick",
1961         .ops            = &clkops_omap2_dflt_wait,
1962         .id             = 5,
1963         .parent         = &core_l4_ick,
1964         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1965         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1966         .clkdm_name     = "core_l4_clkdm",
1967         .recalc         = &followparent_recalc,
1968 };
1969
1970 static struct clk mcbsp1_ick = {
1971         .name           = "mcbsp_ick",
1972         .ops            = &clkops_omap2_dflt_wait,
1973         .id             = 1,
1974         .parent         = &core_l4_ick,
1975         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1976         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1977         .clkdm_name     = "core_l4_clkdm",
1978         .recalc         = &followparent_recalc,
1979 };
1980
1981 static struct clk fac_ick = {
1982         .name           = "fac_ick",
1983         .ops            = &clkops_omap2_dflt_wait,
1984         .parent         = &core_l4_ick,
1985         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1986         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1987         .clkdm_name     = "core_l4_clkdm",
1988         .recalc         = &followparent_recalc,
1989 };
1990
1991 static struct clk mailboxes_ick = {
1992         .name           = "mailboxes_ick",
1993         .ops            = &clkops_omap2_dflt_wait,
1994         .parent         = &core_l4_ick,
1995         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1996         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
1997         .clkdm_name     = "core_l4_clkdm",
1998         .recalc         = &followparent_recalc,
1999 };
2000
2001 static struct clk omapctrl_ick = {
2002         .name           = "omapctrl_ick",
2003         .ops            = &clkops_omap2_dflt_wait,
2004         .parent         = &core_l4_ick,
2005         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2006         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2007         .flags          = ENABLE_ON_INIT,
2008         .recalc         = &followparent_recalc,
2009 };
2010
2011 /* SSI_L4_ICK based clocks */
2012
2013 static struct clk ssi_l4_ick = {
2014         .name           = "ssi_l4_ick",
2015         .ops            = &clkops_null,
2016         .parent         = &l4_ick,
2017         .flags          = RATE_PROPAGATES,
2018         .clkdm_name     = "core_l4_clkdm",
2019         .recalc         = &followparent_recalc,
2020 };
2021
2022 static struct clk ssi_ick = {
2023         .name           = "ssi_ick",
2024         .ops            = &clkops_omap2_dflt,
2025         .parent         = &ssi_l4_ick,
2026         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2027         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2028         .clkdm_name     = "core_l4_clkdm",
2029         .recalc         = &followparent_recalc,
2030 };
2031
2032 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2033  * but l4_ick makes more sense to me */
2034
2035 static const struct clksel usb_l4_clksel[] = {
2036         { .parent = &l4_ick, .rates = div2_rates },
2037         { .parent = NULL },
2038 };
2039
2040 static struct clk usb_l4_ick = {
2041         .name           = "usb_l4_ick",
2042         .ops            = &clkops_omap2_dflt_wait,
2043         .parent         = &l4_ick,
2044         .init           = &omap2_init_clksel_parent,
2045         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2046         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2047         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2048         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2049         .clksel         = usb_l4_clksel,
2050         .recalc         = &omap2_clksel_recalc,
2051 };
2052
2053 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2054
2055 /* SECURITY_L4_ICK2 based clocks */
2056
2057 static struct clk security_l4_ick2 = {
2058         .name           = "security_l4_ick2",
2059         .ops            = &clkops_null,
2060         .parent         = &l4_ick,
2061         .flags          = RATE_PROPAGATES,
2062         .recalc         = &followparent_recalc,
2063 };
2064
2065 static struct clk aes1_ick = {
2066         .name           = "aes1_ick",
2067         .ops            = &clkops_omap2_dflt_wait,
2068         .parent         = &security_l4_ick2,
2069         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2070         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2071         .recalc         = &followparent_recalc,
2072 };
2073
2074 static struct clk rng_ick = {
2075         .name           = "rng_ick",
2076         .ops            = &clkops_omap2_dflt_wait,
2077         .parent         = &security_l4_ick2,
2078         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2079         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2080         .recalc         = &followparent_recalc,
2081 };
2082
2083 static struct clk sha11_ick = {
2084         .name           = "sha11_ick",
2085         .ops            = &clkops_omap2_dflt_wait,
2086         .parent         = &security_l4_ick2,
2087         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2088         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2089         .recalc         = &followparent_recalc,
2090 };
2091
2092 static struct clk des1_ick = {
2093         .name           = "des1_ick",
2094         .ops            = &clkops_omap2_dflt_wait,
2095         .parent         = &security_l4_ick2,
2096         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2097         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2098         .recalc         = &followparent_recalc,
2099 };
2100
2101 /* DSS */
2102 static const struct clksel dss1_alwon_fck_clksel[] = {
2103         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2104         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2105         { .parent = NULL }
2106 };
2107
2108 static struct clk dss1_alwon_fck = {
2109         .name           = "dss1_alwon_fck",
2110         .ops            = &clkops_omap2_dflt,
2111         .parent         = &dpll4_m4x2_ck,
2112         .init           = &omap2_init_clksel_parent,
2113         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2114         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2115         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2116         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2117         .clksel         = dss1_alwon_fck_clksel,
2118         .clkdm_name     = "dss_clkdm",
2119         .recalc         = &omap2_clksel_recalc,
2120 };
2121
2122 static struct clk dss_tv_fck = {
2123         .name           = "dss_tv_fck",
2124         .ops            = &clkops_omap2_dflt,
2125         .parent         = &omap_54m_fck,
2126         .init           = &omap2_init_clk_clkdm,
2127         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2128         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2129         .clkdm_name     = "dss_clkdm",
2130         .recalc         = &followparent_recalc,
2131 };
2132
2133 static struct clk dss_96m_fck = {
2134         .name           = "dss_96m_fck",
2135         .ops            = &clkops_omap2_dflt,
2136         .parent         = &omap_96m_fck,
2137         .init           = &omap2_init_clk_clkdm,
2138         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2139         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2140         .clkdm_name     = "dss_clkdm",
2141         .recalc         = &followparent_recalc,
2142 };
2143
2144 static struct clk dss2_alwon_fck = {
2145         .name           = "dss2_alwon_fck",
2146         .ops            = &clkops_omap2_dflt,
2147         .parent         = &sys_ck,
2148         .init           = &omap2_init_clk_clkdm,
2149         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2150         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2151         .clkdm_name     = "dss_clkdm",
2152         .recalc         = &followparent_recalc,
2153 };
2154
2155 static struct clk dss_ick = {
2156         /* Handles both L3 and L4 clocks */
2157         .name           = "dss_ick",
2158         .ops            = &clkops_omap2_dflt,
2159         .parent         = &l4_ick,
2160         .init           = &omap2_init_clk_clkdm,
2161         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2162         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2163         .clkdm_name     = "dss_clkdm",
2164         .recalc         = &followparent_recalc,
2165 };
2166
2167 /* CAM */
2168
2169 static const struct clksel cam_mclk_clksel[] = {
2170         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2171         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2172         { .parent = NULL }
2173 };
2174
2175 static struct clk cam_mclk = {
2176         .name           = "cam_mclk",
2177         .ops            = &clkops_omap2_dflt_wait,
2178         .parent         = &dpll4_m5x2_ck,
2179         .init           = &omap2_init_clksel_parent,
2180         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2181         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2182         .clksel         = cam_mclk_clksel,
2183         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2184         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2185         .clkdm_name     = "cam_clkdm",
2186         .recalc         = &omap2_clksel_recalc,
2187 };
2188
2189 static struct clk cam_ick = {
2190         /* Handles both L3 and L4 clocks */
2191         .name           = "cam_ick",
2192         .ops            = &clkops_omap2_dflt_wait,
2193         .parent         = &l4_ick,
2194         .init           = &omap2_init_clk_clkdm,
2195         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2196         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2197         .clkdm_name     = "cam_clkdm",
2198         .recalc         = &followparent_recalc,
2199 };
2200
2201 static struct clk csi2_96m_fck = {
2202         .name           = "csi2_96m_fck",
2203         .ops            = &clkops_omap2_dflt_wait,
2204         .parent         = &core_96m_fck,
2205         .init           = &omap2_init_clk_clkdm,
2206         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2207         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2208         .clkdm_name     = "cam_clkdm",
2209         .recalc         = &followparent_recalc,
2210 };
2211
2212 /* USBHOST - 3430ES2 only */
2213
2214 static struct clk usbhost_120m_fck = {
2215         .name           = "usbhost_120m_fck",
2216         .ops            = &clkops_omap2_dflt_wait,
2217         .parent         = &omap_120m_fck,
2218         .init           = &omap2_init_clk_clkdm,
2219         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2220         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2221         .clkdm_name     = "usbhost_clkdm",
2222         .recalc         = &followparent_recalc,
2223 };
2224
2225 static struct clk usbhost_48m_fck = {
2226         .name           = "usbhost_48m_fck",
2227         .ops            = &clkops_omap2_dflt_wait,
2228         .parent         = &omap_48m_fck,
2229         .init           = &omap2_init_clk_clkdm,
2230         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2231         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2232         .clkdm_name     = "usbhost_clkdm",
2233         .recalc         = &followparent_recalc,
2234 };
2235
2236 static struct clk usbhost_ick = {
2237         /* Handles both L3 and L4 clocks */
2238         .name           = "usbhost_ick",
2239         .ops            = &clkops_omap2_dflt_wait,
2240         .parent         = &l4_ick,
2241         .init           = &omap2_init_clk_clkdm,
2242         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2243         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2244         .clkdm_name     = "usbhost_clkdm",
2245         .recalc         = &followparent_recalc,
2246 };
2247
2248 /* WKUP */
2249
2250 static const struct clksel_rate usim_96m_rates[] = {
2251         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2252         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2253         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2254         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2255         { .div = 0 },
2256 };
2257
2258 static const struct clksel_rate usim_120m_rates[] = {
2259         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2260         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2261         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2262         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2263         { .div = 0 },
2264 };
2265
2266 static const struct clksel usim_clksel[] = {
2267         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2268         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2269         { .parent = &sys_ck,            .rates = div2_rates },
2270         { .parent = NULL },
2271 };
2272
2273 /* 3430ES2 only */
2274 static struct clk usim_fck = {
2275         .name           = "usim_fck",
2276         .ops            = &clkops_omap2_dflt_wait,
2277         .init           = &omap2_init_clksel_parent,
2278         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2279         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2280         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2281         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2282         .clksel         = usim_clksel,
2283         .recalc         = &omap2_clksel_recalc,
2284 };
2285
2286 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2287 static struct clk gpt1_fck = {
2288         .name           = "gpt1_fck",
2289         .ops            = &clkops_omap2_dflt_wait,
2290         .init           = &omap2_init_clksel_parent,
2291         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2292         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2293         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2294         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2295         .clksel         = omap343x_gpt_clksel,
2296         .clkdm_name     = "wkup_clkdm",
2297         .recalc         = &omap2_clksel_recalc,
2298 };
2299
2300 static struct clk wkup_32k_fck = {
2301         .name           = "wkup_32k_fck",
2302         .ops            = &clkops_null,
2303         .init           = &omap2_init_clk_clkdm,
2304         .parent         = &omap_32k_fck,
2305         .flags          = RATE_PROPAGATES,
2306         .clkdm_name     = "wkup_clkdm",
2307         .recalc         = &followparent_recalc,
2308 };
2309
2310 static struct clk gpio1_dbck = {
2311         .name           = "gpio1_dbck",
2312         .ops            = &clkops_omap2_dflt_wait,
2313         .parent         = &wkup_32k_fck,
2314         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2315         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2316         .clkdm_name     = "wkup_clkdm",
2317         .recalc         = &followparent_recalc,
2318 };
2319
2320 static struct clk wdt2_fck = {
2321         .name           = "wdt2_fck",
2322         .ops            = &clkops_omap2_dflt_wait,
2323         .parent         = &wkup_32k_fck,
2324         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2325         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2326         .clkdm_name     = "wkup_clkdm",
2327         .recalc         = &followparent_recalc,
2328 };
2329
2330 static struct clk wkup_l4_ick = {
2331         .name           = "wkup_l4_ick",
2332         .ops            = &clkops_null,
2333         .parent         = &sys_ck,
2334         .flags          = RATE_PROPAGATES,
2335         .clkdm_name     = "wkup_clkdm",
2336         .recalc         = &followparent_recalc,
2337 };
2338
2339 /* 3430ES2 only */
2340 /* Never specifically named in the TRM, so we have to infer a likely name */
2341 static struct clk usim_ick = {
2342         .name           = "usim_ick",
2343         .ops            = &clkops_omap2_dflt_wait,
2344         .parent         = &wkup_l4_ick,
2345         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2346         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2347         .clkdm_name     = "wkup_clkdm",
2348         .recalc         = &followparent_recalc,
2349 };
2350
2351 static struct clk wdt2_ick = {
2352         .name           = "wdt2_ick",
2353         .ops            = &clkops_omap2_dflt_wait,
2354         .parent         = &wkup_l4_ick,
2355         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2356         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2357         .clkdm_name     = "wkup_clkdm",
2358         .recalc         = &followparent_recalc,
2359 };
2360
2361 static struct clk wdt1_ick = {
2362         .name           = "wdt1_ick",
2363         .ops            = &clkops_omap2_dflt_wait,
2364         .parent         = &wkup_l4_ick,
2365         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2366         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2367         .clkdm_name     = "wkup_clkdm",
2368         .recalc         = &followparent_recalc,
2369 };
2370
2371 static struct clk gpio1_ick = {
2372         .name           = "gpio1_ick",
2373         .ops            = &clkops_omap2_dflt_wait,
2374         .parent         = &wkup_l4_ick,
2375         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2376         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2377         .clkdm_name     = "wkup_clkdm",
2378         .recalc         = &followparent_recalc,
2379 };
2380
2381 static struct clk omap_32ksync_ick = {
2382         .name           = "omap_32ksync_ick",
2383         .ops            = &clkops_omap2_dflt_wait,
2384         .parent         = &wkup_l4_ick,
2385         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2386         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2387         .clkdm_name     = "wkup_clkdm",
2388         .recalc         = &followparent_recalc,
2389 };
2390
2391 /* XXX This clock no longer exists in 3430 TRM rev F */
2392 static struct clk gpt12_ick = {
2393         .name           = "gpt12_ick",
2394         .ops            = &clkops_omap2_dflt_wait,
2395         .parent         = &wkup_l4_ick,
2396         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2397         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2398         .clkdm_name     = "wkup_clkdm",
2399         .recalc         = &followparent_recalc,
2400 };
2401
2402 static struct clk gpt1_ick = {
2403         .name           = "gpt1_ick",
2404         .ops            = &clkops_omap2_dflt_wait,
2405         .parent         = &wkup_l4_ick,
2406         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2407         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2408         .clkdm_name     = "wkup_clkdm",
2409         .recalc         = &followparent_recalc,
2410 };
2411
2412
2413
2414 /* PER clock domain */
2415
2416 static struct clk per_96m_fck = {
2417         .name           = "per_96m_fck",
2418         .ops            = &clkops_null,
2419         .parent         = &omap_96m_alwon_fck,
2420         .init           = &omap2_init_clk_clkdm,
2421         .flags          = RATE_PROPAGATES,
2422         .clkdm_name     = "per_clkdm",
2423         .recalc         = &followparent_recalc,
2424 };
2425
2426 static struct clk per_48m_fck = {
2427         .name           = "per_48m_fck",
2428         .ops            = &clkops_null,
2429         .parent         = &omap_48m_fck,
2430         .init           = &omap2_init_clk_clkdm,
2431         .flags          = RATE_PROPAGATES,
2432         .clkdm_name     = "per_clkdm",
2433         .recalc         = &followparent_recalc,
2434 };
2435
2436 static struct clk uart3_fck = {
2437         .name           = "uart3_fck",
2438         .ops            = &clkops_omap2_dflt_wait,
2439         .parent         = &per_48m_fck,
2440         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2441         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2442         .clkdm_name     = "per_clkdm",
2443         .recalc         = &followparent_recalc,
2444 };
2445
2446 static struct clk gpt2_fck = {
2447         .name           = "gpt2_fck",
2448         .ops            = &clkops_omap2_dflt_wait,
2449         .init           = &omap2_init_clksel_parent,
2450         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2451         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2452         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2453         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2454         .clksel         = omap343x_gpt_clksel,
2455         .clkdm_name     = "per_clkdm",
2456         .recalc         = &omap2_clksel_recalc,
2457 };
2458
2459 static struct clk gpt3_fck = {
2460         .name           = "gpt3_fck",
2461         .ops            = &clkops_omap2_dflt_wait,
2462         .init           = &omap2_init_clksel_parent,
2463         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2464         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2465         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2466         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2467         .clksel         = omap343x_gpt_clksel,
2468         .clkdm_name     = "per_clkdm",
2469         .recalc         = &omap2_clksel_recalc,
2470 };
2471
2472 static struct clk gpt4_fck = {
2473         .name           = "gpt4_fck",
2474         .ops            = &clkops_omap2_dflt_wait,
2475         .init           = &omap2_init_clksel_parent,
2476         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2477         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2478         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2479         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2480         .clksel         = omap343x_gpt_clksel,
2481         .clkdm_name     = "per_clkdm",
2482         .recalc         = &omap2_clksel_recalc,
2483 };
2484
2485 static struct clk gpt5_fck = {
2486         .name           = "gpt5_fck",
2487         .ops            = &clkops_omap2_dflt_wait,
2488         .init           = &omap2_init_clksel_parent,
2489         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2490         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2491         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2492         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2493         .clksel         = omap343x_gpt_clksel,
2494         .clkdm_name     = "per_clkdm",
2495         .recalc         = &omap2_clksel_recalc,
2496 };
2497
2498 static struct clk gpt6_fck = {
2499         .name           = "gpt6_fck",
2500         .ops            = &clkops_omap2_dflt_wait,
2501         .init           = &omap2_init_clksel_parent,
2502         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2503         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2504         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2505         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2506         .clksel         = omap343x_gpt_clksel,
2507         .clkdm_name     = "per_clkdm",
2508         .recalc         = &omap2_clksel_recalc,
2509 };
2510
2511 static struct clk gpt7_fck = {
2512         .name           = "gpt7_fck",
2513         .ops            = &clkops_omap2_dflt_wait,
2514         .init           = &omap2_init_clksel_parent,
2515         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2516         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2517         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2518         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2519         .clksel         = omap343x_gpt_clksel,
2520         .clkdm_name     = "per_clkdm",
2521         .recalc         = &omap2_clksel_recalc,
2522 };
2523
2524 static struct clk gpt8_fck = {
2525         .name           = "gpt8_fck",
2526         .ops            = &clkops_omap2_dflt_wait,
2527         .init           = &omap2_init_clksel_parent,
2528         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2529         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2530         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2531         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2532         .clksel         = omap343x_gpt_clksel,
2533         .clkdm_name     = "per_clkdm",
2534         .recalc         = &omap2_clksel_recalc,
2535 };
2536
2537 static struct clk gpt9_fck = {
2538         .name           = "gpt9_fck",
2539         .ops            = &clkops_omap2_dflt_wait,
2540         .init           = &omap2_init_clksel_parent,
2541         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2542         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2543         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2544         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2545         .clksel         = omap343x_gpt_clksel,
2546         .clkdm_name     = "per_clkdm",
2547         .recalc         = &omap2_clksel_recalc,
2548 };
2549
2550 static struct clk per_32k_alwon_fck = {
2551         .name           = "per_32k_alwon_fck",
2552         .ops            = &clkops_null,
2553         .parent         = &omap_32k_fck,
2554         .clkdm_name     = "per_clkdm",
2555         .flags          = RATE_PROPAGATES,
2556         .recalc         = &followparent_recalc,
2557 };
2558
2559 static struct clk gpio6_dbck = {
2560         .name           = "gpio6_dbck",
2561         .ops            = &clkops_omap2_dflt_wait,
2562         .parent         = &per_32k_alwon_fck,
2563         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2564         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2565         .clkdm_name     = "per_clkdm",
2566         .recalc         = &followparent_recalc,
2567 };
2568
2569 static struct clk gpio5_dbck = {
2570         .name           = "gpio5_dbck",
2571         .ops            = &clkops_omap2_dflt_wait,
2572         .parent         = &per_32k_alwon_fck,
2573         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2574         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2575         .clkdm_name     = "per_clkdm",
2576         .recalc         = &followparent_recalc,
2577 };
2578
2579 static struct clk gpio4_dbck = {
2580         .name           = "gpio4_dbck",
2581         .ops            = &clkops_omap2_dflt_wait,
2582         .parent         = &per_32k_alwon_fck,
2583         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2584         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2585         .clkdm_name     = "per_clkdm",
2586         .recalc         = &followparent_recalc,
2587 };
2588
2589 static struct clk gpio3_dbck = {
2590         .name           = "gpio3_dbck",
2591         .ops            = &clkops_omap2_dflt_wait,
2592         .parent         = &per_32k_alwon_fck,
2593         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2594         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2595         .clkdm_name     = "per_clkdm",
2596         .recalc         = &followparent_recalc,
2597 };
2598
2599 static struct clk gpio2_dbck = {
2600         .name           = "gpio2_dbck",
2601         .ops            = &clkops_omap2_dflt_wait,
2602         .parent         = &per_32k_alwon_fck,
2603         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2604         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2605         .clkdm_name     = "per_clkdm",
2606         .recalc         = &followparent_recalc,
2607 };
2608
2609 static struct clk wdt3_fck = {
2610         .name           = "wdt3_fck",
2611         .ops            = &clkops_omap2_dflt_wait,
2612         .parent         = &per_32k_alwon_fck,
2613         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2614         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2615         .clkdm_name     = "per_clkdm",
2616         .recalc         = &followparent_recalc,
2617 };
2618
2619 static struct clk per_l4_ick = {
2620         .name           = "per_l4_ick",
2621         .ops            = &clkops_null,
2622         .parent         = &l4_ick,
2623         .flags          = RATE_PROPAGATES,
2624         .clkdm_name     = "per_clkdm",
2625         .recalc         = &followparent_recalc,
2626 };
2627
2628 static struct clk gpio6_ick = {
2629         .name           = "gpio6_ick",
2630         .ops            = &clkops_omap2_dflt_wait,
2631         .parent         = &per_l4_ick,
2632         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2633         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2634         .clkdm_name     = "per_clkdm",
2635         .recalc         = &followparent_recalc,
2636 };
2637
2638 static struct clk gpio5_ick = {
2639         .name           = "gpio5_ick",
2640         .ops            = &clkops_omap2_dflt_wait,
2641         .parent         = &per_l4_ick,
2642         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2643         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2644         .clkdm_name     = "per_clkdm",
2645         .recalc         = &followparent_recalc,
2646 };
2647
2648 static struct clk gpio4_ick = {
2649         .name           = "gpio4_ick",
2650         .ops            = &clkops_omap2_dflt_wait,
2651         .parent         = &per_l4_ick,
2652         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2653         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2654         .clkdm_name     = "per_clkdm",
2655         .recalc         = &followparent_recalc,
2656 };
2657
2658 static struct clk gpio3_ick = {
2659         .name           = "gpio3_ick",
2660         .ops            = &clkops_omap2_dflt_wait,
2661         .parent         = &per_l4_ick,
2662         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2663         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2664         .clkdm_name     = "per_clkdm",
2665         .recalc         = &followparent_recalc,
2666 };
2667
2668 static struct clk gpio2_ick = {
2669         .name           = "gpio2_ick",
2670         .ops            = &clkops_omap2_dflt_wait,
2671         .parent         = &per_l4_ick,
2672         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2673         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2674         .clkdm_name     = "per_clkdm",
2675         .recalc         = &followparent_recalc,
2676 };
2677
2678 static struct clk wdt3_ick = {
2679         .name           = "wdt3_ick",
2680         .ops            = &clkops_omap2_dflt_wait,
2681         .parent         = &per_l4_ick,
2682         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2683         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2684         .clkdm_name     = "per_clkdm",
2685         .recalc         = &followparent_recalc,
2686 };
2687
2688 static struct clk uart3_ick = {
2689         .name           = "uart3_ick",
2690         .ops            = &clkops_omap2_dflt_wait,
2691         .parent         = &per_l4_ick,
2692         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2693         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2694         .clkdm_name     = "per_clkdm",
2695         .recalc         = &followparent_recalc,
2696 };
2697
2698 static struct clk gpt9_ick = {
2699         .name           = "gpt9_ick",
2700         .ops            = &clkops_omap2_dflt_wait,
2701         .parent         = &per_l4_ick,
2702         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2703         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2704         .clkdm_name     = "per_clkdm",
2705         .recalc         = &followparent_recalc,
2706 };
2707
2708 static struct clk gpt8_ick = {
2709         .name           = "gpt8_ick",
2710         .ops            = &clkops_omap2_dflt_wait,
2711         .parent         = &per_l4_ick,
2712         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2713         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2714         .clkdm_name     = "per_clkdm",
2715         .recalc         = &followparent_recalc,
2716 };
2717
2718 static struct clk gpt7_ick = {
2719         .name           = "gpt7_ick",
2720         .ops            = &clkops_omap2_dflt_wait,
2721         .parent         = &per_l4_ick,
2722         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2723         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2724         .clkdm_name     = "per_clkdm",
2725         .recalc         = &followparent_recalc,
2726 };
2727
2728 static struct clk gpt6_ick = {
2729         .name           = "gpt6_ick",
2730         .ops            = &clkops_omap2_dflt_wait,
2731         .parent         = &per_l4_ick,
2732         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2733         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2734         .clkdm_name     = "per_clkdm",
2735         .recalc         = &followparent_recalc,
2736 };
2737
2738 static struct clk gpt5_ick = {
2739         .name           = "gpt5_ick",
2740         .ops            = &clkops_omap2_dflt_wait,
2741         .parent         = &per_l4_ick,
2742         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2743         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2744         .clkdm_name     = "per_clkdm",
2745         .recalc         = &followparent_recalc,
2746 };
2747
2748 static struct clk gpt4_ick = {
2749         .name           = "gpt4_ick",
2750         .ops            = &clkops_omap2_dflt_wait,
2751         .parent         = &per_l4_ick,
2752         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2753         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2754         .clkdm_name     = "per_clkdm",
2755         .recalc         = &followparent_recalc,
2756 };
2757
2758 static struct clk gpt3_ick = {
2759         .name           = "gpt3_ick",
2760         .ops            = &clkops_omap2_dflt_wait,
2761         .parent         = &per_l4_ick,
2762         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2763         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2764         .clkdm_name     = "per_clkdm",
2765         .recalc         = &followparent_recalc,
2766 };
2767
2768 static struct clk gpt2_ick = {
2769         .name           = "gpt2_ick",
2770         .ops            = &clkops_omap2_dflt_wait,
2771         .parent         = &per_l4_ick,
2772         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2773         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2774         .clkdm_name     = "per_clkdm",
2775         .recalc         = &followparent_recalc,
2776 };
2777
2778 static struct clk mcbsp2_ick = {
2779         .name           = "mcbsp_ick",
2780         .ops            = &clkops_omap2_dflt_wait,
2781         .id             = 2,
2782         .parent         = &per_l4_ick,
2783         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2784         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2785         .clkdm_name     = "per_clkdm",
2786         .recalc         = &followparent_recalc,
2787 };
2788
2789 static struct clk mcbsp3_ick = {
2790         .name           = "mcbsp_ick",
2791         .ops            = &clkops_omap2_dflt_wait,
2792         .id             = 3,
2793         .parent         = &per_l4_ick,
2794         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2795         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2796         .clkdm_name     = "per_clkdm",
2797         .recalc         = &followparent_recalc,
2798 };
2799
2800 static struct clk mcbsp4_ick = {
2801         .name           = "mcbsp_ick",
2802         .ops            = &clkops_omap2_dflt_wait,
2803         .id             = 4,
2804         .parent         = &per_l4_ick,
2805         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2806         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2807         .clkdm_name     = "per_clkdm",
2808         .recalc         = &followparent_recalc,
2809 };
2810
2811 static const struct clksel mcbsp_234_clksel[] = {
2812         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2813         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2814         { .parent = NULL }
2815 };
2816
2817 static struct clk mcbsp2_fck = {
2818         .name           = "mcbsp_fck",
2819         .ops            = &clkops_omap2_dflt_wait,
2820         .id             = 2,
2821         .init           = &omap2_init_clksel_parent,
2822         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2823         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2824         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2825         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2826         .clksel         = mcbsp_234_clksel,
2827         .clkdm_name     = "per_clkdm",
2828         .recalc         = &omap2_clksel_recalc,
2829 };
2830
2831 static struct clk mcbsp3_fck = {
2832         .name           = "mcbsp_fck",
2833         .ops            = &clkops_omap2_dflt_wait,
2834         .id             = 3,
2835         .init           = &omap2_init_clksel_parent,
2836         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2837         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2838         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2839         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2840         .clksel         = mcbsp_234_clksel,
2841         .clkdm_name     = "per_clkdm",
2842         .recalc         = &omap2_clksel_recalc,
2843 };
2844
2845 static struct clk mcbsp4_fck = {
2846         .name           = "mcbsp_fck",
2847         .ops            = &clkops_omap2_dflt_wait,
2848         .id             = 4,
2849         .init           = &omap2_init_clksel_parent,
2850         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2851         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2852         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2853         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2854         .clksel         = mcbsp_234_clksel,
2855         .clkdm_name     = "per_clkdm",
2856         .recalc         = &omap2_clksel_recalc,
2857 };
2858
2859 /* EMU clocks */
2860
2861 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2862
2863 static const struct clksel_rate emu_src_sys_rates[] = {
2864         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2865         { .div = 0 },
2866 };
2867
2868 static const struct clksel_rate emu_src_core_rates[] = {
2869         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2870         { .div = 0 },
2871 };
2872
2873 static const struct clksel_rate emu_src_per_rates[] = {
2874         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2875         { .div = 0 },
2876 };
2877
2878 static const struct clksel_rate emu_src_mpu_rates[] = {
2879         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2880         { .div = 0 },
2881 };
2882
2883 static const struct clksel emu_src_clksel[] = {
2884         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2885         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2886         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2887         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2888         { .parent = NULL },
2889 };
2890
2891 /*
2892  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2893  * to switch the source of some of the EMU clocks.
2894  * XXX Are there CLKEN bits for these EMU clks?
2895  */
2896 static struct clk emu_src_ck = {
2897         .name           = "emu_src_ck",
2898         .ops            = &clkops_null,
2899         .init           = &omap2_init_clksel_parent,
2900         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2901         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2902         .clksel         = emu_src_clksel,
2903         .flags          = RATE_PROPAGATES,
2904         .clkdm_name     = "emu_clkdm",
2905         .recalc         = &omap2_clksel_recalc,
2906 };
2907
2908 static const struct clksel_rate pclk_emu_rates[] = {
2909         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2910         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2911         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2912         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2913         { .div = 0 },
2914 };
2915
2916 static const struct clksel pclk_emu_clksel[] = {
2917         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2918         { .parent = NULL },
2919 };
2920
2921 static struct clk pclk_fck = {
2922         .name           = "pclk_fck",
2923         .ops            = &clkops_null,
2924         .init           = &omap2_init_clksel_parent,
2925         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2926         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2927         .clksel         = pclk_emu_clksel,
2928         .flags          = RATE_PROPAGATES,
2929         .clkdm_name     = "emu_clkdm",
2930         .recalc         = &omap2_clksel_recalc,
2931 };
2932
2933 static const struct clksel_rate pclkx2_emu_rates[] = {
2934         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2935         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2936         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2937         { .div = 0 },
2938 };
2939
2940 static const struct clksel pclkx2_emu_clksel[] = {
2941         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2942         { .parent = NULL },
2943 };
2944
2945 static struct clk pclkx2_fck = {
2946         .name           = "pclkx2_fck",
2947         .ops            = &clkops_null,
2948         .init           = &omap2_init_clksel_parent,
2949         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2950         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2951         .clksel         = pclkx2_emu_clksel,
2952         .flags          = RATE_PROPAGATES,
2953         .clkdm_name     = "emu_clkdm",
2954         .recalc         = &omap2_clksel_recalc,
2955 };
2956
2957 static const struct clksel atclk_emu_clksel[] = {
2958         { .parent = &emu_src_ck, .rates = div2_rates },
2959         { .parent = NULL },
2960 };
2961
2962 static struct clk atclk_fck = {
2963         .name           = "atclk_fck",
2964         .ops            = &clkops_null,
2965         .init           = &omap2_init_clksel_parent,
2966         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2967         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2968         .clksel         = atclk_emu_clksel,
2969         .flags          = RATE_PROPAGATES,
2970         .clkdm_name     = "emu_clkdm",
2971         .recalc         = &omap2_clksel_recalc,
2972 };
2973
2974 static struct clk traceclk_src_fck = {
2975         .name           = "traceclk_src_fck",
2976         .ops            = &clkops_null,
2977         .init           = &omap2_init_clksel_parent,
2978         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2979         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2980         .clksel         = emu_src_clksel,
2981         .flags          = RATE_PROPAGATES,
2982         .clkdm_name     = "emu_clkdm",
2983         .recalc         = &omap2_clksel_recalc,
2984 };
2985
2986 static const struct clksel_rate traceclk_rates[] = {
2987         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2988         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2989         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2990         { .div = 0 },
2991 };
2992
2993 static const struct clksel traceclk_clksel[] = {
2994         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2995         { .parent = NULL },
2996 };
2997
2998 static struct clk traceclk_fck = {
2999         .name           = "traceclk_fck",
3000         .ops            = &clkops_null,
3001         .init           = &omap2_init_clksel_parent,
3002         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3003         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3004         .clksel         = traceclk_clksel,
3005         .clkdm_name     = "emu_clkdm",
3006         .recalc         = &omap2_clksel_recalc,
3007 };
3008
3009 /* SR clocks */
3010
3011 /* SmartReflex fclk (VDD1) */
3012 static struct clk sr1_fck = {
3013         .name           = "sr1_fck",
3014         .ops            = &clkops_omap2_dflt_wait,
3015         .parent         = &sys_ck,
3016         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3017         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3018         .flags          = RATE_PROPAGATES,
3019         .recalc         = &followparent_recalc,
3020 };
3021
3022 /* SmartReflex fclk (VDD2) */
3023 static struct clk sr2_fck = {
3024         .name           = "sr2_fck",
3025         .ops            = &clkops_omap2_dflt_wait,
3026         .parent         = &sys_ck,
3027         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3028         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3029         .flags          = RATE_PROPAGATES,
3030         .recalc         = &followparent_recalc,
3031 };
3032
3033 static struct clk sr_l4_ick = {
3034         .name           = "sr_l4_ick",
3035         .ops            = &clkops_null, /* RMK: missing? */
3036         .parent         = &l4_ick,
3037         .clkdm_name     = "core_l4_clkdm",
3038         .recalc         = &followparent_recalc,
3039 };
3040
3041 /* SECURE_32K_FCK clocks */
3042
3043 /* XXX This clock no longer exists in 3430 TRM rev F */
3044 static struct clk gpt12_fck = {
3045         .name           = "gpt12_fck",
3046         .ops            = &clkops_null,
3047         .parent         = &secure_32k_fck,
3048         .recalc         = &followparent_recalc,
3049 };
3050
3051 static struct clk wdt1_fck = {
3052         .name           = "wdt1_fck",
3053         .ops            = &clkops_null,
3054         .parent         = &secure_32k_fck,
3055         .recalc         = &followparent_recalc,
3056 };
3057
3058 #endif