2 * OMAP3 clock framework
4 * Copyright (C) 2007 Texas Instruments, Inc.
5 * Copyright (C) 2007 Nokia Corporation
7 * Written by Paul Walmsley
10 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
11 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
15 #include "cm_regbits_34xx.h"
17 #include "prm_regbits_34xx.h"
19 static void omap3_dpll_recalc(struct clk *clk);
20 static void omap3_clkoutx2_recalc(struct clk *clk);
22 /* REVISIT: this stuff should be moved to a scm.h file */
23 /* CONTROL_DEVCONF0 bits */
24 #define OMAP3430_MCBSP2_CLKS_MASK (1 << 6)
25 #define OMAP3430_MCBSP1_CLKS_MASK (1 << 2)
26 /* OMAP34XX_CONTROL_DEVCONF1 bits */
27 #define OMAP3430_MCBSP5_CLKS_MASK (1 << 4)
28 #define OMAP3430_MCBSP4_CLKS_MASK (1 << 2)
29 #define OMAP3430_MCBSP3_CLKS_MASK (1 << 0)
32 * DPLL1 supplies clock to the MPU.
33 * DPLL2 supplies clock to the IVA2.
34 * DPLL3 supplies CORE domain clocks.
35 * DPLL4 supplies peripheral clocks.
40 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
41 static struct clk omap_32k_fck = {
42 .name = "omap_32k_fck",
44 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
46 .recalc = &propagate_rate,
49 static struct clk secure_32k_fck = {
50 .name = "secure_32k_fck",
52 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
54 .recalc = &propagate_rate,
57 /* Virtual source clocks for osc_sys_ck */
58 static struct clk virt_12m_ck = {
59 .name = "virt_12m_ck",
61 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
63 .recalc = &propagate_rate,
66 static struct clk virt_13m_ck = {
67 .name = "virt_13m_ck",
69 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
71 .recalc = &propagate_rate,
75 static struct clk virt_16_8m_ck = {
76 .name = "virt_16_8m_ck",
78 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
80 .recalc = &propagate_rate,
83 static struct clk virt_19_2m_ck = {
84 .name = "virt_19_2m_ck",
86 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
88 .recalc = &propagate_rate,
91 static struct clk virt_26m_ck = {
92 .name = "virt_26m_ck",
94 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
96 .recalc = &propagate_rate,
99 static struct clk virt_38_4m_ck = {
100 .name = "virt_38_4m_ck",
102 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
104 .recalc = &propagate_rate,
107 static const struct clksel_rate osc_sys_12m_rates[] = {
108 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
112 static const struct clksel_rate osc_sys_13m_rates[] = {
113 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
118 static const struct clksel_rate osc_sys_16_8m_rates[] = {
119 { .div = 1, .val = 5, .flags = RATE_IN_343X | DEFAULT_RATE },
123 static const struct clksel_rate osc_sys_19_2m_rates[] = {
124 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
128 static const struct clksel_rate osc_sys_26m_rates[] = {
129 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
133 static const struct clksel_rate osc_sys_38_4m_rates[] = {
134 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
138 static const struct clksel osc_sys_clksel[] = {
139 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
140 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
141 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
142 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
143 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
144 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
148 /* Oscillator clock */
149 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
150 static struct clk osc_sys_ck = {
151 .name = "osc_sys_ck",
152 .init = &omap2_init_clksel_parent,
153 .clksel_reg = OMAP3430_PRM_CLKSEL,
154 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
155 .clksel = osc_sys_clksel,
156 /* REVISIT: deal with autoextclkmode? */
157 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
159 .recalc = &omap2_clksel_recalc,
162 static const struct clksel_rate sys_osc_rates[] = {
163 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
164 { .div = 2, .val = 2, .flags = RATE_IN_343X },
168 static const struct clksel sys_clksel[] = {
169 { .parent = &osc_sys_ck, .rates = sys_osc_rates },
173 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
174 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
175 static struct clk sys_ck = {
177 .parent = &osc_sys_ck,
178 .init = &omap2_init_clksel_parent,
179 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
180 .clksel_mask = OMAP_SYSCLKDIV_MASK,
181 .clksel = sys_clksel,
182 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
183 .recalc = &omap2_clksel_recalc,
186 static struct clk sys_altclk = {
187 .name = "sys_altclk",
188 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
189 .recalc = &propagate_rate,
192 /* Optional external clock input for some McBSPs */
193 static struct clk mcbsp_clks = {
194 .name = "mcbsp_clks",
195 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
196 .recalc = &propagate_rate,
199 /* PRM EXTERNAL CLOCK OUTPUT */
201 static struct clk sys_clkout1 = {
202 .name = "sys_clkout1",
203 .parent = &osc_sys_ck,
204 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
205 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
206 .flags = CLOCK_IN_OMAP343X,
207 .recalc = &followparent_recalc,
215 /* MPU clock source */
217 static const struct dpll_data dpll1_dd = {
218 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
219 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
220 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
221 .div2_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
222 .div2_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
223 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
224 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
225 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
226 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
227 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
230 static struct clk dpll1_ck = {
233 .dpll_data = &dpll1_dd,
234 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
235 .recalc = &omap3_dpll_recalc,
239 * REVISIT: This clock is never specifically defined in the 3430 TRM,
240 * although it is referenced - so this is a guess
242 static struct clk emu_mpu_alwon_ck = {
243 .name = "emu_mpu_alwon_ck",
245 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
246 .recalc = &followparent_recalc,
250 /* IVA2 clock source */
253 static const struct dpll_data dpll2_dd = {
254 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
255 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
256 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
257 .div2_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL),
258 .div2_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
259 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
260 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
261 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
262 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
263 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
266 static struct clk dpll2_ck = {
269 .dpll_data = &dpll2_dd,
270 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
271 .recalc = &omap3_dpll_recalc,
275 /* Source clock for all interfaces and for some device fclks */
277 static const struct dpll_data dpll3_dd = {
278 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
279 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
280 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
281 .div2_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
282 .div2_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
283 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
284 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
285 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
286 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
287 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
290 static struct clk dpll3_ck = {
293 .dpll_data = &dpll3_dd,
294 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
295 .recalc = &omap3_dpll_recalc,
298 static const struct clksel_rate div16_dpll_rates[] = {
299 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
300 { .div = 2, .val = 2, .flags = RATE_IN_343X },
301 { .div = 3, .val = 3, .flags = RATE_IN_343X },
302 { .div = 4, .val = 4, .flags = RATE_IN_343X },
303 { .div = 5, .val = 5, .flags = RATE_IN_343X },
304 { .div = 6, .val = 6, .flags = RATE_IN_343X },
305 { .div = 7, .val = 7, .flags = RATE_IN_343X },
306 { .div = 8, .val = 8, .flags = RATE_IN_343X },
307 { .div = 9, .val = 9, .flags = RATE_IN_343X },
308 { .div = 10, .val = 10, .flags = RATE_IN_343X },
309 { .div = 11, .val = 11, .flags = RATE_IN_343X },
310 { .div = 12, .val = 12, .flags = RATE_IN_343X },
311 { .div = 13, .val = 13, .flags = RATE_IN_343X },
312 { .div = 14, .val = 14, .flags = RATE_IN_343X },
313 { .div = 15, .val = 15, .flags = RATE_IN_343X },
314 { .div = 16, .val = 16, .flags = RATE_IN_343X },
318 static const struct clksel_rate div2_rates[] = {
319 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
320 { .div = 2, .val = 2, .flags = RATE_IN_343X },
324 static const struct clksel div2_dpll3m2_clksel[] = {
325 { .parent = &dpll3_ck, .rates = div2_rates },
330 * REVISIT: Not sure what to do about clksel & these M2 divider clocks.
331 * Shouldn't they be changed in SRAM?
332 * This should probably remain a 'read-only' clksel clock.
334 static struct clk dpll3_m2_ck = {
335 .name = "dpll3_m2_ck",
337 .init = &omap2_init_clksel_parent,
338 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
339 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
340 .clksel = div2_dpll3m2_clksel,
341 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
342 .recalc = &omap2_clksel_recalc,
345 static struct clk core_ck = {
347 .parent = &dpll3_m2_ck,
348 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
349 .recalc = &followparent_recalc,
353 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
354 * DPLL isn't bypassed
356 static struct clk dpll3_x2_ck = {
357 .name = "dpll3_x2_ck",
359 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
360 .recalc = &omap3_clkoutx2_recalc,
363 static struct clk dpll3_m2x2_ck = {
364 .name = "dpll3_m2x2_ck",
365 .parent = &dpll3_x2_ck,
366 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
367 .recalc = &followparent_recalc,
370 /* The PWRDN bit is apparently only available on 3430ES2 and above */
371 static struct clk dpll3_m3x2_ck = {
372 .name = "dpll3_m3x2_ck",
373 .parent = &dpll3_x2_ck,
374 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
375 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
376 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
377 .recalc = &followparent_recalc,
380 static const struct clksel div16_dpll3_clksel[] = {
381 { .parent = &dpll3_x2_ck, .rates = div16_dpll_rates },
385 static struct clk emu_core_alwon_ck = {
386 .name = "emu_core_alwon_ck",
387 .parent = &dpll3_x2_ck,
388 .init = &omap2_init_clksel_parent,
389 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
390 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
391 .clksel = div16_dpll3_clksel,
392 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
393 .recalc = &followparent_recalc,
397 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
399 static const struct dpll_data dpll4_dd = {
400 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
401 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
402 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
403 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
404 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
405 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
406 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
407 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
410 static struct clk dpll4_ck = {
413 .dpll_data = &dpll4_dd,
414 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
415 .recalc = &omap3_dpll_recalc,
419 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
420 * DPLL isn't bypassed
422 static struct clk dpll4_x2_ck = {
423 .name = "dpll4_x2_ck",
425 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
426 .recalc = &omap3_clkoutx2_recalc,
429 static const struct clksel div16_dpll4_clksel[] = {
430 { .parent = &dpll4_x2_ck, .rates = div16_dpll_rates },
434 /* The PWRDN bit is apparently only available on 3430ES2 and above */
435 static struct clk dpll4_m2x2_ck = {
436 .name = "dpll4_m2x2_ck",
437 .parent = &dpll4_x2_ck,
438 .init = &omap2_init_clksel_parent,
439 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
440 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
441 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
442 .clksel_mask = OMAP3430_DIV_96M_MASK,
443 .clksel = div16_dpll4_clksel,
444 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
445 .recalc = &omap2_clksel_recalc,
448 static struct clk omap_96m_alwon_fck = {
449 .name = "omap_96m_alwon_fck",
450 .parent = &dpll4_m2x2_ck,
451 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
452 PARENT_CONTROLS_CLOCK,
453 .recalc = &followparent_recalc,
456 static struct clk omap_96m_fck = {
457 .name = "omap_96m_fck",
458 .parent = &omap_96m_alwon_fck,
459 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
460 PARENT_CONTROLS_CLOCK,
461 .recalc = &followparent_recalc,
464 static struct clk cm_96m_fck = {
465 .name = "cm_96m_fck",
466 .parent = &dpll4_m2x2_ck,
467 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
468 .recalc = &followparent_recalc,
471 /* The PWRDN bit is apparently only available on 3430ES2 and above */
472 static struct clk dpll4_m3x2_ck = {
473 .name = "dpll4_m3x2_ck",
474 .parent = &dpll4_x2_ck,
475 .init = &omap2_init_clksel_parent,
476 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
477 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
478 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
479 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
480 .clksel = div16_dpll4_clksel,
481 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
482 .recalc = &omap2_clksel_recalc,
485 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
486 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
490 static const struct clksel_rate omap_54m_alt_rates[] = {
491 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
495 static const struct clksel omap_54m_clksel[] = {
496 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
497 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
501 static struct clk omap_54m_fck = {
502 .name = "omap_54m_fck",
503 .init = &omap2_init_clksel_parent,
504 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
505 .clksel_mask = OMAP3430_SOURCE_54M,
506 .clksel = omap_54m_clksel,
507 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
508 .recalc = &omap2_clksel_recalc,
511 static const struct clksel_rate omap_48m_96md2_rates[] = {
512 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
516 static const struct clksel_rate omap_48m_alt_rates[] = {
517 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
521 static const struct clksel omap_48m_clksel[] = {
522 { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
523 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
527 static struct clk omap_48m_fck = {
528 .name = "omap_48m_fck",
529 .init = &omap2_init_clksel_parent,
530 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
531 .clksel_mask = OMAP3430_SOURCE_48M,
532 .clksel = omap_48m_clksel,
533 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
534 .recalc = &omap2_clksel_recalc,
537 static struct clk omap_12m_fck = {
538 .name = "omap_12m_fck",
539 .parent = &omap_48m_fck,
541 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
542 .recalc = &omap2_fixed_divisor_recalc,
545 /* The PWRDN bit is apparently only available on 3430ES2 and above */
546 static struct clk dpll4_m4x2_ck = {
547 .name = "dpll4_m4x2_ck",
548 .parent = &dpll4_x2_ck,
549 .init = &omap2_init_clksel_parent,
550 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
551 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
552 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
553 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
554 .clksel = div16_dpll4_clksel,
555 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
556 .recalc = &omap2_clksel_recalc,
559 /* The PWRDN bit is apparently only available on 3430ES2 and above */
560 static struct clk dpll4_m5x2_ck = {
561 .name = "dpll4_m5x2_ck",
562 .parent = &dpll4_x2_ck,
563 .init = &omap2_init_clksel_parent,
564 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
565 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
566 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
567 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
568 .clksel = div16_dpll4_clksel,
569 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
570 .recalc = &omap2_clksel_recalc,
573 /* The PWRDN bit is apparently only available on 3430ES2 and above */
574 static struct clk dpll4_m6x2_ck = {
575 .name = "dpll4_m6x2_ck",
576 .parent = &dpll4_x2_ck,
577 .init = &omap2_init_clksel_parent,
578 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
579 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
580 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
581 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
582 .clksel = div16_dpll4_clksel,
583 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
584 .recalc = &omap2_clksel_recalc,
587 static struct clk emu_per_alwon_ck = {
588 .name = "emu_per_alwon_ck",
589 .parent = &dpll4_m6x2_ck,
590 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
591 .recalc = &followparent_recalc,
595 /* CM EXTERNAL CLOCK OUTPUTS */
597 static const struct clksel_rate clkout2_src_core_rates[] = {
598 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
602 static const struct clksel_rate clkout2_src_sys_rates[] = {
603 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
607 static const struct clksel_rate clkout2_src_96m_rates[] = {
608 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
612 static const struct clksel_rate clkout2_src_54m_rates[] = {
613 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
617 static const struct clksel clkout2_src_clksel[] = {
618 { .parent = &core_ck, .rates = clkout2_src_core_rates },
619 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
620 { .parent = &omap_96m_alwon_fck, .rates = clkout2_src_96m_rates },
621 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
625 static struct clk clkout2_src_ck = {
626 .name = "clkout2_src_ck",
627 .init = &omap2_init_clksel_parent,
628 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
629 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
630 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
631 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
632 .clksel = clkout2_src_clksel,
633 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
634 .recalc = &omap2_clksel_recalc,
637 static const struct clksel_rate sys_clkout2_rates[] = {
638 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
639 { .div = 2, .val = 1, .flags = RATE_IN_343X },
640 { .div = 4, .val = 2, .flags = RATE_IN_343X },
641 { .div = 8, .val = 3, .flags = RATE_IN_343X },
642 { .div = 16, .val = 4, .flags = RATE_IN_343X },
646 static const struct clksel sys_clkout2_clksel[] = {
647 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
651 static struct clk sys_clkout2 = {
652 .name = "sys_clkout2",
653 .init = &omap2_init_clksel_parent,
654 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
655 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
656 .clksel = sys_clkout2_clksel,
657 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
658 .recalc = &omap2_clksel_recalc,
661 /* CM OUTPUT CLOCKS */
663 static struct clk corex2_fck = {
664 .name = "corex2_fck",
665 .parent = &dpll3_m2x2_ck,
666 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
667 .recalc = &followparent_recalc,
670 /* DPLL power domain clock controls */
672 static const struct clksel div2_core_clksel[] = {
673 { .parent = &core_ck, .rates = div2_rates },
677 /* TRM s. 4.7.7.4 lists the input for these two clocks as CORE_CK,
678 but presuming that is an error, or at least an overgeneralization */
679 /* REVISIT: Are these in DPLL power domain or CM power domain? docs
680 may be inconsistent here? */
681 static struct clk dpll1_fck = {
684 .init = &omap2_init_clksel_parent,
685 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
686 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
687 .clksel = div2_core_clksel,
688 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
689 .recalc = &omap2_clksel_recalc,
692 static struct clk dpll2_fck = {
695 .init = &omap2_init_clksel_parent,
696 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
697 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
698 .clksel = div2_core_clksel,
699 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
700 .recalc = &omap2_clksel_recalc,
703 /* Common interface clocks */
705 static struct clk l3_ick = {
708 .init = &omap2_init_clksel_parent,
709 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
710 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
711 .clksel = div2_core_clksel,
712 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
713 .recalc = &omap2_clksel_recalc,
716 static const struct clksel div2_l3_clksel[] = {
717 { .parent = &l3_ick, .rates = div2_rates },
721 static struct clk l4_ick = {
724 .init = &omap2_init_clksel_parent,
725 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
726 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
727 .clksel = div2_l3_clksel,
728 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
729 .recalc = &omap2_clksel_recalc,
733 static const struct clksel div2_l4_clksel[] = {
734 { .parent = &l4_ick, .rates = div2_rates },
738 static struct clk rm_ick = {
741 .init = &omap2_init_clksel_parent,
742 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
743 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
744 .clksel = div2_l4_clksel,
745 .flags = CLOCK_IN_OMAP343X,
746 .recalc = &omap2_clksel_recalc,
749 /* GFX power domain */
751 /* REVISIT: These clocks have disappeared in the 3430 ES2 TRM ?? */
753 static const struct clksel gfx_l3_clksel[] = {
754 { .parent = &l3_ick, .rates = gfx_l3_rates },
758 static struct clk gfx_l3_fck = {
759 .name = "gfx_l3_fck",
761 .init = &omap2_init_clksel_parent,
762 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
763 .enable_bit = OMAP_EN_GFX_SHIFT,
764 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
765 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
766 .clksel = gfx_l3_clksel,
767 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
768 .recalc = &omap2_clksel_recalc,
771 static struct clk gfx_l3_ick = {
772 .name = "gfx_l3_ick",
774 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
775 .enable_bit = OMAP_EN_GFX_SHIFT,
776 .flags = CLOCK_IN_OMAP343X,
777 .recalc = &followparent_recalc,
780 static struct clk gfx_cg1_ck = {
781 .name = "gfx_cg1_ck",
782 .parent = &gfx_l3_fck, /* REVISIT: correct? */
783 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
784 .enable_bit = OMAP3430_EN_2D_SHIFT,
785 .flags = CLOCK_IN_OMAP343X,
786 .recalc = &followparent_recalc,
789 static struct clk gfx_cg2_ck = {
790 .name = "gfx_cg2_ck",
791 .parent = &gfx_l3_fck, /* REVISIT: correct? */
792 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
793 .enable_bit = OMAP3430_EN_3D_SHIFT,
794 .flags = CLOCK_IN_OMAP343X,
795 .recalc = &followparent_recalc,
798 /* CORE power domain */
800 static struct clk d2d_26m_fck = {
801 .name = "d2d_26m_fck",
803 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
804 .enable_bit = OMAP3430_EN_D2D_SHIFT,
805 .flags = CLOCK_IN_OMAP343X,
806 .recalc = &followparent_recalc,
809 static const struct clksel omap343x_gpt_clksel[] = {
810 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
811 { .parent = &sys_ck, .rates = gpt_sys_rates },
815 static struct clk gpt10_fck = {
818 .init = &omap2_init_clksel_parent,
819 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
820 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
821 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
822 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
823 .clksel = omap343x_gpt_clksel,
824 .flags = CLOCK_IN_OMAP343X,
825 .recalc = &omap2_clksel_recalc,
828 static struct clk gpt11_fck = {
831 .init = &omap2_init_clksel_parent,
832 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
833 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
834 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
835 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
836 .clksel = omap343x_gpt_clksel,
837 .flags = CLOCK_IN_OMAP343X,
838 .recalc = &omap2_clksel_recalc,
841 /* CORE 96M FCLK-derived clocks */
843 static struct clk core_96m_fck = {
844 .name = "core_96m_fck",
845 .parent = &omap_96m_fck,
846 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
847 PARENT_CONTROLS_CLOCK,
848 .recalc = &followparent_recalc,
851 static struct clk mmc2_fck = {
853 .parent = &core_96m_fck,
854 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
855 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
856 .flags = CLOCK_IN_OMAP343X,
857 .recalc = &followparent_recalc,
860 static struct clk mspro_fck = {
862 .parent = &core_96m_fck,
863 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
864 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
865 .flags = CLOCK_IN_OMAP343X,
866 .recalc = &followparent_recalc,
869 static struct clk mmc1_fck = {
871 .parent = &core_96m_fck,
872 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
873 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
874 .flags = CLOCK_IN_OMAP343X,
875 .recalc = &followparent_recalc,
878 static struct clk i2c3_fck = {
881 .parent = &core_96m_fck,
882 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
883 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
884 .flags = CLOCK_IN_OMAP343X,
885 .recalc = &followparent_recalc,
888 static struct clk i2c2_fck = {
891 .parent = &core_96m_fck,
892 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
893 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
894 .flags = CLOCK_IN_OMAP343X,
895 .recalc = &followparent_recalc,
898 static struct clk i2c1_fck = {
901 .parent = &core_96m_fck,
902 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
903 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
904 .flags = CLOCK_IN_OMAP343X,
905 .recalc = &followparent_recalc,
909 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
910 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
912 static const struct clksel_rate common_mcbsp_96m_rates[] = {
913 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
917 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
918 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
922 static const struct clksel mcbsp_15_clksel[] = {
923 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
924 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
928 static struct clk mcbsp5_fck = {
929 .name = "mcbsp5_fck",
930 .init = &omap2_init_clksel_parent,
931 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
932 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
933 .clksel_reg = (void __iomem *)IO_ADDRESS(OMAP34XX_CONTROL_DEVCONF1),
934 .clksel_mask = OMAP3430_MCBSP5_CLKS_MASK,
935 .clksel = mcbsp_15_clksel,
936 .flags = CLOCK_IN_OMAP343X,
937 .recalc = &omap2_clksel_recalc,
940 static struct clk mcbsp1_fck = {
941 .name = "mcbsp1_fck",
942 .init = &omap2_init_clksel_parent,
943 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
944 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
945 .clksel_reg = (void __iomem *)IO_ADDRESS(OMAP34XX_CONTROL_DEVCONF0),
946 .clksel_mask = OMAP3430_MCBSP1_CLKS_MASK,
947 .clksel = mcbsp_15_clksel,
948 .flags = CLOCK_IN_OMAP343X,
949 .recalc = &omap2_clksel_recalc,
952 /* CORE_48M_FCK-derived clocks */
954 static struct clk core_48m_fck = {
955 .name = "core_48m_fck",
956 .parent = &omap_48m_fck,
957 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
958 .recalc = &followparent_recalc,
961 static struct clk mcspi4_fck = {
962 .name = "mcspi4_fck",
963 .parent = &core_48m_fck,
964 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
965 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
966 .flags = CLOCK_IN_OMAP343X,
967 .recalc = &followparent_recalc,
970 static struct clk mcspi3_fck = {
971 .name = "mcspi3_fck",
972 .parent = &core_48m_fck,
973 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
974 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
975 .flags = CLOCK_IN_OMAP343X,
976 .recalc = &followparent_recalc,
979 static struct clk mcspi2_fck = {
980 .name = "mcspi2_fck",
981 .parent = &core_48m_fck,
982 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
983 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
984 .flags = CLOCK_IN_OMAP343X,
985 .recalc = &followparent_recalc,
988 static struct clk mcspi1_fck = {
989 .name = "mcspi1_fck",
990 .parent = &core_48m_fck,
991 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
992 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
993 .flags = CLOCK_IN_OMAP343X,
994 .recalc = &followparent_recalc,
997 static struct clk uart2_fck = {
999 .parent = &core_48m_fck,
1000 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1001 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1002 .flags = CLOCK_IN_OMAP343X,
1003 .recalc = &followparent_recalc,
1006 static struct clk uart1_fck = {
1007 .name = "uart1_fck",
1008 .parent = &core_48m_fck,
1009 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1010 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1011 .flags = CLOCK_IN_OMAP343X,
1012 .recalc = &followparent_recalc,
1015 static struct clk fshostusb_fck = {
1016 .name = "fshostusb_fck",
1017 .parent = &core_48m_fck,
1018 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1019 .enable_bit = OMAP3430_EN_FSHOSTUSB_SHIFT,
1020 .flags = CLOCK_IN_OMAP343X,
1021 .recalc = &followparent_recalc,
1024 /* CORE_12M_FCK based clocks */
1026 static struct clk core_12m_fck = {
1027 .name = "core_12m_fck",
1028 .parent = &omap_12m_fck,
1029 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1030 .recalc = &followparent_recalc,
1033 static struct clk hdq_fck = {
1035 .parent = &core_12m_fck,
1036 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1037 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1038 .flags = CLOCK_IN_OMAP343X,
1039 .recalc = &followparent_recalc,
1042 /* DPLL3-derived clock */
1044 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1045 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1046 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1047 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1048 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1049 { .div = 6, .val = 6, .flags = RATE_IN_343X },
1050 { .div = 8, .val = 8, .flags = RATE_IN_343X },
1054 static const struct clksel ssi_ssr_clksel[] = {
1055 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1059 static struct clk ssi_ssr_fck = {
1060 .name = "ssi_ssr_fck",
1061 .init = &omap2_init_clksel_parent,
1062 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1063 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1064 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1065 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1066 .clksel = ssi_ssr_clksel,
1067 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1068 .recalc = &omap2_clksel_recalc,
1071 static struct clk ssi_sst_fck = {
1072 .name = "ssi_sst_fck",
1073 .parent = &ssi_ssr_fck,
1075 .flags = CLOCK_IN_OMAP343X,
1076 .recalc = &omap2_fixed_divisor_recalc,
1081 /* CORE_L3_ICK based clocks */
1083 static struct clk core_l3_ick = {
1084 .name = "core_l3_ick",
1086 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1087 .recalc = &followparent_recalc,
1090 static struct clk hsotgusb_ick = {
1091 .name = "hsotgusb_fck",
1092 .parent = &core_l3_ick,
1093 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1094 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1095 .flags = CLOCK_IN_OMAP343X,
1096 .recalc = &followparent_recalc,
1099 static struct clk sdrc_ick = {
1101 .parent = &core_l3_ick,
1102 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1103 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1104 .flags = CLOCK_IN_OMAP343X,
1105 .recalc = &followparent_recalc,
1108 static struct clk gpmc_fck = {
1110 .parent = &core_l3_ick,
1111 .flags = CLOCK_IN_OMAP343X,
1112 .recalc = &followparent_recalc,
1115 /* SECURITY_L3_ICK based clocks */
1117 static struct clk security_l3_ick = {
1118 .name = "security_l3_ick",
1120 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1121 .recalc = &followparent_recalc,
1124 static struct clk pka_ick = {
1126 .parent = &security_l3_ick,
1127 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1128 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1129 .flags = CLOCK_IN_OMAP343X,
1130 .recalc = &followparent_recalc,
1133 /* CORE_L4_ICK based clocks */
1135 static struct clk core_l4_ick = {
1136 .name = "core_l4_ick",
1138 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1139 .recalc = &followparent_recalc,
1142 static struct clk aes2_ick = {
1144 .parent = &core_l4_ick,
1145 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1146 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1147 .flags = CLOCK_IN_OMAP343X,
1148 .recalc = &followparent_recalc,
1151 static struct clk sha12_ick = {
1152 .name = "sha12_ick",
1153 .parent = &core_l4_ick,
1154 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1155 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1156 .flags = CLOCK_IN_OMAP343X,
1157 .recalc = &followparent_recalc,
1160 static struct clk des2_ick = {
1162 .parent = &core_l4_ick,
1163 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1164 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1165 .flags = CLOCK_IN_OMAP343X,
1166 .recalc = &followparent_recalc,
1169 static struct clk mmc2_ick = {
1171 .parent = &core_l4_ick,
1172 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1173 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1174 .flags = CLOCK_IN_OMAP343X,
1175 .recalc = &followparent_recalc,
1178 static struct clk mmc1_ick = {
1180 .parent = &core_l4_ick,
1181 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1182 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1183 .flags = CLOCK_IN_OMAP343X,
1184 .recalc = &followparent_recalc,
1187 static struct clk mspro_ick = {
1188 .name = "mspro_ick",
1189 .parent = &core_l4_ick,
1190 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1191 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1192 .flags = CLOCK_IN_OMAP343X,
1193 .recalc = &followparent_recalc,
1196 static struct clk hdq_ick = {
1198 .parent = &core_l4_ick,
1199 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1200 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1201 .flags = CLOCK_IN_OMAP343X,
1202 .recalc = &followparent_recalc,
1205 static struct clk mcspi4_ick = {
1206 .name = "mcspi4_ick",
1207 .parent = &core_l4_ick,
1208 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1209 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1210 .flags = CLOCK_IN_OMAP343X,
1211 .recalc = &followparent_recalc,
1214 static struct clk mcspi3_ick = {
1215 .name = "mcspi3_ick",
1216 .parent = &core_l4_ick,
1217 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1218 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1219 .flags = CLOCK_IN_OMAP343X,
1220 .recalc = &followparent_recalc,
1223 static struct clk mcspi2_ick = {
1224 .name = "mcspi2_ick",
1225 .parent = &core_l4_ick,
1226 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1227 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1228 .flags = CLOCK_IN_OMAP343X,
1229 .recalc = &followparent_recalc,
1232 static struct clk mcspi1_ick = {
1233 .name = "mcspi1_ick",
1234 .parent = &core_l4_ick,
1235 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1236 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1237 .flags = CLOCK_IN_OMAP343X,
1238 .recalc = &followparent_recalc,
1241 static struct clk i2c3_ick = {
1244 .parent = &core_l4_ick,
1245 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1246 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1247 .flags = CLOCK_IN_OMAP343X,
1248 .recalc = &followparent_recalc,
1251 static struct clk i2c2_ick = {
1254 .parent = &core_l4_ick,
1255 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1256 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1257 .flags = CLOCK_IN_OMAP343X,
1258 .recalc = &followparent_recalc,
1261 static struct clk i2c1_ick = {
1264 .parent = &core_l4_ick,
1265 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1266 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1267 .flags = CLOCK_IN_OMAP343X,
1268 .recalc = &followparent_recalc,
1271 static struct clk uart2_ick = {
1272 .name = "uart2_ick",
1273 .parent = &core_l4_ick,
1274 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1275 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1276 .flags = CLOCK_IN_OMAP343X,
1277 .recalc = &followparent_recalc,
1280 static struct clk uart1_ick = {
1281 .name = "uart1_ick",
1282 .parent = &core_l4_ick,
1283 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1284 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1285 .flags = CLOCK_IN_OMAP343X,
1286 .recalc = &followparent_recalc,
1289 static struct clk gpt11_ick = {
1290 .name = "gpt11_ick",
1291 .parent = &core_l4_ick,
1292 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1293 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1294 .flags = CLOCK_IN_OMAP343X,
1295 .recalc = &followparent_recalc,
1298 static struct clk gpt10_ick = {
1299 .name = "gpt10_ick",
1300 .parent = &core_l4_ick,
1301 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1302 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1303 .flags = CLOCK_IN_OMAP343X,
1304 .recalc = &followparent_recalc,
1307 static struct clk mcbsp5_ick = {
1308 .name = "mcbsp5_ick",
1309 .parent = &core_l4_ick,
1310 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1311 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1312 .flags = CLOCK_IN_OMAP343X,
1313 .recalc = &followparent_recalc,
1316 static struct clk mcbsp1_ick = {
1317 .name = "mcbsp1_ick",
1318 .parent = &core_l4_ick,
1319 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1320 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1321 .flags = CLOCK_IN_OMAP343X,
1322 .recalc = &followparent_recalc,
1325 static struct clk fac_ick = {
1327 .parent = &core_l4_ick,
1328 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1329 .enable_bit = OMAP3430_EN_FAC_SHIFT,
1330 .flags = CLOCK_IN_OMAP343X,
1331 .recalc = &followparent_recalc,
1334 static struct clk mailboxes_ick = {
1335 .name = "mailboxes_ick",
1336 .parent = &core_l4_ick,
1337 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1338 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1339 .flags = CLOCK_IN_OMAP343X,
1340 .recalc = &followparent_recalc,
1343 static struct clk omapctrl_ick = {
1344 .name = "omapctrl_ick",
1345 .parent = &core_l4_ick,
1346 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1347 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
1348 .flags = CLOCK_IN_OMAP343X,
1349 .recalc = &followparent_recalc,
1352 /* SSI_L4_ICK based clocks */
1354 static struct clk ssi_l4_ick = {
1355 .name = "ssi_l4_ick",
1357 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1358 .recalc = &followparent_recalc,
1361 static struct clk ssi_ick = {
1363 .parent = &ssi_l4_ick,
1364 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1365 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1366 .flags = CLOCK_IN_OMAP343X,
1367 .recalc = &followparent_recalc,
1370 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
1371 * but l4_ick makes more sense to me */
1373 static const struct clksel_rate usb_l4_l4_rates[] = {
1374 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1375 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1379 static const struct clksel usb_l4_clksel[] = {
1380 { .parent = &l4_ick, .rates = usb_l4_l4_rates },
1384 static struct clk usb_l4_ick = {
1385 .name = "usb_l4_ick",
1387 .init = &omap2_init_clksel_parent,
1388 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1389 .enable_bit = OMAP3430_EN_FSHOSTUSB_SHIFT,
1390 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1391 .clksel_mask = OMAP3430_CLKSEL_FSHOSTUSB_MASK,
1392 .clksel = usb_l4_clksel,
1393 .flags = CLOCK_IN_OMAP343X,
1394 .recalc = &omap2_clksel_recalc,
1397 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
1399 /* SECURITY_L4_ICK2 based clocks */
1401 static struct clk security_l4_ick2 = {
1402 .name = "security_l4_ick2",
1404 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1405 .recalc = &followparent_recalc,
1408 static struct clk aes1_ick = {
1410 .parent = &security_l4_ick2,
1411 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1412 .enable_bit = OMAP3430_EN_AES1_SHIFT,
1413 .flags = CLOCK_IN_OMAP343X,
1414 .recalc = &followparent_recalc,
1417 static struct clk rng_ick = {
1419 .parent = &security_l4_ick2,
1420 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1421 .enable_bit = OMAP3430_EN_RNG_SHIFT,
1422 .flags = CLOCK_IN_OMAP343X,
1423 .recalc = &followparent_recalc,
1426 static struct clk sha11_ick = {
1427 .name = "sha11_ick",
1428 .parent = &security_l4_ick2,
1429 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1430 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
1431 .flags = CLOCK_IN_OMAP343X,
1432 .recalc = &followparent_recalc,
1435 static struct clk des1_ick = {
1437 .parent = &security_l4_ick2,
1438 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1439 .enable_bit = OMAP3430_EN_DES1_SHIFT,
1440 .flags = CLOCK_IN_OMAP343X,
1441 .recalc = &followparent_recalc,
1446 static struct clk dss1_alwon_fck = {
1447 .name = "dss1_alwon_fck",
1448 .parent = &dpll4_m4x2_ck,
1449 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1450 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
1451 .flags = CLOCK_IN_OMAP343X,
1452 .recalc = &followparent_recalc,
1455 static struct clk dss_tv_fck = {
1456 .name = "dss_tv_fck",
1457 .parent = &omap_54m_fck,
1458 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1459 .enable_bit = OMAP3430_EN_TV_SHIFT,
1460 .flags = CLOCK_IN_OMAP343X,
1461 .recalc = &followparent_recalc,
1464 static struct clk dss_96m_fck = {
1465 .name = "dss_96m_fck",
1466 .parent = &omap_96m_fck,
1467 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1468 .enable_bit = OMAP3430_EN_TV_SHIFT,
1469 .flags = CLOCK_IN_OMAP343X,
1470 .recalc = &followparent_recalc,
1473 static struct clk dss2_alwon_fck = {
1474 .name = "dss2_alwon_fck",
1476 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1477 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
1478 .flags = CLOCK_IN_OMAP343X,
1479 .recalc = &followparent_recalc,
1482 static struct clk dss_l3_ick = {
1483 .name = "dss_l3_ick",
1485 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1486 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1487 .flags = CLOCK_IN_OMAP343X,
1488 .recalc = &followparent_recalc,
1491 static struct clk dss_l4_ick = {
1492 .name = "dss_l4_ick",
1494 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1495 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1496 .flags = CLOCK_IN_OMAP343X,
1497 .recalc = &followparent_recalc,
1502 static struct clk cam_mclk = {
1504 .parent = &dpll4_m5x2_ck,
1505 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
1506 .enable_bit = OMAP3430_EN_CAM_SHIFT,
1507 .flags = CLOCK_IN_OMAP343X,
1508 .recalc = &followparent_recalc,
1511 static struct clk cam_l3_ick = {
1512 .name = "cam_l3_ick",
1514 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
1515 .enable_bit = OMAP3430_EN_CAM_SHIFT,
1516 .flags = CLOCK_IN_OMAP343X,
1517 .recalc = &followparent_recalc,
1520 static struct clk cam_l4_ick = {
1521 .name = "cam_l4_ick",
1523 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
1524 .enable_bit = OMAP3430_EN_CAM_SHIFT,
1525 .flags = CLOCK_IN_OMAP343X,
1526 .recalc = &followparent_recalc,
1531 static struct clk gpt1_fck = {
1533 .init = &omap2_init_clksel_parent,
1534 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1535 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
1536 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1537 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
1538 .clksel = omap343x_gpt_clksel,
1539 .flags = CLOCK_IN_OMAP343X,
1540 .recalc = &omap2_clksel_recalc,
1543 static struct clk wkup_32k_fck = {
1544 .name = "wkup_32k_fck",
1545 .parent = &omap_32k_fck,
1546 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1547 .recalc = &followparent_recalc,
1550 static struct clk gpio1_fck = {
1551 .name = "gpio1_fck",
1552 .parent = &wkup_32k_fck,
1553 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1554 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
1555 .flags = CLOCK_IN_OMAP343X,
1556 .recalc = &followparent_recalc,
1559 static struct clk wdt2_fck = {
1561 .parent = &wkup_32k_fck,
1562 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1563 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
1564 .flags = CLOCK_IN_OMAP343X,
1565 .recalc = &followparent_recalc,
1568 static struct clk wkup_l4_ick = {
1569 .name = "wkup_l4_ick",
1571 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1572 .recalc = &followparent_recalc,
1575 static struct clk wdt2_ick = {
1577 .parent = &wkup_l4_ick,
1578 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1579 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
1580 .flags = CLOCK_IN_OMAP343X,
1581 .recalc = &followparent_recalc,
1584 static struct clk wdt1_ick = {
1586 .parent = &wkup_l4_ick,
1587 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1588 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
1589 .flags = CLOCK_IN_OMAP343X,
1590 .recalc = &followparent_recalc,
1593 static struct clk gpio1_ick = {
1594 .name = "gpio1_ick",
1595 .parent = &wkup_l4_ick,
1596 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1597 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
1598 .flags = CLOCK_IN_OMAP343X,
1599 .recalc = &followparent_recalc,
1602 static struct clk omap_32ksync_ick = {
1603 .name = "omap_32ksync_ick",
1604 .parent = &wkup_l4_ick,
1605 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1606 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
1607 .flags = CLOCK_IN_OMAP343X,
1608 .recalc = &followparent_recalc,
1611 static struct clk gpt12_ick = {
1612 .name = "gpt12_ick",
1613 .parent = &wkup_l4_ick,
1614 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1615 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
1616 .flags = CLOCK_IN_OMAP343X,
1617 .recalc = &followparent_recalc,
1620 static struct clk gpt1_ick = {
1622 .parent = &wkup_l4_ick,
1623 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1624 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
1625 .flags = CLOCK_IN_OMAP343X,
1626 .recalc = &followparent_recalc,
1631 /* PER clock domain */
1633 static struct clk per_96m_fck = {
1634 .name = "per_96m_fck",
1635 .parent = &omap_96m_alwon_fck,
1636 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1637 .recalc = &followparent_recalc,
1640 static struct clk per_48m_fck = {
1641 .name = "per_48m_fck",
1642 .parent = &omap_48m_fck,
1643 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1644 .recalc = &followparent_recalc,
1647 static struct clk uart3_fck = {
1648 .name = "uart3_fck",
1649 .parent = &per_48m_fck,
1650 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1651 .enable_bit = OMAP3430_EN_UART3_SHIFT,
1652 .flags = CLOCK_IN_OMAP343X,
1653 .recalc = &followparent_recalc,
1656 static struct clk gpt2_fck = {
1658 .init = &omap2_init_clksel_parent,
1659 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1660 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
1661 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1662 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
1663 .clksel = omap343x_gpt_clksel,
1664 .flags = CLOCK_IN_OMAP343X,
1665 .recalc = &omap2_clksel_recalc,
1668 static struct clk gpt3_fck = {
1670 .init = &omap2_init_clksel_parent,
1671 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1672 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
1673 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1674 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
1675 .clksel = omap343x_gpt_clksel,
1676 .flags = CLOCK_IN_OMAP343X,
1677 .recalc = &omap2_clksel_recalc,
1680 static struct clk gpt4_fck = {
1682 .init = &omap2_init_clksel_parent,
1683 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1684 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
1685 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1686 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
1687 .clksel = omap343x_gpt_clksel,
1688 .flags = CLOCK_IN_OMAP343X,
1689 .recalc = &omap2_clksel_recalc,
1692 static struct clk gpt5_fck = {
1694 .init = &omap2_init_clksel_parent,
1695 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1696 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
1697 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1698 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
1699 .clksel = omap343x_gpt_clksel,
1700 .flags = CLOCK_IN_OMAP343X,
1701 .recalc = &omap2_clksel_recalc,
1704 static struct clk gpt6_fck = {
1706 .init = &omap2_init_clksel_parent,
1707 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1708 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
1709 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1710 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
1711 .clksel = omap343x_gpt_clksel,
1712 .flags = CLOCK_IN_OMAP343X,
1713 .recalc = &omap2_clksel_recalc,
1716 static struct clk gpt7_fck = {
1718 .init = &omap2_init_clksel_parent,
1719 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1720 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
1721 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1722 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
1723 .clksel = omap343x_gpt_clksel,
1724 .flags = CLOCK_IN_OMAP343X,
1725 .recalc = &omap2_clksel_recalc,
1728 static struct clk gpt8_fck = {
1730 .init = &omap2_init_clksel_parent,
1731 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1732 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
1733 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1734 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
1735 .clksel = omap343x_gpt_clksel,
1736 .flags = CLOCK_IN_OMAP343X,
1737 .recalc = &omap2_clksel_recalc,
1740 static struct clk gpt9_fck = {
1742 .init = &omap2_init_clksel_parent,
1743 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1744 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
1745 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1746 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
1747 .clksel = omap343x_gpt_clksel,
1748 .flags = CLOCK_IN_OMAP343X,
1749 .recalc = &omap2_clksel_recalc,
1752 static struct clk per_32k_alwon_fck = {
1753 .name = "per_32k_alwon_fck",
1754 .parent = &omap_32k_fck,
1755 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1756 .recalc = &followparent_recalc,
1759 static struct clk gpio6_fck = {
1760 .name = "gpio6_fck",
1761 .parent = &per_32k_alwon_fck,
1762 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1763 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
1764 .flags = CLOCK_IN_OMAP343X,
1765 .recalc = &followparent_recalc,
1768 static struct clk gpio5_fck = {
1769 .name = "gpio5_fck",
1770 .parent = &per_32k_alwon_fck,
1771 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1772 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
1773 .flags = CLOCK_IN_OMAP343X,
1774 .recalc = &followparent_recalc,
1777 static struct clk gpio4_fck = {
1778 .name = "gpio4_fck",
1779 .parent = &per_32k_alwon_fck,
1780 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1781 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
1782 .flags = CLOCK_IN_OMAP343X,
1783 .recalc = &followparent_recalc,
1786 static struct clk gpio3_fck = {
1787 .name = "gpio3_fck",
1788 .parent = &per_32k_alwon_fck,
1789 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1790 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
1791 .flags = CLOCK_IN_OMAP343X,
1792 .recalc = &followparent_recalc,
1795 static struct clk gpio2_fck = {
1796 .name = "gpio2_fck",
1797 .parent = &per_32k_alwon_fck,
1798 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1799 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
1800 .flags = CLOCK_IN_OMAP343X,
1801 .recalc = &followparent_recalc,
1804 static struct clk wdt3_fck = {
1806 .parent = &per_32k_alwon_fck,
1807 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1808 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
1809 .flags = CLOCK_IN_OMAP343X,
1810 .recalc = &followparent_recalc,
1813 static struct clk per_l4_ick = {
1814 .name = "per_l4_ick",
1816 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1817 .recalc = &followparent_recalc,
1820 static struct clk gpio6_ick = {
1821 .name = "gpio6_ick",
1822 .parent = &per_l4_ick,
1823 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1824 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
1825 .flags = CLOCK_IN_OMAP343X,
1826 .recalc = &followparent_recalc,
1829 static struct clk gpio5_ick = {
1830 .name = "gpio5_ick",
1831 .parent = &per_l4_ick,
1832 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1833 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
1834 .flags = CLOCK_IN_OMAP343X,
1835 .recalc = &followparent_recalc,
1838 static struct clk gpio4_ick = {
1839 .name = "gpio4_ick",
1840 .parent = &per_l4_ick,
1841 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1842 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
1843 .flags = CLOCK_IN_OMAP343X,
1844 .recalc = &followparent_recalc,
1847 static struct clk gpio3_ick = {
1848 .name = "gpio3_ick",
1849 .parent = &per_l4_ick,
1850 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1851 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
1852 .flags = CLOCK_IN_OMAP343X,
1853 .recalc = &followparent_recalc,
1856 static struct clk gpio2_ick = {
1857 .name = "gpio2_ick",
1858 .parent = &per_l4_ick,
1859 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1860 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
1861 .flags = CLOCK_IN_OMAP343X,
1862 .recalc = &followparent_recalc,
1865 static struct clk wdt3_ick = {
1867 .parent = &per_l4_ick,
1868 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1869 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
1870 .flags = CLOCK_IN_OMAP343X,
1871 .recalc = &followparent_recalc,
1874 static struct clk uart3_ick = {
1875 .name = "uart3_ick",
1876 .parent = &per_l4_ick,
1877 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1878 .enable_bit = OMAP3430_EN_UART3_SHIFT,
1879 .flags = CLOCK_IN_OMAP343X,
1880 .recalc = &followparent_recalc,
1883 static struct clk gpt9_ick = {
1885 .parent = &per_l4_ick,
1886 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1887 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
1888 .flags = CLOCK_IN_OMAP343X,
1889 .recalc = &followparent_recalc,
1892 static struct clk gpt8_ick = {
1894 .parent = &per_l4_ick,
1895 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1896 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
1897 .flags = CLOCK_IN_OMAP343X,
1898 .recalc = &followparent_recalc,
1901 static struct clk gpt7_ick = {
1903 .parent = &per_l4_ick,
1904 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1905 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
1906 .flags = CLOCK_IN_OMAP343X,
1907 .recalc = &followparent_recalc,
1910 static struct clk gpt6_ick = {
1912 .parent = &per_l4_ick,
1913 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1914 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
1915 .flags = CLOCK_IN_OMAP343X,
1916 .recalc = &followparent_recalc,
1919 static struct clk gpt5_ick = {
1921 .parent = &per_l4_ick,
1922 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1923 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
1924 .flags = CLOCK_IN_OMAP343X,
1925 .recalc = &followparent_recalc,
1928 static struct clk gpt4_ick = {
1930 .parent = &per_l4_ick,
1931 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1932 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
1933 .flags = CLOCK_IN_OMAP343X,
1934 .recalc = &followparent_recalc,
1937 static struct clk gpt3_ick = {
1939 .parent = &per_l4_ick,
1940 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1941 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
1942 .flags = CLOCK_IN_OMAP343X,
1943 .recalc = &followparent_recalc,
1946 static struct clk gpt2_ick = {
1948 .parent = &per_l4_ick,
1949 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1950 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
1951 .flags = CLOCK_IN_OMAP343X,
1952 .recalc = &followparent_recalc,
1955 static struct clk mcbsp2_ick = {
1956 .name = "mcbsp2_ick",
1957 .parent = &per_l4_ick,
1958 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1959 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
1960 .flags = CLOCK_IN_OMAP343X,
1961 .recalc = &followparent_recalc,
1964 static struct clk mcbsp3_ick = {
1965 .name = "mcbsp3_ick",
1966 .parent = &per_l4_ick,
1967 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1968 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
1969 .flags = CLOCK_IN_OMAP343X,
1970 .recalc = &followparent_recalc,
1973 static struct clk mcbsp4_ick = {
1974 .name = "mcbsp4_ick",
1975 .parent = &per_l4_ick,
1976 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1977 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
1978 .flags = CLOCK_IN_OMAP343X,
1979 .recalc = &followparent_recalc,
1982 static const struct clksel mcbsp_234_clksel[] = {
1983 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
1984 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1988 static struct clk mcbsp2_fck = {
1989 .name = "mcbsp2_fck",
1990 .init = &omap2_init_clksel_parent,
1991 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1992 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
1993 .clksel_reg = (void __iomem *)IO_ADDRESS(OMAP34XX_CONTROL_DEVCONF0),
1994 .clksel_mask = OMAP3430_MCBSP2_CLKS_MASK,
1995 .clksel = mcbsp_234_clksel,
1996 .flags = CLOCK_IN_OMAP343X,
1997 .recalc = &omap2_clksel_recalc,
2000 static struct clk mcbsp3_fck = {
2001 .name = "mcbsp3_fck",
2002 .init = &omap2_init_clksel_parent,
2003 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2004 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2005 .clksel_reg = (void __iomem *)IO_ADDRESS(OMAP34XX_CONTROL_DEVCONF1),
2006 .clksel_mask = OMAP3430_MCBSP3_CLKS_MASK,
2007 .clksel = mcbsp_234_clksel,
2008 .flags = CLOCK_IN_OMAP343X,
2009 .recalc = &omap2_clksel_recalc,
2012 static struct clk mcbsp4_fck = {
2013 .name = "mcbsp4_fck",
2014 .init = &omap2_init_clksel_parent,
2015 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2016 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2017 .clksel_reg = (void __iomem *)IO_ADDRESS(OMAP34XX_CONTROL_DEVCONF1),
2018 .clksel_mask = OMAP3430_MCBSP4_CLKS_MASK,
2019 .clksel = mcbsp_234_clksel,
2020 .flags = CLOCK_IN_OMAP343X,
2021 .recalc = &omap2_clksel_recalc,
2026 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2028 static const struct clksel_rate emu_src_sys_rates[] = {
2029 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2033 static const struct clksel_rate emu_src_core_rates[] = {
2034 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2038 static const struct clksel_rate emu_src_per_rates[] = {
2039 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2043 static const struct clksel_rate emu_src_mpu_rates[] = {
2044 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2048 static const struct clksel emu_src_clksel[] = {
2049 { .parent = &sys_ck, .rates = emu_src_sys_rates },
2050 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2051 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
2052 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
2057 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2058 * to switch the source of some of the EMU clocks.
2059 * XXX Are there CLKEN bits for these EMU clks?
2061 static struct clk emu_src_ck = {
2062 .name = "emu_src_ck",
2063 .init = &omap2_init_clksel_parent,
2064 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2065 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2066 .clksel = emu_src_clksel,
2067 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2068 .recalc = &omap2_clksel_recalc,
2071 static const struct clksel_rate pclk_emu_rates[] = {
2072 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2073 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2074 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2075 { .div = 6, .val = 6, .flags = RATE_IN_343X },
2079 static const struct clksel pclk_emu_clksel[] = {
2080 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2084 static struct clk pclk_fck = {
2086 .init = &omap2_init_clksel_parent,
2087 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2088 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2089 .clksel = pclk_emu_clksel,
2090 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2091 .recalc = &omap2_clksel_recalc,
2094 static const struct clksel_rate pclkx2_emu_rates[] = {
2095 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2096 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2097 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2101 static const struct clksel pclkx2_emu_clksel[] = {
2102 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2106 static struct clk pclkx2_fck = {
2107 .name = "pclkx2_fck",
2108 .init = &omap2_init_clksel_parent,
2109 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2110 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2111 .clksel = pclkx2_emu_clksel,
2112 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2113 .recalc = &omap2_clksel_recalc,
2116 static const struct clksel atclk_emu_clksel[] = {
2117 { .parent = &emu_src_ck, .rates = div2_rates },
2121 static struct clk atclk_fck = {
2122 .name = "atclk_fck",
2123 .init = &omap2_init_clksel_parent,
2124 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2125 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
2126 .clksel = atclk_emu_clksel,
2127 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2128 .recalc = &omap2_clksel_recalc,
2131 static struct clk traceclk_src_fck = {
2132 .name = "traceclk_src_fck",
2133 .init = &omap2_init_clksel_parent,
2134 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2135 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
2136 .clksel = emu_src_clksel,
2137 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2138 .recalc = &omap2_clksel_recalc,
2141 static const struct clksel_rate traceclk_rates[] = {
2142 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2143 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2144 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2148 static const struct clksel traceclk_clksel[] = {
2149 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2153 static struct clk traceclk_fck = {
2154 .name = "traceclk_fck",
2155 .init = &omap2_init_clksel_parent,
2156 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2157 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
2158 .clksel = traceclk_clksel,
2159 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2160 .recalc = &omap2_clksel_recalc,
2165 /* SmartReflex fclk (VDD1) */
2166 static struct clk sr1_fck = {
2169 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2170 .enable_bit = OMAP3430_EN_SR1_SHIFT,
2171 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2172 .recalc = &followparent_recalc,
2175 /* SmartReflex fclk (VDD2) */
2176 static struct clk sr2_fck = {
2179 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2180 .enable_bit = OMAP3430_EN_SR2_SHIFT,
2181 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2182 .recalc = &followparent_recalc,
2185 static struct clk sr_l4_ick = {
2186 .name = "sr_l4_ick",
2188 .flags = CLOCK_IN_OMAP343X,
2189 .recalc = &followparent_recalc,
2192 /* SECURE_32K_FCK clocks */
2194 static struct clk gpt12_fck = {
2195 .name = "gpt12_fck",
2196 .parent = &secure_32k_fck,
2197 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2198 .recalc = &followparent_recalc,
2201 static struct clk wdt1_fck = {
2203 .parent = &secure_32k_fck,
2204 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2205 .recalc = &followparent_recalc,
2209 static struct clk *onchip_34xx_clks[] __initdata = {
2233 &omap_96m_alwon_fck,