arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  36 static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
  37
  38 /* Maximum DPLL multiplier, divider values for OMAP3 */
  39 #define OMAP3_MAX_DPLL_MULT             2048
  40 #define OMAP3_MAX_DPLL_DIV              128
  41
  42 /*
  43  * DPLL1 supplies clock to the MPU.
  44  * DPLL2 supplies clock to the IVA2.
  45  * DPLL3 supplies CORE domain clocks.
  46  * DPLL4 supplies peripheral clocks.
  47  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  48  */
  49
  50 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  51 #define DPLL_LOW_POWER_STOP             0x1
  52 #define DPLL_LOW_POWER_BYPASS           0x5
  53 #define DPLL_LOCKED                     0x7
  54
  55 /* PRM CLOCKS */
  56
  57 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  58 static struct clk omap_32k_fck = {
  59         .name           = "omap_32k_fck",
  60         .ops            = &clkops_null,
  61         .rate           = 32768,
  62         .flags          = RATE_FIXED | RATE_PROPAGATES,
  63 };
  64
  65 static struct clk secure_32k_fck = {
  66         .name           = "secure_32k_fck",
  67         .ops            = &clkops_null,
  68         .rate           = 32768,
  69         .flags          = RATE_FIXED | RATE_PROPAGATES,
  70 };
  71
  72 /* Virtual source clocks for osc_sys_ck */
  73 static struct clk virt_12m_ck = {
  74         .name           = "virt_12m_ck",
  75         .ops            = &clkops_null,
  76         .rate           = 12000000,
  77         .flags          = RATE_FIXED | RATE_PROPAGATES,
  78 };
  79
  80 static struct clk virt_13m_ck = {
  81         .name           = "virt_13m_ck",
  82         .ops            = &clkops_null,
  83         .rate           = 13000000,
  84         .flags          = RATE_FIXED | RATE_PROPAGATES,
  85 };
  86
  87 static struct clk virt_16_8m_ck = {
  88         .name           = "virt_16_8m_ck",
  89         .ops            = &clkops_null,
  90         .rate           = 16800000,
  91         .flags          = RATE_FIXED | RATE_PROPAGATES,
  92 };
  93
  94 static struct clk virt_19_2m_ck = {
  95         .name           = "virt_19_2m_ck",
  96         .ops            = &clkops_null,
  97         .rate           = 19200000,
  98         .flags          = RATE_FIXED | RATE_PROPAGATES,
  99 };
 100
 101 static struct clk virt_26m_ck = {
 102         .name           = "virt_26m_ck",
 103         .ops            = &clkops_null,
 104         .rate           = 26000000,
 105         .flags          = RATE_FIXED | RATE_PROPAGATES,
 106 };
 107
 108 static struct clk virt_38_4m_ck = {
 109         .name           = "virt_38_4m_ck",
 110         .ops            = &clkops_null,
 111         .rate           = 38400000,
 112         .flags          = RATE_FIXED | RATE_PROPAGATES,
 113 };
 114
 115 static const struct clksel_rate osc_sys_12m_rates[] = {
 116         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 117         { .div = 0 }
 118 };
 119
 120 static const struct clksel_rate osc_sys_13m_rates[] = {
 121         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 122         { .div = 0 }
 123 };
 124
 125 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 126         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 127         { .div = 0 }
 128 };
 129
 130 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 131         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 132         { .div = 0 }
 133 };
 134
 135 static const struct clksel_rate osc_sys_26m_rates[] = {
 136         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 137         { .div = 0 }
 138 };
 139
 140 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 141         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 142         { .div = 0 }
 143 };
 144
 145 static const struct clksel osc_sys_clksel[] = {
 146         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 147         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 148         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 149         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 150         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 151         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 152         { .parent = NULL },
 153 };
 154
 155 /* Oscillator clock */
 156 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 157 static struct clk osc_sys_ck = {
 158         .name           = "osc_sys_ck",
 159         .ops            = &clkops_null,
 160         .init           = &omap2_init_clksel_parent,
 161         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 162         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 163         .clksel         = osc_sys_clksel,
 164         /* REVISIT: deal with autoextclkmode? */
 165         .flags          = RATE_FIXED | RATE_PROPAGATES,
 166         .recalc         = &omap2_clksel_recalc,
 167 };
 168
 169 static const struct clksel_rate div2_rates[] = {
 170         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 171         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 172         { .div = 0 }
 173 };
 174
 175 static const struct clksel sys_clksel[] = {
 176         { .parent = &osc_sys_ck, .rates = div2_rates },
 177         { .parent = NULL }
 178 };
 179
 180 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 181 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 182 static struct clk sys_ck = {
 183         .name           = "sys_ck",
 184         .ops            = &clkops_null,
 185         .parent         = &osc_sys_ck,
 186         .init           = &omap2_init_clksel_parent,
 187         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 188         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 189         .clksel         = sys_clksel,
 190         .flags          = RATE_PROPAGATES,
 191         .recalc         = &omap2_clksel_recalc,
 192 };
 193
 194 static struct clk sys_altclk = {
 195         .name           = "sys_altclk",
 196         .ops            = &clkops_null,
 197         .flags          = RATE_PROPAGATES,
 198 };
 199
 200 /* Optional external clock input for some McBSPs */
 201 static struct clk mcbsp_clks = {
 202         .name           = "mcbsp_clks",
 203         .ops            = &clkops_null,
 204         .flags          = RATE_PROPAGATES,
 205 };
 206
 207 /* PRM EXTERNAL CLOCK OUTPUT */
 208
 209 static struct clk sys_clkout1 = {
 210         .name           = "sys_clkout1",
 211         .ops            = &clkops_omap2_dflt,
 212         .parent         = &osc_sys_ck,
 213         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 214         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 215         .recalc         = &followparent_recalc,
 216 };
 217
 218 /* DPLLS */
 219
 220 /* CM CLOCKS */
 221
 222 static const struct clksel_rate dpll_bypass_rates[] = {
 223         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 224         { .div = 0 }
 225 };
 226
 227 static const struct clksel_rate dpll_locked_rates[] = {
 228         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 229         { .div = 0 }
 230 };
 231
 232 static const struct clksel_rate div16_dpll_rates[] = {
 233         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 234         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 235         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 236         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 237         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 238         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 239         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 240         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 241         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 242         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 243         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 244         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 245         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 246         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 247         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 248         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 249         { .div = 0 }
 250 };
 251
 252 /* DPLL1 */
 253 /* MPU clock source */
 254 /* Type: DPLL */
 255 static struct dpll_data dpll1_dd = {
 256         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 257         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 258         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 259         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 260         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 261         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 262         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 263         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 264         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 265         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 266         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 267         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 268         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 269         .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
 270         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 271         .max_divider    = OMAP3_MAX_DPLL_DIV,
 272         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 273 };
 274
 275 static struct clk dpll1_ck = {
 276         .name           = "dpll1_ck",
 277         .ops            = &clkops_null,
 278         .parent         = &sys_ck,
 279         .dpll_data      = &dpll1_dd,
 280         .flags          = RATE_PROPAGATES,
 281         .round_rate     = &omap2_dpll_round_rate,
 282         .set_rate       = &omap3_noncore_dpll_set_rate,
 283         .recalc         = &omap3_dpll_recalc,
 284 };
 285
 286 /*
 287  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 288  * DPLL isn't bypassed.
 289  */
 290 static struct clk dpll1_x2_ck = {
 291         .name           = "dpll1_x2_ck",
 292         .ops            = &clkops_null,
 293         .parent         = &dpll1_ck,
 294         .flags          = RATE_PROPAGATES,
 295         .recalc         = &omap3_clkoutx2_recalc,
 296 };
 297
 298 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 299 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 300         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 301         { .parent = NULL }
 302 };
 303
 304 /*
 305  * Does not exist in the TRM - needed to separate the M2 divider from
 306  * bypass selection in mpu_ck
 307  */
 308 static struct clk dpll1_x2m2_ck = {
 309         .name           = "dpll1_x2m2_ck",
 310         .ops            = &clkops_null,
 311         .parent         = &dpll1_x2_ck,
 312         .init           = &omap2_init_clksel_parent,
 313         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 314         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 315         .clksel         = div16_dpll1_x2m2_clksel,
 316         .flags          = RATE_PROPAGATES,
 317         .recalc         = &omap2_clksel_recalc,
 318 };
 319
 320 /* DPLL2 */
 321 /* IVA2 clock source */
 322 /* Type: DPLL */
 323
 324 static struct dpll_data dpll2_dd = {
 325         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 326         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 327         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 328         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 329         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 330         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 331         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 332                                 (1 << DPLL_LOW_POWER_BYPASS),
 333         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 334         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 335         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 336         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 337         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 338         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 339         .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
 340         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 341         .max_divider    = OMAP3_MAX_DPLL_DIV,
 342         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 343 };
 344
 345 static struct clk dpll2_ck = {
 346         .name           = "dpll2_ck",
 347         .ops            = &clkops_noncore_dpll_ops,
 348         .parent         = &sys_ck,
 349         .dpll_data      = &dpll2_dd,
 350         .flags          = RATE_PROPAGATES,
 351         .round_rate     = &omap2_dpll_round_rate,
 352         .set_rate       = &omap3_noncore_dpll_set_rate,
 353         .recalc         = &omap3_dpll_recalc,
 354 };
 355
 356 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 357         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 358         { .parent = NULL }
 359 };
 360
 361 /*
 362  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 363  * or CLKOUTX2. CLKOUT seems most plausible.
 364  */
 365 static struct clk dpll2_m2_ck = {
 366         .name           = "dpll2_m2_ck",
 367         .ops            = &clkops_null,
 368         .parent         = &dpll2_ck,
 369         .init           = &omap2_init_clksel_parent,
 370         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 371                                           OMAP3430_CM_CLKSEL2_PLL),
 372         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 373         .clksel         = div16_dpll2_m2x2_clksel,
 374         .flags          = RATE_PROPAGATES,
 375         .recalc         = &omap2_clksel_recalc,
 376 };
 377
 378 /*
 379  * DPLL3
 380  * Source clock for all interfaces and for some device fclks
 381  * REVISIT: Also supports fast relock bypass - not included below
 382  */
 383 static struct dpll_data dpll3_dd = {
 384         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 385         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 386         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 387         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 388         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 389         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 390         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 391         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 392         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 393         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 394         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 395         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 396         .max_divider    = OMAP3_MAX_DPLL_DIV,
 397         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 398 };
 399
 400 static struct clk dpll3_ck = {
 401         .name           = "dpll3_ck",
 402         .ops            = &clkops_null,
 403         .parent         = &sys_ck,
 404         .dpll_data      = &dpll3_dd,
 405         .flags          = RATE_PROPAGATES,
 406         .round_rate     = &omap2_dpll_round_rate,
 407         .recalc         = &omap3_dpll_recalc,
 408 };
 409
 410 /*
 411  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 412  * DPLL isn't bypassed
 413  */
 414 static struct clk dpll3_x2_ck = {
 415         .name           = "dpll3_x2_ck",
 416         .ops            = &clkops_null,
 417         .parent         = &dpll3_ck,
 418         .flags          = RATE_PROPAGATES,
 419         .recalc         = &omap3_clkoutx2_recalc,
 420 };
 421
 422 static const struct clksel_rate div31_dpll3_rates[] = {
 423         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 424         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 425         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 426         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 427         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 428         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 429         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 430         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 431         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 432         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 433         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 434         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 435         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 436         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 437         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 438         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 439         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 440         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 441         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 442         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 443         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 444         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 445         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 446         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 447         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 448         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 449         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 450         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 451         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 452         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 453         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 454         { .div = 0 },
 455 };
 456
 457 static const struct clksel div31_dpll3m2_clksel[] = {
 458         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 459         { .parent = NULL }
 460 };
 461
 462 /*
 463  * DPLL3 output M2
 464  * REVISIT: This DPLL output divider must be changed in SRAM, so until
 465  * that code is ready, this should remain a 'read-only' clksel clock.
 466  */
 467 static struct clk dpll3_m2_ck = {
 468         .name           = "dpll3_m2_ck",
 469         .ops            = &clkops_null,
 470         .parent         = &dpll3_ck,
 471         .init           = &omap2_init_clksel_parent,
 472         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 473         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 474         .clksel         = div31_dpll3m2_clksel,
 475         .flags          = RATE_PROPAGATES,
 476         .recalc         = &omap2_clksel_recalc,
 477 };
 478
 479 static const struct clksel core_ck_clksel[] = {
 480         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 481         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 482         { .parent = NULL }
 483 };
 484
 485 static struct clk core_ck = {
 486         .name           = "core_ck",
 487         .ops            = &clkops_null,
 488         .init           = &omap2_init_clksel_parent,
 489         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 490         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 491         .clksel         = core_ck_clksel,
 492         .flags          = RATE_PROPAGATES,
 493         .recalc         = &omap2_clksel_recalc,
 494 };
 495
 496 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 497         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 498         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 499         { .parent = NULL }
 500 };
 501
 502 static struct clk dpll3_m2x2_ck = {
 503         .name           = "dpll3_m2x2_ck",
 504         .ops            = &clkops_null,
 505         .init           = &omap2_init_clksel_parent,
 506         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 507         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 508         .clksel         = dpll3_m2x2_ck_clksel,
 509         .flags          = RATE_PROPAGATES,
 510         .recalc         = &omap2_clksel_recalc,
 511 };
 512
 513 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 514 static const struct clksel div16_dpll3_clksel[] = {
 515         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 516         { .parent = NULL }
 517 };
 518
 519 /* This virtual clock is the source for dpll3_m3x2_ck */
 520 static struct clk dpll3_m3_ck = {
 521         .name           = "dpll3_m3_ck",
 522         .ops            = &clkops_null,
 523         .parent         = &dpll3_ck,
 524         .init           = &omap2_init_clksel_parent,
 525         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 526         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 527         .clksel         = div16_dpll3_clksel,
 528         .flags          = RATE_PROPAGATES,
 529         .recalc         = &omap2_clksel_recalc,
 530 };
 531
 532 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 533 static struct clk dpll3_m3x2_ck = {
 534         .name           = "dpll3_m3x2_ck",
 535         .ops            = &clkops_omap2_dflt_wait,
 536         .parent         = &dpll3_m3_ck,
 537         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 538         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 539         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 540         .recalc         = &omap3_clkoutx2_recalc,
 541 };
 542
 543 static const struct clksel emu_core_alwon_ck_clksel[] = {
 544         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 545         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 546         { .parent = NULL }
 547 };
 548
 549 static struct clk emu_core_alwon_ck = {
 550         .name           = "emu_core_alwon_ck",
 551         .ops            = &clkops_null,
 552         .parent         = &dpll3_m3x2_ck,
 553         .init           = &omap2_init_clksel_parent,
 554         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 555         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 556         .clksel         = emu_core_alwon_ck_clksel,
 557         .flags          = RATE_PROPAGATES,
 558         .recalc         = &omap2_clksel_recalc,
 559 };
 560
 561 /* DPLL4 */
 562 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 563 /* Type: DPLL */
 564 static struct dpll_data dpll4_dd = {
 565         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 566         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 567         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 568         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 569         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 570         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 571         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 572         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 573         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 574         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 575         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 576         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 577         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 578         .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
 579         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 580         .max_divider    = OMAP3_MAX_DPLL_DIV,
 581         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 582 };
 583
 584 static struct clk dpll4_ck = {
 585         .name           = "dpll4_ck",
 586         .ops            = &clkops_noncore_dpll_ops,
 587         .parent         = &sys_ck,
 588         .dpll_data      = &dpll4_dd,
 589         .flags          = RATE_PROPAGATES,
 590         .round_rate     = &omap2_dpll_round_rate,
 591         .set_rate       = &omap3_dpll4_set_rate,
 592         .recalc         = &omap3_dpll_recalc,
 593 };
 594
 595 /*
 596  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 597  * DPLL isn't bypassed --
 598  * XXX does this serve any downstream clocks?
 599  */
 600 static struct clk dpll4_x2_ck = {
 601         .name           = "dpll4_x2_ck",
 602         .ops            = &clkops_null,
 603         .parent         = &dpll4_ck,
 604         .flags          = RATE_PROPAGATES,
 605         .recalc         = &omap3_clkoutx2_recalc,
 606 };
 607
 608 static const struct clksel div16_dpll4_clksel[] = {
 609         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 610         { .parent = NULL }
 611 };
 612
 613 /* This virtual clock is the source for dpll4_m2x2_ck */
 614 static struct clk dpll4_m2_ck = {
 615         .name           = "dpll4_m2_ck",
 616         .ops            = &clkops_null,
 617         .parent         = &dpll4_ck,
 618         .init           = &omap2_init_clksel_parent,
 619         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 620         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 621         .clksel         = div16_dpll4_clksel,
 622         .flags          = RATE_PROPAGATES,
 623         .recalc         = &omap2_clksel_recalc,
 624 };
 625
 626 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 627 static struct clk dpll4_m2x2_ck = {
 628         .name           = "dpll4_m2x2_ck",
 629         .ops            = &clkops_omap2_dflt_wait,
 630         .parent         = &dpll4_m2_ck,
 631         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 632         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 633         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 634         .recalc         = &omap3_clkoutx2_recalc,
 635 };
 636
 637 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 638         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 639         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 640         { .parent = NULL }
 641 };
 642
 643 /*
 644  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 645  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 646  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 647  * CM_96K_(F)CLK.
 648  */
 649 static struct clk omap_96m_alwon_fck = {
 650         .name           = "omap_96m_alwon_fck",
 651         .ops            = &clkops_null,
 652         .parent         = &dpll4_m2x2_ck,
 653         .init           = &omap2_init_clksel_parent,
 654         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 655         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 656         .clksel         = omap_96m_alwon_fck_clksel,
 657         .flags          = RATE_PROPAGATES,
 658         .recalc         = &omap2_clksel_recalc,
 659 };
 660
 661 static struct clk cm_96m_fck = {
 662         .name           = "cm_96m_fck",
 663         .ops            = &clkops_null,
 664         .parent         = &omap_96m_alwon_fck,
 665         .flags          = RATE_PROPAGATES,
 666         .recalc         = &followparent_recalc,
 667 };
 668
 669 static const struct clksel_rate omap_96m_dpll_rates[] = {
 670         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 671         { .div = 0 }
 672 };
 673
 674 static const struct clksel_rate omap_96m_sys_rates[] = {
 675         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 676         { .div = 0 }
 677 };
 678
 679 static const struct clksel omap_96m_fck_clksel[] = {
 680         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 681         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 682         { .parent = NULL }
 683 };
 684
 685 static struct clk omap_96m_fck = {
 686         .name           = "omap_96m_fck",
 687         .ops            = &clkops_null,
 688         .parent         = &sys_ck,
 689         .init           = &omap2_init_clksel_parent,
 690         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 691         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 692         .clksel         = omap_96m_fck_clksel,
 693         .flags          = RATE_PROPAGATES,
 694         .recalc         = &omap2_clksel_recalc,
 695 };
 696
 697 /* This virtual clock is the source for dpll4_m3x2_ck */
 698 static struct clk dpll4_m3_ck = {
 699         .name           = "dpll4_m3_ck",
 700         .ops            = &clkops_null,
 701         .parent         = &dpll4_ck,
 702         .init           = &omap2_init_clksel_parent,
 703         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 704         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 705         .clksel         = div16_dpll4_clksel,
 706         .flags          = RATE_PROPAGATES,
 707         .recalc         = &omap2_clksel_recalc,
 708 };
 709
 710 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 711 static struct clk dpll4_m3x2_ck = {
 712         .name           = "dpll4_m3x2_ck",
 713         .ops            = &clkops_omap2_dflt_wait,
 714         .parent         = &dpll4_m3_ck,
 715         .init           = &omap2_init_clksel_parent,
 716         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 717         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 718         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 719         .recalc         = &omap3_clkoutx2_recalc,
 720 };
 721
 722 static const struct clksel virt_omap_54m_fck_clksel[] = {
 723         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 724         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 725         { .parent = NULL }
 726 };
 727
 728 static struct clk virt_omap_54m_fck = {
 729         .name           = "virt_omap_54m_fck",
 730         .ops            = &clkops_null,
 731         .parent         = &dpll4_m3x2_ck,
 732         .init           = &omap2_init_clksel_parent,
 733         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 734         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 735         .clksel         = virt_omap_54m_fck_clksel,
 736         .flags          = RATE_PROPAGATES,
 737         .recalc         = &omap2_clksel_recalc,
 738 };
 739
 740 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 741         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 742         { .div = 0 }
 743 };
 744
 745 static const struct clksel_rate omap_54m_alt_rates[] = {
 746         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 747         { .div = 0 }
 748 };
 749
 750 static const struct clksel omap_54m_clksel[] = {
 751         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 752         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 753         { .parent = NULL }
 754 };
 755
 756 static struct clk omap_54m_fck = {
 757         .name           = "omap_54m_fck",
 758         .ops            = &clkops_null,
 759         .init           = &omap2_init_clksel_parent,
 760         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 761         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 762         .clksel         = omap_54m_clksel,
 763         .flags          = RATE_PROPAGATES,
 764         .recalc         = &omap2_clksel_recalc,
 765 };
 766
 767 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 768         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 769         { .div = 0 }
 770 };
 771
 772 static const struct clksel_rate omap_48m_alt_rates[] = {
 773         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 774         { .div = 0 }
 775 };
 776
 777 static const struct clksel omap_48m_clksel[] = {
 778         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 779         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 780         { .parent = NULL }
 781 };
 782
 783 static struct clk omap_48m_fck = {
 784         .name           = "omap_48m_fck",
 785         .ops            = &clkops_null,
 786         .init           = &omap2_init_clksel_parent,
 787         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 788         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 789         .clksel         = omap_48m_clksel,
 790         .flags          = RATE_PROPAGATES,
 791         .recalc         = &omap2_clksel_recalc,
 792 };
 793
 794 static struct clk omap_12m_fck = {
 795         .name           = "omap_12m_fck",
 796         .ops            = &clkops_null,
 797         .parent         = &omap_48m_fck,
 798         .fixed_div      = 4,
 799         .flags          = RATE_PROPAGATES,
 800         .recalc         = &omap2_fixed_divisor_recalc,
 801 };
 802
 803 /* This virstual clock is the source for dpll4_m4x2_ck */
 804 static struct clk dpll4_m4_ck = {
 805         .name           = "dpll4_m4_ck",
 806         .ops            = &clkops_null,
 807         .parent         = &dpll4_ck,
 808         .init           = &omap2_init_clksel_parent,
 809         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 810         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 811         .clksel         = div16_dpll4_clksel,
 812         .flags          = RATE_PROPAGATES,
 813         .recalc         = &omap2_clksel_recalc,
 814         .set_rate       = &omap2_clksel_set_rate,
 815         .round_rate     = &omap2_clksel_round_rate,
 816 };
 817
 818 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 819 static struct clk dpll4_m4x2_ck = {
 820         .name           = "dpll4_m4x2_ck",
 821         .ops            = &clkops_omap2_dflt_wait,
 822         .parent         = &dpll4_m4_ck,
 823         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 824         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 825         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 826         .recalc         = &omap3_clkoutx2_recalc,
 827 };
 828
 829 /* This virtual clock is the source for dpll4_m5x2_ck */
 830 static struct clk dpll4_m5_ck = {
 831         .name           = "dpll4_m5_ck",
 832         .ops            = &clkops_null,
 833         .parent         = &dpll4_ck,
 834         .init           = &omap2_init_clksel_parent,
 835         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 836         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 837         .clksel         = div16_dpll4_clksel,
 838         .flags          = RATE_PROPAGATES,
 839         .recalc         = &omap2_clksel_recalc,
 840 };
 841
 842 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 843 static struct clk dpll4_m5x2_ck = {
 844         .name           = "dpll4_m5x2_ck",
 845         .ops            = &clkops_omap2_dflt_wait,
 846         .parent         = &dpll4_m5_ck,
 847         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 848         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 849         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 850         .recalc         = &omap3_clkoutx2_recalc,
 851 };
 852
 853 /* This virtual clock is the source for dpll4_m6x2_ck */
 854 static struct clk dpll4_m6_ck = {
 855         .name           = "dpll4_m6_ck",
 856         .ops            = &clkops_null,
 857         .parent         = &dpll4_ck,
 858         .init           = &omap2_init_clksel_parent,
 859         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 860         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 861         .clksel         = div16_dpll4_clksel,
 862         .flags          = RATE_PROPAGATES,
 863         .recalc         = &omap2_clksel_recalc,
 864 };
 865
 866 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 867 static struct clk dpll4_m6x2_ck = {
 868         .name           = "dpll4_m6x2_ck",
 869         .ops            = &clkops_omap2_dflt_wait,
 870         .parent         = &dpll4_m6_ck,
 871         .init           = &omap2_init_clksel_parent,
 872         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 873         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 874         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 875         .recalc         = &omap3_clkoutx2_recalc,
 876 };
 877
 878 static struct clk emu_per_alwon_ck = {
 879         .name           = "emu_per_alwon_ck",
 880         .ops            = &clkops_null,
 881         .parent         = &dpll4_m6x2_ck,
 882         .flags          = RATE_PROPAGATES,
 883         .recalc         = &followparent_recalc,
 884 };
 885
 886 /* DPLL5 */
 887 /* Supplies 120MHz clock, USIM source clock */
 888 /* Type: DPLL */
 889 /* 3430ES2 only */
 890 static struct dpll_data dpll5_dd = {
 891         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 892         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 893         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 894         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 895         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 896         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 897         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 898         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 899         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 900         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 901         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 902         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 903         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 904         .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
 905         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 906         .max_divider    = OMAP3_MAX_DPLL_DIV,
 907         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 908 };
 909
 910 static struct clk dpll5_ck = {
 911         .name           = "dpll5_ck",
 912         .ops            = &clkops_noncore_dpll_ops,
 913         .parent         = &sys_ck,
 914         .dpll_data      = &dpll5_dd,
 915         .flags          = RATE_PROPAGATES,
 916         .round_rate     = &omap2_dpll_round_rate,
 917         .set_rate       = &omap3_noncore_dpll_set_rate,
 918         .recalc         = &omap3_dpll_recalc,
 919 };
 920
 921 static const struct clksel div16_dpll5_clksel[] = {
 922         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 923         { .parent = NULL }
 924 };
 925
 926 static struct clk dpll5_m2_ck = {
 927         .name           = "dpll5_m2_ck",
 928         .ops            = &clkops_null,
 929         .parent         = &dpll5_ck,
 930         .init           = &omap2_init_clksel_parent,
 931         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 932         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 933         .clksel         = div16_dpll5_clksel,
 934         .flags          = RATE_PROPAGATES,
 935         .recalc         = &omap2_clksel_recalc,
 936 };
 937
 938 static const struct clksel omap_120m_fck_clksel[] = {
 939         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 940         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
 941         { .parent = NULL }
 942 };
 943
 944 static struct clk omap_120m_fck = {
 945         .name           = "omap_120m_fck",
 946         .ops            = &clkops_null,
 947         .parent         = &dpll5_m2_ck,
 948         .init           = &omap2_init_clksel_parent,
 949         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 950         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 951         .clksel         = omap_120m_fck_clksel,
 952         .flags          = RATE_PROPAGATES,
 953         .recalc         = &omap2_clksel_recalc,
 954 };
 955
 956 /* CM EXTERNAL CLOCK OUTPUTS */
 957
 958 static const struct clksel_rate clkout2_src_core_rates[] = {
 959         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 960         { .div = 0 }
 961 };
 962
 963 static const struct clksel_rate clkout2_src_sys_rates[] = {
 964         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 965         { .div = 0 }
 966 };
 967
 968 static const struct clksel_rate clkout2_src_96m_rates[] = {
 969         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 970         { .div = 0 }
 971 };
 972
 973 static const struct clksel_rate clkout2_src_54m_rates[] = {
 974         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 975         { .div = 0 }
 976 };
 977
 978 static const struct clksel clkout2_src_clksel[] = {
 979         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
 980         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
 981         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
 982         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
 983         { .parent = NULL }
 984 };
 985
 986 static struct clk clkout2_src_ck = {
 987         .name           = "clkout2_src_ck",
 988         .ops            = &clkops_omap2_dflt,
 989         .init           = &omap2_init_clksel_parent,
 990         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
 991         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 992         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 993         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 994         .clksel         = clkout2_src_clksel,
 995         .flags          = RATE_PROPAGATES,
 996         .clkdm_name     = "core_clkdm",
 997         .recalc         = &omap2_clksel_recalc,
 998 };
 999
1000 static const struct clksel_rate sys_clkout2_rates[] = {
1001         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1002         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1003         { .div = 4, .val = 2, .flags = RATE_IN_343X },
1004         { .div = 8, .val = 3, .flags = RATE_IN_343X },
1005         { .div = 16, .val = 4, .flags = RATE_IN_343X },
1006         { .div = 0 },
1007 };
1008
1009 static const struct clksel sys_clkout2_clksel[] = {
1010         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1011         { .parent = NULL },
1012 };
1013
1014 static struct clk sys_clkout2 = {
1015         .name           = "sys_clkout2",
1016         .ops            = &clkops_null,
1017         .init           = &omap2_init_clksel_parent,
1018         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
1019         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1020         .clksel         = sys_clkout2_clksel,
1021         .recalc         = &omap2_clksel_recalc,
1022 };
1023
1024 /* CM OUTPUT CLOCKS */
1025
1026 static struct clk corex2_fck = {
1027         .name           = "corex2_fck",
1028         .ops            = &clkops_null,
1029         .parent         = &dpll3_m2x2_ck,
1030         .flags          = RATE_PROPAGATES,
1031         .recalc         = &followparent_recalc,
1032 };
1033
1034 /* DPLL power domain clock controls */
1035
1036 static const struct clksel div2_core_clksel[] = {
1037         { .parent = &core_ck, .rates = div2_rates },
1038         { .parent = NULL }
1039 };
1040
1041 /*
1042  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1043  * may be inconsistent here?
1044  */
1045 static struct clk dpll1_fck = {
1046         .name           = "dpll1_fck",
1047         .ops            = &clkops_null,
1048         .parent         = &core_ck,
1049         .init           = &omap2_init_clksel_parent,
1050         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1051         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1052         .clksel         = div2_core_clksel,
1053         .flags          = RATE_PROPAGATES,
1054         .recalc         = &omap2_clksel_recalc,
1055 };
1056
1057 /*
1058  * MPU clksel:
1059  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1060  * derives from the high-frequency bypass clock originating from DPLL3,
1061  * called 'dpll1_fck'
1062  */
1063 static const struct clksel mpu_clksel[] = {
1064         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1065         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1066         { .parent = NULL }
1067 };
1068
1069 static struct clk mpu_ck = {
1070         .name           = "mpu_ck",
1071         .ops            = &clkops_null,
1072         .parent         = &dpll1_x2m2_ck,
1073         .init           = &omap2_init_clksel_parent,
1074         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1075         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1076         .clksel         = mpu_clksel,
1077         .flags          = RATE_PROPAGATES,
1078         .clkdm_name     = "mpu_clkdm",
1079         .recalc         = &omap2_clksel_recalc,
1080 };
1081
1082 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1083 static const struct clksel_rate arm_fck_rates[] = {
1084         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1085         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1086         { .div = 0 },
1087 };
1088
1089 static const struct clksel arm_fck_clksel[] = {
1090         { .parent = &mpu_ck, .rates = arm_fck_rates },
1091         { .parent = NULL }
1092 };
1093
1094 static struct clk arm_fck = {
1095         .name           = "arm_fck",
1096         .ops            = &clkops_null,
1097         .parent         = &mpu_ck,
1098         .init           = &omap2_init_clksel_parent,
1099         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1100         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1101         .clksel         = arm_fck_clksel,
1102         .flags          = RATE_PROPAGATES,
1103         .recalc         = &omap2_clksel_recalc,
1104 };
1105
1106 /* XXX What about neon_clkdm ? */
1107
1108 /*
1109  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1110  * although it is referenced - so this is a guess
1111  */
1112 static struct clk emu_mpu_alwon_ck = {
1113         .name           = "emu_mpu_alwon_ck",
1114         .ops            = &clkops_null,
1115         .parent         = &mpu_ck,
1116         .flags          = RATE_PROPAGATES,
1117         .recalc         = &followparent_recalc,
1118 };
1119
1120 static struct clk dpll2_fck = {
1121         .name           = "dpll2_fck",
1122         .ops            = &clkops_null,
1123         .parent         = &core_ck,
1124         .init           = &omap2_init_clksel_parent,
1125         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1126         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1127         .clksel         = div2_core_clksel,
1128         .flags          = RATE_PROPAGATES,
1129         .recalc         = &omap2_clksel_recalc,
1130 };
1131
1132 /*
1133  * IVA2 clksel:
1134  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1135  * derives from the high-frequency bypass clock originating from DPLL3,
1136  * called 'dpll2_fck'
1137  */
1138
1139 static const struct clksel iva2_clksel[] = {
1140         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1141         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1142         { .parent = NULL }
1143 };
1144
1145 static struct clk iva2_ck = {
1146         .name           = "iva2_ck",
1147         .ops            = &clkops_omap2_dflt_wait,
1148         .parent         = &dpll2_m2_ck,
1149         .init           = &omap2_init_clksel_parent,
1150         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1151         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1152         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1153                                           OMAP3430_CM_IDLEST_PLL),
1154         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1155         .clksel         = iva2_clksel,
1156         .flags          = RATE_PROPAGATES,
1157         .clkdm_name     = "iva2_clkdm",
1158         .recalc         = &omap2_clksel_recalc,
1159 };
1160
1161 /* Common interface clocks */
1162
1163 static struct clk l3_ick = {
1164         .name           = "l3_ick",
1165         .ops            = &clkops_null,
1166         .parent         = &core_ck,
1167         .init           = &omap2_init_clksel_parent,
1168         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1169         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1170         .clksel         = div2_core_clksel,
1171         .flags          = RATE_PROPAGATES,
1172         .clkdm_name     = "core_l3_clkdm",
1173         .recalc         = &omap2_clksel_recalc,
1174 };
1175
1176 static const struct clksel div2_l3_clksel[] = {
1177         { .parent = &l3_ick, .rates = div2_rates },
1178         { .parent = NULL }
1179 };
1180
1181 static struct clk l4_ick = {
1182         .name           = "l4_ick",
1183         .ops            = &clkops_null,
1184         .parent         = &l3_ick,
1185         .init           = &omap2_init_clksel_parent,
1186         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1187         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1188         .clksel         = div2_l3_clksel,
1189         .flags          = RATE_PROPAGATES,
1190         .clkdm_name     = "core_l4_clkdm",
1191         .recalc         = &omap2_clksel_recalc,
1192
1193 };
1194
1195 static const struct clksel div2_l4_clksel[] = {
1196         { .parent = &l4_ick, .rates = div2_rates },
1197         { .parent = NULL }
1198 };
1199
1200 static struct clk rm_ick = {
1201         .name           = "rm_ick",
1202         .ops            = &clkops_null,
1203         .parent         = &l4_ick,
1204         .init           = &omap2_init_clksel_parent,
1205         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1206         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1207         .clksel         = div2_l4_clksel,
1208         .recalc         = &omap2_clksel_recalc,
1209 };
1210
1211 /* GFX power domain */
1212
1213 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1214
1215 static const struct clksel gfx_l3_clksel[] = {
1216         { .parent = &l3_ick, .rates = gfx_l3_rates },
1217         { .parent = NULL }
1218 };
1219
1220 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1221 static struct clk gfx_l3_ck = {
1222         .name           = "gfx_l3_ck",
1223         .ops            = &clkops_omap2_dflt_wait,
1224         .parent         = &l3_ick,
1225         .init           = &omap2_init_clksel_parent,
1226         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1227         .enable_bit     = OMAP_EN_GFX_SHIFT,
1228         .recalc         = &followparent_recalc,
1229 };
1230
1231 static struct clk gfx_l3_fck = {
1232         .name           = "gfx_l3_fck",
1233         .ops            = &clkops_null,
1234         .parent         = &gfx_l3_ck,
1235         .init           = &omap2_init_clksel_parent,
1236         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1237         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1238         .clksel         = gfx_l3_clksel,
1239         .flags          = RATE_PROPAGATES,
1240         .clkdm_name     = "gfx_3430es1_clkdm",
1241         .recalc         = &omap2_clksel_recalc,
1242 };
1243
1244 static struct clk gfx_l3_ick = {
1245         .name           = "gfx_l3_ick",
1246         .ops            = &clkops_null,
1247         .parent         = &gfx_l3_ck,
1248         .clkdm_name     = "gfx_3430es1_clkdm",
1249         .recalc         = &followparent_recalc,
1250 };
1251
1252 static struct clk gfx_cg1_ck = {
1253         .name           = "gfx_cg1_ck",
1254         .ops            = &clkops_omap2_dflt_wait,
1255         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1256         .init           = &omap2_init_clk_clkdm,
1257         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1258         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1259         .clkdm_name     = "gfx_3430es1_clkdm",
1260         .recalc         = &followparent_recalc,
1261 };
1262
1263 static struct clk gfx_cg2_ck = {
1264         .name           = "gfx_cg2_ck",
1265         .ops            = &clkops_omap2_dflt_wait,
1266         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1267         .init           = &omap2_init_clk_clkdm,
1268         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1269         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1270         .clkdm_name     = "gfx_3430es1_clkdm",
1271         .recalc         = &followparent_recalc,
1272 };
1273
1274 /* SGX power domain - 3430ES2 only */
1275
1276 static const struct clksel_rate sgx_core_rates[] = {
1277         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1278         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1279         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1280         { .div = 0 },
1281 };
1282
1283 static const struct clksel_rate sgx_96m_rates[] = {
1284         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1285         { .div = 0 },
1286 };
1287
1288 static const struct clksel sgx_clksel[] = {
1289         { .parent = &core_ck,    .rates = sgx_core_rates },
1290         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1291         { .parent = NULL },
1292 };
1293
1294 static struct clk sgx_fck = {
1295         .name           = "sgx_fck",
1296         .ops            = &clkops_omap2_dflt_wait,
1297         .init           = &omap2_init_clksel_parent,
1298         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1299         .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1300         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1301         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1302         .clksel         = sgx_clksel,
1303         .clkdm_name     = "sgx_clkdm",
1304         .recalc         = &omap2_clksel_recalc,
1305 };
1306
1307 static struct clk sgx_ick = {
1308         .name           = "sgx_ick",
1309         .ops            = &clkops_omap2_dflt_wait,
1310         .parent         = &l3_ick,
1311         .init           = &omap2_init_clk_clkdm,
1312         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1313         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1314         .clkdm_name     = "sgx_clkdm",
1315         .recalc         = &followparent_recalc,
1316 };
1317
1318 /* CORE power domain */
1319
1320 static struct clk d2d_26m_fck = {
1321         .name           = "d2d_26m_fck",
1322         .ops            = &clkops_omap2_dflt_wait,
1323         .parent         = &sys_ck,
1324         .init           = &omap2_init_clk_clkdm,
1325         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1326         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1327         .clkdm_name     = "d2d_clkdm",
1328         .recalc         = &followparent_recalc,
1329 };
1330
1331 static const struct clksel omap343x_gpt_clksel[] = {
1332         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1333         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1334         { .parent = NULL}
1335 };
1336
1337 static struct clk gpt10_fck = {
1338         .name           = "gpt10_fck",
1339         .ops            = &clkops_omap2_dflt_wait,
1340         .parent         = &sys_ck,
1341         .init           = &omap2_init_clksel_parent,
1342         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1343         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1344         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1345         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1346         .clksel         = omap343x_gpt_clksel,
1347         .clkdm_name     = "core_l4_clkdm",
1348         .recalc         = &omap2_clksel_recalc,
1349 };
1350
1351 static struct clk gpt11_fck = {
1352         .name           = "gpt11_fck",
1353         .ops            = &clkops_omap2_dflt_wait,
1354         .parent         = &sys_ck,
1355         .init           = &omap2_init_clksel_parent,
1356         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1357         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1358         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1359         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1360         .clksel         = omap343x_gpt_clksel,
1361         .clkdm_name     = "core_l4_clkdm",
1362         .recalc         = &omap2_clksel_recalc,
1363 };
1364
1365 static struct clk cpefuse_fck = {
1366         .name           = "cpefuse_fck",
1367         .ops            = &clkops_omap2_dflt,
1368         .parent         = &sys_ck,
1369         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1370         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1371         .recalc         = &followparent_recalc,
1372 };
1373
1374 static struct clk ts_fck = {
1375         .name           = "ts_fck",
1376         .ops            = &clkops_omap2_dflt,
1377         .parent         = &omap_32k_fck,
1378         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1379         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1380         .recalc         = &followparent_recalc,
1381 };
1382
1383 static struct clk usbtll_fck = {
1384         .name           = "usbtll_fck",
1385         .ops            = &clkops_omap2_dflt,
1386         .parent         = &omap_120m_fck,
1387         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1388         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1389         .recalc         = &followparent_recalc,
1390 };
1391
1392 /* CORE 96M FCLK-derived clocks */
1393
1394 static struct clk core_96m_fck = {
1395         .name           = "core_96m_fck",
1396         .ops            = &clkops_null,
1397         .parent         = &omap_96m_fck,
1398         .flags          = RATE_PROPAGATES,
1399         .clkdm_name     = "core_l4_clkdm",
1400         .recalc         = &followparent_recalc,
1401 };
1402
1403 static struct clk mmchs3_fck = {
1404         .name           = "mmchs_fck",
1405         .ops            = &clkops_omap2_dflt_wait,
1406         .id             = 2,
1407         .parent         = &core_96m_fck,
1408         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1409         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1410         .clkdm_name     = "core_l4_clkdm",
1411         .recalc         = &followparent_recalc,
1412 };
1413
1414 static struct clk mmchs2_fck = {
1415         .name           = "mmchs_fck",
1416         .ops            = &clkops_omap2_dflt_wait,
1417         .id             = 1,
1418         .parent         = &core_96m_fck,
1419         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1420         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1421         .clkdm_name     = "core_l4_clkdm",
1422         .recalc         = &followparent_recalc,
1423 };
1424
1425 static struct clk mspro_fck = {
1426         .name           = "mspro_fck",
1427         .ops            = &clkops_omap2_dflt_wait,
1428         .parent         = &core_96m_fck,
1429         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1430         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1431         .clkdm_name     = "core_l4_clkdm",
1432         .recalc         = &followparent_recalc,
1433 };
1434
1435 static struct clk mmchs1_fck = {
1436         .name           = "mmchs_fck",
1437         .ops            = &clkops_omap2_dflt_wait,
1438         .parent         = &core_96m_fck,
1439         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1440         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1441         .clkdm_name     = "core_l4_clkdm",
1442         .recalc         = &followparent_recalc,
1443 };
1444
1445 static struct clk i2c3_fck = {
1446         .name           = "i2c_fck",
1447         .ops            = &clkops_omap2_dflt_wait,
1448         .id             = 3,
1449         .parent         = &core_96m_fck,
1450         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1451         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1452         .clkdm_name     = "core_l4_clkdm",
1453         .recalc         = &followparent_recalc,
1454 };
1455
1456 static struct clk i2c2_fck = {
1457         .name           = "i2c_fck",
1458         .ops            = &clkops_omap2_dflt_wait,
1459         .id             = 2,
1460         .parent         = &core_96m_fck,
1461         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1462         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1463         .clkdm_name     = "core_l4_clkdm",
1464         .recalc         = &followparent_recalc,
1465 };
1466
1467 static struct clk i2c1_fck = {
1468         .name           = "i2c_fck",
1469         .ops            = &clkops_omap2_dflt_wait,
1470         .id             = 1,
1471         .parent         = &core_96m_fck,
1472         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1473         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1474         .clkdm_name     = "core_l4_clkdm",
1475         .recalc         = &followparent_recalc,
1476 };
1477
1478 /*
1479  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1480  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1481  */
1482 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1483         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1484         { .div = 0 }
1485 };
1486
1487 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1488         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1489         { .div = 0 }
1490 };
1491
1492 static const struct clksel mcbsp_15_clksel[] = {
1493         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1494         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1495         { .parent = NULL }
1496 };
1497
1498 static struct clk mcbsp5_fck = {
1499         .name           = "mcbsp_fck",
1500         .ops            = &clkops_omap2_dflt_wait,
1501         .id             = 5,
1502         .init           = &omap2_init_clksel_parent,
1503         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1504         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1505         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1506         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1507         .clksel         = mcbsp_15_clksel,
1508         .clkdm_name     = "core_l4_clkdm",
1509         .recalc         = &omap2_clksel_recalc,
1510 };
1511
1512 static struct clk mcbsp1_fck = {
1513         .name           = "mcbsp_fck",
1514         .ops            = &clkops_omap2_dflt_wait,
1515         .id             = 1,
1516         .init           = &omap2_init_clksel_parent,
1517         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1518         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1519         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1520         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1521         .clksel         = mcbsp_15_clksel,
1522         .clkdm_name     = "core_l4_clkdm",
1523         .recalc         = &omap2_clksel_recalc,
1524 };
1525
1526 /* CORE_48M_FCK-derived clocks */
1527
1528 static struct clk core_48m_fck = {
1529         .name           = "core_48m_fck",
1530         .ops            = &clkops_null,
1531         .parent         = &omap_48m_fck,
1532         .flags          = RATE_PROPAGATES,
1533         .clkdm_name     = "core_l4_clkdm",
1534         .recalc         = &followparent_recalc,
1535 };
1536
1537 static struct clk mcspi4_fck = {
1538         .name           = "mcspi_fck",
1539         .ops            = &clkops_omap2_dflt_wait,
1540         .id             = 4,
1541         .parent         = &core_48m_fck,
1542         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1543         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1544         .recalc         = &followparent_recalc,
1545 };
1546
1547 static struct clk mcspi3_fck = {
1548         .name           = "mcspi_fck",
1549         .ops            = &clkops_omap2_dflt_wait,
1550         .id             = 3,
1551         .parent         = &core_48m_fck,
1552         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1553         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1554         .recalc         = &followparent_recalc,
1555 };
1556
1557 static struct clk mcspi2_fck = {
1558         .name           = "mcspi_fck",
1559         .ops            = &clkops_omap2_dflt_wait,
1560         .id             = 2,
1561         .parent         = &core_48m_fck,
1562         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1563         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1564         .recalc         = &followparent_recalc,
1565 };
1566
1567 static struct clk mcspi1_fck = {
1568         .name           = "mcspi_fck",
1569         .ops            = &clkops_omap2_dflt_wait,
1570         .id             = 1,
1571         .parent         = &core_48m_fck,
1572         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1573         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1574         .recalc         = &followparent_recalc,
1575 };
1576
1577 static struct clk uart2_fck = {
1578         .name           = "uart2_fck",
1579         .ops            = &clkops_omap2_dflt_wait,
1580         .parent         = &core_48m_fck,
1581         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1582         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1583         .recalc         = &followparent_recalc,
1584 };
1585
1586 static struct clk uart1_fck = {
1587         .name           = "uart1_fck",
1588         .ops            = &clkops_omap2_dflt_wait,
1589         .parent         = &core_48m_fck,
1590         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1591         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1592         .recalc         = &followparent_recalc,
1593 };
1594
1595 static struct clk fshostusb_fck = {
1596         .name           = "fshostusb_fck",
1597         .ops            = &clkops_omap2_dflt_wait,
1598         .parent         = &core_48m_fck,
1599         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1600         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1601         .recalc         = &followparent_recalc,
1602 };
1603
1604 /* CORE_12M_FCK based clocks */
1605
1606 static struct clk core_12m_fck = {
1607         .name           = "core_12m_fck",
1608         .ops            = &clkops_null,
1609         .parent         = &omap_12m_fck,
1610         .flags          = RATE_PROPAGATES,
1611         .clkdm_name     = "core_l4_clkdm",
1612         .recalc         = &followparent_recalc,
1613 };
1614
1615 static struct clk hdq_fck = {
1616         .name           = "hdq_fck",
1617         .ops            = &clkops_omap2_dflt_wait,
1618         .parent         = &core_12m_fck,
1619         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1620         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1621         .recalc         = &followparent_recalc,
1622 };
1623
1624 /* DPLL3-derived clock */
1625
1626 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1627         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1628         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1629         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1630         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1631         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1632         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1633         { .div = 0 }
1634 };
1635
1636 static const struct clksel ssi_ssr_clksel[] = {
1637         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1638         { .parent = NULL }
1639 };
1640
1641 static struct clk ssi_ssr_fck = {
1642         .name           = "ssi_ssr_fck",
1643         .ops            = &clkops_omap2_dflt,
1644         .init           = &omap2_init_clksel_parent,
1645         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1646         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1647         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1648         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1649         .clksel         = ssi_ssr_clksel,
1650         .flags          = RATE_PROPAGATES,
1651         .clkdm_name     = "core_l4_clkdm",
1652         .recalc         = &omap2_clksel_recalc,
1653 };
1654
1655 static struct clk ssi_sst_fck = {
1656         .name           = "ssi_sst_fck",
1657         .ops            = &clkops_null,
1658         .parent         = &ssi_ssr_fck,
1659         .fixed_div      = 2,
1660         .recalc         = &omap2_fixed_divisor_recalc,
1661 };
1662
1663
1664
1665 /* CORE_L3_ICK based clocks */
1666
1667 /*
1668  * XXX must add clk_enable/clk_disable for these if standard code won't
1669  * handle it
1670  */
1671 static struct clk core_l3_ick = {
1672         .name           = "core_l3_ick",
1673         .ops            = &clkops_null,
1674         .parent         = &l3_ick,
1675         .init           = &omap2_init_clk_clkdm,
1676         .flags          = RATE_PROPAGATES,
1677         .clkdm_name     = "core_l3_clkdm",
1678         .recalc         = &followparent_recalc,
1679 };
1680
1681 static struct clk hsotgusb_ick = {
1682         .name           = "hsotgusb_ick",
1683         .ops            = &clkops_omap2_dflt_wait,
1684         .parent         = &core_l3_ick,
1685         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1686         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1687         .clkdm_name     = "core_l3_clkdm",
1688         .recalc         = &followparent_recalc,
1689 };
1690
1691 static struct clk sdrc_ick = {
1692         .name           = "sdrc_ick",
1693         .ops            = &clkops_omap2_dflt_wait,
1694         .parent         = &core_l3_ick,
1695         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1696         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1697         .flags          = ENABLE_ON_INIT,
1698         .clkdm_name     = "core_l3_clkdm",
1699         .recalc         = &followparent_recalc,
1700 };
1701
1702 static struct clk gpmc_fck = {
1703         .name           = "gpmc_fck",
1704         .ops            = &clkops_null,
1705         .parent         = &core_l3_ick,
1706         .flags          = ENABLE_ON_INIT, /* huh? */
1707         .clkdm_name     = "core_l3_clkdm",
1708         .recalc         = &followparent_recalc,
1709 };
1710
1711 /* SECURITY_L3_ICK based clocks */
1712
1713 static struct clk security_l3_ick = {
1714         .name           = "security_l3_ick",
1715         .ops            = &clkops_null,
1716         .parent         = &l3_ick,
1717         .flags          = RATE_PROPAGATES,
1718         .recalc         = &followparent_recalc,
1719 };
1720
1721 static struct clk pka_ick = {
1722         .name           = "pka_ick",
1723         .ops            = &clkops_omap2_dflt_wait,
1724         .parent         = &security_l3_ick,
1725         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1726         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1727         .recalc         = &followparent_recalc,
1728 };
1729
1730 /* CORE_L4_ICK based clocks */
1731
1732 static struct clk core_l4_ick = {
1733         .name           = "core_l4_ick",
1734         .ops            = &clkops_null,
1735         .parent         = &l4_ick,
1736         .init           = &omap2_init_clk_clkdm,
1737         .flags          = RATE_PROPAGATES,
1738         .clkdm_name     = "core_l4_clkdm",
1739         .recalc         = &followparent_recalc,
1740 };
1741
1742 static struct clk usbtll_ick = {
1743         .name           = "usbtll_ick",
1744         .ops            = &clkops_omap2_dflt_wait,
1745         .parent         = &core_l4_ick,
1746         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1747         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1748         .clkdm_name     = "core_l4_clkdm",
1749         .recalc         = &followparent_recalc,
1750 };
1751
1752 static struct clk mmchs3_ick = {
1753         .name           = "mmchs_ick",
1754         .ops            = &clkops_omap2_dflt_wait,
1755         .id             = 2,
1756         .parent         = &core_l4_ick,
1757         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1758         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1759         .clkdm_name     = "core_l4_clkdm",
1760         .recalc         = &followparent_recalc,
1761 };
1762
1763 /* Intersystem Communication Registers - chassis mode only */
1764 static struct clk icr_ick = {
1765         .name           = "icr_ick",
1766         .ops            = &clkops_omap2_dflt_wait,
1767         .parent         = &core_l4_ick,
1768         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1769         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1770         .clkdm_name     = "core_l4_clkdm",
1771         .recalc         = &followparent_recalc,
1772 };
1773
1774 static struct clk aes2_ick = {
1775         .name           = "aes2_ick",
1776         .ops            = &clkops_omap2_dflt_wait,
1777         .parent         = &core_l4_ick,
1778         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1779         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1780         .clkdm_name     = "core_l4_clkdm",
1781         .recalc         = &followparent_recalc,
1782 };
1783
1784 static struct clk sha12_ick = {
1785         .name           = "sha12_ick",
1786         .ops            = &clkops_omap2_dflt_wait,
1787         .parent         = &core_l4_ick,
1788         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1789         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1790         .clkdm_name     = "core_l4_clkdm",
1791         .recalc         = &followparent_recalc,
1792 };
1793
1794 static struct clk des2_ick = {
1795         .name           = "des2_ick",
1796         .ops            = &clkops_omap2_dflt_wait,
1797         .parent         = &core_l4_ick,
1798         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1799         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1800         .clkdm_name     = "core_l4_clkdm",
1801         .recalc         = &followparent_recalc,
1802 };
1803
1804 static struct clk mmchs2_ick = {
1805         .name           = "mmchs_ick",
1806         .ops            = &clkops_omap2_dflt_wait,
1807         .id             = 1,
1808         .parent         = &core_l4_ick,
1809         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1810         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1811         .clkdm_name     = "core_l4_clkdm",
1812         .recalc         = &followparent_recalc,
1813 };
1814
1815 static struct clk mmchs1_ick = {
1816         .name           = "mmchs_ick",
1817         .ops            = &clkops_omap2_dflt_wait,
1818         .parent         = &core_l4_ick,
1819         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1820         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1821         .clkdm_name     = "core_l4_clkdm",
1822         .recalc         = &followparent_recalc,
1823 };
1824
1825 static struct clk mspro_ick = {
1826         .name           = "mspro_ick",
1827         .ops            = &clkops_omap2_dflt_wait,
1828         .parent         = &core_l4_ick,
1829         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1830         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1831         .clkdm_name     = "core_l4_clkdm",
1832         .recalc         = &followparent_recalc,
1833 };
1834
1835 static struct clk hdq_ick = {
1836         .name           = "hdq_ick",
1837         .ops            = &clkops_omap2_dflt_wait,
1838         .parent         = &core_l4_ick,
1839         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1840         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1841         .clkdm_name     = "core_l4_clkdm",
1842         .recalc         = &followparent_recalc,
1843 };
1844
1845 static struct clk mcspi4_ick = {
1846         .name           = "mcspi_ick",
1847         .ops            = &clkops_omap2_dflt_wait,
1848         .id             = 4,
1849         .parent         = &core_l4_ick,
1850         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1851         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1852         .clkdm_name     = "core_l4_clkdm",
1853         .recalc         = &followparent_recalc,
1854 };
1855
1856 static struct clk mcspi3_ick = {
1857         .name           = "mcspi_ick",
1858         .ops            = &clkops_omap2_dflt_wait,
1859         .id             = 3,
1860         .parent         = &core_l4_ick,
1861         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1862         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1863         .clkdm_name     = "core_l4_clkdm",
1864         .recalc         = &followparent_recalc,
1865 };
1866
1867 static struct clk mcspi2_ick = {
1868         .name           = "mcspi_ick",
1869         .ops            = &clkops_omap2_dflt_wait,
1870         .id             = 2,
1871         .parent         = &core_l4_ick,
1872         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1873         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1874         .clkdm_name     = "core_l4_clkdm",
1875         .recalc         = &followparent_recalc,
1876 };
1877
1878 static struct clk mcspi1_ick = {
1879         .name           = "mcspi_ick",
1880         .ops            = &clkops_omap2_dflt_wait,
1881         .id             = 1,
1882         .parent         = &core_l4_ick,
1883         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1884         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1885         .clkdm_name     = "core_l4_clkdm",
1886         .recalc         = &followparent_recalc,
1887 };
1888
1889 static struct clk i2c3_ick = {
1890         .name           = "i2c_ick",
1891         .ops            = &clkops_omap2_dflt_wait,
1892         .id             = 3,
1893         .parent         = &core_l4_ick,
1894         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1895         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1896         .clkdm_name     = "core_l4_clkdm",
1897         .recalc         = &followparent_recalc,
1898 };
1899
1900 static struct clk i2c2_ick = {
1901         .name           = "i2c_ick",
1902         .ops            = &clkops_omap2_dflt_wait,
1903         .id             = 2,
1904         .parent         = &core_l4_ick,
1905         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1906         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1907         .clkdm_name     = "core_l4_clkdm",
1908         .recalc         = &followparent_recalc,
1909 };
1910
1911 static struct clk i2c1_ick = {
1912         .name           = "i2c_ick",
1913         .ops            = &clkops_omap2_dflt_wait,
1914         .id             = 1,
1915         .parent         = &core_l4_ick,
1916         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1917         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1918         .clkdm_name     = "core_l4_clkdm",
1919         .recalc         = &followparent_recalc,
1920 };
1921
1922 static struct clk uart2_ick = {
1923         .name           = "uart2_ick",
1924         .ops            = &clkops_omap2_dflt_wait,
1925         .parent         = &core_l4_ick,
1926         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1927         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1928         .clkdm_name     = "core_l4_clkdm",
1929         .recalc         = &followparent_recalc,
1930 };
1931
1932 static struct clk uart1_ick = {
1933         .name           = "uart1_ick",
1934         .ops            = &clkops_omap2_dflt_wait,
1935         .parent         = &core_l4_ick,
1936         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1937         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1938         .clkdm_name     = "core_l4_clkdm",
1939         .recalc         = &followparent_recalc,
1940 };
1941
1942 static struct clk gpt11_ick = {
1943         .name           = "gpt11_ick",
1944         .ops            = &clkops_omap2_dflt_wait,
1945         .parent         = &core_l4_ick,
1946         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1947         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1948         .clkdm_name     = "core_l4_clkdm",
1949         .recalc         = &followparent_recalc,
1950 };
1951
1952 static struct clk gpt10_ick = {
1953         .name           = "gpt10_ick",
1954         .ops            = &clkops_omap2_dflt_wait,
1955         .parent         = &core_l4_ick,
1956         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1957         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1958         .clkdm_name     = "core_l4_clkdm",
1959         .recalc         = &followparent_recalc,
1960 };
1961
1962 static struct clk mcbsp5_ick = {
1963         .name           = "mcbsp_ick",
1964         .ops            = &clkops_omap2_dflt_wait,
1965         .id             = 5,
1966         .parent         = &core_l4_ick,
1967         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1968         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1969         .clkdm_name     = "core_l4_clkdm",
1970         .recalc         = &followparent_recalc,
1971 };
1972
1973 static struct clk mcbsp1_ick = {
1974         .name           = "mcbsp_ick",
1975         .ops            = &clkops_omap2_dflt_wait,
1976         .id             = 1,
1977         .parent         = &core_l4_ick,
1978         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1979         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1980         .clkdm_name     = "core_l4_clkdm",
1981         .recalc         = &followparent_recalc,
1982 };
1983
1984 static struct clk fac_ick = {
1985         .name           = "fac_ick",
1986         .ops            = &clkops_omap2_dflt_wait,
1987         .parent         = &core_l4_ick,
1988         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1989         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1990         .clkdm_name     = "core_l4_clkdm",
1991         .recalc         = &followparent_recalc,
1992 };
1993
1994 static struct clk mailboxes_ick = {
1995         .name           = "mailboxes_ick",
1996         .ops            = &clkops_omap2_dflt_wait,
1997         .parent         = &core_l4_ick,
1998         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1999         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2000         .clkdm_name     = "core_l4_clkdm",
2001         .recalc         = &followparent_recalc,
2002 };
2003
2004 static struct clk omapctrl_ick = {
2005         .name           = "omapctrl_ick",
2006         .ops            = &clkops_omap2_dflt_wait,
2007         .parent         = &core_l4_ick,
2008         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2009         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2010         .flags          = ENABLE_ON_INIT,
2011         .recalc         = &followparent_recalc,
2012 };
2013
2014 /* SSI_L4_ICK based clocks */
2015
2016 static struct clk ssi_l4_ick = {
2017         .name           = "ssi_l4_ick",
2018         .ops            = &clkops_null,
2019         .parent         = &l4_ick,
2020         .flags          = RATE_PROPAGATES,
2021         .clkdm_name     = "core_l4_clkdm",
2022         .recalc         = &followparent_recalc,
2023 };
2024
2025 static struct clk ssi_ick = {
2026         .name           = "ssi_ick",
2027         .ops            = &clkops_omap2_dflt,
2028         .parent         = &ssi_l4_ick,
2029         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2030         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2031         .clkdm_name     = "core_l4_clkdm",
2032         .recalc         = &followparent_recalc,
2033 };
2034
2035 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2036  * but l4_ick makes more sense to me */
2037
2038 static const struct clksel usb_l4_clksel[] = {
2039         { .parent = &l4_ick, .rates = div2_rates },
2040         { .parent = NULL },
2041 };
2042
2043 static struct clk usb_l4_ick = {
2044         .name           = "usb_l4_ick",
2045         .ops            = &clkops_omap2_dflt_wait,
2046         .parent         = &l4_ick,
2047         .init           = &omap2_init_clksel_parent,
2048         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2049         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2050         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2051         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2052         .clksel         = usb_l4_clksel,
2053         .recalc         = &omap2_clksel_recalc,
2054 };
2055
2056 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2057
2058 /* SECURITY_L4_ICK2 based clocks */
2059
2060 static struct clk security_l4_ick2 = {
2061         .name           = "security_l4_ick2",
2062         .ops            = &clkops_null,
2063         .parent         = &l4_ick,
2064         .flags          = RATE_PROPAGATES,
2065         .recalc         = &followparent_recalc,
2066 };
2067
2068 static struct clk aes1_ick = {
2069         .name           = "aes1_ick",
2070         .ops            = &clkops_omap2_dflt_wait,
2071         .parent         = &security_l4_ick2,
2072         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2073         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2074         .recalc         = &followparent_recalc,
2075 };
2076
2077 static struct clk rng_ick = {
2078         .name           = "rng_ick",
2079         .ops            = &clkops_omap2_dflt_wait,
2080         .parent         = &security_l4_ick2,
2081         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2082         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2083         .recalc         = &followparent_recalc,
2084 };
2085
2086 static struct clk sha11_ick = {
2087         .name           = "sha11_ick",
2088         .ops            = &clkops_omap2_dflt_wait,
2089         .parent         = &security_l4_ick2,
2090         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2091         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2092         .recalc         = &followparent_recalc,
2093 };
2094
2095 static struct clk des1_ick = {
2096         .name           = "des1_ick",
2097         .ops            = &clkops_omap2_dflt_wait,
2098         .parent         = &security_l4_ick2,
2099         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2100         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2101         .recalc         = &followparent_recalc,
2102 };
2103
2104 /* DSS */
2105 static const struct clksel dss1_alwon_fck_clksel[] = {
2106         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2107         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2108         { .parent = NULL }
2109 };
2110
2111 static struct clk dss1_alwon_fck = {
2112         .name           = "dss1_alwon_fck",
2113         .ops            = &clkops_omap2_dflt,
2114         .parent         = &dpll4_m4x2_ck,
2115         .init           = &omap2_init_clksel_parent,
2116         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2117         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2118         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2119         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2120         .clksel         = dss1_alwon_fck_clksel,
2121         .clkdm_name     = "dss_clkdm",
2122         .recalc         = &omap2_clksel_recalc,
2123 };
2124
2125 static struct clk dss_tv_fck = {
2126         .name           = "dss_tv_fck",
2127         .ops            = &clkops_omap2_dflt,
2128         .parent         = &omap_54m_fck,
2129         .init           = &omap2_init_clk_clkdm,
2130         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2131         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2132         .clkdm_name     = "dss_clkdm",
2133         .recalc         = &followparent_recalc,
2134 };
2135
2136 static struct clk dss_96m_fck = {
2137         .name           = "dss_96m_fck",
2138         .ops            = &clkops_omap2_dflt,
2139         .parent         = &omap_96m_fck,
2140         .init           = &omap2_init_clk_clkdm,
2141         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2142         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2143         .clkdm_name     = "dss_clkdm",
2144         .recalc         = &followparent_recalc,
2145 };
2146
2147 static struct clk dss2_alwon_fck = {
2148         .name           = "dss2_alwon_fck",
2149         .ops            = &clkops_omap2_dflt,
2150         .parent         = &sys_ck,
2151         .init           = &omap2_init_clk_clkdm,
2152         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2153         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2154         .clkdm_name     = "dss_clkdm",
2155         .recalc         = &followparent_recalc,
2156 };
2157
2158 static struct clk dss_ick = {
2159         /* Handles both L3 and L4 clocks */
2160         .name           = "dss_ick",
2161         .ops            = &clkops_omap2_dflt,
2162         .parent         = &l4_ick,
2163         .init           = &omap2_init_clk_clkdm,
2164         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2165         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2166         .clkdm_name     = "dss_clkdm",
2167         .recalc         = &followparent_recalc,
2168 };
2169
2170 /* CAM */
2171
2172 static const struct clksel cam_mclk_clksel[] = {
2173         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2174         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2175         { .parent = NULL }
2176 };
2177
2178 static struct clk cam_mclk = {
2179         .name           = "cam_mclk",
2180         .ops            = &clkops_omap2_dflt_wait,
2181         .parent         = &dpll4_m5x2_ck,
2182         .init           = &omap2_init_clksel_parent,
2183         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2184         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2185         .clksel         = cam_mclk_clksel,
2186         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2187         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2188         .clkdm_name     = "cam_clkdm",
2189         .recalc         = &omap2_clksel_recalc,
2190 };
2191
2192 static struct clk cam_ick = {
2193         /* Handles both L3 and L4 clocks */
2194         .name           = "cam_ick",
2195         .ops            = &clkops_omap2_dflt_wait,
2196         .parent         = &l4_ick,
2197         .init           = &omap2_init_clk_clkdm,
2198         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2199         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2200         .clkdm_name     = "cam_clkdm",
2201         .recalc         = &followparent_recalc,
2202 };
2203
2204 static struct clk csi2_96m_fck = {
2205         .name           = "csi2_96m_fck",
2206         .ops            = &clkops_omap2_dflt_wait,
2207         .parent         = &core_96m_fck,
2208         .init           = &omap2_init_clk_clkdm,
2209         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2210         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2211         .clkdm_name     = "cam_clkdm",
2212         .recalc         = &followparent_recalc,
2213 };
2214
2215 /* USBHOST - 3430ES2 only */
2216
2217 static struct clk usbhost_120m_fck = {
2218         .name           = "usbhost_120m_fck",
2219         .ops            = &clkops_omap2_dflt_wait,
2220         .parent         = &omap_120m_fck,
2221         .init           = &omap2_init_clk_clkdm,
2222         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2223         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2224         .clkdm_name     = "usbhost_clkdm",
2225         .recalc         = &followparent_recalc,
2226 };
2227
2228 static struct clk usbhost_48m_fck = {
2229         .name           = "usbhost_48m_fck",
2230         .ops            = &clkops_omap2_dflt_wait,
2231         .parent         = &omap_48m_fck,
2232         .init           = &omap2_init_clk_clkdm,
2233         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2234         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2235         .clkdm_name     = "usbhost_clkdm",
2236         .recalc         = &followparent_recalc,
2237 };
2238
2239 static struct clk usbhost_ick = {
2240         /* Handles both L3 and L4 clocks */
2241         .name           = "usbhost_ick",
2242         .ops            = &clkops_omap2_dflt_wait,
2243         .parent         = &l4_ick,
2244         .init           = &omap2_init_clk_clkdm,
2245         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2246         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2247         .clkdm_name     = "usbhost_clkdm",
2248         .recalc         = &followparent_recalc,
2249 };
2250
2251 /* WKUP */
2252
2253 static const struct clksel_rate usim_96m_rates[] = {
2254         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2255         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2256         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2257         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2258         { .div = 0 },
2259 };
2260
2261 static const struct clksel_rate usim_120m_rates[] = {
2262         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2263         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2264         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2265         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2266         { .div = 0 },
2267 };
2268
2269 static const struct clksel usim_clksel[] = {
2270         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2271         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2272         { .parent = &sys_ck,            .rates = div2_rates },
2273         { .parent = NULL },
2274 };
2275
2276 /* 3430ES2 only */
2277 static struct clk usim_fck = {
2278         .name           = "usim_fck",
2279         .ops            = &clkops_omap2_dflt_wait,
2280         .init           = &omap2_init_clksel_parent,
2281         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2282         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2283         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2284         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2285         .clksel         = usim_clksel,
2286         .recalc         = &omap2_clksel_recalc,
2287 };
2288
2289 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2290 static struct clk gpt1_fck = {
2291         .name           = "gpt1_fck",
2292         .ops            = &clkops_omap2_dflt_wait,
2293         .init           = &omap2_init_clksel_parent,
2294         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2295         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2296         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2297         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2298         .clksel         = omap343x_gpt_clksel,
2299         .clkdm_name     = "wkup_clkdm",
2300         .recalc         = &omap2_clksel_recalc,
2301 };
2302
2303 static struct clk wkup_32k_fck = {
2304         .name           = "wkup_32k_fck",
2305         .ops            = &clkops_null,
2306         .init           = &omap2_init_clk_clkdm,
2307         .parent         = &omap_32k_fck,
2308         .flags          = RATE_PROPAGATES,
2309         .clkdm_name     = "wkup_clkdm",
2310         .recalc         = &followparent_recalc,
2311 };
2312
2313 static struct clk gpio1_dbck = {
2314         .name           = "gpio1_dbck",
2315         .ops            = &clkops_omap2_dflt_wait,
2316         .parent         = &wkup_32k_fck,
2317         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2318         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2319         .clkdm_name     = "wkup_clkdm",
2320         .recalc         = &followparent_recalc,
2321 };
2322
2323 static struct clk wdt2_fck = {
2324         .name           = "wdt2_fck",
2325         .ops            = &clkops_omap2_dflt_wait,
2326         .parent         = &wkup_32k_fck,
2327         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2328         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2329         .clkdm_name     = "wkup_clkdm",
2330         .recalc         = &followparent_recalc,
2331 };
2332
2333 static struct clk wkup_l4_ick = {
2334         .name           = "wkup_l4_ick",
2335         .ops            = &clkops_null,
2336         .parent         = &sys_ck,
2337         .flags          = RATE_PROPAGATES,
2338         .clkdm_name     = "wkup_clkdm",
2339         .recalc         = &followparent_recalc,
2340 };
2341
2342 /* 3430ES2 only */
2343 /* Never specifically named in the TRM, so we have to infer a likely name */
2344 static struct clk usim_ick = {
2345         .name           = "usim_ick",
2346         .ops            = &clkops_omap2_dflt_wait,
2347         .parent         = &wkup_l4_ick,
2348         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2349         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2350         .clkdm_name     = "wkup_clkdm",
2351         .recalc         = &followparent_recalc,
2352 };
2353
2354 static struct clk wdt2_ick = {
2355         .name           = "wdt2_ick",
2356         .ops            = &clkops_omap2_dflt_wait,
2357         .parent         = &wkup_l4_ick,
2358         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2359         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2360         .clkdm_name     = "wkup_clkdm",
2361         .recalc         = &followparent_recalc,
2362 };
2363
2364 static struct clk wdt1_ick = {
2365         .name           = "wdt1_ick",
2366         .ops            = &clkops_omap2_dflt_wait,
2367         .parent         = &wkup_l4_ick,
2368         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2369         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2370         .clkdm_name     = "wkup_clkdm",
2371         .recalc         = &followparent_recalc,
2372 };
2373
2374 static struct clk gpio1_ick = {
2375         .name           = "gpio1_ick",
2376         .ops            = &clkops_omap2_dflt_wait,
2377         .parent         = &wkup_l4_ick,
2378         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2379         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2380         .clkdm_name     = "wkup_clkdm",
2381         .recalc         = &followparent_recalc,
2382 };
2383
2384 static struct clk omap_32ksync_ick = {
2385         .name           = "omap_32ksync_ick",
2386         .ops            = &clkops_omap2_dflt_wait,
2387         .parent         = &wkup_l4_ick,
2388         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2389         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2390         .clkdm_name     = "wkup_clkdm",
2391         .recalc         = &followparent_recalc,
2392 };
2393
2394 /* XXX This clock no longer exists in 3430 TRM rev F */
2395 static struct clk gpt12_ick = {
2396         .name           = "gpt12_ick",
2397         .ops            = &clkops_omap2_dflt_wait,
2398         .parent         = &wkup_l4_ick,
2399         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2400         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2401         .clkdm_name     = "wkup_clkdm",
2402         .recalc         = &followparent_recalc,
2403 };
2404
2405 static struct clk gpt1_ick = {
2406         .name           = "gpt1_ick",
2407         .ops            = &clkops_omap2_dflt_wait,
2408         .parent         = &wkup_l4_ick,
2409         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2410         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2411         .clkdm_name     = "wkup_clkdm",
2412         .recalc         = &followparent_recalc,
2413 };
2414
2415
2416
2417 /* PER clock domain */
2418
2419 static struct clk per_96m_fck = {
2420         .name           = "per_96m_fck",
2421         .ops            = &clkops_null,
2422         .parent         = &omap_96m_alwon_fck,
2423         .init           = &omap2_init_clk_clkdm,
2424         .flags          = RATE_PROPAGATES,
2425         .clkdm_name     = "per_clkdm",
2426         .recalc         = &followparent_recalc,
2427 };
2428
2429 static struct clk per_48m_fck = {
2430         .name           = "per_48m_fck",
2431         .ops            = &clkops_null,
2432         .parent         = &omap_48m_fck,
2433         .init           = &omap2_init_clk_clkdm,
2434         .flags          = RATE_PROPAGATES,
2435         .clkdm_name     = "per_clkdm",
2436         .recalc         = &followparent_recalc,
2437 };
2438
2439 static struct clk uart3_fck = {
2440         .name           = "uart3_fck",
2441         .ops            = &clkops_omap2_dflt_wait,
2442         .parent         = &per_48m_fck,
2443         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2444         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2445         .clkdm_name     = "per_clkdm",
2446         .recalc         = &followparent_recalc,
2447 };
2448
2449 static struct clk gpt2_fck = {
2450         .name           = "gpt2_fck",
2451         .ops            = &clkops_omap2_dflt_wait,
2452         .init           = &omap2_init_clksel_parent,
2453         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2454         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2455         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2456         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2457         .clksel         = omap343x_gpt_clksel,
2458         .clkdm_name     = "per_clkdm",
2459         .recalc         = &omap2_clksel_recalc,
2460 };
2461
2462 static struct clk gpt3_fck = {
2463         .name           = "gpt3_fck",
2464         .ops            = &clkops_omap2_dflt_wait,
2465         .init           = &omap2_init_clksel_parent,
2466         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2467         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2468         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2469         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2470         .clksel         = omap343x_gpt_clksel,
2471         .clkdm_name     = "per_clkdm",
2472         .recalc         = &omap2_clksel_recalc,
2473 };
2474
2475 static struct clk gpt4_fck = {
2476         .name           = "gpt4_fck",
2477         .ops            = &clkops_omap2_dflt_wait,
2478         .init           = &omap2_init_clksel_parent,
2479         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2480         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2481         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2482         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2483         .clksel         = omap343x_gpt_clksel,
2484         .clkdm_name     = "per_clkdm",
2485         .recalc         = &omap2_clksel_recalc,
2486 };
2487
2488 static struct clk gpt5_fck = {
2489         .name           = "gpt5_fck",
2490         .ops            = &clkops_omap2_dflt_wait,
2491         .init           = &omap2_init_clksel_parent,
2492         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2493         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2494         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2495         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2496         .clksel         = omap343x_gpt_clksel,
2497         .clkdm_name     = "per_clkdm",
2498         .recalc         = &omap2_clksel_recalc,
2499 };
2500
2501 static struct clk gpt6_fck = {
2502         .name           = "gpt6_fck",
2503         .ops            = &clkops_omap2_dflt_wait,
2504         .init           = &omap2_init_clksel_parent,
2505         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2506         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2507         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2508         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2509         .clksel         = omap343x_gpt_clksel,
2510         .clkdm_name     = "per_clkdm",
2511         .recalc         = &omap2_clksel_recalc,
2512 };
2513
2514 static struct clk gpt7_fck = {
2515         .name           = "gpt7_fck",
2516         .ops            = &clkops_omap2_dflt_wait,
2517         .init           = &omap2_init_clksel_parent,
2518         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2519         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2520         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2521         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2522         .clksel         = omap343x_gpt_clksel,
2523         .clkdm_name     = "per_clkdm",
2524         .recalc         = &omap2_clksel_recalc,
2525 };
2526
2527 static struct clk gpt8_fck = {
2528         .name           = "gpt8_fck",
2529         .ops            = &clkops_omap2_dflt_wait,
2530         .init           = &omap2_init_clksel_parent,
2531         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2532         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2533         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2534         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2535         .clksel         = omap343x_gpt_clksel,
2536         .clkdm_name     = "per_clkdm",
2537         .recalc         = &omap2_clksel_recalc,
2538 };
2539
2540 static struct clk gpt9_fck = {
2541         .name           = "gpt9_fck",
2542         .ops            = &clkops_omap2_dflt_wait,
2543         .init           = &omap2_init_clksel_parent,
2544         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2545         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2546         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2547         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2548         .clksel         = omap343x_gpt_clksel,
2549         .clkdm_name     = "per_clkdm",
2550         .recalc         = &omap2_clksel_recalc,
2551 };
2552
2553 static struct clk per_32k_alwon_fck = {
2554         .name           = "per_32k_alwon_fck",
2555         .ops            = &clkops_null,
2556         .parent         = &omap_32k_fck,
2557         .clkdm_name     = "per_clkdm",
2558         .flags          = RATE_PROPAGATES,
2559         .recalc         = &followparent_recalc,
2560 };
2561
2562 static struct clk gpio6_dbck = {
2563         .name           = "gpio6_dbck",
2564         .ops            = &clkops_omap2_dflt_wait,
2565         .parent         = &per_32k_alwon_fck,
2566         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2567         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2568         .clkdm_name     = "per_clkdm",
2569         .recalc         = &followparent_recalc,
2570 };
2571
2572 static struct clk gpio5_dbck = {
2573         .name           = "gpio5_dbck",
2574         .ops            = &clkops_omap2_dflt_wait,
2575         .parent         = &per_32k_alwon_fck,
2576         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2577         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2578         .clkdm_name     = "per_clkdm",
2579         .recalc         = &followparent_recalc,
2580 };
2581
2582 static struct clk gpio4_dbck = {
2583         .name           = "gpio4_dbck",
2584         .ops            = &clkops_omap2_dflt_wait,
2585         .parent         = &per_32k_alwon_fck,
2586         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2587         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2588         .clkdm_name     = "per_clkdm",
2589         .recalc         = &followparent_recalc,
2590 };
2591
2592 static struct clk gpio3_dbck = {
2593         .name           = "gpio3_dbck",
2594         .ops            = &clkops_omap2_dflt_wait,
2595         .parent         = &per_32k_alwon_fck,
2596         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2597         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2598         .clkdm_name     = "per_clkdm",
2599         .recalc         = &followparent_recalc,
2600 };
2601
2602 static struct clk gpio2_dbck = {
2603         .name           = "gpio2_dbck",
2604         .ops            = &clkops_omap2_dflt_wait,
2605         .parent         = &per_32k_alwon_fck,
2606         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2607         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2608         .clkdm_name     = "per_clkdm",
2609         .recalc         = &followparent_recalc,
2610 };
2611
2612 static struct clk wdt3_fck = {
2613         .name           = "wdt3_fck",
2614         .ops            = &clkops_omap2_dflt_wait,
2615         .parent         = &per_32k_alwon_fck,
2616         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2617         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2618         .clkdm_name     = "per_clkdm",
2619         .recalc         = &followparent_recalc,
2620 };
2621
2622 static struct clk per_l4_ick = {
2623         .name           = "per_l4_ick",
2624         .ops            = &clkops_null,
2625         .parent         = &l4_ick,
2626         .flags          = RATE_PROPAGATES,
2627         .clkdm_name     = "per_clkdm",
2628         .recalc         = &followparent_recalc,
2629 };
2630
2631 static struct clk gpio6_ick = {
2632         .name           = "gpio6_ick",
2633         .ops            = &clkops_omap2_dflt_wait,
2634         .parent         = &per_l4_ick,
2635         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2636         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2637         .clkdm_name     = "per_clkdm",
2638         .recalc         = &followparent_recalc,
2639 };
2640
2641 static struct clk gpio5_ick = {
2642         .name           = "gpio5_ick",
2643         .ops            = &clkops_omap2_dflt_wait,
2644         .parent         = &per_l4_ick,
2645         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2646         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2647         .clkdm_name     = "per_clkdm",
2648         .recalc         = &followparent_recalc,
2649 };
2650
2651 static struct clk gpio4_ick = {
2652         .name           = "gpio4_ick",
2653         .ops            = &clkops_omap2_dflt_wait,
2654         .parent         = &per_l4_ick,
2655         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2656         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2657         .clkdm_name     = "per_clkdm",
2658         .recalc         = &followparent_recalc,
2659 };
2660
2661 static struct clk gpio3_ick = {
2662         .name           = "gpio3_ick",
2663         .ops            = &clkops_omap2_dflt_wait,
2664         .parent         = &per_l4_ick,
2665         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2666         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2667         .clkdm_name     = "per_clkdm",
2668         .recalc         = &followparent_recalc,
2669 };
2670
2671 static struct clk gpio2_ick = {
2672         .name           = "gpio2_ick",
2673         .ops            = &clkops_omap2_dflt_wait,
2674         .parent         = &per_l4_ick,
2675         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2676         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2677         .clkdm_name     = "per_clkdm",
2678         .recalc         = &followparent_recalc,
2679 };
2680
2681 static struct clk wdt3_ick = {
2682         .name           = "wdt3_ick",
2683         .ops            = &clkops_omap2_dflt_wait,
2684         .parent         = &per_l4_ick,
2685         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2686         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2687         .clkdm_name     = "per_clkdm",
2688         .recalc         = &followparent_recalc,
2689 };
2690
2691 static struct clk uart3_ick = {
2692         .name           = "uart3_ick",
2693         .ops            = &clkops_omap2_dflt_wait,
2694         .parent         = &per_l4_ick,
2695         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2696         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2697         .clkdm_name     = "per_clkdm",
2698         .recalc         = &followparent_recalc,
2699 };
2700
2701 static struct clk gpt9_ick = {
2702         .name           = "gpt9_ick",
2703         .ops            = &clkops_omap2_dflt_wait,
2704         .parent         = &per_l4_ick,
2705         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2706         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2707         .clkdm_name     = "per_clkdm",
2708         .recalc         = &followparent_recalc,
2709 };
2710
2711 static struct clk gpt8_ick = {
2712         .name           = "gpt8_ick",
2713         .ops            = &clkops_omap2_dflt_wait,
2714         .parent         = &per_l4_ick,
2715         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2716         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2717         .clkdm_name     = "per_clkdm",
2718         .recalc         = &followparent_recalc,
2719 };
2720
2721 static struct clk gpt7_ick = {
2722         .name           = "gpt7_ick",
2723         .ops            = &clkops_omap2_dflt_wait,
2724         .parent         = &per_l4_ick,
2725         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2726         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2727         .clkdm_name     = "per_clkdm",
2728         .recalc         = &followparent_recalc,
2729 };
2730
2731 static struct clk gpt6_ick = {
2732         .name           = "gpt6_ick",
2733         .ops            = &clkops_omap2_dflt_wait,
2734         .parent         = &per_l4_ick,
2735         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2736         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2737         .clkdm_name     = "per_clkdm",
2738         .recalc         = &followparent_recalc,
2739 };
2740
2741 static struct clk gpt5_ick = {
2742         .name           = "gpt5_ick",
2743         .ops            = &clkops_omap2_dflt_wait,
2744         .parent         = &per_l4_ick,
2745         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2746         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2747         .clkdm_name     = "per_clkdm",
2748         .recalc         = &followparent_recalc,
2749 };
2750
2751 static struct clk gpt4_ick = {
2752         .name           = "gpt4_ick",
2753         .ops            = &clkops_omap2_dflt_wait,
2754         .parent         = &per_l4_ick,
2755         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2756         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2757         .clkdm_name     = "per_clkdm",
2758         .recalc         = &followparent_recalc,
2759 };
2760
2761 static struct clk gpt3_ick = {
2762         .name           = "gpt3_ick",
2763         .ops            = &clkops_omap2_dflt_wait,
2764         .parent         = &per_l4_ick,
2765         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2766         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2767         .clkdm_name     = "per_clkdm",
2768         .recalc         = &followparent_recalc,
2769 };
2770
2771 static struct clk gpt2_ick = {
2772         .name           = "gpt2_ick",
2773         .ops            = &clkops_omap2_dflt_wait,
2774         .parent         = &per_l4_ick,
2775         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2776         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2777         .clkdm_name     = "per_clkdm",
2778         .recalc         = &followparent_recalc,
2779 };
2780
2781 static struct clk mcbsp2_ick = {
2782         .name           = "mcbsp_ick",
2783         .ops            = &clkops_omap2_dflt_wait,
2784         .id             = 2,
2785         .parent         = &per_l4_ick,
2786         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2787         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2788         .clkdm_name     = "per_clkdm",
2789         .recalc         = &followparent_recalc,
2790 };
2791
2792 static struct clk mcbsp3_ick = {
2793         .name           = "mcbsp_ick",
2794         .ops            = &clkops_omap2_dflt_wait,
2795         .id             = 3,
2796         .parent         = &per_l4_ick,
2797         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2798         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2799         .clkdm_name     = "per_clkdm",
2800         .recalc         = &followparent_recalc,
2801 };
2802
2803 static struct clk mcbsp4_ick = {
2804         .name           = "mcbsp_ick",
2805         .ops            = &clkops_omap2_dflt_wait,
2806         .id             = 4,
2807         .parent         = &per_l4_ick,
2808         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2809         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2810         .clkdm_name     = "per_clkdm",
2811         .recalc         = &followparent_recalc,
2812 };
2813
2814 static const struct clksel mcbsp_234_clksel[] = {
2815         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2816         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2817         { .parent = NULL }
2818 };
2819
2820 static struct clk mcbsp2_fck = {
2821         .name           = "mcbsp_fck",
2822         .ops            = &clkops_omap2_dflt_wait,
2823         .id             = 2,
2824         .init           = &omap2_init_clksel_parent,
2825         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2826         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2827         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2828         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2829         .clksel         = mcbsp_234_clksel,
2830         .clkdm_name     = "per_clkdm",
2831         .recalc         = &omap2_clksel_recalc,
2832 };
2833
2834 static struct clk mcbsp3_fck = {
2835         .name           = "mcbsp_fck",
2836         .ops            = &clkops_omap2_dflt_wait,
2837         .id             = 3,
2838         .init           = &omap2_init_clksel_parent,
2839         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2840         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2841         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2842         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2843         .clksel         = mcbsp_234_clksel,
2844         .clkdm_name     = "per_clkdm",
2845         .recalc         = &omap2_clksel_recalc,
2846 };
2847
2848 static struct clk mcbsp4_fck = {
2849         .name           = "mcbsp_fck",
2850         .ops            = &clkops_omap2_dflt_wait,
2851         .id             = 4,
2852         .init           = &omap2_init_clksel_parent,
2853         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2854         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2855         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2856         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2857         .clksel         = mcbsp_234_clksel,
2858         .clkdm_name     = "per_clkdm",
2859         .recalc         = &omap2_clksel_recalc,
2860 };
2861
2862 /* EMU clocks */
2863
2864 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2865
2866 static const struct clksel_rate emu_src_sys_rates[] = {
2867         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2868         { .div = 0 },
2869 };
2870
2871 static const struct clksel_rate emu_src_core_rates[] = {
2872         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2873         { .div = 0 },
2874 };
2875
2876 static const struct clksel_rate emu_src_per_rates[] = {
2877         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2878         { .div = 0 },
2879 };
2880
2881 static const struct clksel_rate emu_src_mpu_rates[] = {
2882         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2883         { .div = 0 },
2884 };
2885
2886 static const struct clksel emu_src_clksel[] = {
2887         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2888         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2889         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2890         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2891         { .parent = NULL },
2892 };
2893
2894 /*
2895  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2896  * to switch the source of some of the EMU clocks.
2897  * XXX Are there CLKEN bits for these EMU clks?
2898  */
2899 static struct clk emu_src_ck = {
2900         .name           = "emu_src_ck",
2901         .ops            = &clkops_null,
2902         .init           = &omap2_init_clksel_parent,
2903         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2904         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2905         .clksel         = emu_src_clksel,
2906         .flags          = RATE_PROPAGATES,
2907         .clkdm_name     = "emu_clkdm",
2908         .recalc         = &omap2_clksel_recalc,
2909 };
2910
2911 static const struct clksel_rate pclk_emu_rates[] = {
2912         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2913         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2914         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2915         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2916         { .div = 0 },
2917 };
2918
2919 static const struct clksel pclk_emu_clksel[] = {
2920         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2921         { .parent = NULL },
2922 };
2923
2924 static struct clk pclk_fck = {
2925         .name           = "pclk_fck",
2926         .ops            = &clkops_null,
2927         .init           = &omap2_init_clksel_parent,
2928         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2929         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2930         .clksel         = pclk_emu_clksel,
2931         .flags          = RATE_PROPAGATES,
2932         .clkdm_name     = "emu_clkdm",
2933         .recalc         = &omap2_clksel_recalc,
2934 };
2935
2936 static const struct clksel_rate pclkx2_emu_rates[] = {
2937         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2938         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2939         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2940         { .div = 0 },
2941 };
2942
2943 static const struct clksel pclkx2_emu_clksel[] = {
2944         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2945         { .parent = NULL },
2946 };
2947
2948 static struct clk pclkx2_fck = {
2949         .name           = "pclkx2_fck",
2950         .ops            = &clkops_null,
2951         .init           = &omap2_init_clksel_parent,
2952         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2953         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2954         .clksel         = pclkx2_emu_clksel,
2955         .flags          = RATE_PROPAGATES,
2956         .clkdm_name     = "emu_clkdm",
2957         .recalc         = &omap2_clksel_recalc,
2958 };
2959
2960 static const struct clksel atclk_emu_clksel[] = {
2961         { .parent = &emu_src_ck, .rates = div2_rates },
2962         { .parent = NULL },
2963 };
2964
2965 static struct clk atclk_fck = {
2966         .name           = "atclk_fck",
2967         .ops            = &clkops_null,
2968         .init           = &omap2_init_clksel_parent,
2969         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2970         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2971         .clksel         = atclk_emu_clksel,
2972         .flags          = RATE_PROPAGATES,
2973         .clkdm_name     = "emu_clkdm",
2974         .recalc         = &omap2_clksel_recalc,
2975 };
2976
2977 static struct clk traceclk_src_fck = {
2978         .name           = "traceclk_src_fck",
2979         .ops            = &clkops_null,
2980         .init           = &omap2_init_clksel_parent,
2981         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2982         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2983         .clksel         = emu_src_clksel,
2984         .flags          = RATE_PROPAGATES,
2985         .clkdm_name     = "emu_clkdm",
2986         .recalc         = &omap2_clksel_recalc,
2987 };
2988
2989 static const struct clksel_rate traceclk_rates[] = {
2990         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2991         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2992         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2993         { .div = 0 },
2994 };
2995
2996 static const struct clksel traceclk_clksel[] = {
2997         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2998         { .parent = NULL },
2999 };
3000
3001 static struct clk traceclk_fck = {
3002         .name           = "traceclk_fck",
3003         .ops            = &clkops_null,
3004         .init           = &omap2_init_clksel_parent,
3005         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3006         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3007         .clksel         = traceclk_clksel,
3008         .clkdm_name     = "emu_clkdm",
3009         .recalc         = &omap2_clksel_recalc,
3010 };
3011
3012 /* SR clocks */
3013
3014 /* SmartReflex fclk (VDD1) */
3015 static struct clk sr1_fck = {
3016         .name           = "sr1_fck",
3017         .ops            = &clkops_omap2_dflt_wait,
3018         .parent         = &sys_ck,
3019         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3020         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3021         .flags          = RATE_PROPAGATES,
3022         .recalc         = &followparent_recalc,
3023 };
3024
3025 /* SmartReflex fclk (VDD2) */
3026 static struct clk sr2_fck = {
3027         .name           = "sr2_fck",
3028         .ops            = &clkops_omap2_dflt_wait,
3029         .parent         = &sys_ck,
3030         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3031         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3032         .flags          = RATE_PROPAGATES,
3033         .recalc         = &followparent_recalc,
3034 };
3035
3036 static struct clk sr_l4_ick = {
3037         .name           = "sr_l4_ick",
3038         .ops            = &clkops_null, /* RMK: missing? */
3039         .parent         = &l4_ick,
3040         .clkdm_name     = "core_l4_clkdm",
3041         .recalc         = &followparent_recalc,
3042 };
3043
3044 /* SECURE_32K_FCK clocks */
3045
3046 /* XXX This clock no longer exists in 3430 TRM rev F */
3047 static struct clk gpt12_fck = {
3048         .name           = "gpt12_fck",
3049         .ops            = &clkops_null,
3050         .parent         = &secure_32k_fck,
3051         .recalc         = &followparent_recalc,
3052 };
3053
3054 static struct clk wdt1_fck = {
3055         .name           = "wdt1_fck",
3056         .ops            = &clkops_null,
3057         .parent         = &secure_32k_fck,
3058         .recalc         = &followparent_recalc,
3059 };
3060
3061 #endif