arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  36 static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
  37
  38 /* Maximum DPLL multiplier, divider values for OMAP3 */
  39 #define OMAP3_MAX_DPLL_MULT             2048
  40 #define OMAP3_MAX_DPLL_DIV              128
  41
  42 /*
  43  * DPLL1 supplies clock to the MPU.
  44  * DPLL2 supplies clock to the IVA2.
  45  * DPLL3 supplies CORE domain clocks.
  46  * DPLL4 supplies peripheral clocks.
  47  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  48  */
  49
  50 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  51 #define DPLL_LOW_POWER_STOP             0x1
  52 #define DPLL_LOW_POWER_BYPASS           0x5
  53 #define DPLL_LOCKED                     0x7
  54
  55 /* PRM CLOCKS */
  56
  57 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  58 static struct clk omap_32k_fck = {
  59         .name           = "omap_32k_fck",
  60         .ops            = &clkops_null,
  61         .rate           = 32768,
  62         .flags          = RATE_FIXED | RATE_PROPAGATES,
  63 };
  64
  65 static struct clk secure_32k_fck = {
  66         .name           = "secure_32k_fck",
  67         .ops            = &clkops_null,
  68         .rate           = 32768,
  69         .flags          = RATE_FIXED | RATE_PROPAGATES,
  70 };
  71
  72 /* Virtual source clocks for osc_sys_ck */
  73 static struct clk virt_12m_ck = {
  74         .name           = "virt_12m_ck",
  75         .ops            = &clkops_null,
  76         .rate           = 12000000,
  77         .flags          = RATE_FIXED | RATE_PROPAGATES,
  78 };
  79
  80 static struct clk virt_13m_ck = {
  81         .name           = "virt_13m_ck",
  82         .ops            = &clkops_null,
  83         .rate           = 13000000,
  84         .flags          = RATE_FIXED | RATE_PROPAGATES,
  85 };
  86
  87 static struct clk virt_16_8m_ck = {
  88         .name           = "virt_16_8m_ck",
  89         .ops            = &clkops_null,
  90         .rate           = 16800000,
  91         .flags          = RATE_FIXED | RATE_PROPAGATES,
  92 };
  93
  94 static struct clk virt_19_2m_ck = {
  95         .name           = "virt_19_2m_ck",
  96         .ops            = &clkops_null,
  97         .rate           = 19200000,
  98         .flags          = RATE_FIXED | RATE_PROPAGATES,
  99 };
 100
 101 static struct clk virt_26m_ck = {
 102         .name           = "virt_26m_ck",
 103         .ops            = &clkops_null,
 104         .rate           = 26000000,
 105         .flags          = RATE_FIXED | RATE_PROPAGATES,
 106 };
 107
 108 static struct clk virt_38_4m_ck = {
 109         .name           = "virt_38_4m_ck",
 110         .ops            = &clkops_null,
 111         .rate           = 38400000,
 112         .flags          = RATE_FIXED | RATE_PROPAGATES,
 113 };
 114
 115 static const struct clksel_rate osc_sys_12m_rates[] = {
 116         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 117         { .div = 0 }
 118 };
 119
 120 static const struct clksel_rate osc_sys_13m_rates[] = {
 121         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 122         { .div = 0 }
 123 };
 124
 125 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 126         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 127         { .div = 0 }
 128 };
 129
 130 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 131         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 132         { .div = 0 }
 133 };
 134
 135 static const struct clksel_rate osc_sys_26m_rates[] = {
 136         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 137         { .div = 0 }
 138 };
 139
 140 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 141         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 142         { .div = 0 }
 143 };
 144
 145 static const struct clksel osc_sys_clksel[] = {
 146         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 147         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 148         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 149         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 150         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 151         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 152         { .parent = NULL },
 153 };
 154
 155 /* Oscillator clock */
 156 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 157 static struct clk osc_sys_ck = {
 158         .name           = "osc_sys_ck",
 159         .ops            = &clkops_null,
 160         .init           = &omap2_init_clksel_parent,
 161         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 162         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 163         .clksel         = osc_sys_clksel,
 164         /* REVISIT: deal with autoextclkmode? */
 165         .flags          = RATE_FIXED | RATE_PROPAGATES,
 166         .recalc         = &omap2_clksel_recalc,
 167 };
 168
 169 static const struct clksel_rate div2_rates[] = {
 170         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 171         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 172         { .div = 0 }
 173 };
 174
 175 static const struct clksel sys_clksel[] = {
 176         { .parent = &osc_sys_ck, .rates = div2_rates },
 177         { .parent = NULL }
 178 };
 179
 180 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 181 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 182 static struct clk sys_ck = {
 183         .name           = "sys_ck",
 184         .ops            = &clkops_null,
 185         .parent         = &osc_sys_ck,
 186         .init           = &omap2_init_clksel_parent,
 187         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 188         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 189         .clksel         = sys_clksel,
 190         .flags          = RATE_PROPAGATES,
 191         .recalc         = &omap2_clksel_recalc,
 192 };
 193
 194 static struct clk sys_altclk = {
 195         .name           = "sys_altclk",
 196         .ops            = &clkops_null,
 197         .flags          = RATE_PROPAGATES,
 198 };
 199
 200 /* Optional external clock input for some McBSPs */
 201 static struct clk mcbsp_clks = {
 202         .name           = "mcbsp_clks",
 203         .ops            = &clkops_null,
 204         .flags          = RATE_PROPAGATES,
 205 };
 206
 207 /* PRM EXTERNAL CLOCK OUTPUT */
 208
 209 static struct clk sys_clkout1 = {
 210         .name           = "sys_clkout1",
 211         .ops            = &clkops_omap2_dflt,
 212         .parent         = &osc_sys_ck,
 213         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 214         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 215         .recalc         = &followparent_recalc,
 216 };
 217
 218 /* DPLLS */
 219
 220 /* CM CLOCKS */
 221
 222 static const struct clksel_rate dpll_bypass_rates[] = {
 223         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 224         { .div = 0 }
 225 };
 226
 227 static const struct clksel_rate dpll_locked_rates[] = {
 228         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 229         { .div = 0 }
 230 };
 231
 232 static const struct clksel_rate div16_dpll_rates[] = {
 233         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 234         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 235         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 236         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 237         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 238         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 239         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 240         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 241         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 242         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 243         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 244         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 245         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 246         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 247         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 248         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 249         { .div = 0 }
 250 };
 251
 252 /* DPLL1 */
 253 /* MPU clock source */
 254 /* Type: DPLL */
 255 static struct dpll_data dpll1_dd = {
 256         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 257         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 258         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 259         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 260         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 261         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 262         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 263         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 264         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 265         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 266         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 267         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 268         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 269         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
 270         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 271         .min_divider    = 1,
 272         .max_divider    = OMAP3_MAX_DPLL_DIV,
 273         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 274 };
 275
 276 static struct clk dpll1_ck = {
 277         .name           = "dpll1_ck",
 278         .ops            = &clkops_null,
 279         .parent         = &sys_ck,
 280         .dpll_data      = &dpll1_dd,
 281         .flags          = RATE_PROPAGATES,
 282         .round_rate     = &omap2_dpll_round_rate,
 283         .set_rate       = &omap3_noncore_dpll_set_rate,
 284         .clkdm_name     = "dpll1_clkdm",
 285         .recalc         = &omap3_dpll_recalc,
 286 };
 287
 288 /*
 289  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 290  * DPLL isn't bypassed.
 291  */
 292 static struct clk dpll1_x2_ck = {
 293         .name           = "dpll1_x2_ck",
 294         .ops            = &clkops_null,
 295         .parent         = &dpll1_ck,
 296         .flags          = RATE_PROPAGATES,
 297         .clkdm_name     = "dpll1_clkdm",
 298         .recalc         = &omap3_clkoutx2_recalc,
 299 };
 300
 301 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 302 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 303         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 304         { .parent = NULL }
 305 };
 306
 307 /*
 308  * Does not exist in the TRM - needed to separate the M2 divider from
 309  * bypass selection in mpu_ck
 310  */
 311 static struct clk dpll1_x2m2_ck = {
 312         .name           = "dpll1_x2m2_ck",
 313         .ops            = &clkops_null,
 314         .parent         = &dpll1_x2_ck,
 315         .init           = &omap2_init_clksel_parent,
 316         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 317         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 318         .clksel         = div16_dpll1_x2m2_clksel,
 319         .flags          = RATE_PROPAGATES,
 320         .clkdm_name     = "dpll1_clkdm",
 321         .recalc         = &omap2_clksel_recalc,
 322 };
 323
 324 /* DPLL2 */
 325 /* IVA2 clock source */
 326 /* Type: DPLL */
 327
 328 static struct dpll_data dpll2_dd = {
 329         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 330         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 331         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 332         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 333         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 334         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 335         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 336                                 (1 << DPLL_LOW_POWER_BYPASS),
 337         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 338         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 339         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 340         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 341         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 342         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 343         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
 344         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 345         .min_divider    = 1,
 346         .max_divider    = OMAP3_MAX_DPLL_DIV,
 347         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 348 };
 349
 350 static struct clk dpll2_ck = {
 351         .name           = "dpll2_ck",
 352         .ops            = &clkops_noncore_dpll_ops,
 353         .parent         = &sys_ck,
 354         .dpll_data      = &dpll2_dd,
 355         .flags          = RATE_PROPAGATES,
 356         .round_rate     = &omap2_dpll_round_rate,
 357         .set_rate       = &omap3_noncore_dpll_set_rate,
 358         .clkdm_name     = "dpll2_clkdm",
 359         .recalc         = &omap3_dpll_recalc,
 360 };
 361
 362 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 363         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 364         { .parent = NULL }
 365 };
 366
 367 /*
 368  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 369  * or CLKOUTX2. CLKOUT seems most plausible.
 370  */
 371 static struct clk dpll2_m2_ck = {
 372         .name           = "dpll2_m2_ck",
 373         .ops            = &clkops_null,
 374         .parent         = &dpll2_ck,
 375         .init           = &omap2_init_clksel_parent,
 376         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 377                                           OMAP3430_CM_CLKSEL2_PLL),
 378         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 379         .clksel         = div16_dpll2_m2x2_clksel,
 380         .flags          = RATE_PROPAGATES,
 381         .clkdm_name     = "dpll2_clkdm",
 382         .recalc         = &omap2_clksel_recalc,
 383 };
 384
 385 /*
 386  * DPLL3
 387  * Source clock for all interfaces and for some device fclks
 388  * REVISIT: Also supports fast relock bypass - not included below
 389  */
 390 static struct dpll_data dpll3_dd = {
 391         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 392         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 393         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 394         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 395         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 396         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 397         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 398         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 399         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 400         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 401         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 402         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 403         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
 404         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 405         .min_divider    = 1,
 406         .max_divider    = OMAP3_MAX_DPLL_DIV,
 407         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 408 };
 409
 410 static struct clk dpll3_ck = {
 411         .name           = "dpll3_ck",
 412         .ops            = &clkops_null,
 413         .parent         = &sys_ck,
 414         .dpll_data      = &dpll3_dd,
 415         .flags          = RATE_PROPAGATES,
 416         .round_rate     = &omap2_dpll_round_rate,
 417         .clkdm_name     = "dpll3_clkdm",
 418         .recalc         = &omap3_dpll_recalc,
 419 };
 420
 421 /*
 422  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 423  * DPLL isn't bypassed
 424  */
 425 static struct clk dpll3_x2_ck = {
 426         .name           = "dpll3_x2_ck",
 427         .ops            = &clkops_null,
 428         .parent         = &dpll3_ck,
 429         .flags          = RATE_PROPAGATES,
 430         .clkdm_name     = "dpll3_clkdm",
 431         .recalc         = &omap3_clkoutx2_recalc,
 432 };
 433
 434 static const struct clksel_rate div31_dpll3_rates[] = {
 435         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 436         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 437         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 438         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 439         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 440         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 441         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 442         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 443         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 444         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 445         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 446         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 447         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 448         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 449         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 450         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 451         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 452         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 453         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 454         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 455         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 456         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 457         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 458         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 459         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 460         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 461         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 462         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 463         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 464         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 465         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 466         { .div = 0 },
 467 };
 468
 469 static const struct clksel div31_dpll3m2_clksel[] = {
 470         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 471         { .parent = NULL }
 472 };
 473
 474 /*
 475  * DPLL3 output M2
 476  * REVISIT: This DPLL output divider must be changed in SRAM, so until
 477  * that code is ready, this should remain a 'read-only' clksel clock.
 478  */
 479 static struct clk dpll3_m2_ck = {
 480         .name           = "dpll3_m2_ck",
 481         .ops            = &clkops_null,
 482         .parent         = &dpll3_ck,
 483         .init           = &omap2_init_clksel_parent,
 484         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 485         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 486         .clksel         = div31_dpll3m2_clksel,
 487         .flags          = RATE_PROPAGATES,
 488         .clkdm_name     = "dpll3_clkdm",
 489         .recalc         = &omap2_clksel_recalc,
 490 };
 491
 492 static const struct clksel core_ck_clksel[] = {
 493         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 494         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 495         { .parent = NULL }
 496 };
 497
 498 static struct clk core_ck = {
 499         .name           = "core_ck",
 500         .ops            = &clkops_null,
 501         .init           = &omap2_init_clksel_parent,
 502         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 503         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 504         .clksel         = core_ck_clksel,
 505         .flags          = RATE_PROPAGATES,
 506         .recalc         = &omap2_clksel_recalc,
 507 };
 508
 509 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 510         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 511         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 512         { .parent = NULL }
 513 };
 514
 515 static struct clk dpll3_m2x2_ck = {
 516         .name           = "dpll3_m2x2_ck",
 517         .ops            = &clkops_null,
 518         .init           = &omap2_init_clksel_parent,
 519         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 520         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 521         .clksel         = dpll3_m2x2_ck_clksel,
 522         .flags          = RATE_PROPAGATES,
 523         .clkdm_name     = "dpll3_clkdm",
 524         .recalc         = &omap2_clksel_recalc,
 525 };
 526
 527 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 528 static const struct clksel div16_dpll3_clksel[] = {
 529         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 530         { .parent = NULL }
 531 };
 532
 533 /* This virtual clock is the source for dpll3_m3x2_ck */
 534 static struct clk dpll3_m3_ck = {
 535         .name           = "dpll3_m3_ck",
 536         .ops            = &clkops_null,
 537         .parent         = &dpll3_ck,
 538         .init           = &omap2_init_clksel_parent,
 539         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 540         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 541         .clksel         = div16_dpll3_clksel,
 542         .flags          = RATE_PROPAGATES,
 543         .clkdm_name     = "dpll3_clkdm",
 544         .recalc         = &omap2_clksel_recalc,
 545 };
 546
 547 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 548 static struct clk dpll3_m3x2_ck = {
 549         .name           = "dpll3_m3x2_ck",
 550         .ops            = &clkops_omap2_dflt_wait,
 551         .parent         = &dpll3_m3_ck,
 552         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 553         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 554         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 555         .clkdm_name     = "dpll3_clkdm",
 556         .recalc         = &omap3_clkoutx2_recalc,
 557 };
 558
 559 static const struct clksel emu_core_alwon_ck_clksel[] = {
 560         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 561         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 562         { .parent = NULL }
 563 };
 564
 565 static struct clk emu_core_alwon_ck = {
 566         .name           = "emu_core_alwon_ck",
 567         .ops            = &clkops_null,
 568         .parent         = &dpll3_m3x2_ck,
 569         .init           = &omap2_init_clksel_parent,
 570         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 571         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 572         .clksel         = emu_core_alwon_ck_clksel,
 573         .flags          = RATE_PROPAGATES,
 574         .clkdm_name     = "dpll3_clkdm",
 575         .recalc         = &omap2_clksel_recalc,
 576 };
 577
 578 /* DPLL4 */
 579 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 580 /* Type: DPLL */
 581 static struct dpll_data dpll4_dd = {
 582         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 583         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 584         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 585         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 586         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 587         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 588         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 589         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 590         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 591         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 592         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 593         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 594         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 595         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 596         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 597         .min_divider    = 1,
 598         .max_divider    = OMAP3_MAX_DPLL_DIV,
 599         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 600 };
 601
 602 static struct clk dpll4_ck = {
 603         .name           = "dpll4_ck",
 604         .ops            = &clkops_noncore_dpll_ops,
 605         .parent         = &sys_ck,
 606         .dpll_data      = &dpll4_dd,
 607         .flags          = RATE_PROPAGATES,
 608         .round_rate     = &omap2_dpll_round_rate,
 609         .set_rate       = &omap3_dpll4_set_rate,
 610         .clkdm_name     = "dpll4_clkdm",
 611         .recalc         = &omap3_dpll_recalc,
 612 };
 613
 614 /*
 615  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 616  * DPLL isn't bypassed --
 617  * XXX does this serve any downstream clocks?
 618  */
 619 static struct clk dpll4_x2_ck = {
 620         .name           = "dpll4_x2_ck",
 621         .ops            = &clkops_null,
 622         .parent         = &dpll4_ck,
 623         .flags          = RATE_PROPAGATES,
 624         .clkdm_name     = "dpll4_clkdm",
 625         .recalc         = &omap3_clkoutx2_recalc,
 626 };
 627
 628 static const struct clksel div16_dpll4_clksel[] = {
 629         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 630         { .parent = NULL }
 631 };
 632
 633 /* This virtual clock is the source for dpll4_m2x2_ck */
 634 static struct clk dpll4_m2_ck = {
 635         .name           = "dpll4_m2_ck",
 636         .ops            = &clkops_null,
 637         .parent         = &dpll4_ck,
 638         .init           = &omap2_init_clksel_parent,
 639         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 640         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 641         .clksel         = div16_dpll4_clksel,
 642         .flags          = RATE_PROPAGATES,
 643         .clkdm_name     = "dpll4_clkdm",
 644         .recalc         = &omap2_clksel_recalc,
 645 };
 646
 647 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 648 static struct clk dpll4_m2x2_ck = {
 649         .name           = "dpll4_m2x2_ck",
 650         .ops            = &clkops_omap2_dflt_wait,
 651         .parent         = &dpll4_m2_ck,
 652         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 653         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 654         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 655         .clkdm_name     = "dpll4_clkdm",
 656         .recalc         = &omap3_clkoutx2_recalc,
 657 };
 658
 659 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 660         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 661         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 662         { .parent = NULL }
 663 };
 664
 665 /*
 666  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 667  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 668  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 669  * CM_96K_(F)CLK.
 670  */
 671 static struct clk omap_96m_alwon_fck = {
 672         .name           = "omap_96m_alwon_fck",
 673         .ops            = &clkops_null,
 674         .parent         = &dpll4_m2x2_ck,
 675         .init           = &omap2_init_clksel_parent,
 676         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 677         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 678         .clksel         = omap_96m_alwon_fck_clksel,
 679         .flags          = RATE_PROPAGATES,
 680         .recalc         = &omap2_clksel_recalc,
 681 };
 682
 683 static struct clk cm_96m_fck = {
 684         .name           = "cm_96m_fck",
 685         .ops            = &clkops_null,
 686         .parent         = &omap_96m_alwon_fck,
 687         .flags          = RATE_PROPAGATES,
 688         .recalc         = &followparent_recalc,
 689 };
 690
 691 static const struct clksel_rate omap_96m_dpll_rates[] = {
 692         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 693         { .div = 0 }
 694 };
 695
 696 static const struct clksel_rate omap_96m_sys_rates[] = {
 697         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 698         { .div = 0 }
 699 };
 700
 701 static const struct clksel omap_96m_fck_clksel[] = {
 702         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 703         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 704         { .parent = NULL }
 705 };
 706
 707 static struct clk omap_96m_fck = {
 708         .name           = "omap_96m_fck",
 709         .ops            = &clkops_null,
 710         .parent         = &sys_ck,
 711         .init           = &omap2_init_clksel_parent,
 712         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 713         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 714         .clksel         = omap_96m_fck_clksel,
 715         .flags          = RATE_PROPAGATES,
 716         .recalc         = &omap2_clksel_recalc,
 717 };
 718
 719 /* This virtual clock is the source for dpll4_m3x2_ck */
 720 static struct clk dpll4_m3_ck = {
 721         .name           = "dpll4_m3_ck",
 722         .ops            = &clkops_null,
 723         .parent         = &dpll4_ck,
 724         .init           = &omap2_init_clksel_parent,
 725         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 726         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 727         .clksel         = div16_dpll4_clksel,
 728         .flags          = RATE_PROPAGATES,
 729         .clkdm_name     = "dpll4_clkdm",
 730         .recalc         = &omap2_clksel_recalc,
 731 };
 732
 733 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 734 static struct clk dpll4_m3x2_ck = {
 735         .name           = "dpll4_m3x2_ck",
 736         .ops            = &clkops_omap2_dflt_wait,
 737         .parent         = &dpll4_m3_ck,
 738         .init           = &omap2_init_clksel_parent,
 739         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 740         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 741         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 742         .clkdm_name     = "dpll4_clkdm",
 743         .recalc         = &omap3_clkoutx2_recalc,
 744 };
 745
 746 static const struct clksel virt_omap_54m_fck_clksel[] = {
 747         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 748         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 749         { .parent = NULL }
 750 };
 751
 752 static struct clk virt_omap_54m_fck = {
 753         .name           = "virt_omap_54m_fck",
 754         .ops            = &clkops_null,
 755         .parent         = &dpll4_m3x2_ck,
 756         .init           = &omap2_init_clksel_parent,
 757         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 758         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 759         .clksel         = virt_omap_54m_fck_clksel,
 760         .flags          = RATE_PROPAGATES,
 761         .recalc         = &omap2_clksel_recalc,
 762 };
 763
 764 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 765         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 766         { .div = 0 }
 767 };
 768
 769 static const struct clksel_rate omap_54m_alt_rates[] = {
 770         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 771         { .div = 0 }
 772 };
 773
 774 static const struct clksel omap_54m_clksel[] = {
 775         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 776         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 777         { .parent = NULL }
 778 };
 779
 780 static struct clk omap_54m_fck = {
 781         .name           = "omap_54m_fck",
 782         .ops            = &clkops_null,
 783         .init           = &omap2_init_clksel_parent,
 784         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 785         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 786         .clksel         = omap_54m_clksel,
 787         .flags          = RATE_PROPAGATES,
 788         .recalc         = &omap2_clksel_recalc,
 789 };
 790
 791 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 792         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 793         { .div = 0 }
 794 };
 795
 796 static const struct clksel_rate omap_48m_alt_rates[] = {
 797         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 798         { .div = 0 }
 799 };
 800
 801 static const struct clksel omap_48m_clksel[] = {
 802         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 803         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 804         { .parent = NULL }
 805 };
 806
 807 static struct clk omap_48m_fck = {
 808         .name           = "omap_48m_fck",
 809         .ops            = &clkops_null,
 810         .init           = &omap2_init_clksel_parent,
 811         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 812         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 813         .clksel         = omap_48m_clksel,
 814         .flags          = RATE_PROPAGATES,
 815         .recalc         = &omap2_clksel_recalc,
 816 };
 817
 818 static struct clk omap_12m_fck = {
 819         .name           = "omap_12m_fck",
 820         .ops            = &clkops_null,
 821         .parent         = &omap_48m_fck,
 822         .fixed_div      = 4,
 823         .flags          = RATE_PROPAGATES,
 824         .recalc         = &omap2_fixed_divisor_recalc,
 825 };
 826
 827 /* This virstual clock is the source for dpll4_m4x2_ck */
 828 static struct clk dpll4_m4_ck = {
 829         .name           = "dpll4_m4_ck",
 830         .ops            = &clkops_null,
 831         .parent         = &dpll4_ck,
 832         .init           = &omap2_init_clksel_parent,
 833         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 834         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 835         .clksel         = div16_dpll4_clksel,
 836         .flags          = RATE_PROPAGATES,
 837         .clkdm_name     = "dpll4_clkdm",
 838         .recalc         = &omap2_clksel_recalc,
 839         .set_rate       = &omap2_clksel_set_rate,
 840         .round_rate     = &omap2_clksel_round_rate,
 841 };
 842
 843 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 844 static struct clk dpll4_m4x2_ck = {
 845         .name           = "dpll4_m4x2_ck",
 846         .ops            = &clkops_omap2_dflt_wait,
 847         .parent         = &dpll4_m4_ck,
 848         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 849         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 850         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 851         .clkdm_name     = "dpll4_clkdm",
 852         .recalc         = &omap3_clkoutx2_recalc,
 853 };
 854
 855 /* This virtual clock is the source for dpll4_m5x2_ck */
 856 static struct clk dpll4_m5_ck = {
 857         .name           = "dpll4_m5_ck",
 858         .ops            = &clkops_null,
 859         .parent         = &dpll4_ck,
 860         .init           = &omap2_init_clksel_parent,
 861         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 862         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 863         .clksel         = div16_dpll4_clksel,
 864         .flags          = RATE_PROPAGATES,
 865         .clkdm_name     = "dpll4_clkdm",
 866         .recalc         = &omap2_clksel_recalc,
 867 };
 868
 869 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 870 static struct clk dpll4_m5x2_ck = {
 871         .name           = "dpll4_m5x2_ck",
 872         .ops            = &clkops_omap2_dflt_wait,
 873         .parent         = &dpll4_m5_ck,
 874         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 875         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 876         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 877         .clkdm_name     = "dpll4_clkdm",
 878         .recalc         = &omap3_clkoutx2_recalc,
 879 };
 880
 881 /* This virtual clock is the source for dpll4_m6x2_ck */
 882 static struct clk dpll4_m6_ck = {
 883         .name           = "dpll4_m6_ck",
 884         .ops            = &clkops_null,
 885         .parent         = &dpll4_ck,
 886         .init           = &omap2_init_clksel_parent,
 887         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 888         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 889         .clksel         = div16_dpll4_clksel,
 890         .flags          = RATE_PROPAGATES,
 891         .clkdm_name     = "dpll4_clkdm",
 892         .recalc         = &omap2_clksel_recalc,
 893 };
 894
 895 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 896 static struct clk dpll4_m6x2_ck = {
 897         .name           = "dpll4_m6x2_ck",
 898         .ops            = &clkops_omap2_dflt_wait,
 899         .parent         = &dpll4_m6_ck,
 900         .init           = &omap2_init_clksel_parent,
 901         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 902         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 903         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 904         .clkdm_name     = "dpll4_clkdm",
 905         .recalc         = &omap3_clkoutx2_recalc,
 906 };
 907
 908 static struct clk emu_per_alwon_ck = {
 909         .name           = "emu_per_alwon_ck",
 910         .ops            = &clkops_null,
 911         .parent         = &dpll4_m6x2_ck,
 912         .flags          = RATE_PROPAGATES,
 913         .clkdm_name     = "dpll4_clkdm",
 914         .recalc         = &followparent_recalc,
 915 };
 916
 917 /* DPLL5 */
 918 /* Supplies 120MHz clock, USIM source clock */
 919 /* Type: DPLL */
 920 /* 3430ES2 only */
 921 static struct dpll_data dpll5_dd = {
 922         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 923         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 924         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 925         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 926         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 927         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 928         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 929         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 930         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 931         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 932         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 933         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 934         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 935         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 936         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 937         .min_divider    = 1,
 938         .max_divider    = OMAP3_MAX_DPLL_DIV,
 939         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 940 };
 941
 942 static struct clk dpll5_ck = {
 943         .name           = "dpll5_ck",
 944         .ops            = &clkops_noncore_dpll_ops,
 945         .parent         = &sys_ck,
 946         .dpll_data      = &dpll5_dd,
 947         .flags          = RATE_PROPAGATES,
 948         .round_rate     = &omap2_dpll_round_rate,
 949         .set_rate       = &omap3_noncore_dpll_set_rate,
 950         .clkdm_name     = "dpll5_clkdm",
 951         .recalc         = &omap3_dpll_recalc,
 952 };
 953
 954 static const struct clksel div16_dpll5_clksel[] = {
 955         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 956         { .parent = NULL }
 957 };
 958
 959 static struct clk dpll5_m2_ck = {
 960         .name           = "dpll5_m2_ck",
 961         .ops            = &clkops_null,
 962         .parent         = &dpll5_ck,
 963         .init           = &omap2_init_clksel_parent,
 964         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 965         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 966         .clksel         = div16_dpll5_clksel,
 967         .flags          = RATE_PROPAGATES,
 968         .clkdm_name     = "dpll5_clkdm",
 969         .recalc         = &omap2_clksel_recalc,
 970 };
 971
 972 static const struct clksel omap_120m_fck_clksel[] = {
 973         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 974         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
 975         { .parent = NULL }
 976 };
 977
 978 static struct clk omap_120m_fck = {
 979         .name           = "omap_120m_fck",
 980         .ops            = &clkops_null,
 981         .parent         = &dpll5_m2_ck,
 982         .init           = &omap2_init_clksel_parent,
 983         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 984         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 985         .clksel         = omap_120m_fck_clksel,
 986         .flags          = RATE_PROPAGATES,
 987         .recalc         = &omap2_clksel_recalc,
 988 };
 989
 990 /* CM EXTERNAL CLOCK OUTPUTS */
 991
 992 static const struct clksel_rate clkout2_src_core_rates[] = {
 993         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 994         { .div = 0 }
 995 };
 996
 997 static const struct clksel_rate clkout2_src_sys_rates[] = {
 998         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 999         { .div = 0 }
1000 };
1001
1002 static const struct clksel_rate clkout2_src_96m_rates[] = {
1003         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
1004         { .div = 0 }
1005 };
1006
1007 static const struct clksel_rate clkout2_src_54m_rates[] = {
1008         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1009         { .div = 0 }
1010 };
1011
1012 static const struct clksel clkout2_src_clksel[] = {
1013         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
1014         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
1015         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
1016         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
1017         { .parent = NULL }
1018 };
1019
1020 static struct clk clkout2_src_ck = {
1021         .name           = "clkout2_src_ck",
1022         .ops            = &clkops_omap2_dflt,
1023         .init           = &omap2_init_clksel_parent,
1024         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
1025         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
1026         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
1027         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
1028         .clksel         = clkout2_src_clksel,
1029         .flags          = RATE_PROPAGATES,
1030         .clkdm_name     = "core_clkdm",
1031         .recalc         = &omap2_clksel_recalc,
1032 };
1033
1034 static const struct clksel_rate sys_clkout2_rates[] = {
1035         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1036         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1037         { .div = 4, .val = 2, .flags = RATE_IN_343X },
1038         { .div = 8, .val = 3, .flags = RATE_IN_343X },
1039         { .div = 16, .val = 4, .flags = RATE_IN_343X },
1040         { .div = 0 },
1041 };
1042
1043 static const struct clksel sys_clkout2_clksel[] = {
1044         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1045         { .parent = NULL },
1046 };
1047
1048 static struct clk sys_clkout2 = {
1049         .name           = "sys_clkout2",
1050         .ops            = &clkops_null,
1051         .init           = &omap2_init_clksel_parent,
1052         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
1053         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1054         .clksel         = sys_clkout2_clksel,
1055         .recalc         = &omap2_clksel_recalc,
1056 };
1057
1058 /* CM OUTPUT CLOCKS */
1059
1060 static struct clk corex2_fck = {
1061         .name           = "corex2_fck",
1062         .ops            = &clkops_null,
1063         .parent         = &dpll3_m2x2_ck,
1064         .flags          = RATE_PROPAGATES,
1065         .recalc         = &followparent_recalc,
1066 };
1067
1068 /* DPLL power domain clock controls */
1069
1070 static const struct clksel_rate div4_rates[] = {
1071         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1072         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1073         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1074         { .div = 0 }
1075 };
1076
1077 static const struct clksel div4_core_clksel[] = {
1078         { .parent = &core_ck, .rates = div4_rates },
1079         { .parent = NULL }
1080 };
1081
1082 /*
1083  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1084  * may be inconsistent here?
1085  */
1086 static struct clk dpll1_fck = {
1087         .name           = "dpll1_fck",
1088         .ops            = &clkops_null,
1089         .parent         = &core_ck,
1090         .init           = &omap2_init_clksel_parent,
1091         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1092         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1093         .clksel         = div4_core_clksel,
1094         .flags          = RATE_PROPAGATES,
1095         .recalc         = &omap2_clksel_recalc,
1096 };
1097
1098 /*
1099  * MPU clksel:
1100  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1101  * derives from the high-frequency bypass clock originating from DPLL3,
1102  * called 'dpll1_fck'
1103  */
1104 static const struct clksel mpu_clksel[] = {
1105         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1106         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1107         { .parent = NULL }
1108 };
1109
1110 static struct clk mpu_ck = {
1111         .name           = "mpu_ck",
1112         .ops            = &clkops_null,
1113         .parent         = &dpll1_x2m2_ck,
1114         .init           = &omap2_init_clksel_parent,
1115         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1116         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1117         .clksel         = mpu_clksel,
1118         .flags          = RATE_PROPAGATES,
1119         .clkdm_name     = "mpu_clkdm",
1120         .recalc         = &omap2_clksel_recalc,
1121 };
1122
1123 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1124 static const struct clksel_rate arm_fck_rates[] = {
1125         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1126         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1127         { .div = 0 },
1128 };
1129
1130 static const struct clksel arm_fck_clksel[] = {
1131         { .parent = &mpu_ck, .rates = arm_fck_rates },
1132         { .parent = NULL }
1133 };
1134
1135 static struct clk arm_fck = {
1136         .name           = "arm_fck",
1137         .ops            = &clkops_null,
1138         .parent         = &mpu_ck,
1139         .init           = &omap2_init_clksel_parent,
1140         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1141         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1142         .clksel         = arm_fck_clksel,
1143         .flags          = RATE_PROPAGATES,
1144         .recalc         = &omap2_clksel_recalc,
1145 };
1146
1147 /* XXX What about neon_clkdm ? */
1148
1149 /*
1150  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1151  * although it is referenced - so this is a guess
1152  */
1153 static struct clk emu_mpu_alwon_ck = {
1154         .name           = "emu_mpu_alwon_ck",
1155         .ops            = &clkops_null,
1156         .parent         = &mpu_ck,
1157         .flags          = RATE_PROPAGATES,
1158         .recalc         = &followparent_recalc,
1159 };
1160
1161 static struct clk dpll2_fck = {
1162         .name           = "dpll2_fck",
1163         .ops            = &clkops_null,
1164         .parent         = &core_ck,
1165         .init           = &omap2_init_clksel_parent,
1166         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1167         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1168         .clksel         = div4_core_clksel,
1169         .flags          = RATE_PROPAGATES,
1170         .recalc         = &omap2_clksel_recalc,
1171 };
1172
1173 /*
1174  * IVA2 clksel:
1175  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1176  * derives from the high-frequency bypass clock originating from DPLL3,
1177  * called 'dpll2_fck'
1178  */
1179
1180 static const struct clksel iva2_clksel[] = {
1181         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1182         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1183         { .parent = NULL }
1184 };
1185
1186 static struct clk iva2_ck = {
1187         .name           = "iva2_ck",
1188         .ops            = &clkops_omap2_dflt_wait,
1189         .parent         = &dpll2_m2_ck,
1190         .init           = &omap2_init_clksel_parent,
1191         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1192         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1193         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1194                                           OMAP3430_CM_IDLEST_PLL),
1195         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1196         .clksel         = iva2_clksel,
1197         .flags          = RATE_PROPAGATES,
1198         .clkdm_name     = "iva2_clkdm",
1199         .recalc         = &omap2_clksel_recalc,
1200 };
1201
1202 /* Common interface clocks */
1203
1204 static const struct clksel div2_core_clksel[] = {
1205         { .parent = &core_ck, .rates = div2_rates },
1206         { .parent = NULL }
1207 };
1208
1209 static struct clk l3_ick = {
1210         .name           = "l3_ick",
1211         .ops            = &clkops_null,
1212         .parent         = &core_ck,
1213         .init           = &omap2_init_clksel_parent,
1214         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1215         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1216         .clksel         = div2_core_clksel,
1217         .flags          = RATE_PROPAGATES,
1218         .clkdm_name     = "core_l3_clkdm",
1219         .recalc         = &omap2_clksel_recalc,
1220 };
1221
1222 static const struct clksel div2_l3_clksel[] = {
1223         { .parent = &l3_ick, .rates = div2_rates },
1224         { .parent = NULL }
1225 };
1226
1227 static struct clk l4_ick = {
1228         .name           = "l4_ick",
1229         .ops            = &clkops_null,
1230         .parent         = &l3_ick,
1231         .init           = &omap2_init_clksel_parent,
1232         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1233         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1234         .clksel         = div2_l3_clksel,
1235         .flags          = RATE_PROPAGATES,
1236         .clkdm_name     = "core_l4_clkdm",
1237         .recalc         = &omap2_clksel_recalc,
1238
1239 };
1240
1241 static const struct clksel div2_l4_clksel[] = {
1242         { .parent = &l4_ick, .rates = div2_rates },
1243         { .parent = NULL }
1244 };
1245
1246 static struct clk rm_ick = {
1247         .name           = "rm_ick",
1248         .ops            = &clkops_null,
1249         .parent         = &l4_ick,
1250         .init           = &omap2_init_clksel_parent,
1251         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1252         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1253         .clksel         = div2_l4_clksel,
1254         .recalc         = &omap2_clksel_recalc,
1255 };
1256
1257 /* GFX power domain */
1258
1259 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1260
1261 static const struct clksel gfx_l3_clksel[] = {
1262         { .parent = &l3_ick, .rates = gfx_l3_rates },
1263         { .parent = NULL }
1264 };
1265
1266 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1267 static struct clk gfx_l3_ck = {
1268         .name           = "gfx_l3_ck",
1269         .ops            = &clkops_omap2_dflt_wait,
1270         .parent         = &l3_ick,
1271         .init           = &omap2_init_clksel_parent,
1272         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1273         .enable_bit     = OMAP_EN_GFX_SHIFT,
1274         .recalc         = &followparent_recalc,
1275 };
1276
1277 static struct clk gfx_l3_fck = {
1278         .name           = "gfx_l3_fck",
1279         .ops            = &clkops_null,
1280         .parent         = &gfx_l3_ck,
1281         .init           = &omap2_init_clksel_parent,
1282         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1283         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1284         .clksel         = gfx_l3_clksel,
1285         .flags          = RATE_PROPAGATES,
1286         .clkdm_name     = "gfx_3430es1_clkdm",
1287         .recalc         = &omap2_clksel_recalc,
1288 };
1289
1290 static struct clk gfx_l3_ick = {
1291         .name           = "gfx_l3_ick",
1292         .ops            = &clkops_null,
1293         .parent         = &gfx_l3_ck,
1294         .clkdm_name     = "gfx_3430es1_clkdm",
1295         .recalc         = &followparent_recalc,
1296 };
1297
1298 static struct clk gfx_cg1_ck = {
1299         .name           = "gfx_cg1_ck",
1300         .ops            = &clkops_omap2_dflt_wait,
1301         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1302         .init           = &omap2_init_clk_clkdm,
1303         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1304         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1305         .clkdm_name     = "gfx_3430es1_clkdm",
1306         .recalc         = &followparent_recalc,
1307 };
1308
1309 static struct clk gfx_cg2_ck = {
1310         .name           = "gfx_cg2_ck",
1311         .ops            = &clkops_omap2_dflt_wait,
1312         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1313         .init           = &omap2_init_clk_clkdm,
1314         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1315         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1316         .clkdm_name     = "gfx_3430es1_clkdm",
1317         .recalc         = &followparent_recalc,
1318 };
1319
1320 /* SGX power domain - 3430ES2 only */
1321
1322 static const struct clksel_rate sgx_core_rates[] = {
1323         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1324         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1325         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1326         { .div = 0 },
1327 };
1328
1329 static const struct clksel_rate sgx_96m_rates[] = {
1330         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1331         { .div = 0 },
1332 };
1333
1334 static const struct clksel sgx_clksel[] = {
1335         { .parent = &core_ck,    .rates = sgx_core_rates },
1336         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1337         { .parent = NULL },
1338 };
1339
1340 static struct clk sgx_fck = {
1341         .name           = "sgx_fck",
1342         .ops            = &clkops_omap2_dflt_wait,
1343         .init           = &omap2_init_clksel_parent,
1344         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1345         .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1346         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1347         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1348         .clksel         = sgx_clksel,
1349         .clkdm_name     = "sgx_clkdm",
1350         .recalc         = &omap2_clksel_recalc,
1351 };
1352
1353 static struct clk sgx_ick = {
1354         .name           = "sgx_ick",
1355         .ops            = &clkops_omap2_dflt_wait,
1356         .parent         = &l3_ick,
1357         .init           = &omap2_init_clk_clkdm,
1358         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1359         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1360         .clkdm_name     = "sgx_clkdm",
1361         .recalc         = &followparent_recalc,
1362 };
1363
1364 /* CORE power domain */
1365
1366 static struct clk d2d_26m_fck = {
1367         .name           = "d2d_26m_fck",
1368         .ops            = &clkops_omap2_dflt_wait,
1369         .parent         = &sys_ck,
1370         .init           = &omap2_init_clk_clkdm,
1371         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1372         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1373         .clkdm_name     = "d2d_clkdm",
1374         .recalc         = &followparent_recalc,
1375 };
1376
1377 static const struct clksel omap343x_gpt_clksel[] = {
1378         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1379         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1380         { .parent = NULL}
1381 };
1382
1383 static struct clk gpt10_fck = {
1384         .name           = "gpt10_fck",
1385         .ops            = &clkops_omap2_dflt_wait,
1386         .parent         = &sys_ck,
1387         .init           = &omap2_init_clksel_parent,
1388         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1389         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1390         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1391         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1392         .clksel         = omap343x_gpt_clksel,
1393         .clkdm_name     = "core_l4_clkdm",
1394         .recalc         = &omap2_clksel_recalc,
1395 };
1396
1397 static struct clk gpt11_fck = {
1398         .name           = "gpt11_fck",
1399         .ops            = &clkops_omap2_dflt_wait,
1400         .parent         = &sys_ck,
1401         .init           = &omap2_init_clksel_parent,
1402         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1403         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1404         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1405         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1406         .clksel         = omap343x_gpt_clksel,
1407         .clkdm_name     = "core_l4_clkdm",
1408         .recalc         = &omap2_clksel_recalc,
1409 };
1410
1411 static struct clk cpefuse_fck = {
1412         .name           = "cpefuse_fck",
1413         .ops            = &clkops_omap2_dflt,
1414         .parent         = &sys_ck,
1415         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1416         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1417         .recalc         = &followparent_recalc,
1418 };
1419
1420 static struct clk ts_fck = {
1421         .name           = "ts_fck",
1422         .ops            = &clkops_omap2_dflt,
1423         .parent         = &omap_32k_fck,
1424         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1425         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1426         .recalc         = &followparent_recalc,
1427 };
1428
1429 static struct clk usbtll_fck = {
1430         .name           = "usbtll_fck",
1431         .ops            = &clkops_omap2_dflt,
1432         .parent         = &omap_120m_fck,
1433         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1434         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1435         .recalc         = &followparent_recalc,
1436 };
1437
1438 /* CORE 96M FCLK-derived clocks */
1439
1440 static struct clk core_96m_fck = {
1441         .name           = "core_96m_fck",
1442         .ops            = &clkops_null,
1443         .parent         = &omap_96m_fck,
1444         .flags          = RATE_PROPAGATES,
1445         .clkdm_name     = "core_l4_clkdm",
1446         .recalc         = &followparent_recalc,
1447 };
1448
1449 static struct clk mmchs3_fck = {
1450         .name           = "mmchs_fck",
1451         .ops            = &clkops_omap2_dflt_wait,
1452         .id             = 2,
1453         .parent         = &core_96m_fck,
1454         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1455         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1456         .clkdm_name     = "core_l4_clkdm",
1457         .recalc         = &followparent_recalc,
1458 };
1459
1460 static struct clk mmchs2_fck = {
1461         .name           = "mmchs_fck",
1462         .ops            = &clkops_omap2_dflt_wait,
1463         .id             = 1,
1464         .parent         = &core_96m_fck,
1465         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1466         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1467         .clkdm_name     = "core_l4_clkdm",
1468         .recalc         = &followparent_recalc,
1469 };
1470
1471 static struct clk mspro_fck = {
1472         .name           = "mspro_fck",
1473         .ops            = &clkops_omap2_dflt_wait,
1474         .parent         = &core_96m_fck,
1475         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1476         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1477         .clkdm_name     = "core_l4_clkdm",
1478         .recalc         = &followparent_recalc,
1479 };
1480
1481 static struct clk mmchs1_fck = {
1482         .name           = "mmchs_fck",
1483         .ops            = &clkops_omap2_dflt_wait,
1484         .parent         = &core_96m_fck,
1485         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1486         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1487         .clkdm_name     = "core_l4_clkdm",
1488         .recalc         = &followparent_recalc,
1489 };
1490
1491 static struct clk i2c3_fck = {
1492         .name           = "i2c_fck",
1493         .ops            = &clkops_omap2_dflt_wait,
1494         .id             = 3,
1495         .parent         = &core_96m_fck,
1496         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1497         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1498         .clkdm_name     = "core_l4_clkdm",
1499         .recalc         = &followparent_recalc,
1500 };
1501
1502 static struct clk i2c2_fck = {
1503         .name           = "i2c_fck",
1504         .ops            = &clkops_omap2_dflt_wait,
1505         .id             = 2,
1506         .parent         = &core_96m_fck,
1507         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1508         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1509         .clkdm_name     = "core_l4_clkdm",
1510         .recalc         = &followparent_recalc,
1511 };
1512
1513 static struct clk i2c1_fck = {
1514         .name           = "i2c_fck",
1515         .ops            = &clkops_omap2_dflt_wait,
1516         .id             = 1,
1517         .parent         = &core_96m_fck,
1518         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1519         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1520         .clkdm_name     = "core_l4_clkdm",
1521         .recalc         = &followparent_recalc,
1522 };
1523
1524 /*
1525  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1526  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1527  */
1528 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1529         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1530         { .div = 0 }
1531 };
1532
1533 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1534         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1535         { .div = 0 }
1536 };
1537
1538 static const struct clksel mcbsp_15_clksel[] = {
1539         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1540         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1541         { .parent = NULL }
1542 };
1543
1544 static struct clk mcbsp5_fck = {
1545         .name           = "mcbsp_fck",
1546         .ops            = &clkops_omap2_dflt_wait,
1547         .id             = 5,
1548         .init           = &omap2_init_clksel_parent,
1549         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1550         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1551         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1552         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1553         .clksel         = mcbsp_15_clksel,
1554         .clkdm_name     = "core_l4_clkdm",
1555         .recalc         = &omap2_clksel_recalc,
1556 };
1557
1558 static struct clk mcbsp1_fck = {
1559         .name           = "mcbsp_fck",
1560         .ops            = &clkops_omap2_dflt_wait,
1561         .id             = 1,
1562         .init           = &omap2_init_clksel_parent,
1563         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1564         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1565         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1566         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1567         .clksel         = mcbsp_15_clksel,
1568         .clkdm_name     = "core_l4_clkdm",
1569         .recalc         = &omap2_clksel_recalc,
1570 };
1571
1572 /* CORE_48M_FCK-derived clocks */
1573
1574 static struct clk core_48m_fck = {
1575         .name           = "core_48m_fck",
1576         .ops            = &clkops_null,
1577         .parent         = &omap_48m_fck,
1578         .flags          = RATE_PROPAGATES,
1579         .clkdm_name     = "core_l4_clkdm",
1580         .recalc         = &followparent_recalc,
1581 };
1582
1583 static struct clk mcspi4_fck = {
1584         .name           = "mcspi_fck",
1585         .ops            = &clkops_omap2_dflt_wait,
1586         .id             = 4,
1587         .parent         = &core_48m_fck,
1588         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1589         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1590         .recalc         = &followparent_recalc,
1591 };
1592
1593 static struct clk mcspi3_fck = {
1594         .name           = "mcspi_fck",
1595         .ops            = &clkops_omap2_dflt_wait,
1596         .id             = 3,
1597         .parent         = &core_48m_fck,
1598         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1599         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1600         .recalc         = &followparent_recalc,
1601 };
1602
1603 static struct clk mcspi2_fck = {
1604         .name           = "mcspi_fck",
1605         .ops            = &clkops_omap2_dflt_wait,
1606         .id             = 2,
1607         .parent         = &core_48m_fck,
1608         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1609         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1610         .recalc         = &followparent_recalc,
1611 };
1612
1613 static struct clk mcspi1_fck = {
1614         .name           = "mcspi_fck",
1615         .ops            = &clkops_omap2_dflt_wait,
1616         .id             = 1,
1617         .parent         = &core_48m_fck,
1618         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1619         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1620         .recalc         = &followparent_recalc,
1621 };
1622
1623 static struct clk uart2_fck = {
1624         .name           = "uart2_fck",
1625         .ops            = &clkops_omap2_dflt_wait,
1626         .parent         = &core_48m_fck,
1627         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1628         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1629         .recalc         = &followparent_recalc,
1630 };
1631
1632 static struct clk uart1_fck = {
1633         .name           = "uart1_fck",
1634         .ops            = &clkops_omap2_dflt_wait,
1635         .parent         = &core_48m_fck,
1636         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1637         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1638         .recalc         = &followparent_recalc,
1639 };
1640
1641 static struct clk fshostusb_fck = {
1642         .name           = "fshostusb_fck",
1643         .ops            = &clkops_omap2_dflt_wait,
1644         .parent         = &core_48m_fck,
1645         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1646         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1647         .recalc         = &followparent_recalc,
1648 };
1649
1650 /* CORE_12M_FCK based clocks */
1651
1652 static struct clk core_12m_fck = {
1653         .name           = "core_12m_fck",
1654         .ops            = &clkops_null,
1655         .parent         = &omap_12m_fck,
1656         .flags          = RATE_PROPAGATES,
1657         .clkdm_name     = "core_l4_clkdm",
1658         .recalc         = &followparent_recalc,
1659 };
1660
1661 static struct clk hdq_fck = {
1662         .name           = "hdq_fck",
1663         .ops            = &clkops_omap2_dflt_wait,
1664         .parent         = &core_12m_fck,
1665         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1666         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1667         .recalc         = &followparent_recalc,
1668 };
1669
1670 /* DPLL3-derived clock */
1671
1672 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1673         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1674         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1675         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1676         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1677         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1678         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1679         { .div = 0 }
1680 };
1681
1682 static const struct clksel ssi_ssr_clksel[] = {
1683         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1684         { .parent = NULL }
1685 };
1686
1687 static struct clk ssi_ssr_fck = {
1688         .name           = "ssi_ssr_fck",
1689         .ops            = &clkops_omap2_dflt,
1690         .init           = &omap2_init_clksel_parent,
1691         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1692         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1693         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1694         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1695         .clksel         = ssi_ssr_clksel,
1696         .flags          = RATE_PROPAGATES,
1697         .clkdm_name     = "core_l4_clkdm",
1698         .recalc         = &omap2_clksel_recalc,
1699 };
1700
1701 static struct clk ssi_sst_fck = {
1702         .name           = "ssi_sst_fck",
1703         .ops            = &clkops_null,
1704         .parent         = &ssi_ssr_fck,
1705         .fixed_div      = 2,
1706         .recalc         = &omap2_fixed_divisor_recalc,
1707 };
1708
1709
1710
1711 /* CORE_L3_ICK based clocks */
1712
1713 /*
1714  * XXX must add clk_enable/clk_disable for these if standard code won't
1715  * handle it
1716  */
1717 static struct clk core_l3_ick = {
1718         .name           = "core_l3_ick",
1719         .ops            = &clkops_null,
1720         .parent         = &l3_ick,
1721         .init           = &omap2_init_clk_clkdm,
1722         .flags          = RATE_PROPAGATES,
1723         .clkdm_name     = "core_l3_clkdm",
1724         .recalc         = &followparent_recalc,
1725 };
1726
1727 static struct clk hsotgusb_ick = {
1728         .name           = "hsotgusb_ick",
1729         .ops            = &clkops_omap2_dflt_wait,
1730         .parent         = &core_l3_ick,
1731         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1732         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1733         .clkdm_name     = "core_l3_clkdm",
1734         .recalc         = &followparent_recalc,
1735 };
1736
1737 static struct clk sdrc_ick = {
1738         .name           = "sdrc_ick",
1739         .ops            = &clkops_omap2_dflt_wait,
1740         .parent         = &core_l3_ick,
1741         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1742         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1743         .flags          = ENABLE_ON_INIT,
1744         .clkdm_name     = "core_l3_clkdm",
1745         .recalc         = &followparent_recalc,
1746 };
1747
1748 static struct clk gpmc_fck = {
1749         .name           = "gpmc_fck",
1750         .ops            = &clkops_null,
1751         .parent         = &core_l3_ick,
1752         .flags          = ENABLE_ON_INIT, /* huh? */
1753         .clkdm_name     = "core_l3_clkdm",
1754         .recalc         = &followparent_recalc,
1755 };
1756
1757 /* SECURITY_L3_ICK based clocks */
1758
1759 static struct clk security_l3_ick = {
1760         .name           = "security_l3_ick",
1761         .ops            = &clkops_null,
1762         .parent         = &l3_ick,
1763         .flags          = RATE_PROPAGATES,
1764         .recalc         = &followparent_recalc,
1765 };
1766
1767 static struct clk pka_ick = {
1768         .name           = "pka_ick",
1769         .ops            = &clkops_omap2_dflt_wait,
1770         .parent         = &security_l3_ick,
1771         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1772         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1773         .recalc         = &followparent_recalc,
1774 };
1775
1776 /* CORE_L4_ICK based clocks */
1777
1778 static struct clk core_l4_ick = {
1779         .name           = "core_l4_ick",
1780         .ops            = &clkops_null,
1781         .parent         = &l4_ick,
1782         .init           = &omap2_init_clk_clkdm,
1783         .flags          = RATE_PROPAGATES,
1784         .clkdm_name     = "core_l4_clkdm",
1785         .recalc         = &followparent_recalc,
1786 };
1787
1788 static struct clk usbtll_ick = {
1789         .name           = "usbtll_ick",
1790         .ops            = &clkops_omap2_dflt_wait,
1791         .parent         = &core_l4_ick,
1792         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1793         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1794         .clkdm_name     = "core_l4_clkdm",
1795         .recalc         = &followparent_recalc,
1796 };
1797
1798 static struct clk mmchs3_ick = {
1799         .name           = "mmchs_ick",
1800         .ops            = &clkops_omap2_dflt_wait,
1801         .id             = 2,
1802         .parent         = &core_l4_ick,
1803         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1804         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1805         .clkdm_name     = "core_l4_clkdm",
1806         .recalc         = &followparent_recalc,
1807 };
1808
1809 /* Intersystem Communication Registers - chassis mode only */
1810 static struct clk icr_ick = {
1811         .name           = "icr_ick",
1812         .ops            = &clkops_omap2_dflt_wait,
1813         .parent         = &core_l4_ick,
1814         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1815         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1816         .clkdm_name     = "core_l4_clkdm",
1817         .recalc         = &followparent_recalc,
1818 };
1819
1820 static struct clk aes2_ick = {
1821         .name           = "aes2_ick",
1822         .ops            = &clkops_omap2_dflt_wait,
1823         .parent         = &core_l4_ick,
1824         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1825         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1826         .clkdm_name     = "core_l4_clkdm",
1827         .recalc         = &followparent_recalc,
1828 };
1829
1830 static struct clk sha12_ick = {
1831         .name           = "sha12_ick",
1832         .ops            = &clkops_omap2_dflt_wait,
1833         .parent         = &core_l4_ick,
1834         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1835         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1836         .clkdm_name     = "core_l4_clkdm",
1837         .recalc         = &followparent_recalc,
1838 };
1839
1840 static struct clk des2_ick = {
1841         .name           = "des2_ick",
1842         .ops            = &clkops_omap2_dflt_wait,
1843         .parent         = &core_l4_ick,
1844         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1845         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1846         .clkdm_name     = "core_l4_clkdm",
1847         .recalc         = &followparent_recalc,
1848 };
1849
1850 static struct clk mmchs2_ick = {
1851         .name           = "mmchs_ick",
1852         .ops            = &clkops_omap2_dflt_wait,
1853         .id             = 1,
1854         .parent         = &core_l4_ick,
1855         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1856         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1857         .clkdm_name     = "core_l4_clkdm",
1858         .recalc         = &followparent_recalc,
1859 };
1860
1861 static struct clk mmchs1_ick = {
1862         .name           = "mmchs_ick",
1863         .ops            = &clkops_omap2_dflt_wait,
1864         .parent         = &core_l4_ick,
1865         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1866         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1867         .clkdm_name     = "core_l4_clkdm",
1868         .recalc         = &followparent_recalc,
1869 };
1870
1871 static struct clk mspro_ick = {
1872         .name           = "mspro_ick",
1873         .ops            = &clkops_omap2_dflt_wait,
1874         .parent         = &core_l4_ick,
1875         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1876         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1877         .clkdm_name     = "core_l4_clkdm",
1878         .recalc         = &followparent_recalc,
1879 };
1880
1881 static struct clk hdq_ick = {
1882         .name           = "hdq_ick",
1883         .ops            = &clkops_omap2_dflt_wait,
1884         .parent         = &core_l4_ick,
1885         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1886         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1887         .clkdm_name     = "core_l4_clkdm",
1888         .recalc         = &followparent_recalc,
1889 };
1890
1891 static struct clk mcspi4_ick = {
1892         .name           = "mcspi_ick",
1893         .ops            = &clkops_omap2_dflt_wait,
1894         .id             = 4,
1895         .parent         = &core_l4_ick,
1896         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1897         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1898         .clkdm_name     = "core_l4_clkdm",
1899         .recalc         = &followparent_recalc,
1900 };
1901
1902 static struct clk mcspi3_ick = {
1903         .name           = "mcspi_ick",
1904         .ops            = &clkops_omap2_dflt_wait,
1905         .id             = 3,
1906         .parent         = &core_l4_ick,
1907         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1908         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1909         .clkdm_name     = "core_l4_clkdm",
1910         .recalc         = &followparent_recalc,
1911 };
1912
1913 static struct clk mcspi2_ick = {
1914         .name           = "mcspi_ick",
1915         .ops            = &clkops_omap2_dflt_wait,
1916         .id             = 2,
1917         .parent         = &core_l4_ick,
1918         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1919         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1920         .clkdm_name     = "core_l4_clkdm",
1921         .recalc         = &followparent_recalc,
1922 };
1923
1924 static struct clk mcspi1_ick = {
1925         .name           = "mcspi_ick",
1926         .ops            = &clkops_omap2_dflt_wait,
1927         .id             = 1,
1928         .parent         = &core_l4_ick,
1929         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1930         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1931         .clkdm_name     = "core_l4_clkdm",
1932         .recalc         = &followparent_recalc,
1933 };
1934
1935 static struct clk i2c3_ick = {
1936         .name           = "i2c_ick",
1937         .ops            = &clkops_omap2_dflt_wait,
1938         .id             = 3,
1939         .parent         = &core_l4_ick,
1940         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1941         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1942         .clkdm_name     = "core_l4_clkdm",
1943         .recalc         = &followparent_recalc,
1944 };
1945
1946 static struct clk i2c2_ick = {
1947         .name           = "i2c_ick",
1948         .ops            = &clkops_omap2_dflt_wait,
1949         .id             = 2,
1950         .parent         = &core_l4_ick,
1951         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1952         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1953         .clkdm_name     = "core_l4_clkdm",
1954         .recalc         = &followparent_recalc,
1955 };
1956
1957 static struct clk i2c1_ick = {
1958         .name           = "i2c_ick",
1959         .ops            = &clkops_omap2_dflt_wait,
1960         .id             = 1,
1961         .parent         = &core_l4_ick,
1962         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1963         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1964         .clkdm_name     = "core_l4_clkdm",
1965         .recalc         = &followparent_recalc,
1966 };
1967
1968 static struct clk uart2_ick = {
1969         .name           = "uart2_ick",
1970         .ops            = &clkops_omap2_dflt_wait,
1971         .parent         = &core_l4_ick,
1972         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1973         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1974         .clkdm_name     = "core_l4_clkdm",
1975         .recalc         = &followparent_recalc,
1976 };
1977
1978 static struct clk uart1_ick = {
1979         .name           = "uart1_ick",
1980         .ops            = &clkops_omap2_dflt_wait,
1981         .parent         = &core_l4_ick,
1982         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1983         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1984         .clkdm_name     = "core_l4_clkdm",
1985         .recalc         = &followparent_recalc,
1986 };
1987
1988 static struct clk gpt11_ick = {
1989         .name           = "gpt11_ick",
1990         .ops            = &clkops_omap2_dflt_wait,
1991         .parent         = &core_l4_ick,
1992         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1993         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1994         .clkdm_name     = "core_l4_clkdm",
1995         .recalc         = &followparent_recalc,
1996 };
1997
1998 static struct clk gpt10_ick = {
1999         .name           = "gpt10_ick",
2000         .ops            = &clkops_omap2_dflt_wait,
2001         .parent         = &core_l4_ick,
2002         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2003         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
2004         .clkdm_name     = "core_l4_clkdm",
2005         .recalc         = &followparent_recalc,
2006 };
2007
2008 static struct clk mcbsp5_ick = {
2009         .name           = "mcbsp_ick",
2010         .ops            = &clkops_omap2_dflt_wait,
2011         .id             = 5,
2012         .parent         = &core_l4_ick,
2013         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2014         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
2015         .clkdm_name     = "core_l4_clkdm",
2016         .recalc         = &followparent_recalc,
2017 };
2018
2019 static struct clk mcbsp1_ick = {
2020         .name           = "mcbsp_ick",
2021         .ops            = &clkops_omap2_dflt_wait,
2022         .id             = 1,
2023         .parent         = &core_l4_ick,
2024         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2025         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2026         .clkdm_name     = "core_l4_clkdm",
2027         .recalc         = &followparent_recalc,
2028 };
2029
2030 static struct clk fac_ick = {
2031         .name           = "fac_ick",
2032         .ops            = &clkops_omap2_dflt_wait,
2033         .parent         = &core_l4_ick,
2034         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2035         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
2036         .clkdm_name     = "core_l4_clkdm",
2037         .recalc         = &followparent_recalc,
2038 };
2039
2040 static struct clk mailboxes_ick = {
2041         .name           = "mailboxes_ick",
2042         .ops            = &clkops_omap2_dflt_wait,
2043         .parent         = &core_l4_ick,
2044         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2045         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2046         .clkdm_name     = "core_l4_clkdm",
2047         .recalc         = &followparent_recalc,
2048 };
2049
2050 static struct clk omapctrl_ick = {
2051         .name           = "omapctrl_ick",
2052         .ops            = &clkops_omap2_dflt_wait,
2053         .parent         = &core_l4_ick,
2054         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2055         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2056         .flags          = ENABLE_ON_INIT,
2057         .recalc         = &followparent_recalc,
2058 };
2059
2060 /* SSI_L4_ICK based clocks */
2061
2062 static struct clk ssi_l4_ick = {
2063         .name           = "ssi_l4_ick",
2064         .ops            = &clkops_null,
2065         .parent         = &l4_ick,
2066         .flags          = RATE_PROPAGATES,
2067         .clkdm_name     = "core_l4_clkdm",
2068         .recalc         = &followparent_recalc,
2069 };
2070
2071 static struct clk ssi_ick = {
2072         .name           = "ssi_ick",
2073         .ops            = &clkops_omap2_dflt,
2074         .parent         = &ssi_l4_ick,
2075         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2076         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2077         .clkdm_name     = "core_l4_clkdm",
2078         .recalc         = &followparent_recalc,
2079 };
2080
2081 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2082  * but l4_ick makes more sense to me */
2083
2084 static const struct clksel usb_l4_clksel[] = {
2085         { .parent = &l4_ick, .rates = div2_rates },
2086         { .parent = NULL },
2087 };
2088
2089 static struct clk usb_l4_ick = {
2090         .name           = "usb_l4_ick",
2091         .ops            = &clkops_omap2_dflt_wait,
2092         .parent         = &l4_ick,
2093         .init           = &omap2_init_clksel_parent,
2094         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2095         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2096         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2097         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2098         .clksel         = usb_l4_clksel,
2099         .recalc         = &omap2_clksel_recalc,
2100 };
2101
2102 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2103
2104 /* SECURITY_L4_ICK2 based clocks */
2105
2106 static struct clk security_l4_ick2 = {
2107         .name           = "security_l4_ick2",
2108         .ops            = &clkops_null,
2109         .parent         = &l4_ick,
2110         .flags          = RATE_PROPAGATES,
2111         .recalc         = &followparent_recalc,
2112 };
2113
2114 static struct clk aes1_ick = {
2115         .name           = "aes1_ick",
2116         .ops            = &clkops_omap2_dflt_wait,
2117         .parent         = &security_l4_ick2,
2118         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2119         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2120         .recalc         = &followparent_recalc,
2121 };
2122
2123 static struct clk rng_ick = {
2124         .name           = "rng_ick",
2125         .ops            = &clkops_omap2_dflt_wait,
2126         .parent         = &security_l4_ick2,
2127         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2128         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2129         .recalc         = &followparent_recalc,
2130 };
2131
2132 static struct clk sha11_ick = {
2133         .name           = "sha11_ick",
2134         .ops            = &clkops_omap2_dflt_wait,
2135         .parent         = &security_l4_ick2,
2136         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2137         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2138         .recalc         = &followparent_recalc,
2139 };
2140
2141 static struct clk des1_ick = {
2142         .name           = "des1_ick",
2143         .ops            = &clkops_omap2_dflt_wait,
2144         .parent         = &security_l4_ick2,
2145         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2146         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2147         .recalc         = &followparent_recalc,
2148 };
2149
2150 /* DSS */
2151 static const struct clksel dss1_alwon_fck_clksel[] = {
2152         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2153         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2154         { .parent = NULL }
2155 };
2156
2157 static struct clk dss1_alwon_fck = {
2158         .name           = "dss1_alwon_fck",
2159         .ops            = &clkops_omap2_dflt,
2160         .parent         = &dpll4_m4x2_ck,
2161         .init           = &omap2_init_clksel_parent,
2162         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2163         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2164         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2165         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2166         .clksel         = dss1_alwon_fck_clksel,
2167         .clkdm_name     = "dss_clkdm",
2168         .recalc         = &omap2_clksel_recalc,
2169 };
2170
2171 static struct clk dss_tv_fck = {
2172         .name           = "dss_tv_fck",
2173         .ops            = &clkops_omap2_dflt,
2174         .parent         = &omap_54m_fck,
2175         .init           = &omap2_init_clk_clkdm,
2176         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2177         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2178         .clkdm_name     = "dss_clkdm",
2179         .recalc         = &followparent_recalc,
2180 };
2181
2182 static struct clk dss_96m_fck = {
2183         .name           = "dss_96m_fck",
2184         .ops            = &clkops_omap2_dflt,
2185         .parent         = &omap_96m_fck,
2186         .init           = &omap2_init_clk_clkdm,
2187         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2188         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2189         .clkdm_name     = "dss_clkdm",
2190         .recalc         = &followparent_recalc,
2191 };
2192
2193 static struct clk dss2_alwon_fck = {
2194         .name           = "dss2_alwon_fck",
2195         .ops            = &clkops_omap2_dflt,
2196         .parent         = &sys_ck,
2197         .init           = &omap2_init_clk_clkdm,
2198         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2199         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2200         .clkdm_name     = "dss_clkdm",
2201         .recalc         = &followparent_recalc,
2202 };
2203
2204 static struct clk dss_ick = {
2205         /* Handles both L3 and L4 clocks */
2206         .name           = "dss_ick",
2207         .ops            = &clkops_omap2_dflt,
2208         .parent         = &l4_ick,
2209         .init           = &omap2_init_clk_clkdm,
2210         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2211         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2212         .clkdm_name     = "dss_clkdm",
2213         .recalc         = &followparent_recalc,
2214 };
2215
2216 /* CAM */
2217
2218 static const struct clksel cam_mclk_clksel[] = {
2219         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2220         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2221         { .parent = NULL }
2222 };
2223
2224 static struct clk cam_mclk = {
2225         .name           = "cam_mclk",
2226         .ops            = &clkops_omap2_dflt_wait,
2227         .parent         = &dpll4_m5x2_ck,
2228         .init           = &omap2_init_clksel_parent,
2229         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2230         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2231         .clksel         = cam_mclk_clksel,
2232         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2233         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2234         .clkdm_name     = "cam_clkdm",
2235         .recalc         = &omap2_clksel_recalc,
2236 };
2237
2238 static struct clk cam_ick = {
2239         /* Handles both L3 and L4 clocks */
2240         .name           = "cam_ick",
2241         .ops            = &clkops_omap2_dflt_wait,
2242         .parent         = &l4_ick,
2243         .init           = &omap2_init_clk_clkdm,
2244         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2245         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2246         .clkdm_name     = "cam_clkdm",
2247         .recalc         = &followparent_recalc,
2248 };
2249
2250 static struct clk csi2_96m_fck = {
2251         .name           = "csi2_96m_fck",
2252         .ops            = &clkops_omap2_dflt_wait,
2253         .parent         = &core_96m_fck,
2254         .init           = &omap2_init_clk_clkdm,
2255         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2256         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2257         .clkdm_name     = "cam_clkdm",
2258         .recalc         = &followparent_recalc,
2259 };
2260
2261 /* USBHOST - 3430ES2 only */
2262
2263 static struct clk usbhost_120m_fck = {
2264         .name           = "usbhost_120m_fck",
2265         .ops            = &clkops_omap2_dflt_wait,
2266         .parent         = &omap_120m_fck,
2267         .init           = &omap2_init_clk_clkdm,
2268         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2269         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2270         .clkdm_name     = "usbhost_clkdm",
2271         .recalc         = &followparent_recalc,
2272 };
2273
2274 static struct clk usbhost_48m_fck = {
2275         .name           = "usbhost_48m_fck",
2276         .ops            = &clkops_omap2_dflt_wait,
2277         .parent         = &omap_48m_fck,
2278         .init           = &omap2_init_clk_clkdm,
2279         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2280         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2281         .clkdm_name     = "usbhost_clkdm",
2282         .recalc         = &followparent_recalc,
2283 };
2284
2285 static struct clk usbhost_ick = {
2286         /* Handles both L3 and L4 clocks */
2287         .name           = "usbhost_ick",
2288         .ops            = &clkops_omap2_dflt_wait,
2289         .parent         = &l4_ick,
2290         .init           = &omap2_init_clk_clkdm,
2291         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2292         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2293         .clkdm_name     = "usbhost_clkdm",
2294         .recalc         = &followparent_recalc,
2295 };
2296
2297 /* WKUP */
2298
2299 static const struct clksel_rate usim_96m_rates[] = {
2300         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2301         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2302         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2303         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2304         { .div = 0 },
2305 };
2306
2307 static const struct clksel_rate usim_120m_rates[] = {
2308         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2309         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2310         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2311         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2312         { .div = 0 },
2313 };
2314
2315 static const struct clksel usim_clksel[] = {
2316         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2317         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2318         { .parent = &sys_ck,            .rates = div2_rates },
2319         { .parent = NULL },
2320 };
2321
2322 /* 3430ES2 only */
2323 static struct clk usim_fck = {
2324         .name           = "usim_fck",
2325         .ops            = &clkops_omap2_dflt_wait,
2326         .init           = &omap2_init_clksel_parent,
2327         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2328         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2329         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2330         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2331         .clksel         = usim_clksel,
2332         .recalc         = &omap2_clksel_recalc,
2333 };
2334
2335 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2336 static struct clk gpt1_fck = {
2337         .name           = "gpt1_fck",
2338         .ops            = &clkops_omap2_dflt_wait,
2339         .init           = &omap2_init_clksel_parent,
2340         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2341         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2342         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2343         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2344         .clksel         = omap343x_gpt_clksel,
2345         .clkdm_name     = "wkup_clkdm",
2346         .recalc         = &omap2_clksel_recalc,
2347 };
2348
2349 static struct clk wkup_32k_fck = {
2350         .name           = "wkup_32k_fck",
2351         .ops            = &clkops_null,
2352         .init           = &omap2_init_clk_clkdm,
2353         .parent         = &omap_32k_fck,
2354         .flags          = RATE_PROPAGATES,
2355         .clkdm_name     = "wkup_clkdm",
2356         .recalc         = &followparent_recalc,
2357 };
2358
2359 static struct clk gpio1_dbck = {
2360         .name           = "gpio1_dbck",
2361         .ops            = &clkops_omap2_dflt_wait,
2362         .parent         = &wkup_32k_fck,
2363         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2364         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2365         .clkdm_name     = "wkup_clkdm",
2366         .recalc         = &followparent_recalc,
2367 };
2368
2369 static struct clk wdt2_fck = {
2370         .name           = "wdt2_fck",
2371         .ops            = &clkops_omap2_dflt_wait,
2372         .parent         = &wkup_32k_fck,
2373         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2374         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2375         .clkdm_name     = "wkup_clkdm",
2376         .recalc         = &followparent_recalc,
2377 };
2378
2379 static struct clk wkup_l4_ick = {
2380         .name           = "wkup_l4_ick",
2381         .ops            = &clkops_null,
2382         .parent         = &sys_ck,
2383         .flags          = RATE_PROPAGATES,
2384         .clkdm_name     = "wkup_clkdm",
2385         .recalc         = &followparent_recalc,
2386 };
2387
2388 /* 3430ES2 only */
2389 /* Never specifically named in the TRM, so we have to infer a likely name */
2390 static struct clk usim_ick = {
2391         .name           = "usim_ick",
2392         .ops            = &clkops_omap2_dflt_wait,
2393         .parent         = &wkup_l4_ick,
2394         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2395         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2396         .clkdm_name     = "wkup_clkdm",
2397         .recalc         = &followparent_recalc,
2398 };
2399
2400 static struct clk wdt2_ick = {
2401         .name           = "wdt2_ick",
2402         .ops            = &clkops_omap2_dflt_wait,
2403         .parent         = &wkup_l4_ick,
2404         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2405         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2406         .clkdm_name     = "wkup_clkdm",
2407         .recalc         = &followparent_recalc,
2408 };
2409
2410 static struct clk wdt1_ick = {
2411         .name           = "wdt1_ick",
2412         .ops            = &clkops_omap2_dflt_wait,
2413         .parent         = &wkup_l4_ick,
2414         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2415         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2416         .clkdm_name     = "wkup_clkdm",
2417         .recalc         = &followparent_recalc,
2418 };
2419
2420 static struct clk gpio1_ick = {
2421         .name           = "gpio1_ick",
2422         .ops            = &clkops_omap2_dflt_wait,
2423         .parent         = &wkup_l4_ick,
2424         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2425         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2426         .clkdm_name     = "wkup_clkdm",
2427         .recalc         = &followparent_recalc,
2428 };
2429
2430 static struct clk omap_32ksync_ick = {
2431         .name           = "omap_32ksync_ick",
2432         .ops            = &clkops_omap2_dflt_wait,
2433         .parent         = &wkup_l4_ick,
2434         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2435         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2436         .clkdm_name     = "wkup_clkdm",
2437         .recalc         = &followparent_recalc,
2438 };
2439
2440 /* XXX This clock no longer exists in 3430 TRM rev F */
2441 static struct clk gpt12_ick = {
2442         .name           = "gpt12_ick",
2443         .ops            = &clkops_omap2_dflt_wait,
2444         .parent         = &wkup_l4_ick,
2445         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2446         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2447         .clkdm_name     = "wkup_clkdm",
2448         .recalc         = &followparent_recalc,
2449 };
2450
2451 static struct clk gpt1_ick = {
2452         .name           = "gpt1_ick",
2453         .ops            = &clkops_omap2_dflt_wait,
2454         .parent         = &wkup_l4_ick,
2455         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2456         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2457         .clkdm_name     = "wkup_clkdm",
2458         .recalc         = &followparent_recalc,
2459 };
2460
2461
2462
2463 /* PER clock domain */
2464
2465 static struct clk per_96m_fck = {
2466         .name           = "per_96m_fck",
2467         .ops            = &clkops_null,
2468         .parent         = &omap_96m_alwon_fck,
2469         .init           = &omap2_init_clk_clkdm,
2470         .flags          = RATE_PROPAGATES,
2471         .clkdm_name     = "per_clkdm",
2472         .recalc         = &followparent_recalc,
2473 };
2474
2475 static struct clk per_48m_fck = {
2476         .name           = "per_48m_fck",
2477         .ops            = &clkops_null,
2478         .parent         = &omap_48m_fck,
2479         .init           = &omap2_init_clk_clkdm,
2480         .flags          = RATE_PROPAGATES,
2481         .clkdm_name     = "per_clkdm",
2482         .recalc         = &followparent_recalc,
2483 };
2484
2485 static struct clk uart3_fck = {
2486         .name           = "uart3_fck",
2487         .ops            = &clkops_omap2_dflt_wait,
2488         .parent         = &per_48m_fck,
2489         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2490         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2491         .clkdm_name     = "per_clkdm",
2492         .recalc         = &followparent_recalc,
2493 };
2494
2495 static struct clk gpt2_fck = {
2496         .name           = "gpt2_fck",
2497         .ops            = &clkops_omap2_dflt_wait,
2498         .init           = &omap2_init_clksel_parent,
2499         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2500         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2501         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2502         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2503         .clksel         = omap343x_gpt_clksel,
2504         .clkdm_name     = "per_clkdm",
2505         .recalc         = &omap2_clksel_recalc,
2506 };
2507
2508 static struct clk gpt3_fck = {
2509         .name           = "gpt3_fck",
2510         .ops            = &clkops_omap2_dflt_wait,
2511         .init           = &omap2_init_clksel_parent,
2512         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2513         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2514         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2515         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2516         .clksel         = omap343x_gpt_clksel,
2517         .clkdm_name     = "per_clkdm",
2518         .recalc         = &omap2_clksel_recalc,
2519 };
2520
2521 static struct clk gpt4_fck = {
2522         .name           = "gpt4_fck",
2523         .ops            = &clkops_omap2_dflt_wait,
2524         .init           = &omap2_init_clksel_parent,
2525         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2526         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2527         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2528         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2529         .clksel         = omap343x_gpt_clksel,
2530         .clkdm_name     = "per_clkdm",
2531         .recalc         = &omap2_clksel_recalc,
2532 };
2533
2534 static struct clk gpt5_fck = {
2535         .name           = "gpt5_fck",
2536         .ops            = &clkops_omap2_dflt_wait,
2537         .init           = &omap2_init_clksel_parent,
2538         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2539         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2540         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2541         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2542         .clksel         = omap343x_gpt_clksel,
2543         .clkdm_name     = "per_clkdm",
2544         .recalc         = &omap2_clksel_recalc,
2545 };
2546
2547 static struct clk gpt6_fck = {
2548         .name           = "gpt6_fck",
2549         .ops            = &clkops_omap2_dflt_wait,
2550         .init           = &omap2_init_clksel_parent,
2551         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2552         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2553         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2554         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2555         .clksel         = omap343x_gpt_clksel,
2556         .clkdm_name     = "per_clkdm",
2557         .recalc         = &omap2_clksel_recalc,
2558 };
2559
2560 static struct clk gpt7_fck = {
2561         .name           = "gpt7_fck",
2562         .ops            = &clkops_omap2_dflt_wait,
2563         .init           = &omap2_init_clksel_parent,
2564         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2565         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2566         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2567         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2568         .clksel         = omap343x_gpt_clksel,
2569         .clkdm_name     = "per_clkdm",
2570         .recalc         = &omap2_clksel_recalc,
2571 };
2572
2573 static struct clk gpt8_fck = {
2574         .name           = "gpt8_fck",
2575         .ops            = &clkops_omap2_dflt_wait,
2576         .init           = &omap2_init_clksel_parent,
2577         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2578         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2579         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2580         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2581         .clksel         = omap343x_gpt_clksel,
2582         .clkdm_name     = "per_clkdm",
2583         .recalc         = &omap2_clksel_recalc,
2584 };
2585
2586 static struct clk gpt9_fck = {
2587         .name           = "gpt9_fck",
2588         .ops            = &clkops_omap2_dflt_wait,
2589         .init           = &omap2_init_clksel_parent,
2590         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2591         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2592         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2593         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2594         .clksel         = omap343x_gpt_clksel,
2595         .clkdm_name     = "per_clkdm",
2596         .recalc         = &omap2_clksel_recalc,
2597 };
2598
2599 static struct clk per_32k_alwon_fck = {
2600         .name           = "per_32k_alwon_fck",
2601         .ops            = &clkops_null,
2602         .parent         = &omap_32k_fck,
2603         .clkdm_name     = "per_clkdm",
2604         .flags          = RATE_PROPAGATES,
2605         .recalc         = &followparent_recalc,
2606 };
2607
2608 static struct clk gpio6_dbck = {
2609         .name           = "gpio6_dbck",
2610         .ops            = &clkops_omap2_dflt_wait,
2611         .parent         = &per_32k_alwon_fck,
2612         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2613         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2614         .clkdm_name     = "per_clkdm",
2615         .recalc         = &followparent_recalc,
2616 };
2617
2618 static struct clk gpio5_dbck = {
2619         .name           = "gpio5_dbck",
2620         .ops            = &clkops_omap2_dflt_wait,
2621         .parent         = &per_32k_alwon_fck,
2622         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2623         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2624         .clkdm_name     = "per_clkdm",
2625         .recalc         = &followparent_recalc,
2626 };
2627
2628 static struct clk gpio4_dbck = {
2629         .name           = "gpio4_dbck",
2630         .ops            = &clkops_omap2_dflt_wait,
2631         .parent         = &per_32k_alwon_fck,
2632         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2633         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2634         .clkdm_name     = "per_clkdm",
2635         .recalc         = &followparent_recalc,
2636 };
2637
2638 static struct clk gpio3_dbck = {
2639         .name           = "gpio3_dbck",
2640         .ops            = &clkops_omap2_dflt_wait,
2641         .parent         = &per_32k_alwon_fck,
2642         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2643         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2644         .clkdm_name     = "per_clkdm",
2645         .recalc         = &followparent_recalc,
2646 };
2647
2648 static struct clk gpio2_dbck = {
2649         .name           = "gpio2_dbck",
2650         .ops            = &clkops_omap2_dflt_wait,
2651         .parent         = &per_32k_alwon_fck,
2652         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2653         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2654         .clkdm_name     = "per_clkdm",
2655         .recalc         = &followparent_recalc,
2656 };
2657
2658 static struct clk wdt3_fck = {
2659         .name           = "wdt3_fck",
2660         .ops            = &clkops_omap2_dflt_wait,
2661         .parent         = &per_32k_alwon_fck,
2662         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2663         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2664         .clkdm_name     = "per_clkdm",
2665         .recalc         = &followparent_recalc,
2666 };
2667
2668 static struct clk per_l4_ick = {
2669         .name           = "per_l4_ick",
2670         .ops            = &clkops_null,
2671         .parent         = &l4_ick,
2672         .flags          = RATE_PROPAGATES,
2673         .clkdm_name     = "per_clkdm",
2674         .recalc         = &followparent_recalc,
2675 };
2676
2677 static struct clk gpio6_ick = {
2678         .name           = "gpio6_ick",
2679         .ops            = &clkops_omap2_dflt_wait,
2680         .parent         = &per_l4_ick,
2681         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2682         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2683         .clkdm_name     = "per_clkdm",
2684         .recalc         = &followparent_recalc,
2685 };
2686
2687 static struct clk gpio5_ick = {
2688         .name           = "gpio5_ick",
2689         .ops            = &clkops_omap2_dflt_wait,
2690         .parent         = &per_l4_ick,
2691         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2692         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2693         .clkdm_name     = "per_clkdm",
2694         .recalc         = &followparent_recalc,
2695 };
2696
2697 static struct clk gpio4_ick = {
2698         .name           = "gpio4_ick",
2699         .ops            = &clkops_omap2_dflt_wait,
2700         .parent         = &per_l4_ick,
2701         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2702         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2703         .clkdm_name     = "per_clkdm",
2704         .recalc         = &followparent_recalc,
2705 };
2706
2707 static struct clk gpio3_ick = {
2708         .name           = "gpio3_ick",
2709         .ops            = &clkops_omap2_dflt_wait,
2710         .parent         = &per_l4_ick,
2711         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2712         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2713         .clkdm_name     = "per_clkdm",
2714         .recalc         = &followparent_recalc,
2715 };
2716
2717 static struct clk gpio2_ick = {
2718         .name           = "gpio2_ick",
2719         .ops            = &clkops_omap2_dflt_wait,
2720         .parent         = &per_l4_ick,
2721         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2722         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2723         .clkdm_name     = "per_clkdm",
2724         .recalc         = &followparent_recalc,
2725 };
2726
2727 static struct clk wdt3_ick = {
2728         .name           = "wdt3_ick",
2729         .ops            = &clkops_omap2_dflt_wait,
2730         .parent         = &per_l4_ick,
2731         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2732         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2733         .clkdm_name     = "per_clkdm",
2734         .recalc         = &followparent_recalc,
2735 };
2736
2737 static struct clk uart3_ick = {
2738         .name           = "uart3_ick",
2739         .ops            = &clkops_omap2_dflt_wait,
2740         .parent         = &per_l4_ick,
2741         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2742         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2743         .clkdm_name     = "per_clkdm",
2744         .recalc         = &followparent_recalc,
2745 };
2746
2747 static struct clk gpt9_ick = {
2748         .name           = "gpt9_ick",
2749         .ops            = &clkops_omap2_dflt_wait,
2750         .parent         = &per_l4_ick,
2751         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2752         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2753         .clkdm_name     = "per_clkdm",
2754         .recalc         = &followparent_recalc,
2755 };
2756
2757 static struct clk gpt8_ick = {
2758         .name           = "gpt8_ick",
2759         .ops            = &clkops_omap2_dflt_wait,
2760         .parent         = &per_l4_ick,
2761         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2762         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2763         .clkdm_name     = "per_clkdm",
2764         .recalc         = &followparent_recalc,
2765 };
2766
2767 static struct clk gpt7_ick = {
2768         .name           = "gpt7_ick",
2769         .ops            = &clkops_omap2_dflt_wait,
2770         .parent         = &per_l4_ick,
2771         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2772         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2773         .clkdm_name     = "per_clkdm",
2774         .recalc         = &followparent_recalc,
2775 };
2776
2777 static struct clk gpt6_ick = {
2778         .name           = "gpt6_ick",
2779         .ops            = &clkops_omap2_dflt_wait,
2780         .parent         = &per_l4_ick,
2781         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2782         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2783         .clkdm_name     = "per_clkdm",
2784         .recalc         = &followparent_recalc,
2785 };
2786
2787 static struct clk gpt5_ick = {
2788         .name           = "gpt5_ick",
2789         .ops            = &clkops_omap2_dflt_wait,
2790         .parent         = &per_l4_ick,
2791         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2792         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2793         .clkdm_name     = "per_clkdm",
2794         .recalc         = &followparent_recalc,
2795 };
2796
2797 static struct clk gpt4_ick = {
2798         .name           = "gpt4_ick",
2799         .ops            = &clkops_omap2_dflt_wait,
2800         .parent         = &per_l4_ick,
2801         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2802         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2803         .clkdm_name     = "per_clkdm",
2804         .recalc         = &followparent_recalc,
2805 };
2806
2807 static struct clk gpt3_ick = {
2808         .name           = "gpt3_ick",
2809         .ops            = &clkops_omap2_dflt_wait,
2810         .parent         = &per_l4_ick,
2811         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2812         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2813         .clkdm_name     = "per_clkdm",
2814         .recalc         = &followparent_recalc,
2815 };
2816
2817 static struct clk gpt2_ick = {
2818         .name           = "gpt2_ick",
2819         .ops            = &clkops_omap2_dflt_wait,
2820         .parent         = &per_l4_ick,
2821         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2822         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2823         .clkdm_name     = "per_clkdm",
2824         .recalc         = &followparent_recalc,
2825 };
2826
2827 static struct clk mcbsp2_ick = {
2828         .name           = "mcbsp_ick",
2829         .ops            = &clkops_omap2_dflt_wait,
2830         .id             = 2,
2831         .parent         = &per_l4_ick,
2832         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2833         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2834         .clkdm_name     = "per_clkdm",
2835         .recalc         = &followparent_recalc,
2836 };
2837
2838 static struct clk mcbsp3_ick = {
2839         .name           = "mcbsp_ick",
2840         .ops            = &clkops_omap2_dflt_wait,
2841         .id             = 3,
2842         .parent         = &per_l4_ick,
2843         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2844         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2845         .clkdm_name     = "per_clkdm",
2846         .recalc         = &followparent_recalc,
2847 };
2848
2849 static struct clk mcbsp4_ick = {
2850         .name           = "mcbsp_ick",
2851         .ops            = &clkops_omap2_dflt_wait,
2852         .id             = 4,
2853         .parent         = &per_l4_ick,
2854         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2855         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2856         .clkdm_name     = "per_clkdm",
2857         .recalc         = &followparent_recalc,
2858 };
2859
2860 static const struct clksel mcbsp_234_clksel[] = {
2861         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2862         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2863         { .parent = NULL }
2864 };
2865
2866 static struct clk mcbsp2_fck = {
2867         .name           = "mcbsp_fck",
2868         .ops            = &clkops_omap2_dflt_wait,
2869         .id             = 2,
2870         .init           = &omap2_init_clksel_parent,
2871         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2872         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2873         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2874         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2875         .clksel         = mcbsp_234_clksel,
2876         .clkdm_name     = "per_clkdm",
2877         .recalc         = &omap2_clksel_recalc,
2878 };
2879
2880 static struct clk mcbsp3_fck = {
2881         .name           = "mcbsp_fck",
2882         .ops            = &clkops_omap2_dflt_wait,
2883         .id             = 3,
2884         .init           = &omap2_init_clksel_parent,
2885         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2886         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2887         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2888         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2889         .clksel         = mcbsp_234_clksel,
2890         .clkdm_name     = "per_clkdm",
2891         .recalc         = &omap2_clksel_recalc,
2892 };
2893
2894 static struct clk mcbsp4_fck = {
2895         .name           = "mcbsp_fck",
2896         .ops            = &clkops_omap2_dflt_wait,
2897         .id             = 4,
2898         .init           = &omap2_init_clksel_parent,
2899         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2900         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2901         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2902         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2903         .clksel         = mcbsp_234_clksel,
2904         .clkdm_name     = "per_clkdm",
2905         .recalc         = &omap2_clksel_recalc,
2906 };
2907
2908 /* EMU clocks */
2909
2910 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2911
2912 static const struct clksel_rate emu_src_sys_rates[] = {
2913         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2914         { .div = 0 },
2915 };
2916
2917 static const struct clksel_rate emu_src_core_rates[] = {
2918         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2919         { .div = 0 },
2920 };
2921
2922 static const struct clksel_rate emu_src_per_rates[] = {
2923         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2924         { .div = 0 },
2925 };
2926
2927 static const struct clksel_rate emu_src_mpu_rates[] = {
2928         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2929         { .div = 0 },
2930 };
2931
2932 static const struct clksel emu_src_clksel[] = {
2933         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2934         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2935         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2936         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2937         { .parent = NULL },
2938 };
2939
2940 /*
2941  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2942  * to switch the source of some of the EMU clocks.
2943  * XXX Are there CLKEN bits for these EMU clks?
2944  */
2945 static struct clk emu_src_ck = {
2946         .name           = "emu_src_ck",
2947         .ops            = &clkops_null,
2948         .init           = &omap2_init_clksel_parent,
2949         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2950         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2951         .clksel         = emu_src_clksel,
2952         .flags          = RATE_PROPAGATES,
2953         .clkdm_name     = "emu_clkdm",
2954         .recalc         = &omap2_clksel_recalc,
2955 };
2956
2957 static const struct clksel_rate pclk_emu_rates[] = {
2958         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2959         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2960         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2961         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2962         { .div = 0 },
2963 };
2964
2965 static const struct clksel pclk_emu_clksel[] = {
2966         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2967         { .parent = NULL },
2968 };
2969
2970 static struct clk pclk_fck = {
2971         .name           = "pclk_fck",
2972         .ops            = &clkops_null,
2973         .init           = &omap2_init_clksel_parent,
2974         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2975         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2976         .clksel         = pclk_emu_clksel,
2977         .flags          = RATE_PROPAGATES,
2978         .clkdm_name     = "emu_clkdm",
2979         .recalc         = &omap2_clksel_recalc,
2980 };
2981
2982 static const struct clksel_rate pclkx2_emu_rates[] = {
2983         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2984         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2985         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2986         { .div = 0 },
2987 };
2988
2989 static const struct clksel pclkx2_emu_clksel[] = {
2990         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2991         { .parent = NULL },
2992 };
2993
2994 static struct clk pclkx2_fck = {
2995         .name           = "pclkx2_fck",
2996         .ops            = &clkops_null,
2997         .init           = &omap2_init_clksel_parent,
2998         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2999         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
3000         .clksel         = pclkx2_emu_clksel,
3001         .flags          = RATE_PROPAGATES,
3002         .clkdm_name     = "emu_clkdm",
3003         .recalc         = &omap2_clksel_recalc,
3004 };
3005
3006 static const struct clksel atclk_emu_clksel[] = {
3007         { .parent = &emu_src_ck, .rates = div2_rates },
3008         { .parent = NULL },
3009 };
3010
3011 static struct clk atclk_fck = {
3012         .name           = "atclk_fck",
3013         .ops            = &clkops_null,
3014         .init           = &omap2_init_clksel_parent,
3015         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3016         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
3017         .clksel         = atclk_emu_clksel,
3018         .flags          = RATE_PROPAGATES,
3019         .clkdm_name     = "emu_clkdm",
3020         .recalc         = &omap2_clksel_recalc,
3021 };
3022
3023 static struct clk traceclk_src_fck = {
3024         .name           = "traceclk_src_fck",
3025         .ops            = &clkops_null,
3026         .init           = &omap2_init_clksel_parent,
3027         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3028         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
3029         .clksel         = emu_src_clksel,
3030         .flags          = RATE_PROPAGATES,
3031         .clkdm_name     = "emu_clkdm",
3032         .recalc         = &omap2_clksel_recalc,
3033 };
3034
3035 static const struct clksel_rate traceclk_rates[] = {
3036         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3037         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3038         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3039         { .div = 0 },
3040 };
3041
3042 static const struct clksel traceclk_clksel[] = {
3043         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3044         { .parent = NULL },
3045 };
3046
3047 static struct clk traceclk_fck = {
3048         .name           = "traceclk_fck",
3049         .ops            = &clkops_null,
3050         .init           = &omap2_init_clksel_parent,
3051         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3052         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3053         .clksel         = traceclk_clksel,
3054         .clkdm_name     = "emu_clkdm",
3055         .recalc         = &omap2_clksel_recalc,
3056 };
3057
3058 /* SR clocks */
3059
3060 /* SmartReflex fclk (VDD1) */
3061 static struct clk sr1_fck = {
3062         .name           = "sr1_fck",
3063         .ops            = &clkops_omap2_dflt_wait,
3064         .parent         = &sys_ck,
3065         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3066         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3067         .flags          = RATE_PROPAGATES,
3068         .recalc         = &followparent_recalc,
3069 };
3070
3071 /* SmartReflex fclk (VDD2) */
3072 static struct clk sr2_fck = {
3073         .name           = "sr2_fck",
3074         .ops            = &clkops_omap2_dflt_wait,
3075         .parent         = &sys_ck,
3076         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3077         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3078         .flags          = RATE_PROPAGATES,
3079         .recalc         = &followparent_recalc,
3080 };
3081
3082 static struct clk sr_l4_ick = {
3083         .name           = "sr_l4_ick",
3084         .ops            = &clkops_null, /* RMK: missing? */
3085         .parent         = &l4_ick,
3086         .clkdm_name     = "core_l4_clkdm",
3087         .recalc         = &followparent_recalc,
3088 };
3089
3090 /* SECURE_32K_FCK clocks */
3091
3092 /* XXX This clock no longer exists in 3430 TRM rev F */
3093 static struct clk gpt12_fck = {
3094         .name           = "gpt12_fck",
3095         .ops            = &clkops_null,
3096         .parent         = &secure_32k_fck,
3097         .recalc         = &followparent_recalc,
3098 };
3099
3100 static struct clk wdt1_fck = {
3101         .name           = "wdt1_fck",
3102         .ops            = &clkops_null,
3103         .parent         = &secure_32k_fck,
3104         .recalc         = &followparent_recalc,
3105 };
3106
3107 #endif