arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35
  36 /* Maximum DPLL multiplier, divider values for OMAP3 */
  37 #define OMAP3_MAX_DPLL_MULT             2048
  38 #define OMAP3_MAX_DPLL_DIV              128
  39
  40 /*
  41  * DPLL1 supplies clock to the MPU.
  42  * DPLL2 supplies clock to the IVA2.
  43  * DPLL3 supplies CORE domain clocks.
  44  * DPLL4 supplies peripheral clocks.
  45  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  46  */
  47
  48 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  49 #define DPLL_LOW_POWER_STOP             0x1
  50 #define DPLL_LOW_POWER_BYPASS           0x5
  51 #define DPLL_LOCKED                     0x7
  52
  53 /* PRM CLOCKS */
  54
  55 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  56 static struct clk omap_32k_fck = {
  57         .name           = "omap_32k_fck",
  58         .ops            = &clkops_null,
  59         .rate           = 32768,
  60         .flags          = RATE_FIXED | RATE_PROPAGATES,
  61 };
  62
  63 static struct clk secure_32k_fck = {
  64         .name           = "secure_32k_fck",
  65         .ops            = &clkops_null,
  66         .rate           = 32768,
  67         .flags          = RATE_FIXED | RATE_PROPAGATES,
  68 };
  69
  70 /* Virtual source clocks for osc_sys_ck */
  71 static struct clk virt_12m_ck = {
  72         .name           = "virt_12m_ck",
  73         .ops            = &clkops_null,
  74         .rate           = 12000000,
  75         .flags          = RATE_FIXED | RATE_PROPAGATES,
  76 };
  77
  78 static struct clk virt_13m_ck = {
  79         .name           = "virt_13m_ck",
  80         .ops            = &clkops_null,
  81         .rate           = 13000000,
  82         .flags          = RATE_FIXED | RATE_PROPAGATES,
  83 };
  84
  85 static struct clk virt_16_8m_ck = {
  86         .name           = "virt_16_8m_ck",
  87         .ops            = &clkops_null,
  88         .rate           = 16800000,
  89         .flags          = RATE_FIXED | RATE_PROPAGATES,
  90 };
  91
  92 static struct clk virt_19_2m_ck = {
  93         .name           = "virt_19_2m_ck",
  94         .ops            = &clkops_null,
  95         .rate           = 19200000,
  96         .flags          = RATE_FIXED | RATE_PROPAGATES,
  97 };
  98
  99 static struct clk virt_26m_ck = {
 100         .name           = "virt_26m_ck",
 101         .ops            = &clkops_null,
 102         .rate           = 26000000,
 103         .flags          = RATE_FIXED | RATE_PROPAGATES,
 104 };
 105
 106 static struct clk virt_38_4m_ck = {
 107         .name           = "virt_38_4m_ck",
 108         .ops            = &clkops_null,
 109         .rate           = 38400000,
 110         .flags          = RATE_FIXED | RATE_PROPAGATES,
 111 };
 112
 113 static const struct clksel_rate osc_sys_12m_rates[] = {
 114         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 115         { .div = 0 }
 116 };
 117
 118 static const struct clksel_rate osc_sys_13m_rates[] = {
 119         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 120         { .div = 0 }
 121 };
 122
 123 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 124         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 125         { .div = 0 }
 126 };
 127
 128 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 129         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 130         { .div = 0 }
 131 };
 132
 133 static const struct clksel_rate osc_sys_26m_rates[] = {
 134         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 135         { .div = 0 }
 136 };
 137
 138 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 139         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 140         { .div = 0 }
 141 };
 142
 143 static const struct clksel osc_sys_clksel[] = {
 144         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 145         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 146         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 147         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 148         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 149         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 150         { .parent = NULL },
 151 };
 152
 153 /* Oscillator clock */
 154 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 155 static struct clk osc_sys_ck = {
 156         .name           = "osc_sys_ck",
 157         .ops            = &clkops_null,
 158         .init           = &omap2_init_clksel_parent,
 159         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 160         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 161         .clksel         = osc_sys_clksel,
 162         /* REVISIT: deal with autoextclkmode? */
 163         .flags          = RATE_FIXED | RATE_PROPAGATES,
 164         .recalc         = &omap2_clksel_recalc,
 165 };
 166
 167 static const struct clksel_rate div2_rates[] = {
 168         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 169         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 170         { .div = 0 }
 171 };
 172
 173 static const struct clksel sys_clksel[] = {
 174         { .parent = &osc_sys_ck, .rates = div2_rates },
 175         { .parent = NULL }
 176 };
 177
 178 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 179 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 180 static struct clk sys_ck = {
 181         .name           = "sys_ck",
 182         .ops            = &clkops_null,
 183         .parent         = &osc_sys_ck,
 184         .init           = &omap2_init_clksel_parent,
 185         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 186         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 187         .clksel         = sys_clksel,
 188         .flags          = RATE_PROPAGATES,
 189         .recalc         = &omap2_clksel_recalc,
 190 };
 191
 192 static struct clk sys_altclk = {
 193         .name           = "sys_altclk",
 194         .ops            = &clkops_null,
 195         .flags          = RATE_PROPAGATES,
 196 };
 197
 198 /* Optional external clock input for some McBSPs */
 199 static struct clk mcbsp_clks = {
 200         .name           = "mcbsp_clks",
 201         .ops            = &clkops_null,
 202         .flags          = RATE_PROPAGATES,
 203 };
 204
 205 /* PRM EXTERNAL CLOCK OUTPUT */
 206
 207 static struct clk sys_clkout1 = {
 208         .name           = "sys_clkout1",
 209         .ops            = &clkops_omap2_dflt,
 210         .parent         = &osc_sys_ck,
 211         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 212         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 213         .recalc         = &followparent_recalc,
 214 };
 215
 216 /* DPLLS */
 217
 218 /* CM CLOCKS */
 219
 220 static const struct clksel_rate dpll_bypass_rates[] = {
 221         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 222         { .div = 0 }
 223 };
 224
 225 static const struct clksel_rate dpll_locked_rates[] = {
 226         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 227         { .div = 0 }
 228 };
 229
 230 static const struct clksel_rate div16_dpll_rates[] = {
 231         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 232         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 233         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 234         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 235         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 236         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 237         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 238         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 239         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 240         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 241         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 242         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 243         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 244         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 245         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 246         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 247         { .div = 0 }
 248 };
 249
 250 /* DPLL1 */
 251 /* MPU clock source */
 252 /* Type: DPLL */
 253 static struct dpll_data dpll1_dd = {
 254         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 255         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 256         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 257         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 258         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 259         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 260         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 261         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 262         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 263         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 264         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 265         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 266         .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
 267         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 268         .max_divider    = OMAP3_MAX_DPLL_DIV,
 269         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 270 };
 271
 272 static struct clk dpll1_ck = {
 273         .name           = "dpll1_ck",
 274         .ops            = &clkops_null,
 275         .parent         = &sys_ck,
 276         .dpll_data      = &dpll1_dd,
 277         .flags          = RATE_PROPAGATES,
 278         .round_rate     = &omap2_dpll_round_rate,
 279         .recalc         = &omap3_dpll_recalc,
 280 };
 281
 282 /*
 283  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 284  * DPLL isn't bypassed.
 285  */
 286 static struct clk dpll1_x2_ck = {
 287         .name           = "dpll1_x2_ck",
 288         .ops            = &clkops_null,
 289         .parent         = &dpll1_ck,
 290         .flags          = RATE_PROPAGATES,
 291         .recalc         = &omap3_clkoutx2_recalc,
 292 };
 293
 294 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 295 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 296         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 297         { .parent = NULL }
 298 };
 299
 300 /*
 301  * Does not exist in the TRM - needed to separate the M2 divider from
 302  * bypass selection in mpu_ck
 303  */
 304 static struct clk dpll1_x2m2_ck = {
 305         .name           = "dpll1_x2m2_ck",
 306         .ops            = &clkops_null,
 307         .parent         = &dpll1_x2_ck,
 308         .init           = &omap2_init_clksel_parent,
 309         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 310         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 311         .clksel         = div16_dpll1_x2m2_clksel,
 312         .flags          = RATE_PROPAGATES,
 313         .recalc         = &omap2_clksel_recalc,
 314 };
 315
 316 /* DPLL2 */
 317 /* IVA2 clock source */
 318 /* Type: DPLL */
 319
 320 static struct dpll_data dpll2_dd = {
 321         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 322         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 323         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 324         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 325         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 326         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 327                                 (1 << DPLL_LOW_POWER_BYPASS),
 328         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 329         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 330         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 331         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 332         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 333         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 334         .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
 335         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 336         .max_divider    = OMAP3_MAX_DPLL_DIV,
 337         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 338 };
 339
 340 static struct clk dpll2_ck = {
 341         .name           = "dpll2_ck",
 342         .ops            = &clkops_noncore_dpll_ops,
 343         .parent         = &sys_ck,
 344         .dpll_data      = &dpll2_dd,
 345         .flags          = RATE_PROPAGATES,
 346         .round_rate     = &omap2_dpll_round_rate,
 347         .recalc         = &omap3_dpll_recalc,
 348 };
 349
 350 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 351         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 352         { .parent = NULL }
 353 };
 354
 355 /*
 356  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 357  * or CLKOUTX2. CLKOUT seems most plausible.
 358  */
 359 static struct clk dpll2_m2_ck = {
 360         .name           = "dpll2_m2_ck",
 361         .ops            = &clkops_null,
 362         .parent         = &dpll2_ck,
 363         .init           = &omap2_init_clksel_parent,
 364         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 365                                           OMAP3430_CM_CLKSEL2_PLL),
 366         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 367         .clksel         = div16_dpll2_m2x2_clksel,
 368         .flags          = RATE_PROPAGATES,
 369         .recalc         = &omap2_clksel_recalc,
 370 };
 371
 372 /*
 373  * DPLL3
 374  * Source clock for all interfaces and for some device fclks
 375  * REVISIT: Also supports fast relock bypass - not included below
 376  */
 377 static struct dpll_data dpll3_dd = {
 378         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 379         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 380         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 381         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 382         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 383         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 384         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 385         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 386         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 387         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 388         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 389         .max_divider    = OMAP3_MAX_DPLL_DIV,
 390         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 391 };
 392
 393 static struct clk dpll3_ck = {
 394         .name           = "dpll3_ck",
 395         .ops            = &clkops_null,
 396         .parent         = &sys_ck,
 397         .dpll_data      = &dpll3_dd,
 398         .flags          = RATE_PROPAGATES,
 399         .round_rate     = &omap2_dpll_round_rate,
 400         .recalc         = &omap3_dpll_recalc,
 401 };
 402
 403 /*
 404  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 405  * DPLL isn't bypassed
 406  */
 407 static struct clk dpll3_x2_ck = {
 408         .name           = "dpll3_x2_ck",
 409         .ops            = &clkops_null,
 410         .parent         = &dpll3_ck,
 411         .flags          = RATE_PROPAGATES,
 412         .recalc         = &omap3_clkoutx2_recalc,
 413 };
 414
 415 static const struct clksel_rate div31_dpll3_rates[] = {
 416         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 417         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 418         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 419         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 420         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 421         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 422         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 423         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 424         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 425         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 426         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 427         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 428         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 429         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 430         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 431         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 432         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 433         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 434         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 435         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 436         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 437         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 438         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 439         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 440         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 441         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 442         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 443         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 444         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 445         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 446         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 447         { .div = 0 },
 448 };
 449
 450 static const struct clksel div31_dpll3m2_clksel[] = {
 451         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 452         { .parent = NULL }
 453 };
 454
 455 /*
 456  * DPLL3 output M2
 457  * REVISIT: This DPLL output divider must be changed in SRAM, so until
 458  * that code is ready, this should remain a 'read-only' clksel clock.
 459  */
 460 static struct clk dpll3_m2_ck = {
 461         .name           = "dpll3_m2_ck",
 462         .ops            = &clkops_null,
 463         .parent         = &dpll3_ck,
 464         .init           = &omap2_init_clksel_parent,
 465         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 466         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 467         .clksel         = div31_dpll3m2_clksel,
 468         .flags          = RATE_PROPAGATES,
 469         .recalc         = &omap2_clksel_recalc,
 470 };
 471
 472 static const struct clksel core_ck_clksel[] = {
 473         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 474         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 475         { .parent = NULL }
 476 };
 477
 478 static struct clk core_ck = {
 479         .name           = "core_ck",
 480         .ops            = &clkops_null,
 481         .init           = &omap2_init_clksel_parent,
 482         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 483         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 484         .clksel         = core_ck_clksel,
 485         .flags          = RATE_PROPAGATES,
 486         .recalc         = &omap2_clksel_recalc,
 487 };
 488
 489 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 490         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 491         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 492         { .parent = NULL }
 493 };
 494
 495 static struct clk dpll3_m2x2_ck = {
 496         .name           = "dpll3_m2x2_ck",
 497         .ops            = &clkops_null,
 498         .init           = &omap2_init_clksel_parent,
 499         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 500         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 501         .clksel         = dpll3_m2x2_ck_clksel,
 502         .flags          = RATE_PROPAGATES,
 503         .recalc         = &omap2_clksel_recalc,
 504 };
 505
 506 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 507 static const struct clksel div16_dpll3_clksel[] = {
 508         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 509         { .parent = NULL }
 510 };
 511
 512 /* This virtual clock is the source for dpll3_m3x2_ck */
 513 static struct clk dpll3_m3_ck = {
 514         .name           = "dpll3_m3_ck",
 515         .ops            = &clkops_null,
 516         .parent         = &dpll3_ck,
 517         .init           = &omap2_init_clksel_parent,
 518         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 519         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 520         .clksel         = div16_dpll3_clksel,
 521         .flags          = RATE_PROPAGATES,
 522         .recalc         = &omap2_clksel_recalc,
 523 };
 524
 525 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 526 static struct clk dpll3_m3x2_ck = {
 527         .name           = "dpll3_m3x2_ck",
 528         .ops            = &clkops_omap2_dflt_wait,
 529         .parent         = &dpll3_m3_ck,
 530         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 531         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 532         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 533         .recalc         = &omap3_clkoutx2_recalc,
 534 };
 535
 536 static const struct clksel emu_core_alwon_ck_clksel[] = {
 537         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 538         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 539         { .parent = NULL }
 540 };
 541
 542 static struct clk emu_core_alwon_ck = {
 543         .name           = "emu_core_alwon_ck",
 544         .ops            = &clkops_null,
 545         .parent         = &dpll3_m3x2_ck,
 546         .init           = &omap2_init_clksel_parent,
 547         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 548         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 549         .clksel         = emu_core_alwon_ck_clksel,
 550         .flags          = RATE_PROPAGATES,
 551         .recalc         = &omap2_clksel_recalc,
 552 };
 553
 554 /* DPLL4 */
 555 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 556 /* Type: DPLL */
 557 static struct dpll_data dpll4_dd = {
 558         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 559         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 560         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 561         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 562         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 563         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 564         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 565         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 566         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 567         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 568         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 569         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 570         .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
 571         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 572         .max_divider    = OMAP3_MAX_DPLL_DIV,
 573         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 574 };
 575
 576 static struct clk dpll4_ck = {
 577         .name           = "dpll4_ck",
 578         .ops            = &clkops_noncore_dpll_ops,
 579         .parent         = &sys_ck,
 580         .dpll_data      = &dpll4_dd,
 581         .flags          = RATE_PROPAGATES,
 582         .round_rate     = &omap2_dpll_round_rate,
 583         .recalc         = &omap3_dpll_recalc,
 584 };
 585
 586 /*
 587  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 588  * DPLL isn't bypassed --
 589  * XXX does this serve any downstream clocks?
 590  */
 591 static struct clk dpll4_x2_ck = {
 592         .name           = "dpll4_x2_ck",
 593         .ops            = &clkops_null,
 594         .parent         = &dpll4_ck,
 595         .flags          = RATE_PROPAGATES,
 596         .recalc         = &omap3_clkoutx2_recalc,
 597 };
 598
 599 static const struct clksel div16_dpll4_clksel[] = {
 600         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 601         { .parent = NULL }
 602 };
 603
 604 /* This virtual clock is the source for dpll4_m2x2_ck */
 605 static struct clk dpll4_m2_ck = {
 606         .name           = "dpll4_m2_ck",
 607         .ops            = &clkops_null,
 608         .parent         = &dpll4_ck,
 609         .init           = &omap2_init_clksel_parent,
 610         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 611         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 612         .clksel         = div16_dpll4_clksel,
 613         .flags          = RATE_PROPAGATES,
 614         .recalc         = &omap2_clksel_recalc,
 615 };
 616
 617 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 618 static struct clk dpll4_m2x2_ck = {
 619         .name           = "dpll4_m2x2_ck",
 620         .ops            = &clkops_omap2_dflt_wait,
 621         .parent         = &dpll4_m2_ck,
 622         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 623         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 624         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 625         .recalc         = &omap3_clkoutx2_recalc,
 626 };
 627
 628 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 629         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 630         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 631         { .parent = NULL }
 632 };
 633
 634 static struct clk omap_96m_alwon_fck = {
 635         .name           = "omap_96m_alwon_fck",
 636         .ops            = &clkops_null,
 637         .parent         = &dpll4_m2x2_ck,
 638         .init           = &omap2_init_clksel_parent,
 639         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 640         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 641         .clksel         = omap_96m_alwon_fck_clksel,
 642         .flags          = RATE_PROPAGATES,
 643         .recalc         = &omap2_clksel_recalc,
 644 };
 645
 646 static struct clk omap_96m_fck = {
 647         .name           = "omap_96m_fck",
 648         .ops            = &clkops_null,
 649         .parent         = &omap_96m_alwon_fck,
 650         .flags          = RATE_PROPAGATES,
 651         .recalc         = &followparent_recalc,
 652 };
 653
 654 static const struct clksel cm_96m_fck_clksel[] = {
 655         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 656         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 657         { .parent = NULL }
 658 };
 659
 660 static struct clk cm_96m_fck = {
 661         .name           = "cm_96m_fck",
 662         .ops            = &clkops_null,
 663         .parent         = &dpll4_m2x2_ck,
 664         .init           = &omap2_init_clksel_parent,
 665         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 666         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 667         .clksel         = cm_96m_fck_clksel,
 668         .flags          = RATE_PROPAGATES,
 669         .recalc         = &omap2_clksel_recalc,
 670 };
 671
 672 /* This virtual clock is the source for dpll4_m3x2_ck */
 673 static struct clk dpll4_m3_ck = {
 674         .name           = "dpll4_m3_ck",
 675         .ops            = &clkops_null,
 676         .parent         = &dpll4_ck,
 677         .init           = &omap2_init_clksel_parent,
 678         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 679         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 680         .clksel         = div16_dpll4_clksel,
 681         .flags          = RATE_PROPAGATES,
 682         .recalc         = &omap2_clksel_recalc,
 683 };
 684
 685 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 686 static struct clk dpll4_m3x2_ck = {
 687         .name           = "dpll4_m3x2_ck",
 688         .ops            = &clkops_omap2_dflt_wait,
 689         .parent         = &dpll4_m3_ck,
 690         .init           = &omap2_init_clksel_parent,
 691         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 692         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 693         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 694         .recalc         = &omap3_clkoutx2_recalc,
 695 };
 696
 697 static const struct clksel virt_omap_54m_fck_clksel[] = {
 698         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 699         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 700         { .parent = NULL }
 701 };
 702
 703 static struct clk virt_omap_54m_fck = {
 704         .name           = "virt_omap_54m_fck",
 705         .ops            = &clkops_null,
 706         .parent         = &dpll4_m3x2_ck,
 707         .init           = &omap2_init_clksel_parent,
 708         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 709         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 710         .clksel         = virt_omap_54m_fck_clksel,
 711         .flags          = RATE_PROPAGATES,
 712         .recalc         = &omap2_clksel_recalc,
 713 };
 714
 715 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 716         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 717         { .div = 0 }
 718 };
 719
 720 static const struct clksel_rate omap_54m_alt_rates[] = {
 721         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 722         { .div = 0 }
 723 };
 724
 725 static const struct clksel omap_54m_clksel[] = {
 726         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 727         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 728         { .parent = NULL }
 729 };
 730
 731 static struct clk omap_54m_fck = {
 732         .name           = "omap_54m_fck",
 733         .ops            = &clkops_null,
 734         .init           = &omap2_init_clksel_parent,
 735         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 736         .clksel_mask    = OMAP3430_SOURCE_54M,
 737         .clksel         = omap_54m_clksel,
 738         .flags          = RATE_PROPAGATES,
 739         .recalc         = &omap2_clksel_recalc,
 740 };
 741
 742 static const struct clksel_rate omap_48m_96md2_rates[] = {
 743         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 744         { .div = 0 }
 745 };
 746
 747 static const struct clksel_rate omap_48m_alt_rates[] = {
 748         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 749         { .div = 0 }
 750 };
 751
 752 static const struct clksel omap_48m_clksel[] = {
 753         { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
 754         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 755         { .parent = NULL }
 756 };
 757
 758 static struct clk omap_48m_fck = {
 759         .name           = "omap_48m_fck",
 760         .ops            = &clkops_null,
 761         .init           = &omap2_init_clksel_parent,
 762         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 763         .clksel_mask    = OMAP3430_SOURCE_48M,
 764         .clksel         = omap_48m_clksel,
 765         .flags          = RATE_PROPAGATES,
 766         .recalc         = &omap2_clksel_recalc,
 767 };
 768
 769 static struct clk omap_12m_fck = {
 770         .name           = "omap_12m_fck",
 771         .ops            = &clkops_null,
 772         .parent         = &omap_48m_fck,
 773         .fixed_div      = 4,
 774         .flags          = RATE_PROPAGATES,
 775         .recalc         = &omap2_fixed_divisor_recalc,
 776 };
 777
 778 /* This virstual clock is the source for dpll4_m4x2_ck */
 779 static struct clk dpll4_m4_ck = {
 780         .name           = "dpll4_m4_ck",
 781         .ops            = &clkops_null,
 782         .parent         = &dpll4_ck,
 783         .init           = &omap2_init_clksel_parent,
 784         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 785         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 786         .clksel         = div16_dpll4_clksel,
 787         .flags          = RATE_PROPAGATES,
 788         .recalc         = &omap2_clksel_recalc,
 789 };
 790
 791 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 792 static struct clk dpll4_m4x2_ck = {
 793         .name           = "dpll4_m4x2_ck",
 794         .ops            = &clkops_omap2_dflt_wait,
 795         .parent         = &dpll4_m4_ck,
 796         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 797         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 798         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 799         .recalc         = &omap3_clkoutx2_recalc,
 800 };
 801
 802 /* This virtual clock is the source for dpll4_m5x2_ck */
 803 static struct clk dpll4_m5_ck = {
 804         .name           = "dpll4_m5_ck",
 805         .ops            = &clkops_null,
 806         .parent         = &dpll4_ck,
 807         .init           = &omap2_init_clksel_parent,
 808         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 809         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 810         .clksel         = div16_dpll4_clksel,
 811         .flags          = RATE_PROPAGATES,
 812         .recalc         = &omap2_clksel_recalc,
 813 };
 814
 815 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 816 static struct clk dpll4_m5x2_ck = {
 817         .name           = "dpll4_m5x2_ck",
 818         .ops            = &clkops_omap2_dflt_wait,
 819         .parent         = &dpll4_m5_ck,
 820         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 821         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 822         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 823         .recalc         = &omap3_clkoutx2_recalc,
 824 };
 825
 826 /* This virtual clock is the source for dpll4_m6x2_ck */
 827 static struct clk dpll4_m6_ck = {
 828         .name           = "dpll4_m6_ck",
 829         .ops            = &clkops_null,
 830         .parent         = &dpll4_ck,
 831         .init           = &omap2_init_clksel_parent,
 832         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 833         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 834         .clksel         = div16_dpll4_clksel,
 835         .flags          = RATE_PROPAGATES,
 836         .recalc         = &omap2_clksel_recalc,
 837 };
 838
 839 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 840 static struct clk dpll4_m6x2_ck = {
 841         .name           = "dpll4_m6x2_ck",
 842         .ops            = &clkops_omap2_dflt_wait,
 843         .parent         = &dpll4_m6_ck,
 844         .init           = &omap2_init_clksel_parent,
 845         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 846         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 847         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 848         .recalc         = &omap3_clkoutx2_recalc,
 849 };
 850
 851 static struct clk emu_per_alwon_ck = {
 852         .name           = "emu_per_alwon_ck",
 853         .ops            = &clkops_null,
 854         .parent         = &dpll4_m6x2_ck,
 855         .flags          = RATE_PROPAGATES,
 856         .recalc         = &followparent_recalc,
 857 };
 858
 859 /* DPLL5 */
 860 /* Supplies 120MHz clock, USIM source clock */
 861 /* Type: DPLL */
 862 /* 3430ES2 only */
 863 static struct dpll_data dpll5_dd = {
 864         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 865         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 866         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 867         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 868         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 869         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 870         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 871         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 872         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 873         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 874         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 875         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 876         .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
 877         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 878         .max_divider    = OMAP3_MAX_DPLL_DIV,
 879         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 880 };
 881
 882 static struct clk dpll5_ck = {
 883         .name           = "dpll5_ck",
 884         .ops            = &clkops_noncore_dpll_ops,
 885         .parent         = &sys_ck,
 886         .dpll_data      = &dpll5_dd,
 887         .flags          = RATE_PROPAGATES,
 888         .round_rate     = &omap2_dpll_round_rate,
 889         .recalc         = &omap3_dpll_recalc,
 890 };
 891
 892 static const struct clksel div16_dpll5_clksel[] = {
 893         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 894         { .parent = NULL }
 895 };
 896
 897 static struct clk dpll5_m2_ck = {
 898         .name           = "dpll5_m2_ck",
 899         .ops            = &clkops_null,
 900         .parent         = &dpll5_ck,
 901         .init           = &omap2_init_clksel_parent,
 902         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 903         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 904         .clksel         = div16_dpll5_clksel,
 905         .flags          = RATE_PROPAGATES,
 906         .recalc         = &omap2_clksel_recalc,
 907 };
 908
 909 static const struct clksel omap_120m_fck_clksel[] = {
 910         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 911         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
 912         { .parent = NULL }
 913 };
 914
 915 static struct clk omap_120m_fck = {
 916         .name           = "omap_120m_fck",
 917         .ops            = &clkops_null,
 918         .parent         = &dpll5_m2_ck,
 919         .init           = &omap2_init_clksel_parent,
 920         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 921         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 922         .clksel         = omap_120m_fck_clksel,
 923         .flags          = RATE_PROPAGATES,
 924         .recalc         = &omap2_clksel_recalc,
 925 };
 926
 927 /* CM EXTERNAL CLOCK OUTPUTS */
 928
 929 static const struct clksel_rate clkout2_src_core_rates[] = {
 930         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 931         { .div = 0 }
 932 };
 933
 934 static const struct clksel_rate clkout2_src_sys_rates[] = {
 935         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 936         { .div = 0 }
 937 };
 938
 939 static const struct clksel_rate clkout2_src_96m_rates[] = {
 940         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 941         { .div = 0 }
 942 };
 943
 944 static const struct clksel_rate clkout2_src_54m_rates[] = {
 945         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 946         { .div = 0 }
 947 };
 948
 949 static const struct clksel clkout2_src_clksel[] = {
 950         { .parent = &core_ck,             .rates = clkout2_src_core_rates },
 951         { .parent = &sys_ck,              .rates = clkout2_src_sys_rates },
 952         { .parent = &omap_96m_alwon_fck,  .rates = clkout2_src_96m_rates },
 953         { .parent = &omap_54m_fck,        .rates = clkout2_src_54m_rates },
 954         { .parent = NULL }
 955 };
 956
 957 static struct clk clkout2_src_ck = {
 958         .name           = "clkout2_src_ck",
 959         .ops            = &clkops_omap2_dflt,
 960         .init           = &omap2_init_clksel_parent,
 961         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
 962         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 963         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 964         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 965         .clksel         = clkout2_src_clksel,
 966         .flags          = RATE_PROPAGATES,
 967         .recalc         = &omap2_clksel_recalc,
 968 };
 969
 970 static const struct clksel_rate sys_clkout2_rates[] = {
 971         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 972         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 973         { .div = 4, .val = 2, .flags = RATE_IN_343X },
 974         { .div = 8, .val = 3, .flags = RATE_IN_343X },
 975         { .div = 16, .val = 4, .flags = RATE_IN_343X },
 976         { .div = 0 },
 977 };
 978
 979 static const struct clksel sys_clkout2_clksel[] = {
 980         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
 981         { .parent = NULL },
 982 };
 983
 984 static struct clk sys_clkout2 = {
 985         .name           = "sys_clkout2",
 986         .ops            = &clkops_null,
 987         .init           = &omap2_init_clksel_parent,
 988         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 989         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
 990         .clksel         = sys_clkout2_clksel,
 991         .recalc         = &omap2_clksel_recalc,
 992 };
 993
 994 /* CM OUTPUT CLOCKS */
 995
 996 static struct clk corex2_fck = {
 997         .name           = "corex2_fck",
 998         .ops            = &clkops_null,
 999         .parent         = &dpll3_m2x2_ck,
1000         .flags          = RATE_PROPAGATES,
1001         .recalc         = &followparent_recalc,
1002 };
1003
1004 /* DPLL power domain clock controls */
1005
1006 static const struct clksel div2_core_clksel[] = {
1007         { .parent = &core_ck, .rates = div2_rates },
1008         { .parent = NULL }
1009 };
1010
1011 /*
1012  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1013  * may be inconsistent here?
1014  */
1015 static struct clk dpll1_fck = {
1016         .name           = "dpll1_fck",
1017         .ops            = &clkops_null,
1018         .parent         = &core_ck,
1019         .init           = &omap2_init_clksel_parent,
1020         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1021         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1022         .clksel         = div2_core_clksel,
1023         .flags          = RATE_PROPAGATES,
1024         .recalc         = &omap2_clksel_recalc,
1025 };
1026
1027 /*
1028  * MPU clksel:
1029  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1030  * derives from the high-frequency bypass clock originating from DPLL3,
1031  * called 'dpll1_fck'
1032  */
1033 static const struct clksel mpu_clksel[] = {
1034         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1035         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1036         { .parent = NULL }
1037 };
1038
1039 static struct clk mpu_ck = {
1040         .name           = "mpu_ck",
1041         .ops            = &clkops_null,
1042         .parent         = &dpll1_x2m2_ck,
1043         .init           = &omap2_init_clksel_parent,
1044         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1045         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1046         .clksel         = mpu_clksel,
1047         .flags          = RATE_PROPAGATES,
1048         .clkdm_name     = "mpu_clkdm",
1049         .recalc         = &omap2_clksel_recalc,
1050 };
1051
1052 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1053 static const struct clksel_rate arm_fck_rates[] = {
1054         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1055         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1056         { .div = 0 },
1057 };
1058
1059 static const struct clksel arm_fck_clksel[] = {
1060         { .parent = &mpu_ck, .rates = arm_fck_rates },
1061         { .parent = NULL }
1062 };
1063
1064 static struct clk arm_fck = {
1065         .name           = "arm_fck",
1066         .ops            = &clkops_null,
1067         .parent         = &mpu_ck,
1068         .init           = &omap2_init_clksel_parent,
1069         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1070         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1071         .clksel         = arm_fck_clksel,
1072         .flags          = RATE_PROPAGATES,
1073         .recalc         = &omap2_clksel_recalc,
1074 };
1075
1076 /* XXX What about neon_clkdm ? */
1077
1078 /*
1079  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1080  * although it is referenced - so this is a guess
1081  */
1082 static struct clk emu_mpu_alwon_ck = {
1083         .name           = "emu_mpu_alwon_ck",
1084         .ops            = &clkops_null,
1085         .parent         = &mpu_ck,
1086         .flags          = RATE_PROPAGATES,
1087         .recalc         = &followparent_recalc,
1088 };
1089
1090 static struct clk dpll2_fck = {
1091         .name           = "dpll2_fck",
1092         .ops            = &clkops_null,
1093         .parent         = &core_ck,
1094         .init           = &omap2_init_clksel_parent,
1095         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1096         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1097         .clksel         = div2_core_clksel,
1098         .flags          = RATE_PROPAGATES,
1099         .recalc         = &omap2_clksel_recalc,
1100 };
1101
1102 /*
1103  * IVA2 clksel:
1104  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1105  * derives from the high-frequency bypass clock originating from DPLL3,
1106  * called 'dpll2_fck'
1107  */
1108
1109 static const struct clksel iva2_clksel[] = {
1110         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1111         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1112         { .parent = NULL }
1113 };
1114
1115 static struct clk iva2_ck = {
1116         .name           = "iva2_ck",
1117         .ops            = &clkops_omap2_dflt_wait,
1118         .parent         = &dpll2_m2_ck,
1119         .init           = &omap2_init_clksel_parent,
1120         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1121         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1122         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1123                                           OMAP3430_CM_IDLEST_PLL),
1124         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1125         .clksel         = iva2_clksel,
1126         .flags          = RATE_PROPAGATES,
1127         .clkdm_name     = "iva2_clkdm",
1128         .recalc         = &omap2_clksel_recalc,
1129 };
1130
1131 /* Common interface clocks */
1132
1133 static struct clk l3_ick = {
1134         .name           = "l3_ick",
1135         .ops            = &clkops_null,
1136         .parent         = &core_ck,
1137         .init           = &omap2_init_clksel_parent,
1138         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1139         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1140         .clksel         = div2_core_clksel,
1141         .flags          = RATE_PROPAGATES,
1142         .clkdm_name     = "core_l3_clkdm",
1143         .recalc         = &omap2_clksel_recalc,
1144 };
1145
1146 static const struct clksel div2_l3_clksel[] = {
1147         { .parent = &l3_ick, .rates = div2_rates },
1148         { .parent = NULL }
1149 };
1150
1151 static struct clk l4_ick = {
1152         .name           = "l4_ick",
1153         .ops            = &clkops_null,
1154         .parent         = &l3_ick,
1155         .init           = &omap2_init_clksel_parent,
1156         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1157         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1158         .clksel         = div2_l3_clksel,
1159         .flags          = RATE_PROPAGATES,
1160         .clkdm_name     = "core_l4_clkdm",
1161         .recalc         = &omap2_clksel_recalc,
1162
1163 };
1164
1165 static const struct clksel div2_l4_clksel[] = {
1166         { .parent = &l4_ick, .rates = div2_rates },
1167         { .parent = NULL }
1168 };
1169
1170 static struct clk rm_ick = {
1171         .name           = "rm_ick",
1172         .ops            = &clkops_null,
1173         .parent         = &l4_ick,
1174         .init           = &omap2_init_clksel_parent,
1175         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1176         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1177         .clksel         = div2_l4_clksel,
1178         .recalc         = &omap2_clksel_recalc,
1179 };
1180
1181 /* GFX power domain */
1182
1183 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1184
1185 static const struct clksel gfx_l3_clksel[] = {
1186         { .parent = &l3_ick, .rates = gfx_l3_rates },
1187         { .parent = NULL }
1188 };
1189
1190 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1191 static struct clk gfx_l3_ck = {
1192         .name           = "gfx_l3_ck",
1193         .ops            = &clkops_omap2_dflt_wait,
1194         .parent         = &l3_ick,
1195         .init           = &omap2_init_clksel_parent,
1196         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1197         .enable_bit     = OMAP_EN_GFX_SHIFT,
1198         .recalc         = &followparent_recalc,
1199 };
1200
1201 static struct clk gfx_l3_fck = {
1202         .name           = "gfx_l3_fck",
1203         .ops            = &clkops_null,
1204         .parent         = &gfx_l3_ck,
1205         .init           = &omap2_init_clksel_parent,
1206         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1207         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1208         .clksel         = gfx_l3_clksel,
1209         .flags          = RATE_PROPAGATES,
1210         .clkdm_name     = "gfx_3430es1_clkdm",
1211         .recalc         = &omap2_clksel_recalc,
1212 };
1213
1214 static struct clk gfx_l3_ick = {
1215         .name           = "gfx_l3_ick",
1216         .ops            = &clkops_null,
1217         .parent         = &gfx_l3_ck,
1218         .clkdm_name     = "gfx_3430es1_clkdm",
1219         .recalc         = &followparent_recalc,
1220 };
1221
1222 static struct clk gfx_cg1_ck = {
1223         .name           = "gfx_cg1_ck",
1224         .ops            = &clkops_omap2_dflt_wait,
1225         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1226         .init           = &omap2_init_clk_clkdm,
1227         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1228         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1229         .clkdm_name     = "gfx_3430es1_clkdm",
1230         .recalc         = &followparent_recalc,
1231 };
1232
1233 static struct clk gfx_cg2_ck = {
1234         .name           = "gfx_cg2_ck",
1235         .ops            = &clkops_omap2_dflt_wait,
1236         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1237         .init           = &omap2_init_clk_clkdm,
1238         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1239         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1240         .clkdm_name     = "gfx_3430es1_clkdm",
1241         .recalc         = &followparent_recalc,
1242 };
1243
1244 /* SGX power domain - 3430ES2 only */
1245
1246 static const struct clksel_rate sgx_core_rates[] = {
1247         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1248         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1249         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1250         { .div = 0 },
1251 };
1252
1253 static const struct clksel_rate sgx_96m_rates[] = {
1254         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1255         { .div = 0 },
1256 };
1257
1258 static const struct clksel sgx_clksel[] = {
1259         { .parent = &core_ck,    .rates = sgx_core_rates },
1260         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1261         { .parent = NULL },
1262 };
1263
1264 static struct clk sgx_fck = {
1265         .name           = "sgx_fck",
1266         .ops            = &clkops_omap2_dflt_wait,
1267         .init           = &omap2_init_clksel_parent,
1268         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1269         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1270         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1271         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1272         .clksel         = sgx_clksel,
1273         .clkdm_name     = "sgx_clkdm",
1274         .recalc         = &omap2_clksel_recalc,
1275 };
1276
1277 static struct clk sgx_ick = {
1278         .name           = "sgx_ick",
1279         .ops            = &clkops_omap2_dflt_wait,
1280         .parent         = &l3_ick,
1281         .init           = &omap2_init_clk_clkdm,
1282         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1283         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1284         .clkdm_name     = "sgx_clkdm",
1285         .recalc         = &followparent_recalc,
1286 };
1287
1288 /* CORE power domain */
1289
1290 static struct clk d2d_26m_fck = {
1291         .name           = "d2d_26m_fck",
1292         .ops            = &clkops_omap2_dflt_wait,
1293         .parent         = &sys_ck,
1294         .init           = &omap2_init_clk_clkdm,
1295         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1296         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1297         .clkdm_name     = "d2d_clkdm",
1298         .recalc         = &followparent_recalc,
1299 };
1300
1301 static const struct clksel omap343x_gpt_clksel[] = {
1302         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1303         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1304         { .parent = NULL}
1305 };
1306
1307 static struct clk gpt10_fck = {
1308         .name           = "gpt10_fck",
1309         .ops            = &clkops_omap2_dflt_wait,
1310         .parent         = &sys_ck,
1311         .init           = &omap2_init_clksel_parent,
1312         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1313         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1314         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1315         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1316         .clksel         = omap343x_gpt_clksel,
1317         .clkdm_name     = "core_l4_clkdm",
1318         .recalc         = &omap2_clksel_recalc,
1319 };
1320
1321 static struct clk gpt11_fck = {
1322         .name           = "gpt11_fck",
1323         .ops            = &clkops_omap2_dflt_wait,
1324         .parent         = &sys_ck,
1325         .init           = &omap2_init_clksel_parent,
1326         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1327         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1328         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1329         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1330         .clksel         = omap343x_gpt_clksel,
1331         .clkdm_name     = "core_l4_clkdm",
1332         .recalc         = &omap2_clksel_recalc,
1333 };
1334
1335 static struct clk cpefuse_fck = {
1336         .name           = "cpefuse_fck",
1337         .ops            = &clkops_omap2_dflt,
1338         .parent         = &sys_ck,
1339         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1340         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1341         .recalc         = &followparent_recalc,
1342 };
1343
1344 static struct clk ts_fck = {
1345         .name           = "ts_fck",
1346         .ops            = &clkops_omap2_dflt,
1347         .parent         = &omap_32k_fck,
1348         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1349         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1350         .recalc         = &followparent_recalc,
1351 };
1352
1353 static struct clk usbtll_fck = {
1354         .name           = "usbtll_fck",
1355         .ops            = &clkops_omap2_dflt,
1356         .parent         = &omap_120m_fck,
1357         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1358         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1359         .recalc         = &followparent_recalc,
1360 };
1361
1362 /* CORE 96M FCLK-derived clocks */
1363
1364 static struct clk core_96m_fck = {
1365         .name           = "core_96m_fck",
1366         .ops            = &clkops_null,
1367         .parent         = &omap_96m_fck,
1368         .flags          = RATE_PROPAGATES,
1369         .clkdm_name     = "core_l4_clkdm",
1370         .recalc         = &followparent_recalc,
1371 };
1372
1373 static struct clk mmchs3_fck = {
1374         .name           = "mmchs_fck",
1375         .ops            = &clkops_omap2_dflt_wait,
1376         .id             = 2,
1377         .parent         = &core_96m_fck,
1378         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1379         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1380         .clkdm_name     = "core_l4_clkdm",
1381         .recalc         = &followparent_recalc,
1382 };
1383
1384 static struct clk mmchs2_fck = {
1385         .name           = "mmchs_fck",
1386         .ops            = &clkops_omap2_dflt_wait,
1387         .id             = 1,
1388         .parent         = &core_96m_fck,
1389         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1390         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1391         .clkdm_name     = "core_l4_clkdm",
1392         .recalc         = &followparent_recalc,
1393 };
1394
1395 static struct clk mspro_fck = {
1396         .name           = "mspro_fck",
1397         .ops            = &clkops_omap2_dflt_wait,
1398         .parent         = &core_96m_fck,
1399         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1400         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1401         .clkdm_name     = "core_l4_clkdm",
1402         .recalc         = &followparent_recalc,
1403 };
1404
1405 static struct clk mmchs1_fck = {
1406         .name           = "mmchs_fck",
1407         .ops            = &clkops_omap2_dflt_wait,
1408         .parent         = &core_96m_fck,
1409         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1410         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1411         .clkdm_name     = "core_l4_clkdm",
1412         .recalc         = &followparent_recalc,
1413 };
1414
1415 static struct clk i2c3_fck = {
1416         .name           = "i2c_fck",
1417         .ops            = &clkops_omap2_dflt_wait,
1418         .id             = 3,
1419         .parent         = &core_96m_fck,
1420         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1421         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1422         .clkdm_name     = "core_l4_clkdm",
1423         .recalc         = &followparent_recalc,
1424 };
1425
1426 static struct clk i2c2_fck = {
1427         .name           = "i2c_fck",
1428         .ops            = &clkops_omap2_dflt_wait,
1429         .id             = 2,
1430         .parent         = &core_96m_fck,
1431         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1432         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1433         .clkdm_name     = "core_l4_clkdm",
1434         .recalc         = &followparent_recalc,
1435 };
1436
1437 static struct clk i2c1_fck = {
1438         .name           = "i2c_fck",
1439         .ops            = &clkops_omap2_dflt_wait,
1440         .id             = 1,
1441         .parent         = &core_96m_fck,
1442         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1443         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1444         .clkdm_name     = "core_l4_clkdm",
1445         .recalc         = &followparent_recalc,
1446 };
1447
1448 /*
1449  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1450  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1451  */
1452 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1453         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1454         { .div = 0 }
1455 };
1456
1457 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1458         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1459         { .div = 0 }
1460 };
1461
1462 static const struct clksel mcbsp_15_clksel[] = {
1463         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1464         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1465         { .parent = NULL }
1466 };
1467
1468 static struct clk mcbsp5_fck = {
1469         .name           = "mcbsp_fck",
1470         .ops            = &clkops_omap2_dflt_wait,
1471         .id             = 5,
1472         .init           = &omap2_init_clksel_parent,
1473         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1474         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1475         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1476         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1477         .clksel         = mcbsp_15_clksel,
1478         .clkdm_name     = "core_l4_clkdm",
1479         .recalc         = &omap2_clksel_recalc,
1480 };
1481
1482 static struct clk mcbsp1_fck = {
1483         .name           = "mcbsp_fck",
1484         .ops            = &clkops_omap2_dflt_wait,
1485         .id             = 1,
1486         .init           = &omap2_init_clksel_parent,
1487         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1488         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1489         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1490         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1491         .clksel         = mcbsp_15_clksel,
1492         .clkdm_name     = "core_l4_clkdm",
1493         .recalc         = &omap2_clksel_recalc,
1494 };
1495
1496 /* CORE_48M_FCK-derived clocks */
1497
1498 static struct clk core_48m_fck = {
1499         .name           = "core_48m_fck",
1500         .ops            = &clkops_null,
1501         .parent         = &omap_48m_fck,
1502         .flags          = RATE_PROPAGATES,
1503         .clkdm_name     = "core_l4_clkdm",
1504         .recalc         = &followparent_recalc,
1505 };
1506
1507 static struct clk mcspi4_fck = {
1508         .name           = "mcspi_fck",
1509         .ops            = &clkops_omap2_dflt_wait,
1510         .id             = 4,
1511         .parent         = &core_48m_fck,
1512         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1513         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1514         .recalc         = &followparent_recalc,
1515 };
1516
1517 static struct clk mcspi3_fck = {
1518         .name           = "mcspi_fck",
1519         .ops            = &clkops_omap2_dflt_wait,
1520         .id             = 3,
1521         .parent         = &core_48m_fck,
1522         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1523         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1524         .recalc         = &followparent_recalc,
1525 };
1526
1527 static struct clk mcspi2_fck = {
1528         .name           = "mcspi_fck",
1529         .ops            = &clkops_omap2_dflt_wait,
1530         .id             = 2,
1531         .parent         = &core_48m_fck,
1532         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1533         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1534         .recalc         = &followparent_recalc,
1535 };
1536
1537 static struct clk mcspi1_fck = {
1538         .name           = "mcspi_fck",
1539         .ops            = &clkops_omap2_dflt_wait,
1540         .id             = 1,
1541         .parent         = &core_48m_fck,
1542         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1543         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1544         .recalc         = &followparent_recalc,
1545 };
1546
1547 static struct clk uart2_fck = {
1548         .name           = "uart2_fck",
1549         .ops            = &clkops_omap2_dflt_wait,
1550         .parent         = &core_48m_fck,
1551         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1552         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1553         .recalc         = &followparent_recalc,
1554 };
1555
1556 static struct clk uart1_fck = {
1557         .name           = "uart1_fck",
1558         .ops            = &clkops_omap2_dflt_wait,
1559         .parent         = &core_48m_fck,
1560         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1561         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1562         .recalc         = &followparent_recalc,
1563 };
1564
1565 static struct clk fshostusb_fck = {
1566         .name           = "fshostusb_fck",
1567         .ops            = &clkops_omap2_dflt_wait,
1568         .parent         = &core_48m_fck,
1569         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1570         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1571         .recalc         = &followparent_recalc,
1572 };
1573
1574 /* CORE_12M_FCK based clocks */
1575
1576 static struct clk core_12m_fck = {
1577         .name           = "core_12m_fck",
1578         .ops            = &clkops_null,
1579         .parent         = &omap_12m_fck,
1580         .flags          = RATE_PROPAGATES,
1581         .clkdm_name     = "core_l4_clkdm",
1582         .recalc         = &followparent_recalc,
1583 };
1584
1585 static struct clk hdq_fck = {
1586         .name           = "hdq_fck",
1587         .ops            = &clkops_omap2_dflt_wait,
1588         .parent         = &core_12m_fck,
1589         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1590         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1591         .recalc         = &followparent_recalc,
1592 };
1593
1594 /* DPLL3-derived clock */
1595
1596 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1597         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1598         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1599         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1600         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1601         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1602         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1603         { .div = 0 }
1604 };
1605
1606 static const struct clksel ssi_ssr_clksel[] = {
1607         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1608         { .parent = NULL }
1609 };
1610
1611 static struct clk ssi_ssr_fck = {
1612         .name           = "ssi_ssr_fck",
1613         .ops            = &clkops_omap2_dflt,
1614         .init           = &omap2_init_clksel_parent,
1615         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1616         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1617         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1618         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1619         .clksel         = ssi_ssr_clksel,
1620         .flags          = RATE_PROPAGATES,
1621         .clkdm_name     = "core_l4_clkdm",
1622         .recalc         = &omap2_clksel_recalc,
1623 };
1624
1625 static struct clk ssi_sst_fck = {
1626         .name           = "ssi_sst_fck",
1627         .ops            = &clkops_null,
1628         .parent         = &ssi_ssr_fck,
1629         .fixed_div      = 2,
1630         .recalc         = &omap2_fixed_divisor_recalc,
1631 };
1632
1633
1634
1635 /* CORE_L3_ICK based clocks */
1636
1637 /*
1638  * XXX must add clk_enable/clk_disable for these if standard code won't
1639  * handle it
1640  */
1641 static struct clk core_l3_ick = {
1642         .name           = "core_l3_ick",
1643         .ops            = &clkops_null,
1644         .parent         = &l3_ick,
1645         .init           = &omap2_init_clk_clkdm,
1646         .flags          = RATE_PROPAGATES,
1647         .clkdm_name     = "core_l3_clkdm",
1648         .recalc         = &followparent_recalc,
1649 };
1650
1651 static struct clk hsotgusb_ick = {
1652         .name           = "hsotgusb_ick",
1653         .ops            = &clkops_omap2_dflt_wait,
1654         .parent         = &core_l3_ick,
1655         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1656         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1657         .clkdm_name     = "core_l3_clkdm",
1658         .recalc         = &followparent_recalc,
1659 };
1660
1661 static struct clk sdrc_ick = {
1662         .name           = "sdrc_ick",
1663         .ops            = &clkops_omap2_dflt_wait,
1664         .parent         = &core_l3_ick,
1665         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1666         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1667         .flags          = ENABLE_ON_INIT,
1668         .clkdm_name     = "core_l3_clkdm",
1669         .recalc         = &followparent_recalc,
1670 };
1671
1672 static struct clk gpmc_fck = {
1673         .name           = "gpmc_fck",
1674         .ops            = &clkops_null,
1675         .parent         = &core_l3_ick,
1676         .flags          = ENABLE_ON_INIT, /* huh? */
1677         .clkdm_name     = "core_l3_clkdm",
1678         .recalc         = &followparent_recalc,
1679 };
1680
1681 /* SECURITY_L3_ICK based clocks */
1682
1683 static struct clk security_l3_ick = {
1684         .name           = "security_l3_ick",
1685         .ops            = &clkops_null,
1686         .parent         = &l3_ick,
1687         .flags          = RATE_PROPAGATES,
1688         .recalc         = &followparent_recalc,
1689 };
1690
1691 static struct clk pka_ick = {
1692         .name           = "pka_ick",
1693         .ops            = &clkops_omap2_dflt_wait,
1694         .parent         = &security_l3_ick,
1695         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1696         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1697         .recalc         = &followparent_recalc,
1698 };
1699
1700 /* CORE_L4_ICK based clocks */
1701
1702 static struct clk core_l4_ick = {
1703         .name           = "core_l4_ick",
1704         .ops            = &clkops_null,
1705         .parent         = &l4_ick,
1706         .init           = &omap2_init_clk_clkdm,
1707         .flags          = RATE_PROPAGATES,
1708         .clkdm_name     = "core_l4_clkdm",
1709         .recalc         = &followparent_recalc,
1710 };
1711
1712 static struct clk usbtll_ick = {
1713         .name           = "usbtll_ick",
1714         .ops            = &clkops_omap2_dflt_wait,
1715         .parent         = &core_l4_ick,
1716         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1717         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1718         .clkdm_name     = "core_l4_clkdm",
1719         .recalc         = &followparent_recalc,
1720 };
1721
1722 static struct clk mmchs3_ick = {
1723         .name           = "mmchs_ick",
1724         .ops            = &clkops_omap2_dflt_wait,
1725         .id             = 2,
1726         .parent         = &core_l4_ick,
1727         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1728         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1729         .clkdm_name     = "core_l4_clkdm",
1730         .recalc         = &followparent_recalc,
1731 };
1732
1733 /* Intersystem Communication Registers - chassis mode only */
1734 static struct clk icr_ick = {
1735         .name           = "icr_ick",
1736         .ops            = &clkops_omap2_dflt_wait,
1737         .parent         = &core_l4_ick,
1738         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1739         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1740         .clkdm_name     = "core_l4_clkdm",
1741         .recalc         = &followparent_recalc,
1742 };
1743
1744 static struct clk aes2_ick = {
1745         .name           = "aes2_ick",
1746         .ops            = &clkops_omap2_dflt_wait,
1747         .parent         = &core_l4_ick,
1748         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1749         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1750         .clkdm_name     = "core_l4_clkdm",
1751         .recalc         = &followparent_recalc,
1752 };
1753
1754 static struct clk sha12_ick = {
1755         .name           = "sha12_ick",
1756         .ops            = &clkops_omap2_dflt_wait,
1757         .parent         = &core_l4_ick,
1758         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1759         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1760         .clkdm_name     = "core_l4_clkdm",
1761         .recalc         = &followparent_recalc,
1762 };
1763
1764 static struct clk des2_ick = {
1765         .name           = "des2_ick",
1766         .ops            = &clkops_omap2_dflt_wait,
1767         .parent         = &core_l4_ick,
1768         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1769         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1770         .clkdm_name     = "core_l4_clkdm",
1771         .recalc         = &followparent_recalc,
1772 };
1773
1774 static struct clk mmchs2_ick = {
1775         .name           = "mmchs_ick",
1776         .ops            = &clkops_omap2_dflt_wait,
1777         .id             = 1,
1778         .parent         = &core_l4_ick,
1779         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1780         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1781         .clkdm_name     = "core_l4_clkdm",
1782         .recalc         = &followparent_recalc,
1783 };
1784
1785 static struct clk mmchs1_ick = {
1786         .name           = "mmchs_ick",
1787         .ops            = &clkops_omap2_dflt_wait,
1788         .parent         = &core_l4_ick,
1789         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1790         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1791         .clkdm_name     = "core_l4_clkdm",
1792         .recalc         = &followparent_recalc,
1793 };
1794
1795 static struct clk mspro_ick = {
1796         .name           = "mspro_ick",
1797         .ops            = &clkops_omap2_dflt_wait,
1798         .parent         = &core_l4_ick,
1799         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1800         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1801         .clkdm_name     = "core_l4_clkdm",
1802         .recalc         = &followparent_recalc,
1803 };
1804
1805 static struct clk hdq_ick = {
1806         .name           = "hdq_ick",
1807         .ops            = &clkops_omap2_dflt_wait,
1808         .parent         = &core_l4_ick,
1809         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1810         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1811         .clkdm_name     = "core_l4_clkdm",
1812         .recalc         = &followparent_recalc,
1813 };
1814
1815 static struct clk mcspi4_ick = {
1816         .name           = "mcspi_ick",
1817         .ops            = &clkops_omap2_dflt_wait,
1818         .id             = 4,
1819         .parent         = &core_l4_ick,
1820         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1821         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1822         .clkdm_name     = "core_l4_clkdm",
1823         .recalc         = &followparent_recalc,
1824 };
1825
1826 static struct clk mcspi3_ick = {
1827         .name           = "mcspi_ick",
1828         .ops            = &clkops_omap2_dflt_wait,
1829         .id             = 3,
1830         .parent         = &core_l4_ick,
1831         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1832         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1833         .clkdm_name     = "core_l4_clkdm",
1834         .recalc         = &followparent_recalc,
1835 };
1836
1837 static struct clk mcspi2_ick = {
1838         .name           = "mcspi_ick",
1839         .ops            = &clkops_omap2_dflt_wait,
1840         .id             = 2,
1841         .parent         = &core_l4_ick,
1842         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1843         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1844         .clkdm_name     = "core_l4_clkdm",
1845         .recalc         = &followparent_recalc,
1846 };
1847
1848 static struct clk mcspi1_ick = {
1849         .name           = "mcspi_ick",
1850         .ops            = &clkops_omap2_dflt_wait,
1851         .id             = 1,
1852         .parent         = &core_l4_ick,
1853         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1854         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1855         .clkdm_name     = "core_l4_clkdm",
1856         .recalc         = &followparent_recalc,
1857 };
1858
1859 static struct clk i2c3_ick = {
1860         .name           = "i2c_ick",
1861         .ops            = &clkops_omap2_dflt_wait,
1862         .id             = 3,
1863         .parent         = &core_l4_ick,
1864         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1865         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1866         .clkdm_name     = "core_l4_clkdm",
1867         .recalc         = &followparent_recalc,
1868 };
1869
1870 static struct clk i2c2_ick = {
1871         .name           = "i2c_ick",
1872         .ops            = &clkops_omap2_dflt_wait,
1873         .id             = 2,
1874         .parent         = &core_l4_ick,
1875         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1876         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1877         .clkdm_name     = "core_l4_clkdm",
1878         .recalc         = &followparent_recalc,
1879 };
1880
1881 static struct clk i2c1_ick = {
1882         .name           = "i2c_ick",
1883         .ops            = &clkops_omap2_dflt_wait,
1884         .id             = 1,
1885         .parent         = &core_l4_ick,
1886         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1887         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1888         .clkdm_name     = "core_l4_clkdm",
1889         .recalc         = &followparent_recalc,
1890 };
1891
1892 static struct clk uart2_ick = {
1893         .name           = "uart2_ick",
1894         .ops            = &clkops_omap2_dflt_wait,
1895         .parent         = &core_l4_ick,
1896         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1897         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1898         .clkdm_name     = "core_l4_clkdm",
1899         .recalc         = &followparent_recalc,
1900 };
1901
1902 static struct clk uart1_ick = {
1903         .name           = "uart1_ick",
1904         .ops            = &clkops_omap2_dflt_wait,
1905         .parent         = &core_l4_ick,
1906         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1907         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1908         .clkdm_name     = "core_l4_clkdm",
1909         .recalc         = &followparent_recalc,
1910 };
1911
1912 static struct clk gpt11_ick = {
1913         .name           = "gpt11_ick",
1914         .ops            = &clkops_omap2_dflt_wait,
1915         .parent         = &core_l4_ick,
1916         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1917         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1918         .clkdm_name     = "core_l4_clkdm",
1919         .recalc         = &followparent_recalc,
1920 };
1921
1922 static struct clk gpt10_ick = {
1923         .name           = "gpt10_ick",
1924         .ops            = &clkops_omap2_dflt_wait,
1925         .parent         = &core_l4_ick,
1926         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1927         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1928         .clkdm_name     = "core_l4_clkdm",
1929         .recalc         = &followparent_recalc,
1930 };
1931
1932 static struct clk mcbsp5_ick = {
1933         .name           = "mcbsp_ick",
1934         .ops            = &clkops_omap2_dflt_wait,
1935         .id             = 5,
1936         .parent         = &core_l4_ick,
1937         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1938         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1939         .clkdm_name     = "core_l4_clkdm",
1940         .recalc         = &followparent_recalc,
1941 };
1942
1943 static struct clk mcbsp1_ick = {
1944         .name           = "mcbsp_ick",
1945         .ops            = &clkops_omap2_dflt_wait,
1946         .id             = 1,
1947         .parent         = &core_l4_ick,
1948         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1949         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1950         .clkdm_name     = "core_l4_clkdm",
1951         .recalc         = &followparent_recalc,
1952 };
1953
1954 static struct clk fac_ick = {
1955         .name           = "fac_ick",
1956         .ops            = &clkops_omap2_dflt_wait,
1957         .parent         = &core_l4_ick,
1958         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1959         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1960         .clkdm_name     = "core_l4_clkdm",
1961         .recalc         = &followparent_recalc,
1962 };
1963
1964 static struct clk mailboxes_ick = {
1965         .name           = "mailboxes_ick",
1966         .ops            = &clkops_omap2_dflt_wait,
1967         .parent         = &core_l4_ick,
1968         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1969         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
1970         .clkdm_name     = "core_l4_clkdm",
1971         .recalc         = &followparent_recalc,
1972 };
1973
1974 static struct clk omapctrl_ick = {
1975         .name           = "omapctrl_ick",
1976         .ops            = &clkops_omap2_dflt_wait,
1977         .parent         = &core_l4_ick,
1978         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1979         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
1980         .flags          = ENABLE_ON_INIT,
1981         .recalc         = &followparent_recalc,
1982 };
1983
1984 /* SSI_L4_ICK based clocks */
1985
1986 static struct clk ssi_l4_ick = {
1987         .name           = "ssi_l4_ick",
1988         .ops            = &clkops_null,
1989         .parent         = &l4_ick,
1990         .flags          = RATE_PROPAGATES,
1991         .clkdm_name     = "core_l4_clkdm",
1992         .recalc         = &followparent_recalc,
1993 };
1994
1995 static struct clk ssi_ick = {
1996         .name           = "ssi_ick",
1997         .ops            = &clkops_omap2_dflt,
1998         .parent         = &ssi_l4_ick,
1999         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2000         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2001         .clkdm_name     = "core_l4_clkdm",
2002         .recalc         = &followparent_recalc,
2003 };
2004
2005 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2006  * but l4_ick makes more sense to me */
2007
2008 static const struct clksel usb_l4_clksel[] = {
2009         { .parent = &l4_ick, .rates = div2_rates },
2010         { .parent = NULL },
2011 };
2012
2013 static struct clk usb_l4_ick = {
2014         .name           = "usb_l4_ick",
2015         .ops            = &clkops_omap2_dflt_wait,
2016         .parent         = &l4_ick,
2017         .init           = &omap2_init_clksel_parent,
2018         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2019         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2020         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2021         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2022         .clksel         = usb_l4_clksel,
2023         .recalc         = &omap2_clksel_recalc,
2024 };
2025
2026 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2027
2028 /* SECURITY_L4_ICK2 based clocks */
2029
2030 static struct clk security_l4_ick2 = {
2031         .name           = "security_l4_ick2",
2032         .ops            = &clkops_null,
2033         .parent         = &l4_ick,
2034         .flags          = RATE_PROPAGATES,
2035         .recalc         = &followparent_recalc,
2036 };
2037
2038 static struct clk aes1_ick = {
2039         .name           = "aes1_ick",
2040         .ops            = &clkops_omap2_dflt_wait,
2041         .parent         = &security_l4_ick2,
2042         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2043         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2044         .recalc         = &followparent_recalc,
2045 };
2046
2047 static struct clk rng_ick = {
2048         .name           = "rng_ick",
2049         .ops            = &clkops_omap2_dflt_wait,
2050         .parent         = &security_l4_ick2,
2051         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2052         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2053         .recalc         = &followparent_recalc,
2054 };
2055
2056 static struct clk sha11_ick = {
2057         .name           = "sha11_ick",
2058         .ops            = &clkops_omap2_dflt_wait,
2059         .parent         = &security_l4_ick2,
2060         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2061         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2062         .recalc         = &followparent_recalc,
2063 };
2064
2065 static struct clk des1_ick = {
2066         .name           = "des1_ick",
2067         .ops            = &clkops_omap2_dflt_wait,
2068         .parent         = &security_l4_ick2,
2069         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2070         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2071         .recalc         = &followparent_recalc,
2072 };
2073
2074 /* DSS */
2075 static const struct clksel dss1_alwon_fck_clksel[] = {
2076         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2077         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2078         { .parent = NULL }
2079 };
2080
2081 static struct clk dss1_alwon_fck = {
2082         .name           = "dss1_alwon_fck",
2083         .ops            = &clkops_omap2_dflt,
2084         .parent         = &dpll4_m4x2_ck,
2085         .init           = &omap2_init_clksel_parent,
2086         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2087         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2088         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2089         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2090         .clksel         = dss1_alwon_fck_clksel,
2091         .clkdm_name     = "dss_clkdm",
2092         .recalc         = &omap2_clksel_recalc,
2093 };
2094
2095 static struct clk dss_tv_fck = {
2096         .name           = "dss_tv_fck",
2097         .ops            = &clkops_omap2_dflt,
2098         .parent         = &omap_54m_fck,
2099         .init           = &omap2_init_clk_clkdm,
2100         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2101         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2102         .clkdm_name     = "dss_clkdm",
2103         .recalc         = &followparent_recalc,
2104 };
2105
2106 static struct clk dss_96m_fck = {
2107         .name           = "dss_96m_fck",
2108         .ops            = &clkops_omap2_dflt,
2109         .parent         = &omap_96m_fck,
2110         .init           = &omap2_init_clk_clkdm,
2111         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2112         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2113         .clkdm_name     = "dss_clkdm",
2114         .recalc         = &followparent_recalc,
2115 };
2116
2117 static struct clk dss2_alwon_fck = {
2118         .name           = "dss2_alwon_fck",
2119         .ops            = &clkops_omap2_dflt,
2120         .parent         = &sys_ck,
2121         .init           = &omap2_init_clk_clkdm,
2122         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2123         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2124         .clkdm_name     = "dss_clkdm",
2125         .recalc         = &followparent_recalc,
2126 };
2127
2128 static struct clk dss_ick = {
2129         /* Handles both L3 and L4 clocks */
2130         .name           = "dss_ick",
2131         .ops            = &clkops_omap2_dflt,
2132         .parent         = &l4_ick,
2133         .init           = &omap2_init_clk_clkdm,
2134         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2135         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2136         .clkdm_name     = "dss_clkdm",
2137         .recalc         = &followparent_recalc,
2138 };
2139
2140 /* CAM */
2141
2142 static const struct clksel cam_mclk_clksel[] = {
2143         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2144         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2145         { .parent = NULL }
2146 };
2147
2148 static struct clk cam_mclk = {
2149         .name           = "cam_mclk",
2150         .ops            = &clkops_omap2_dflt_wait,
2151         .parent         = &dpll4_m5x2_ck,
2152         .init           = &omap2_init_clksel_parent,
2153         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2154         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2155         .clksel         = cam_mclk_clksel,
2156         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2157         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2158         .clkdm_name     = "cam_clkdm",
2159         .recalc         = &omap2_clksel_recalc,
2160 };
2161
2162 static struct clk cam_ick = {
2163         /* Handles both L3 and L4 clocks */
2164         .name           = "cam_ick",
2165         .ops            = &clkops_omap2_dflt_wait,
2166         .parent         = &l4_ick,
2167         .init           = &omap2_init_clk_clkdm,
2168         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2169         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2170         .clkdm_name     = "cam_clkdm",
2171         .recalc         = &followparent_recalc,
2172 };
2173
2174 /* USBHOST - 3430ES2 only */
2175
2176 static struct clk usbhost_120m_fck = {
2177         .name           = "usbhost_120m_fck",
2178         .ops            = &clkops_omap2_dflt_wait,
2179         .parent         = &omap_120m_fck,
2180         .init           = &omap2_init_clk_clkdm,
2181         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2182         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2183         .clkdm_name     = "usbhost_clkdm",
2184         .recalc         = &followparent_recalc,
2185 };
2186
2187 static struct clk usbhost_48m_fck = {
2188         .name           = "usbhost_48m_fck",
2189         .ops            = &clkops_omap2_dflt_wait,
2190         .parent         = &omap_48m_fck,
2191         .init           = &omap2_init_clk_clkdm,
2192         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2193         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2194         .clkdm_name     = "usbhost_clkdm",
2195         .recalc         = &followparent_recalc,
2196 };
2197
2198 static struct clk usbhost_ick = {
2199         /* Handles both L3 and L4 clocks */
2200         .name           = "usbhost_ick",
2201         .ops            = &clkops_omap2_dflt_wait,
2202         .parent         = &l4_ick,
2203         .init           = &omap2_init_clk_clkdm,
2204         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2205         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2206         .clkdm_name     = "usbhost_clkdm",
2207         .recalc         = &followparent_recalc,
2208 };
2209
2210 static struct clk usbhost_sar_fck = {
2211         .name           = "usbhost_sar_fck",
2212         .ops            = &clkops_omap2_dflt,
2213         .parent         = &osc_sys_ck,
2214         .init           = &omap2_init_clk_clkdm,
2215         .enable_reg     = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
2216         .enable_bit     = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
2217         .clkdm_name     = "usbhost_clkdm",
2218         .recalc         = &followparent_recalc,
2219 };
2220
2221 /* WKUP */
2222
2223 static const struct clksel_rate usim_96m_rates[] = {
2224         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2225         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2226         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2227         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2228         { .div = 0 },
2229 };
2230
2231 static const struct clksel_rate usim_120m_rates[] = {
2232         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2233         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2234         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2235         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2236         { .div = 0 },
2237 };
2238
2239 static const struct clksel usim_clksel[] = {
2240         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2241         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2242         { .parent = &sys_ck,            .rates = div2_rates },
2243         { .parent = NULL },
2244 };
2245
2246 /* 3430ES2 only */
2247 static struct clk usim_fck = {
2248         .name           = "usim_fck",
2249         .ops            = &clkops_omap2_dflt_wait,
2250         .init           = &omap2_init_clksel_parent,
2251         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2252         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2253         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2254         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2255         .clksel         = usim_clksel,
2256         .recalc         = &omap2_clksel_recalc,
2257 };
2258
2259 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2260 static struct clk gpt1_fck = {
2261         .name           = "gpt1_fck",
2262         .ops            = &clkops_omap2_dflt_wait,
2263         .init           = &omap2_init_clksel_parent,
2264         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2265         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2266         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2267         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2268         .clksel         = omap343x_gpt_clksel,
2269         .clkdm_name     = "wkup_clkdm",
2270         .recalc         = &omap2_clksel_recalc,
2271 };
2272
2273 static struct clk wkup_32k_fck = {
2274         .name           = "wkup_32k_fck",
2275         .ops            = &clkops_null,
2276         .init           = &omap2_init_clk_clkdm,
2277         .parent         = &omap_32k_fck,
2278         .flags          = RATE_PROPAGATES,
2279         .clkdm_name     = "wkup_clkdm",
2280         .recalc         = &followparent_recalc,
2281 };
2282
2283 static struct clk gpio1_dbck = {
2284         .name           = "gpio1_dbck",
2285         .ops            = &clkops_omap2_dflt_wait,
2286         .parent         = &wkup_32k_fck,
2287         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2288         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2289         .clkdm_name     = "wkup_clkdm",
2290         .recalc         = &followparent_recalc,
2291 };
2292
2293 static struct clk wdt2_fck = {
2294         .name           = "wdt2_fck",
2295         .ops            = &clkops_omap2_dflt_wait,
2296         .parent         = &wkup_32k_fck,
2297         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2298         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2299         .clkdm_name     = "wkup_clkdm",
2300         .recalc         = &followparent_recalc,
2301 };
2302
2303 static struct clk wkup_l4_ick = {
2304         .name           = "wkup_l4_ick",
2305         .ops            = &clkops_null,
2306         .parent         = &sys_ck,
2307         .flags          = RATE_PROPAGATES,
2308         .clkdm_name     = "wkup_clkdm",
2309         .recalc         = &followparent_recalc,
2310 };
2311
2312 /* 3430ES2 only */
2313 /* Never specifically named in the TRM, so we have to infer a likely name */
2314 static struct clk usim_ick = {
2315         .name           = "usim_ick",
2316         .ops            = &clkops_omap2_dflt_wait,
2317         .parent         = &wkup_l4_ick,
2318         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2319         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2320         .clkdm_name     = "wkup_clkdm",
2321         .recalc         = &followparent_recalc,
2322 };
2323
2324 static struct clk wdt2_ick = {
2325         .name           = "wdt2_ick",
2326         .ops            = &clkops_omap2_dflt_wait,
2327         .parent         = &wkup_l4_ick,
2328         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2329         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2330         .clkdm_name     = "wkup_clkdm",
2331         .recalc         = &followparent_recalc,
2332 };
2333
2334 static struct clk wdt1_ick = {
2335         .name           = "wdt1_ick",
2336         .ops            = &clkops_omap2_dflt_wait,
2337         .parent         = &wkup_l4_ick,
2338         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2339         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2340         .clkdm_name     = "wkup_clkdm",
2341         .recalc         = &followparent_recalc,
2342 };
2343
2344 static struct clk gpio1_ick = {
2345         .name           = "gpio1_ick",
2346         .ops            = &clkops_omap2_dflt_wait,
2347         .parent         = &wkup_l4_ick,
2348         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2349         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2350         .clkdm_name     = "wkup_clkdm",
2351         .recalc         = &followparent_recalc,
2352 };
2353
2354 static struct clk omap_32ksync_ick = {
2355         .name           = "omap_32ksync_ick",
2356         .ops            = &clkops_omap2_dflt_wait,
2357         .parent         = &wkup_l4_ick,
2358         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2359         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2360         .clkdm_name     = "wkup_clkdm",
2361         .recalc         = &followparent_recalc,
2362 };
2363
2364 /* XXX This clock no longer exists in 3430 TRM rev F */
2365 static struct clk gpt12_ick = {
2366         .name           = "gpt12_ick",
2367         .ops            = &clkops_omap2_dflt_wait,
2368         .parent         = &wkup_l4_ick,
2369         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2370         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2371         .clkdm_name     = "wkup_clkdm",
2372         .recalc         = &followparent_recalc,
2373 };
2374
2375 static struct clk gpt1_ick = {
2376         .name           = "gpt1_ick",
2377         .ops            = &clkops_omap2_dflt_wait,
2378         .parent         = &wkup_l4_ick,
2379         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2380         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2381         .clkdm_name     = "wkup_clkdm",
2382         .recalc         = &followparent_recalc,
2383 };
2384
2385
2386
2387 /* PER clock domain */
2388
2389 static struct clk per_96m_fck = {
2390         .name           = "per_96m_fck",
2391         .ops            = &clkops_null,
2392         .parent         = &omap_96m_alwon_fck,
2393         .init           = &omap2_init_clk_clkdm,
2394         .flags          = RATE_PROPAGATES,
2395         .clkdm_name     = "per_clkdm",
2396         .recalc         = &followparent_recalc,
2397 };
2398
2399 static struct clk per_48m_fck = {
2400         .name           = "per_48m_fck",
2401         .ops            = &clkops_null,
2402         .parent         = &omap_48m_fck,
2403         .init           = &omap2_init_clk_clkdm,
2404         .flags          = RATE_PROPAGATES,
2405         .clkdm_name     = "per_clkdm",
2406         .recalc         = &followparent_recalc,
2407 };
2408
2409 static struct clk uart3_fck = {
2410         .name           = "uart3_fck",
2411         .ops            = &clkops_omap2_dflt_wait,
2412         .parent         = &per_48m_fck,
2413         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2414         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2415         .clkdm_name     = "per_clkdm",
2416         .recalc         = &followparent_recalc,
2417 };
2418
2419 static struct clk gpt2_fck = {
2420         .name           = "gpt2_fck",
2421         .ops            = &clkops_omap2_dflt_wait,
2422         .init           = &omap2_init_clksel_parent,
2423         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2424         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2425         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2426         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2427         .clksel         = omap343x_gpt_clksel,
2428         .clkdm_name     = "per_clkdm",
2429         .recalc         = &omap2_clksel_recalc,
2430 };
2431
2432 static struct clk gpt3_fck = {
2433         .name           = "gpt3_fck",
2434         .ops            = &clkops_omap2_dflt_wait,
2435         .init           = &omap2_init_clksel_parent,
2436         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2437         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2438         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2439         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2440         .clksel         = omap343x_gpt_clksel,
2441         .clkdm_name     = "per_clkdm",
2442         .recalc         = &omap2_clksel_recalc,
2443 };
2444
2445 static struct clk gpt4_fck = {
2446         .name           = "gpt4_fck",
2447         .ops            = &clkops_omap2_dflt_wait,
2448         .init           = &omap2_init_clksel_parent,
2449         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2450         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2451         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2452         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2453         .clksel         = omap343x_gpt_clksel,
2454         .clkdm_name     = "per_clkdm",
2455         .recalc         = &omap2_clksel_recalc,
2456 };
2457
2458 static struct clk gpt5_fck = {
2459         .name           = "gpt5_fck",
2460         .ops            = &clkops_omap2_dflt_wait,
2461         .init           = &omap2_init_clksel_parent,
2462         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2463         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2464         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2465         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2466         .clksel         = omap343x_gpt_clksel,
2467         .clkdm_name     = "per_clkdm",
2468         .recalc         = &omap2_clksel_recalc,
2469 };
2470
2471 static struct clk gpt6_fck = {
2472         .name           = "gpt6_fck",
2473         .ops            = &clkops_omap2_dflt_wait,
2474         .init           = &omap2_init_clksel_parent,
2475         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2476         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2477         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2478         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2479         .clksel         = omap343x_gpt_clksel,
2480         .clkdm_name     = "per_clkdm",
2481         .recalc         = &omap2_clksel_recalc,
2482 };
2483
2484 static struct clk gpt7_fck = {
2485         .name           = "gpt7_fck",
2486         .ops            = &clkops_omap2_dflt_wait,
2487         .init           = &omap2_init_clksel_parent,
2488         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2489         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2490         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2491         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2492         .clksel         = omap343x_gpt_clksel,
2493         .clkdm_name     = "per_clkdm",
2494         .recalc         = &omap2_clksel_recalc,
2495 };
2496
2497 static struct clk gpt8_fck = {
2498         .name           = "gpt8_fck",
2499         .ops            = &clkops_omap2_dflt_wait,
2500         .init           = &omap2_init_clksel_parent,
2501         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2502         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2503         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2504         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2505         .clksel         = omap343x_gpt_clksel,
2506         .clkdm_name     = "per_clkdm",
2507         .recalc         = &omap2_clksel_recalc,
2508 };
2509
2510 static struct clk gpt9_fck = {
2511         .name           = "gpt9_fck",
2512         .ops            = &clkops_omap2_dflt_wait,
2513         .init           = &omap2_init_clksel_parent,
2514         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2515         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2516         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2517         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2518         .clksel         = omap343x_gpt_clksel,
2519         .clkdm_name     = "per_clkdm",
2520         .recalc         = &omap2_clksel_recalc,
2521 };
2522
2523 static struct clk per_32k_alwon_fck = {
2524         .name           = "per_32k_alwon_fck",
2525         .ops            = &clkops_null,
2526         .parent         = &omap_32k_fck,
2527         .clkdm_name     = "per_clkdm",
2528         .flags          = RATE_PROPAGATES,
2529         .recalc         = &followparent_recalc,
2530 };
2531
2532 static struct clk gpio6_dbck = {
2533         .name           = "gpio6_dbck",
2534         .ops            = &clkops_omap2_dflt_wait,
2535         .parent         = &per_32k_alwon_fck,
2536         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2537         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2538         .clkdm_name     = "per_clkdm",
2539         .recalc         = &followparent_recalc,
2540 };
2541
2542 static struct clk gpio5_dbck = {
2543         .name           = "gpio5_dbck",
2544         .ops            = &clkops_omap2_dflt_wait,
2545         .parent         = &per_32k_alwon_fck,
2546         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2547         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2548         .clkdm_name     = "per_clkdm",
2549         .recalc         = &followparent_recalc,
2550 };
2551
2552 static struct clk gpio4_dbck = {
2553         .name           = "gpio4_dbck",
2554         .ops            = &clkops_omap2_dflt_wait,
2555         .parent         = &per_32k_alwon_fck,
2556         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2557         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2558         .clkdm_name     = "per_clkdm",
2559         .recalc         = &followparent_recalc,
2560 };
2561
2562 static struct clk gpio3_dbck = {
2563         .name           = "gpio3_dbck",
2564         .ops            = &clkops_omap2_dflt_wait,
2565         .parent         = &per_32k_alwon_fck,
2566         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2567         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2568         .clkdm_name     = "per_clkdm",
2569         .recalc         = &followparent_recalc,
2570 };
2571
2572 static struct clk gpio2_dbck = {
2573         .name           = "gpio2_dbck",
2574         .ops            = &clkops_omap2_dflt_wait,
2575         .parent         = &per_32k_alwon_fck,
2576         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2577         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2578         .clkdm_name     = "per_clkdm",
2579         .recalc         = &followparent_recalc,
2580 };
2581
2582 static struct clk wdt3_fck = {
2583         .name           = "wdt3_fck",
2584         .ops            = &clkops_omap2_dflt_wait,
2585         .parent         = &per_32k_alwon_fck,
2586         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2587         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2588         .clkdm_name     = "per_clkdm",
2589         .recalc         = &followparent_recalc,
2590 };
2591
2592 static struct clk per_l4_ick = {
2593         .name           = "per_l4_ick",
2594         .ops            = &clkops_null,
2595         .parent         = &l4_ick,
2596         .flags          = RATE_PROPAGATES,
2597         .clkdm_name     = "per_clkdm",
2598         .recalc         = &followparent_recalc,
2599 };
2600
2601 static struct clk gpio6_ick = {
2602         .name           = "gpio6_ick",
2603         .ops            = &clkops_omap2_dflt_wait,
2604         .parent         = &per_l4_ick,
2605         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2606         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2607         .clkdm_name     = "per_clkdm",
2608         .recalc         = &followparent_recalc,
2609 };
2610
2611 static struct clk gpio5_ick = {
2612         .name           = "gpio5_ick",
2613         .ops            = &clkops_omap2_dflt_wait,
2614         .parent         = &per_l4_ick,
2615         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2616         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2617         .clkdm_name     = "per_clkdm",
2618         .recalc         = &followparent_recalc,
2619 };
2620
2621 static struct clk gpio4_ick = {
2622         .name           = "gpio4_ick",
2623         .ops            = &clkops_omap2_dflt_wait,
2624         .parent         = &per_l4_ick,
2625         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2626         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2627         .clkdm_name     = "per_clkdm",
2628         .recalc         = &followparent_recalc,
2629 };
2630
2631 static struct clk gpio3_ick = {
2632         .name           = "gpio3_ick",
2633         .ops            = &clkops_omap2_dflt_wait,
2634         .parent         = &per_l4_ick,
2635         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2636         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2637         .clkdm_name     = "per_clkdm",
2638         .recalc         = &followparent_recalc,
2639 };
2640
2641 static struct clk gpio2_ick = {
2642         .name           = "gpio2_ick",
2643         .ops            = &clkops_omap2_dflt_wait,
2644         .parent         = &per_l4_ick,
2645         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2646         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2647         .clkdm_name     = "per_clkdm",
2648         .recalc         = &followparent_recalc,
2649 };
2650
2651 static struct clk wdt3_ick = {
2652         .name           = "wdt3_ick",
2653         .ops            = &clkops_omap2_dflt_wait,
2654         .parent         = &per_l4_ick,
2655         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2656         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2657         .clkdm_name     = "per_clkdm",
2658         .recalc         = &followparent_recalc,
2659 };
2660
2661 static struct clk uart3_ick = {
2662         .name           = "uart3_ick",
2663         .ops            = &clkops_omap2_dflt_wait,
2664         .parent         = &per_l4_ick,
2665         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2666         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2667         .clkdm_name     = "per_clkdm",
2668         .recalc         = &followparent_recalc,
2669 };
2670
2671 static struct clk gpt9_ick = {
2672         .name           = "gpt9_ick",
2673         .ops            = &clkops_omap2_dflt_wait,
2674         .parent         = &per_l4_ick,
2675         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2676         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2677         .clkdm_name     = "per_clkdm",
2678         .recalc         = &followparent_recalc,
2679 };
2680
2681 static struct clk gpt8_ick = {
2682         .name           = "gpt8_ick",
2683         .ops            = &clkops_omap2_dflt_wait,
2684         .parent         = &per_l4_ick,
2685         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2686         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2687         .clkdm_name     = "per_clkdm",
2688         .recalc         = &followparent_recalc,
2689 };
2690
2691 static struct clk gpt7_ick = {
2692         .name           = "gpt7_ick",
2693         .ops            = &clkops_omap2_dflt_wait,
2694         .parent         = &per_l4_ick,
2695         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2696         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2697         .clkdm_name     = "per_clkdm",
2698         .recalc         = &followparent_recalc,
2699 };
2700
2701 static struct clk gpt6_ick = {
2702         .name           = "gpt6_ick",
2703         .ops            = &clkops_omap2_dflt_wait,
2704         .parent         = &per_l4_ick,
2705         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2706         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2707         .clkdm_name     = "per_clkdm",
2708         .recalc         = &followparent_recalc,
2709 };
2710
2711 static struct clk gpt5_ick = {
2712         .name           = "gpt5_ick",
2713         .ops            = &clkops_omap2_dflt_wait,
2714         .parent         = &per_l4_ick,
2715         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2716         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2717         .clkdm_name     = "per_clkdm",
2718         .recalc         = &followparent_recalc,
2719 };
2720
2721 static struct clk gpt4_ick = {
2722         .name           = "gpt4_ick",
2723         .ops            = &clkops_omap2_dflt_wait,
2724         .parent         = &per_l4_ick,
2725         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2726         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2727         .clkdm_name     = "per_clkdm",
2728         .recalc         = &followparent_recalc,
2729 };
2730
2731 static struct clk gpt3_ick = {
2732         .name           = "gpt3_ick",
2733         .ops            = &clkops_omap2_dflt_wait,
2734         .parent         = &per_l4_ick,
2735         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2736         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2737         .clkdm_name     = "per_clkdm",
2738         .recalc         = &followparent_recalc,
2739 };
2740
2741 static struct clk gpt2_ick = {
2742         .name           = "gpt2_ick",
2743         .ops            = &clkops_omap2_dflt_wait,
2744         .parent         = &per_l4_ick,
2745         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2746         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2747         .clkdm_name     = "per_clkdm",
2748         .recalc         = &followparent_recalc,
2749 };
2750
2751 static struct clk mcbsp2_ick = {
2752         .name           = "mcbsp_ick",
2753         .ops            = &clkops_omap2_dflt_wait,
2754         .id             = 2,
2755         .parent         = &per_l4_ick,
2756         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2757         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2758         .clkdm_name     = "per_clkdm",
2759         .recalc         = &followparent_recalc,
2760 };
2761
2762 static struct clk mcbsp3_ick = {
2763         .name           = "mcbsp_ick",
2764         .ops            = &clkops_omap2_dflt_wait,
2765         .id             = 3,
2766         .parent         = &per_l4_ick,
2767         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2768         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2769         .clkdm_name     = "per_clkdm",
2770         .recalc         = &followparent_recalc,
2771 };
2772
2773 static struct clk mcbsp4_ick = {
2774         .name           = "mcbsp_ick",
2775         .ops            = &clkops_omap2_dflt_wait,
2776         .id             = 4,
2777         .parent         = &per_l4_ick,
2778         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2779         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2780         .clkdm_name     = "per_clkdm",
2781         .recalc         = &followparent_recalc,
2782 };
2783
2784 static const struct clksel mcbsp_234_clksel[] = {
2785         { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2786         { .parent = &mcbsp_clks,  .rates = common_mcbsp_mcbsp_rates },
2787         { .parent = NULL }
2788 };
2789
2790 static struct clk mcbsp2_fck = {
2791         .name           = "mcbsp_fck",
2792         .ops            = &clkops_omap2_dflt_wait,
2793         .id             = 2,
2794         .init           = &omap2_init_clksel_parent,
2795         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2796         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2797         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2798         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2799         .clksel         = mcbsp_234_clksel,
2800         .clkdm_name     = "per_clkdm",
2801         .recalc         = &omap2_clksel_recalc,
2802 };
2803
2804 static struct clk mcbsp3_fck = {
2805         .name           = "mcbsp_fck",
2806         .ops            = &clkops_omap2_dflt_wait,
2807         .id             = 3,
2808         .init           = &omap2_init_clksel_parent,
2809         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2810         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2811         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2812         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2813         .clksel         = mcbsp_234_clksel,
2814         .clkdm_name     = "per_clkdm",
2815         .recalc         = &omap2_clksel_recalc,
2816 };
2817
2818 static struct clk mcbsp4_fck = {
2819         .name           = "mcbsp_fck",
2820         .ops            = &clkops_omap2_dflt_wait,
2821         .id             = 4,
2822         .init           = &omap2_init_clksel_parent,
2823         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2824         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2825         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2826         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2827         .clksel         = mcbsp_234_clksel,
2828         .clkdm_name     = "per_clkdm",
2829         .recalc         = &omap2_clksel_recalc,
2830 };
2831
2832 /* EMU clocks */
2833
2834 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2835
2836 static const struct clksel_rate emu_src_sys_rates[] = {
2837         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2838         { .div = 0 },
2839 };
2840
2841 static const struct clksel_rate emu_src_core_rates[] = {
2842         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2843         { .div = 0 },
2844 };
2845
2846 static const struct clksel_rate emu_src_per_rates[] = {
2847         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2848         { .div = 0 },
2849 };
2850
2851 static const struct clksel_rate emu_src_mpu_rates[] = {
2852         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2853         { .div = 0 },
2854 };
2855
2856 static const struct clksel emu_src_clksel[] = {
2857         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2858         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2859         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2860         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2861         { .parent = NULL },
2862 };
2863
2864 /*
2865  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2866  * to switch the source of some of the EMU clocks.
2867  * XXX Are there CLKEN bits for these EMU clks?
2868  */
2869 static struct clk emu_src_ck = {
2870         .name           = "emu_src_ck",
2871         .ops            = &clkops_null,
2872         .init           = &omap2_init_clksel_parent,
2873         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2874         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2875         .clksel         = emu_src_clksel,
2876         .flags          = RATE_PROPAGATES,
2877         .clkdm_name     = "emu_clkdm",
2878         .recalc         = &omap2_clksel_recalc,
2879 };
2880
2881 static const struct clksel_rate pclk_emu_rates[] = {
2882         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2883         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2884         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2885         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2886         { .div = 0 },
2887 };
2888
2889 static const struct clksel pclk_emu_clksel[] = {
2890         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2891         { .parent = NULL },
2892 };
2893
2894 static struct clk pclk_fck = {
2895         .name           = "pclk_fck",
2896         .ops            = &clkops_null,
2897         .init           = &omap2_init_clksel_parent,
2898         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2899         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2900         .clksel         = pclk_emu_clksel,
2901         .flags          = RATE_PROPAGATES,
2902         .clkdm_name     = "emu_clkdm",
2903         .recalc         = &omap2_clksel_recalc,
2904 };
2905
2906 static const struct clksel_rate pclkx2_emu_rates[] = {
2907         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2908         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2909         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2910         { .div = 0 },
2911 };
2912
2913 static const struct clksel pclkx2_emu_clksel[] = {
2914         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2915         { .parent = NULL },
2916 };
2917
2918 static struct clk pclkx2_fck = {
2919         .name           = "pclkx2_fck",
2920         .ops            = &clkops_null,
2921         .init           = &omap2_init_clksel_parent,
2922         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2923         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2924         .clksel         = pclkx2_emu_clksel,
2925         .flags          = RATE_PROPAGATES,
2926         .clkdm_name     = "emu_clkdm",
2927         .recalc         = &omap2_clksel_recalc,
2928 };
2929
2930 static const struct clksel atclk_emu_clksel[] = {
2931         { .parent = &emu_src_ck, .rates = div2_rates },
2932         { .parent = NULL },
2933 };
2934
2935 static struct clk atclk_fck = {
2936         .name           = "atclk_fck",
2937         .ops            = &clkops_null,
2938         .init           = &omap2_init_clksel_parent,
2939         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2940         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2941         .clksel         = atclk_emu_clksel,
2942         .flags          = RATE_PROPAGATES,
2943         .clkdm_name     = "emu_clkdm",
2944         .recalc         = &omap2_clksel_recalc,
2945 };
2946
2947 static struct clk traceclk_src_fck = {
2948         .name           = "traceclk_src_fck",
2949         .ops            = &clkops_null,
2950         .init           = &omap2_init_clksel_parent,
2951         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2952         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2953         .clksel         = emu_src_clksel,
2954         .flags          = RATE_PROPAGATES,
2955         .clkdm_name     = "emu_clkdm",
2956         .recalc         = &omap2_clksel_recalc,
2957 };
2958
2959 static const struct clksel_rate traceclk_rates[] = {
2960         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2961         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2962         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2963         { .div = 0 },
2964 };
2965
2966 static const struct clksel traceclk_clksel[] = {
2967         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2968         { .parent = NULL },
2969 };
2970
2971 static struct clk traceclk_fck = {
2972         .name           = "traceclk_fck",
2973         .ops            = &clkops_null,
2974         .init           = &omap2_init_clksel_parent,
2975         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2976         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
2977         .clksel         = traceclk_clksel,
2978         .clkdm_name     = "emu_clkdm",
2979         .recalc         = &omap2_clksel_recalc,
2980 };
2981
2982 /* SR clocks */
2983
2984 /* SmartReflex fclk (VDD1) */
2985 static struct clk sr1_fck = {
2986         .name           = "sr1_fck",
2987         .ops            = &clkops_omap2_dflt_wait,
2988         .parent         = &sys_ck,
2989         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2990         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
2991         .flags          = RATE_PROPAGATES,
2992         .recalc         = &followparent_recalc,
2993 };
2994
2995 /* SmartReflex fclk (VDD2) */
2996 static struct clk sr2_fck = {
2997         .name           = "sr2_fck",
2998         .ops            = &clkops_omap2_dflt_wait,
2999         .parent         = &sys_ck,
3000         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3001         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3002         .flags          = RATE_PROPAGATES,
3003         .recalc         = &followparent_recalc,
3004 };
3005
3006 static struct clk sr_l4_ick = {
3007         .name           = "sr_l4_ick",
3008         .ops            = &clkops_null, /* RMK: missing? */
3009         .parent         = &l4_ick,
3010         .clkdm_name     = "core_l4_clkdm",
3011         .recalc         = &followparent_recalc,
3012 };
3013
3014 /* SECURE_32K_FCK clocks */
3015
3016 /* XXX This clock no longer exists in 3430 TRM rev F */
3017 static struct clk gpt12_fck = {
3018         .name           = "gpt12_fck",
3019         .ops            = &clkops_null,
3020         .parent         = &secure_32k_fck,
3021         .recalc         = &followparent_recalc,
3022 };
3023
3024 static struct clk wdt1_fck = {
3025         .name           = "wdt1_fck",
3026         .ops            = &clkops_null,
3027         .parent         = &secure_32k_fck,
3028         .recalc         = &followparent_recalc,
3029 };
3030
3031 #endif