2 * OMAP3 clock framework
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
22 #include <mach/control.h>
26 #include "cm-regbits-34xx.h"
28 #include "prm-regbits-34xx.h"
30 static void omap3_dpll_recalc(struct clk *clk);
31 static void omap3_clkoutx2_recalc(struct clk *clk);
32 static void omap3_dpll_allow_idle(struct clk *clk);
33 static void omap3_dpll_deny_idle(struct clk *clk);
34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
35 static int omap3_noncore_dpll_enable(struct clk *clk);
36 static void omap3_noncore_dpll_disable(struct clk *clk);
37 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
38 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
40 /* Maximum DPLL multiplier, divider values for OMAP3 */
41 #define OMAP3_MAX_DPLL_MULT 2048
42 #define OMAP3_MAX_DPLL_DIV 128
45 * DPLL1 supplies clock to the MPU.
46 * DPLL2 supplies clock to the IVA2.
47 * DPLL3 supplies CORE domain clocks.
48 * DPLL4 supplies peripheral clocks.
49 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
52 /* Forward declarations for DPLL bypass clocks */
53 static struct clk dpll1_fck;
54 static struct clk dpll2_fck;
56 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
57 #define DPLL_LOW_POWER_STOP 0x1
58 #define DPLL_LOW_POWER_BYPASS 0x5
59 #define DPLL_LOCKED 0x7
63 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
64 static struct clk omap_32k_fck = {
65 .name = "omap_32k_fck",
67 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
69 .clkdm = { .name = "prm_clkdm" },
72 static struct clk secure_32k_fck = {
73 .name = "secure_32k_fck",
75 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
77 .clkdm = { .name = "prm_clkdm" },
80 /* Virtual source clocks for osc_sys_ck */
81 static struct clk virt_12m_ck = {
82 .name = "virt_12m_ck",
84 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
86 .clkdm = { .name = "prm_clkdm" },
89 static struct clk virt_13m_ck = {
90 .name = "virt_13m_ck",
92 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
94 .clkdm = { .name = "prm_clkdm" },
97 static struct clk virt_16_8m_ck = {
98 .name = "virt_16_8m_ck",
100 .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
102 .clkdm = { .name = "prm_clkdm" },
105 static struct clk virt_19_2m_ck = {
106 .name = "virt_19_2m_ck",
108 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
110 .clkdm = { .name = "prm_clkdm" },
113 static struct clk virt_26m_ck = {
114 .name = "virt_26m_ck",
116 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
118 .clkdm = { .name = "prm_clkdm" },
121 static struct clk virt_38_4m_ck = {
122 .name = "virt_38_4m_ck",
124 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
126 .clkdm = { .name = "prm_clkdm" },
129 static const struct clksel_rate osc_sys_12m_rates[] = {
130 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
134 static const struct clksel_rate osc_sys_13m_rates[] = {
135 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
139 static const struct clksel_rate osc_sys_16_8m_rates[] = {
140 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
144 static const struct clksel_rate osc_sys_19_2m_rates[] = {
145 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
149 static const struct clksel_rate osc_sys_26m_rates[] = {
150 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
154 static const struct clksel_rate osc_sys_38_4m_rates[] = {
155 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
159 static const struct clksel osc_sys_clksel[] = {
160 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
161 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
162 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
163 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
164 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
165 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
169 /* Oscillator clock */
170 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
171 static struct clk osc_sys_ck = {
172 .name = "osc_sys_ck",
173 .prcm_mod = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
174 .init = &omap2_init_clksel_parent,
175 .clksel_reg = OMAP3_PRM_CLKSEL_OFFSET,
176 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
177 .clksel = osc_sys_clksel,
178 /* REVISIT: deal with autoextclkmode? */
179 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
181 .clkdm = { .name = "prm_clkdm" },
182 .recalc = &omap2_clksel_recalc,
185 static const struct clksel_rate div2_rates[] = {
186 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
187 { .div = 2, .val = 2, .flags = RATE_IN_343X },
191 static const struct clksel sys_clksel[] = {
192 { .parent = &osc_sys_ck, .rates = div2_rates },
196 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
197 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
198 static struct clk sys_ck = {
200 .parent = &osc_sys_ck,
201 .prcm_mod = OMAP3430_GR_MOD | CLK_REG_IN_PRM,
202 .init = &omap2_init_clksel_parent,
203 .clksel_reg = OMAP3_PRM_CLKSRC_CTRL_OFFSET,
204 .clksel_mask = OMAP_SYSCLKDIV_MASK,
205 .clksel = sys_clksel,
206 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
207 .clkdm = { .name = "prm_clkdm" },
208 .recalc = &omap2_clksel_recalc,
211 static struct clk sys_altclk = {
212 .name = "sys_altclk",
213 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
214 .clkdm = { .name = "cm_clkdm" },
218 * Optional external clock input for some McBSPs
219 * Apparently this is not really in prm_clkdm, but rather is fed into
220 * both CORE and PER separately.
222 static struct clk mcbsp_clks = {
223 .name = "mcbsp_clks",
224 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
225 .clkdm = { .name = "prm_clkdm" },
228 /* PRM EXTERNAL CLOCK OUTPUT */
230 static struct clk sys_clkout1 = {
231 .name = "sys_clkout1",
232 .parent = &osc_sys_ck,
233 .prcm_mod = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
234 .enable_reg = OMAP3_PRM_CLKOUT_CTRL_OFFSET,
235 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
236 .flags = CLOCK_IN_OMAP343X,
237 .clkdm = { .name = "prm_clkdm" },
238 .recalc = &followparent_recalc,
245 static const struct clksel_rate div16_dpll_rates[] = {
246 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
247 { .div = 2, .val = 2, .flags = RATE_IN_343X },
248 { .div = 3, .val = 3, .flags = RATE_IN_343X },
249 { .div = 4, .val = 4, .flags = RATE_IN_343X },
250 { .div = 5, .val = 5, .flags = RATE_IN_343X },
251 { .div = 6, .val = 6, .flags = RATE_IN_343X },
252 { .div = 7, .val = 7, .flags = RATE_IN_343X },
253 { .div = 8, .val = 8, .flags = RATE_IN_343X },
254 { .div = 9, .val = 9, .flags = RATE_IN_343X },
255 { .div = 10, .val = 10, .flags = RATE_IN_343X },
256 { .div = 11, .val = 11, .flags = RATE_IN_343X },
257 { .div = 12, .val = 12, .flags = RATE_IN_343X },
258 { .div = 13, .val = 13, .flags = RATE_IN_343X },
259 { .div = 14, .val = 14, .flags = RATE_IN_343X },
260 { .div = 15, .val = 15, .flags = RATE_IN_343X },
261 { .div = 16, .val = 16, .flags = RATE_IN_343X },
266 /* MPU clock source */
268 static struct dpll_data dpll1_dd = {
269 .mult_div1_reg = OMAP3430_CM_CLKSEL1_PLL,
270 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
271 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
272 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
273 .control_reg = OMAP3430_CM_CLKEN_PLL,
274 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
275 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
276 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
277 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
278 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
279 .autoidle_reg = OMAP3430_CM_AUTOIDLE_PLL,
280 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
281 .idlest_reg = OMAP3430_CM_IDLEST_PLL,
282 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
283 .bypass_clk = &dpll1_fck,
284 .max_multiplier = OMAP3_MAX_DPLL_MULT,
286 .max_divider = OMAP3_MAX_DPLL_DIV,
287 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
290 static struct clk dpll1_ck = {
294 .dpll_data = &dpll1_dd,
295 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
296 .round_rate = &omap2_dpll_round_rate,
297 .set_rate = &omap3_noncore_dpll_set_rate,
298 .clkdm = { .name = "dpll1_clkdm" },
299 .recalc = &omap3_dpll_recalc,
303 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
304 * DPLL isn't bypassed.
306 static struct clk dpll1_x2_ck = {
307 .name = "dpll1_x2_ck",
309 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
310 PARENT_CONTROLS_CLOCK,
311 .clkdm = { .name = "dpll1_clkdm" },
312 .recalc = &omap3_clkoutx2_recalc,
315 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
316 static const struct clksel div16_dpll1_x2m2_clksel[] = {
317 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
322 * Does not exist in the TRM - needed to separate the M2 divider from
323 * bypass selection in mpu_ck
325 static struct clk dpll1_x2m2_ck = {
326 .name = "dpll1_x2m2_ck",
327 .parent = &dpll1_x2_ck,
329 .init = &omap2_init_clksel_parent,
330 .clksel_reg = OMAP3430_CM_CLKSEL2_PLL,
331 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
332 .clksel = div16_dpll1_x2m2_clksel,
333 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
334 PARENT_CONTROLS_CLOCK,
335 .clkdm = { .name = "dpll1_clkdm" },
336 .recalc = &omap2_clksel_recalc,
340 /* IVA2 clock source */
343 static struct dpll_data dpll2_dd = {
344 .mult_div1_reg = OMAP3430_CM_CLKSEL1_PLL,
345 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
346 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
347 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
348 .control_reg = OMAP3430_CM_CLKEN_PLL,
349 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
350 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
351 (1 << DPLL_LOW_POWER_BYPASS),
352 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
353 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
354 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
355 .autoidle_reg = OMAP3430_CM_AUTOIDLE_PLL,
356 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
357 .idlest_reg = OMAP3430_CM_IDLEST_PLL,
358 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
359 .bypass_clk = &dpll2_fck,
360 .max_multiplier = OMAP3_MAX_DPLL_MULT,
362 .max_divider = OMAP3_MAX_DPLL_DIV,
363 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
366 static struct clk dpll2_ck = {
369 .prcm_mod = OMAP3430_IVA2_MOD,
370 .dpll_data = &dpll2_dd,
371 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
372 .enable = &omap3_noncore_dpll_enable,
373 .disable = &omap3_noncore_dpll_disable,
374 .round_rate = &omap2_dpll_round_rate,
375 .set_rate = &omap3_noncore_dpll_set_rate,
376 .clkdm = { .name = "dpll2_clkdm" },
377 .recalc = &omap3_dpll_recalc,
380 static const struct clksel div16_dpll2_m2x2_clksel[] = {
381 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
386 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
387 * or CLKOUTX2. CLKOUT seems most plausible.
389 static struct clk dpll2_m2_ck = {
390 .name = "dpll2_m2_ck",
392 .prcm_mod = OMAP3430_IVA2_MOD,
393 .init = &omap2_init_clksel_parent,
394 .clksel_reg = OMAP3430_CM_CLKSEL2_PLL,
395 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
396 .clksel = div16_dpll2_m2x2_clksel,
397 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
398 PARENT_CONTROLS_CLOCK,
399 .clkdm = { .name = "dpll2_clkdm" },
400 .recalc = &omap2_clksel_recalc,
405 * Source clock for all interfaces and for some device fclks
406 * REVISIT: Also supports fast relock bypass - not included below
408 static struct dpll_data dpll3_dd = {
409 .mult_div1_reg = CM_CLKSEL1,
410 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
411 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
412 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
413 .control_reg = CM_CLKEN,
414 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
415 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
416 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
417 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
418 .autoidle_reg = CM_AUTOIDLE,
419 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
420 .idlest_reg = CM_IDLEST,
421 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
422 .bypass_clk = &sys_ck,
423 .max_multiplier = OMAP3_MAX_DPLL_MULT,
425 .max_divider = OMAP3_MAX_DPLL_DIV,
426 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
429 static struct clk dpll3_ck = {
433 .dpll_data = &dpll3_dd,
434 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
435 .round_rate = &omap2_dpll_round_rate,
436 .clkdm = { .name = "dpll3_clkdm" },
437 .recalc = &omap3_dpll_recalc,
441 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
442 * DPLL isn't bypassed
444 static struct clk dpll3_x2_ck = {
445 .name = "dpll3_x2_ck",
447 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
448 PARENT_CONTROLS_CLOCK,
449 .clkdm = { .name = "dpll3_clkdm" },
450 .recalc = &omap3_clkoutx2_recalc,
453 static const struct clksel_rate div31_dpll3_rates[] = {
454 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
455 { .div = 2, .val = 2, .flags = RATE_IN_343X },
456 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
457 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
458 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
459 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
460 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
461 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
462 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
463 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
464 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
465 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
466 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
467 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
468 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
469 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
470 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
471 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
472 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
473 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
474 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
475 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
476 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
477 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
478 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
479 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
480 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
481 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
482 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
483 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
484 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
488 static const struct clksel div31_dpll3m2_clksel[] = {
489 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
493 /* DPLL3 output M2 - primary control point for CORE speed */
494 static struct clk dpll3_m2_ck = {
495 .name = "dpll3_m2_ck",
498 .init = &omap2_init_clksel_parent,
499 .clksel_reg = CM_CLKSEL1,
500 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
501 .clksel = div31_dpll3m2_clksel,
502 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
503 PARENT_CONTROLS_CLOCK,
504 .clkdm = { .name = "dpll3_clkdm" },
505 .round_rate = &omap2_clksel_round_rate,
506 .set_rate = &omap3_core_dpll_m2_set_rate,
507 .recalc = &omap2_clksel_recalc,
510 static struct clk core_ck = {
512 .parent = &dpll3_m2_ck,
513 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
514 PARENT_CONTROLS_CLOCK,
515 .clkdm = { .name = "cm_clkdm" },
516 .recalc = &followparent_recalc,
519 static struct clk dpll3_m2x2_ck = {
520 .name = "dpll3_m2x2_ck",
521 .parent = &dpll3_x2_ck,
522 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
523 PARENT_CONTROLS_CLOCK,
524 .clkdm = { .name = "dpll3_clkdm" },
525 .recalc = &followparent_recalc,
528 /* The PWRDN bit is apparently only available on 3430ES2 and above */
529 static const struct clksel div16_dpll3_clksel[] = {
530 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
534 /* This virtual clock is the source for dpll3_m3x2_ck */
535 static struct clk dpll3_m3_ck = {
536 .name = "dpll3_m3_ck",
538 .prcm_mod = OMAP3430_EMU_MOD,
539 .init = &omap2_init_clksel_parent,
540 .clksel_reg = CM_CLKSEL1,
541 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
542 .clksel = div16_dpll3_clksel,
543 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
544 PARENT_CONTROLS_CLOCK,
545 .clkdm = { .name = "dpll3_clkdm" },
546 .recalc = &omap2_clksel_recalc,
549 /* The PWRDN bit is apparently only available on 3430ES2 and above */
550 static struct clk dpll3_m3x2_ck = {
551 .name = "dpll3_m3x2_ck",
552 .parent = &dpll3_m3_ck,
554 .enable_reg = CM_CLKEN,
555 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
556 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
557 .clkdm = { .name = "dpll3_clkdm" },
558 .recalc = &omap3_clkoutx2_recalc,
561 static struct clk emu_core_alwon_ck = {
562 .name = "emu_core_alwon_ck",
563 .parent = &dpll3_m3x2_ck,
564 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
565 PARENT_CONTROLS_CLOCK,
566 .clkdm = { .name = "dpll3_clkdm" },
567 .recalc = &followparent_recalc,
571 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
573 static struct dpll_data dpll4_dd = {
574 .mult_div1_reg = CM_CLKSEL2,
575 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
576 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
577 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
578 .control_reg = CM_CLKEN,
579 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
580 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
581 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
582 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
583 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
584 .autoidle_reg = CM_AUTOIDLE,
585 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
586 .idlest_reg = CM_IDLEST,
587 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
588 .bypass_clk = &sys_ck,
589 .max_multiplier = OMAP3_MAX_DPLL_MULT,
591 .max_divider = OMAP3_MAX_DPLL_DIV,
592 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
595 static struct clk dpll4_ck = {
599 .dpll_data = &dpll4_dd,
600 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
601 .enable = &omap3_noncore_dpll_enable,
602 .disable = &omap3_noncore_dpll_disable,
603 .round_rate = &omap2_dpll_round_rate,
604 .set_rate = &omap3_noncore_dpll_set_rate,
605 .clkdm = { .name = "dpll4_clkdm" },
606 .recalc = &omap3_dpll_recalc,
610 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
611 * DPLL isn't bypassed --
612 * XXX does this serve any downstream clocks?
614 static struct clk dpll4_x2_ck = {
615 .name = "dpll4_x2_ck",
617 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
618 PARENT_CONTROLS_CLOCK,
619 .clkdm = { .name = "dpll4_clkdm" },
620 .recalc = &omap3_clkoutx2_recalc,
623 static const struct clksel div16_dpll4_clksel[] = {
624 { .parent = &dpll4_ck, .rates = div16_dpll_rates },
628 /* This virtual clock is the source for dpll4_m2x2_ck */
629 static struct clk dpll4_m2_ck = {
630 .name = "dpll4_m2_ck",
633 .init = &omap2_init_clksel_parent,
634 .clksel_reg = OMAP3430_CM_CLKSEL3,
635 .clksel_mask = OMAP3430_DIV_96M_MASK,
636 .clksel = div16_dpll4_clksel,
637 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
638 PARENT_CONTROLS_CLOCK,
639 .clkdm = { .name = "dpll4_clkdm" },
640 .recalc = &omap2_clksel_recalc,
643 /* The PWRDN bit is apparently only available on 3430ES2 and above */
644 static struct clk dpll4_m2x2_ck = {
645 .name = "dpll4_m2x2_ck",
646 .parent = &dpll4_m2_ck,
648 .enable_reg = CM_CLKEN,
649 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
650 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
651 .clkdm = { .name = "dpll4_clkdm" },
652 .recalc = &omap3_clkoutx2_recalc,
656 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
657 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
658 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
661 static struct clk omap_96m_alwon_fck = {
662 .name = "omap_96m_alwon_fck",
663 .parent = &dpll4_m2x2_ck,
664 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
665 PARENT_CONTROLS_CLOCK,
666 .clkdm = { .name = "prm_clkdm" },
667 .recalc = &followparent_recalc,
670 static struct clk cm_96m_fck = {
671 .name = "cm_96m_fck",
672 .parent = &omap_96m_alwon_fck,
673 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
674 PARENT_CONTROLS_CLOCK,
675 .clkdm = { .name = "cm_clkdm" },
676 .recalc = &followparent_recalc,
679 static const struct clksel_rate omap_96m_dpll_rates[] = {
680 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
684 static const struct clksel_rate omap_96m_sys_rates[] = {
685 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
689 static const struct clksel omap_96m_fck_clksel[] = {
690 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
691 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
695 static struct clk omap_96m_fck = {
696 .name = "omap_96m_fck",
699 .init = &omap2_init_clksel_parent,
700 .clksel_reg = CM_CLKSEL1,
701 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
702 .clksel = omap_96m_fck_clksel,
703 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
704 PARENT_CONTROLS_CLOCK,
705 .clkdm = { .name = "cm_clkdm" },
706 .recalc = &omap2_clksel_recalc,
709 /* This virtual clock is the source for dpll4_m3x2_ck */
710 static struct clk dpll4_m3_ck = {
711 .name = "dpll4_m3_ck",
713 .prcm_mod = OMAP3430_DSS_MOD,
714 .init = &omap2_init_clksel_parent,
715 .clksel_reg = CM_CLKSEL,
716 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
717 .clksel = div16_dpll4_clksel,
718 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
719 PARENT_CONTROLS_CLOCK,
720 .clkdm = { .name = "dpll4_clkdm" },
721 .recalc = &omap2_clksel_recalc,
724 /* The PWRDN bit is apparently only available on 3430ES2 and above */
725 static struct clk dpll4_m3x2_ck = {
726 .name = "dpll4_m3x2_ck",
727 .parent = &dpll4_m3_ck,
729 .init = &omap2_init_clksel_parent,
730 .enable_reg = CM_CLKEN,
731 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
732 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
733 .clkdm = { .name = "dpll4_clkdm" },
734 .recalc = &omap3_clkoutx2_recalc,
737 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
738 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
742 static const struct clksel_rate omap_54m_alt_rates[] = {
743 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
747 static const struct clksel omap_54m_clksel[] = {
748 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
749 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
753 static struct clk omap_54m_fck = {
754 .name = "omap_54m_fck",
756 .init = &omap2_init_clksel_parent,
757 .clksel_reg = CM_CLKSEL1,
758 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
759 .clksel = omap_54m_clksel,
760 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
761 PARENT_CONTROLS_CLOCK,
762 .clkdm = { .name = "cm_clkdm" },
763 .recalc = &omap2_clksel_recalc,
766 static const struct clksel_rate omap_48m_cm96m_rates[] = {
767 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
771 static const struct clksel_rate omap_48m_alt_rates[] = {
772 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
776 static const struct clksel omap_48m_clksel[] = {
777 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
778 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
782 static struct clk omap_48m_fck = {
783 .name = "omap_48m_fck",
785 .init = &omap2_init_clksel_parent,
786 .clksel_reg = CM_CLKSEL1,
787 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
788 .clksel = omap_48m_clksel,
789 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
790 PARENT_CONTROLS_CLOCK,
791 .clkdm = { .name = "cm_clkdm" },
792 .recalc = &omap2_clksel_recalc,
795 static struct clk omap_12m_fck = {
796 .name = "omap_12m_fck",
797 .parent = &omap_48m_fck,
799 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
800 PARENT_CONTROLS_CLOCK,
801 .clkdm = { .name = "cm_clkdm" },
802 .recalc = &omap2_fixed_divisor_recalc,
805 /* This virstual clock is the source for dpll4_m4x2_ck */
806 static struct clk dpll4_m4_ck = {
807 .name = "dpll4_m4_ck",
809 .prcm_mod = OMAP3430_DSS_MOD,
810 .init = &omap2_init_clksel_parent,
811 .clksel_reg = CM_CLKSEL,
812 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
813 .clksel = div16_dpll4_clksel,
814 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
815 PARENT_CONTROLS_CLOCK,
816 .clkdm = { .name = "dpll4_clkdm" },
817 .recalc = &omap2_clksel_recalc,
818 .set_rate = &omap2_clksel_set_rate,
819 .round_rate = &omap2_clksel_round_rate,
822 /* The PWRDN bit is apparently only available on 3430ES2 and above */
823 static struct clk dpll4_m4x2_ck = {
824 .name = "dpll4_m4x2_ck",
825 .parent = &dpll4_m4_ck,
827 .enable_reg = CM_CLKEN,
828 .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
829 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
830 .clkdm = { .name = "dpll4_clkdm" },
831 .recalc = &omap3_clkoutx2_recalc,
834 /* This virtual clock is the source for dpll4_m5x2_ck */
835 static struct clk dpll4_m5_ck = {
836 .name = "dpll4_m5_ck",
838 .prcm_mod = OMAP3430_CAM_MOD,
839 .init = &omap2_init_clksel_parent,
840 .clksel_reg = CM_CLKSEL,
841 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
842 .clksel = div16_dpll4_clksel,
843 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
844 PARENT_CONTROLS_CLOCK,
845 .clkdm = { .name = "dpll4_clkdm" },
846 .recalc = &omap2_clksel_recalc,
849 /* The PWRDN bit is apparently only available on 3430ES2 and above */
850 static struct clk dpll4_m5x2_ck = {
851 .name = "dpll4_m5x2_ck",
852 .parent = &dpll4_m5_ck,
854 .enable_reg = CM_CLKEN,
855 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
856 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
857 .clkdm = { .name = "dpll4_clkdm" },
858 .recalc = &omap3_clkoutx2_recalc,
861 /* This virtual clock is the source for dpll4_m6x2_ck */
862 static struct clk dpll4_m6_ck = {
863 .name = "dpll4_m6_ck",
865 .prcm_mod = OMAP3430_EMU_MOD,
866 .init = &omap2_init_clksel_parent,
867 .clksel_reg = CM_CLKSEL1,
868 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
869 .clksel = div16_dpll4_clksel,
870 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
871 PARENT_CONTROLS_CLOCK,
872 .clkdm = { .name = "dpll4_clkdm" },
873 .recalc = &omap2_clksel_recalc,
876 /* The PWRDN bit is apparently only available on 3430ES2 and above */
877 static struct clk dpll4_m6x2_ck = {
878 .name = "dpll4_m6x2_ck",
879 .parent = &dpll4_m6_ck,
881 .init = &omap2_init_clksel_parent,
882 .enable_reg = CM_CLKEN,
883 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
884 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
885 .clkdm = { .name = "dpll4_clkdm" },
886 .recalc = &omap3_clkoutx2_recalc,
889 static struct clk emu_per_alwon_ck = {
890 .name = "emu_per_alwon_ck",
891 .parent = &dpll4_m6x2_ck,
892 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
893 PARENT_CONTROLS_CLOCK,
894 .clkdm = { .name = "dpll4_clkdm" },
895 .recalc = &followparent_recalc,
899 /* Supplies 120MHz clock, USIM source clock */
902 static struct dpll_data dpll5_dd = {
903 .mult_div1_reg = OMAP3430ES2_CM_CLKSEL4,
904 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
905 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
906 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
907 .control_reg = OMAP3430ES2_CM_CLKEN2,
908 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
909 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
910 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
911 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
912 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
913 .autoidle_reg = OMAP3430ES2_CM_AUTOIDLE2_PLL,
914 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
915 .idlest_reg = CM_IDLEST2,
916 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
917 .bypass_clk = &sys_ck,
918 .max_multiplier = OMAP3_MAX_DPLL_MULT,
920 .max_divider = OMAP3_MAX_DPLL_DIV,
921 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
924 static struct clk dpll5_ck = {
928 .dpll_data = &dpll5_dd,
929 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
930 .enable = &omap3_noncore_dpll_enable,
931 .disable = &omap3_noncore_dpll_disable,
932 .round_rate = &omap2_dpll_round_rate,
933 .set_rate = &omap3_noncore_dpll_set_rate,
934 .clkdm = { .name = "dpll5_clkdm" },
935 .recalc = &omap3_dpll_recalc,
938 static const struct clksel div16_dpll5_clksel[] = {
939 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
943 static struct clk dpll5_m2_ck = {
944 .name = "dpll5_m2_ck",
947 .init = &omap2_init_clksel_parent,
948 .clksel_reg = OMAP3430ES2_CM_CLKSEL5,
949 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
950 .clksel = div16_dpll5_clksel,
951 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
952 PARENT_CONTROLS_CLOCK,
953 .clkdm = { .name = "dpll5_clkdm" },
954 .recalc = &omap2_clksel_recalc,
957 /* CM EXTERNAL CLOCK OUTPUTS */
959 static const struct clksel_rate clkout2_src_core_rates[] = {
960 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
964 static const struct clksel_rate clkout2_src_sys_rates[] = {
965 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
969 static const struct clksel_rate clkout2_src_96m_rates[] = {
970 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
974 static const struct clksel_rate clkout2_src_54m_rates[] = {
975 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
979 static const struct clksel clkout2_src_clksel[] = {
980 { .parent = &core_ck, .rates = clkout2_src_core_rates },
981 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
982 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
983 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
987 static struct clk clkout2_src_ck = {
988 .name = "clkout2_src_ck",
989 .prcm_mod = OMAP3430_CCR_MOD,
990 .init = &omap2_init_clksel_parent,
991 .enable_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
992 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
993 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
994 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
995 .clksel = clkout2_src_clksel,
996 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
997 .clkdm = { .name = "cm_clkdm" },
998 .recalc = &omap2_clksel_recalc,
1001 static const struct clksel_rate sys_clkout2_rates[] = {
1002 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1003 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1004 { .div = 4, .val = 2, .flags = RATE_IN_343X },
1005 { .div = 8, .val = 3, .flags = RATE_IN_343X },
1006 { .div = 16, .val = 4, .flags = RATE_IN_343X },
1010 static const struct clksel sys_clkout2_clksel[] = {
1011 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1015 static struct clk sys_clkout2 = {
1016 .name = "sys_clkout2",
1017 .prcm_mod = OMAP3430_CCR_MOD,
1018 .init = &omap2_init_clksel_parent,
1019 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
1020 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
1021 .clksel = sys_clkout2_clksel,
1022 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1023 .clkdm = { .name = "cm_clkdm" },
1024 .recalc = &omap2_clksel_recalc,
1027 /* CM OUTPUT CLOCKS */
1029 static struct clk corex2_fck = {
1030 .name = "corex2_fck",
1031 .parent = &dpll3_m2x2_ck,
1032 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1033 PARENT_CONTROLS_CLOCK,
1034 .clkdm = { .name = "cm_clkdm" },
1035 .recalc = &followparent_recalc,
1038 /* DPLL power domain clock controls */
1040 static const struct clksel_rate div4_rates[] = {
1041 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1042 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1043 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1047 static const struct clksel div4_core_clksel[] = {
1048 { .parent = &core_ck, .rates = div4_rates },
1052 static struct clk dpll1_fck = {
1053 .name = "dpll1_fck",
1055 .prcm_mod = MPU_MOD,
1056 .init = &omap2_init_clksel_parent,
1057 .clksel_reg = OMAP3430_CM_CLKSEL1_PLL,
1058 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1059 .clksel = div4_core_clksel,
1060 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1061 PARENT_CONTROLS_CLOCK,
1062 .clkdm = { .name = "cm_clkdm" },
1063 .recalc = &omap2_clksel_recalc,
1066 static struct clk mpu_ck = {
1068 .parent = &dpll1_x2m2_ck,
1069 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1070 PARENT_CONTROLS_CLOCK,
1071 .clkdm = { .name = "mpu_clkdm" },
1072 .recalc = &followparent_recalc,
1075 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1076 static const struct clksel_rate arm_fck_rates[] = {
1077 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1078 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1082 static const struct clksel arm_fck_clksel[] = {
1083 { .parent = &mpu_ck, .rates = arm_fck_rates },
1087 static struct clk arm_fck = {
1090 .prcm_mod = MPU_MOD,
1091 .init = &omap2_init_clksel_parent,
1092 .clksel_reg = OMAP3430_CM_IDLEST_PLL,
1093 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1094 .clksel = arm_fck_clksel,
1095 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1096 PARENT_CONTROLS_CLOCK,
1097 .clkdm = { .name = "mpu_clkdm" },
1098 .recalc = &omap2_clksel_recalc,
1101 /* XXX What about neon_clkdm ? */
1104 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1105 * although it is referenced - so this is a guess
1107 static struct clk emu_mpu_alwon_ck = {
1108 .name = "emu_mpu_alwon_ck",
1110 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1111 PARENT_CONTROLS_CLOCK,
1112 .clkdm = { .name = "mpu_clkdm" },
1113 .recalc = &followparent_recalc,
1116 static struct clk dpll2_fck = {
1117 .name = "dpll2_fck",
1119 .prcm_mod = OMAP3430_IVA2_MOD,
1120 .init = &omap2_init_clksel_parent,
1121 .clksel_reg = OMAP3430_CM_CLKSEL1_PLL,
1122 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1123 .clksel = div4_core_clksel,
1124 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1125 PARENT_CONTROLS_CLOCK,
1126 .clkdm = { .name = "cm_clkdm" },
1127 .recalc = &omap2_clksel_recalc,
1130 static struct clk iva2_ck = {
1132 .parent = &dpll2_m2_ck,
1133 .prcm_mod = OMAP3430_IVA2_MOD,
1134 .init = &omap2_init_clksel_parent,
1135 .enable_reg = CM_FCLKEN,
1136 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1137 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1138 .clkdm = { .name = "iva2_clkdm" },
1139 .recalc = &followparent_recalc,
1142 /* Common interface clocks */
1144 static const struct clksel div2_core_clksel[] = {
1145 { .parent = &core_ck, .rates = div2_rates },
1149 static struct clk l3_ick = {
1152 .prcm_mod = CORE_MOD,
1153 .init = &omap2_init_clksel_parent,
1154 .clksel_reg = CM_CLKSEL,
1155 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1156 .clksel = div2_core_clksel,
1157 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1158 PARENT_CONTROLS_CLOCK,
1159 .clkdm = { .name = "core_l3_clkdm" },
1160 .recalc = &omap2_clksel_recalc,
1163 static const struct clksel div2_l3_clksel[] = {
1164 { .parent = &l3_ick, .rates = div2_rates },
1168 static struct clk l4_ick = {
1171 .prcm_mod = CORE_MOD,
1172 .init = &omap2_init_clksel_parent,
1173 .clksel_reg = CM_CLKSEL,
1174 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1175 .clksel = div2_l3_clksel,
1176 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1177 PARENT_CONTROLS_CLOCK,
1178 .clkdm = { .name = "core_l4_clkdm" },
1179 .recalc = &omap2_clksel_recalc,
1183 static const struct clksel div2_l4_clksel[] = {
1184 { .parent = &l4_ick, .rates = div2_rates },
1188 static struct clk rm_ick = {
1191 .prcm_mod = WKUP_MOD,
1192 .init = &omap2_init_clksel_parent,
1193 .clksel_reg = CM_CLKSEL,
1194 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1195 .clksel = div2_l4_clksel,
1196 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1197 .clkdm = { .name = "cm_clkdm" },
1198 .recalc = &omap2_clksel_recalc,
1201 /* GFX power domain */
1203 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1205 static const struct clksel gfx_l3_clksel[] = {
1206 { .parent = &l3_ick, .rates = gfx_l3_rates },
1210 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1211 static struct clk gfx_l3_ck = {
1212 .name = "gfx_l3_ck",
1214 .prcm_mod = GFX_MOD,
1215 .init = &omap2_init_clksel_parent,
1216 .enable_reg = CM_ICLKEN,
1217 .enable_bit = OMAP_EN_GFX_SHIFT,
1218 .flags = CLOCK_IN_OMAP3430ES1,
1219 .clkdm = { .name = "gfx_3430es1_clkdm" },
1220 .recalc = &followparent_recalc,
1223 static struct clk gfx_l3_fck = {
1224 .name = "gfx_l3_fck",
1225 .parent = &gfx_l3_ck,
1226 .prcm_mod = GFX_MOD,
1227 .init = &omap2_init_clksel_parent,
1228 .clksel_reg = CM_CLKSEL,
1229 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1230 .clksel = gfx_l3_clksel,
1231 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1232 PARENT_CONTROLS_CLOCK,
1233 .clkdm = { .name = "gfx_3430es1_clkdm" },
1234 .recalc = &omap2_clksel_recalc,
1237 static struct clk gfx_l3_ick = {
1238 .name = "gfx_l3_ick",
1239 .parent = &gfx_l3_ck,
1240 .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1241 .clkdm = { .name = "gfx_3430es1_clkdm" },
1242 .recalc = &followparent_recalc,
1245 static struct clk gfx_cg1_ck = {
1246 .name = "gfx_cg1_ck",
1247 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1248 .prcm_mod = GFX_MOD,
1249 .enable_reg = CM_FCLKEN,
1250 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1251 .flags = CLOCK_IN_OMAP3430ES1,
1252 .clkdm = { .name = "gfx_3430es1_clkdm" },
1253 .recalc = &followparent_recalc,
1256 static struct clk gfx_cg2_ck = {
1257 .name = "gfx_cg2_ck",
1258 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1259 .prcm_mod = GFX_MOD,
1260 .enable_reg = CM_FCLKEN,
1261 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1262 .flags = CLOCK_IN_OMAP3430ES1,
1263 .clkdm = { .name = "gfx_3430es1_clkdm" },
1264 .recalc = &followparent_recalc,
1267 /* SGX power domain - 3430ES2 only */
1269 static const struct clksel_rate sgx_core_rates[] = {
1270 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1271 { .div = 4, .val = 1, .flags = RATE_IN_343X },
1272 { .div = 6, .val = 2, .flags = RATE_IN_343X },
1276 static const struct clksel_rate sgx_96m_rates[] = {
1277 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1281 static const struct clksel sgx_clksel[] = {
1282 { .parent = &core_ck, .rates = sgx_core_rates },
1283 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1287 static struct clk sgx_fck = {
1289 .init = &omap2_init_clksel_parent,
1290 .prcm_mod = OMAP3430ES2_SGX_MOD,
1291 .enable_reg = CM_FCLKEN,
1292 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1293 .clksel_reg = CM_CLKSEL,
1294 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1295 .clksel = sgx_clksel,
1296 .flags = CLOCK_IN_OMAP3430ES2,
1297 .clkdm = { .name = "sgx_clkdm" },
1298 .recalc = &omap2_clksel_recalc,
1301 static struct clk sgx_ick = {
1304 .prcm_mod = OMAP3430ES2_SGX_MOD,
1305 .enable_reg = CM_ICLKEN,
1306 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1307 .flags = CLOCK_IN_OMAP3430ES2,
1308 .clkdm = { .name = "sgx_clkdm" },
1309 .recalc = &followparent_recalc,
1312 /* CORE power domain */
1314 static struct clk d2d_26m_fck = {
1315 .name = "d2d_26m_fck",
1317 .prcm_mod = CORE_MOD,
1318 .enable_reg = CM_FCLKEN1,
1319 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1320 .flags = CLOCK_IN_OMAP3430ES1,
1321 .clkdm = { .name = "d2d_clkdm" },
1322 .recalc = &followparent_recalc,
1325 static const struct clksel omap343x_gpt_clksel[] = {
1326 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1327 { .parent = &sys_ck, .rates = gpt_sys_rates },
1331 static struct clk gpt10_fck = {
1332 .name = "gpt10_fck",
1334 .prcm_mod = CORE_MOD,
1335 .init = &omap2_init_clksel_parent,
1336 .enable_reg = CM_FCLKEN1,
1337 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1338 .idlest_bit = OMAP3430_ST_GPT10_SHIFT,
1339 .clksel_reg = CM_CLKSEL,
1340 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1341 .clksel = omap343x_gpt_clksel,
1342 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1343 .clkdm = { .name = "core_l4_clkdm" },
1344 .recalc = &omap2_clksel_recalc,
1347 static struct clk gpt11_fck = {
1348 .name = "gpt11_fck",
1350 .prcm_mod = CORE_MOD,
1351 .init = &omap2_init_clksel_parent,
1352 .enable_reg = CM_FCLKEN1,
1353 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1354 .idlest_bit = OMAP3430_ST_GPT11_SHIFT,
1355 .clksel_reg = CM_CLKSEL,
1356 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1357 .clksel = omap343x_gpt_clksel,
1358 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1359 .clkdm = { .name = "core_l4_clkdm" },
1360 .recalc = &omap2_clksel_recalc,
1363 static struct clk cpefuse_fck = {
1364 .name = "cpefuse_fck",
1366 .prcm_mod = CORE_MOD,
1367 .enable_reg = OMAP3430ES2_CM_FCLKEN3,
1368 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1369 .idlest_bit = OMAP3430ES2_ST_CPEFUSE_SHIFT,
1370 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1371 .clkdm = { .name = "cm_clkdm" },
1372 .recalc = &followparent_recalc,
1375 static struct clk ts_fck = {
1377 .parent = &omap_32k_fck,
1378 .prcm_mod = CORE_MOD,
1379 .enable_reg = OMAP3430ES2_CM_FCLKEN3,
1380 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1381 .flags = CLOCK_IN_OMAP3430ES2,
1382 .clkdm = { .name = "core_l4_clkdm" },
1383 .recalc = &followparent_recalc,
1386 static struct clk usbtll_fck = {
1387 .name = "usbtll_fck",
1388 .parent = &dpll5_m2_ck,
1389 .prcm_mod = CORE_MOD,
1390 .enable_reg = OMAP3430ES2_CM_FCLKEN3,
1391 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1392 .idlest_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1393 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1394 .clkdm = { .name = "core_l4_clkdm" },
1395 .recalc = &followparent_recalc,
1398 /* CORE 96M FCLK-derived clocks */
1400 static struct clk core_96m_fck = {
1401 .name = "core_96m_fck",
1402 .parent = &omap_96m_fck,
1403 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1404 PARENT_CONTROLS_CLOCK,
1405 .clkdm = { .name = "core_l4_clkdm" },
1406 .recalc = &followparent_recalc,
1409 static struct clk mmchs3_fck = {
1410 .name = "mmchs_fck",
1412 .parent = &core_96m_fck,
1413 .prcm_mod = CORE_MOD,
1414 .enable_reg = CM_FCLKEN1,
1415 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1416 .idlest_bit = OMAP3430ES2_ST_MMC3_SHIFT,
1417 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1418 .clkdm = { .name = "core_l4_clkdm" },
1419 .recalc = &followparent_recalc,
1422 static struct clk mmchs2_fck = {
1423 .name = "mmchs_fck",
1425 .parent = &core_96m_fck,
1426 .prcm_mod = CORE_MOD,
1427 .enable_reg = CM_FCLKEN1,
1428 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1429 .idlest_bit = OMAP3430_ST_MMC2_SHIFT,
1430 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1431 .clkdm = { .name = "core_l4_clkdm" },
1432 .recalc = &followparent_recalc,
1435 static struct clk mspro_fck = {
1436 .name = "mspro_fck",
1437 .parent = &core_96m_fck,
1438 .prcm_mod = CORE_MOD,
1439 .enable_reg = CM_FCLKEN1,
1440 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1441 .idlest_bit = OMAP3430_ST_MSPRO_SHIFT,
1442 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1443 .clkdm = { .name = "core_l4_clkdm" },
1444 .recalc = &followparent_recalc,
1447 static struct clk mmchs1_fck = {
1448 .name = "mmchs_fck",
1449 .parent = &core_96m_fck,
1450 .prcm_mod = CORE_MOD,
1451 .enable_reg = CM_FCLKEN1,
1452 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1453 .idlest_bit = OMAP3430_ST_MMC1_SHIFT,
1454 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1455 .clkdm = { .name = "core_l4_clkdm" },
1456 .recalc = &followparent_recalc,
1459 static struct clk i2c3_fck = {
1462 .parent = &core_96m_fck,
1463 .prcm_mod = CORE_MOD,
1464 .enable_reg = CM_FCLKEN1,
1465 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1466 .idlest_bit = OMAP3430_ST_I2C3_SHIFT,
1467 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1468 .clkdm = { .name = "core_l4_clkdm" },
1469 .recalc = &followparent_recalc,
1472 static struct clk i2c2_fck = {
1475 .parent = &core_96m_fck,
1476 .prcm_mod = CORE_MOD,
1477 .enable_reg = CM_FCLKEN1,
1478 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1479 .idlest_bit = OMAP3430_ST_I2C2_SHIFT,
1480 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1481 .clkdm = { .name = "core_l4_clkdm" },
1482 .recalc = &followparent_recalc,
1485 static struct clk i2c1_fck = {
1488 .parent = &core_96m_fck,
1489 .prcm_mod = CORE_MOD,
1490 .enable_reg = CM_FCLKEN1,
1491 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1492 .idlest_bit = OMAP3430_ST_I2C1_SHIFT,
1493 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1494 .clkdm = { .name = "core_l4_clkdm" },
1495 .recalc = &followparent_recalc,
1499 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1500 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1502 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1503 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1507 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1508 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1512 static const struct clksel mcbsp_15_clksel[] = {
1513 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1514 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1518 static struct clk mcbsp5_src_fck = {
1519 .name = "mcbsp_src_fck",
1521 .prcm_mod = CLK_REG_IN_SCM,
1522 .init = &omap2_init_clksel_parent,
1523 .clksel_reg = OMAP343X_CONTROL_DEVCONF1,
1524 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1525 .clksel = mcbsp_15_clksel,
1526 .flags = CLOCK_IN_OMAP343X,
1527 .clkdm = { .name = "core_l4_clkdm" },
1528 .recalc = &omap2_clksel_recalc,
1531 static struct clk mcbsp5_fck = {
1532 .name = "mcbsp_fck",
1534 .parent = &mcbsp5_src_fck,
1535 .prcm_mod = CORE_MOD,
1536 .enable_reg = CM_FCLKEN1,
1537 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1538 .idlest_bit = OMAP3430_ST_MCBSP5_SHIFT,
1539 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1540 .clkdm = { .name = "core_l4_clkdm" },
1541 .recalc = &followparent_recalc,
1544 static struct clk mcbsp1_src_fck = {
1545 .name = "mcbsp_src_fck",
1547 .prcm_mod = CLK_REG_IN_SCM,
1548 .init = &omap2_init_clksel_parent,
1549 .clksel_reg = OMAP2_CONTROL_DEVCONF0,
1550 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1551 .clksel = mcbsp_15_clksel,
1552 .flags = CLOCK_IN_OMAP343X,
1553 .clkdm = { .name = "core_l4_clkdm" },
1554 .recalc = &omap2_clksel_recalc,
1557 static struct clk mcbsp1_fck = {
1558 .name = "mcbsp_fck",
1560 .parent = &mcbsp1_src_fck,
1561 .prcm_mod = CORE_MOD,
1562 .enable_reg = CM_FCLKEN1,
1563 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1564 .idlest_bit = OMAP3430_ST_MCBSP1_SHIFT,
1565 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1566 .clkdm = { .name = "core_l4_clkdm" },
1567 .recalc = &followparent_recalc,
1570 /* CORE_48M_FCK-derived clocks */
1572 static struct clk core_48m_fck = {
1573 .name = "core_48m_fck",
1574 .parent = &omap_48m_fck,
1575 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1576 PARENT_CONTROLS_CLOCK,
1577 .clkdm = { .name = "core_l4_clkdm" },
1578 .recalc = &followparent_recalc,
1581 static struct clk mcspi4_fck = {
1582 .name = "mcspi_fck",
1584 .parent = &core_48m_fck,
1585 .prcm_mod = CORE_MOD,
1586 .enable_reg = CM_FCLKEN1,
1587 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1588 .idlest_bit = OMAP3430_ST_MCSPI4_SHIFT,
1589 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1590 .clkdm = { .name = "core_l4_clkdm" },
1591 .recalc = &followparent_recalc,
1594 static struct clk mcspi3_fck = {
1595 .name = "mcspi_fck",
1597 .parent = &core_48m_fck,
1598 .prcm_mod = CORE_MOD,
1599 .enable_reg = CM_FCLKEN1,
1600 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1601 .idlest_bit = OMAP3430_ST_MCSPI3_SHIFT,
1602 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1603 .clkdm = { .name = "core_l4_clkdm" },
1604 .recalc = &followparent_recalc,
1607 static struct clk mcspi2_fck = {
1608 .name = "mcspi_fck",
1610 .parent = &core_48m_fck,
1611 .prcm_mod = CORE_MOD,
1612 .enable_reg = CM_FCLKEN1,
1613 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1614 .idlest_bit = OMAP3430_ST_MCSPI2_SHIFT,
1615 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1616 .clkdm = { .name = "core_l4_clkdm" },
1617 .recalc = &followparent_recalc,
1620 static struct clk mcspi1_fck = {
1621 .name = "mcspi_fck",
1623 .parent = &core_48m_fck,
1624 .prcm_mod = CORE_MOD,
1625 .enable_reg = CM_FCLKEN1,
1626 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1627 .idlest_bit = OMAP3430_ST_MCSPI1_SHIFT,
1628 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1629 .clkdm = { .name = "core_l4_clkdm" },
1630 .recalc = &followparent_recalc,
1633 static struct clk uart2_fck = {
1634 .name = "uart2_fck",
1635 .parent = &core_48m_fck,
1636 .prcm_mod = CORE_MOD,
1637 .enable_reg = CM_FCLKEN1,
1638 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1639 .idlest_bit = OMAP3430_ST_UART2_SHIFT,
1640 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1641 .clkdm = { .name = "core_l4_clkdm" },
1642 .recalc = &followparent_recalc,
1645 static struct clk uart1_fck = {
1646 .name = "uart1_fck",
1647 .parent = &core_48m_fck,
1648 .prcm_mod = CORE_MOD,
1649 .enable_reg = CM_FCLKEN1,
1650 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1651 .idlest_bit = OMAP3430_ST_UART1_SHIFT,
1652 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1653 .clkdm = { .name = "core_l4_clkdm" },
1654 .recalc = &followparent_recalc,
1657 /* XXX doublecheck: is this idle or standby? */
1658 static struct clk fshostusb_fck = {
1659 .name = "fshostusb_fck",
1660 .parent = &core_48m_fck,
1661 .prcm_mod = CORE_MOD,
1662 .enable_reg = CM_FCLKEN1,
1663 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1664 .idlest_bit = OMAP3430ES1_ST_FSHOSTUSB_SHIFT,
1665 .flags = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
1666 .clkdm = { .name = "core_l4_clkdm" },
1667 .recalc = &followparent_recalc,
1670 /* CORE_12M_FCK based clocks */
1672 static struct clk core_12m_fck = {
1673 .name = "core_12m_fck",
1674 .parent = &omap_12m_fck,
1675 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1676 PARENT_CONTROLS_CLOCK,
1677 .clkdm = { .name = "core_l4_clkdm" },
1678 .recalc = &followparent_recalc,
1681 static struct clk hdq_fck = {
1683 .parent = &core_12m_fck,
1684 .prcm_mod = CORE_MOD,
1685 .enable_reg = CM_FCLKEN1,
1686 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1687 .idlest_bit = OMAP3430_ST_HDQ_SHIFT,
1688 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1689 .clkdm = { .name = "core_l4_clkdm" },
1690 .recalc = &followparent_recalc,
1693 /* DPLL3-derived clock */
1695 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1696 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1697 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1698 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1699 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1700 { .div = 6, .val = 6, .flags = RATE_IN_343X },
1701 { .div = 8, .val = 8, .flags = RATE_IN_343X },
1705 static const struct clksel ssi_ssr_clksel[] = {
1706 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1710 static struct clk ssi_ssr_fck_3430es1 = {
1711 .name = "ssi_ssr_fck",
1712 .init = &omap2_init_clksel_parent,
1713 .prcm_mod = CORE_MOD,
1714 .enable_reg = CM_FCLKEN1,
1715 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1716 .clksel_reg = CM_CLKSEL,
1717 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1718 .clksel = ssi_ssr_clksel,
1719 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
1720 .clkdm = { .name = "core_l4_clkdm" },
1721 .recalc = &omap2_clksel_recalc,
1724 static struct clk ssi_ssr_fck_3430es2 = {
1725 .name = "ssi_ssr_fck",
1726 .init = &omap2_init_clksel_parent,
1727 .prcm_mod = CORE_MOD,
1728 .enable_reg = CM_FCLKEN1,
1729 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1730 .idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
1731 .clksel_reg = CM_CLKSEL,
1732 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1733 .clksel = ssi_ssr_clksel,
1734 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | WAIT_READY,
1735 .clkdm = { .name = "core_l4_clkdm" },
1736 .recalc = &omap2_clksel_recalc,
1739 /* It's unfortunate that we need to duplicate this clock. */
1740 static struct clk ssi_sst_fck_3430es1 = {
1741 .name = "ssi_sst_fck",
1742 .parent = &ssi_ssr_fck_3430es1,
1744 .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1745 .clkdm = { .name = "core_l4_clkdm" },
1746 .recalc = &omap2_fixed_divisor_recalc,
1749 static struct clk ssi_sst_fck_3430es2 = {
1750 .name = "ssi_sst_fck",
1751 .parent = &ssi_ssr_fck_3430es2,
1753 .flags = CLOCK_IN_OMAP3430ES2 | PARENT_CONTROLS_CLOCK,
1754 .clkdm = { .name = "core_l4_clkdm" },
1755 .recalc = &omap2_fixed_divisor_recalc,
1760 /* CORE_L3_ICK based clocks */
1763 * XXX must add clk_enable/clk_disable for these if standard code won't
1766 static struct clk core_l3_ick = {
1767 .name = "core_l3_ick",
1769 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1770 PARENT_CONTROLS_CLOCK,
1771 .clkdm = { .name = "core_l3_clkdm" },
1772 .recalc = &followparent_recalc,
1775 static struct clk hsotgusb_ick_3430es1 = {
1776 .name = "hsotgusb_ick",
1777 .parent = &core_l3_ick,
1778 .prcm_mod = CORE_MOD,
1779 .enable_reg = CM_ICLKEN1,
1780 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1781 .flags = CLOCK_IN_OMAP3430ES1,
1782 .clkdm = { .name = "core_l3_clkdm" },
1783 .recalc = &followparent_recalc,
1786 static struct clk hsotgusb_ick_3430es2 = {
1787 .name = "hsotgusb_ick",
1788 .parent = &core_l3_ick,
1789 .prcm_mod = CORE_MOD,
1790 .enable_reg = CM_ICLKEN1,
1791 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1792 .idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1793 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1794 .clkdm = { .name = "core_l3_clkdm" },
1795 .recalc = &followparent_recalc,
1798 static struct clk sdrc_ick = {
1800 .parent = &core_l3_ick,
1801 .prcm_mod = CORE_MOD,
1802 .enable_reg = CM_ICLKEN1,
1803 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1804 .idlest_bit = OMAP3430_ST_SDRC_SHIFT,
1805 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT | WAIT_READY,
1806 .clkdm = { .name = "core_l3_clkdm" },
1807 .recalc = &followparent_recalc,
1810 static struct clk gpmc_fck = {
1812 .parent = &core_l3_ick,
1813 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1815 .clkdm = { .name = "core_l3_clkdm" },
1816 .recalc = &followparent_recalc,
1819 /* SECURITY_L3_ICK based clocks */
1821 static struct clk security_l3_ick = {
1822 .name = "security_l3_ick",
1824 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1825 PARENT_CONTROLS_CLOCK,
1826 .clkdm = { .name = "core_l3_clkdm" },
1827 .recalc = &followparent_recalc,
1830 static struct clk pka_ick = {
1832 .parent = &security_l3_ick,
1833 .prcm_mod = CORE_MOD,
1834 .enable_reg = CM_ICLKEN2,
1835 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1836 .idlest_bit = OMAP3430_ST_PKA_SHIFT,
1837 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1838 .clkdm = { .name = "core_l3_clkdm" },
1839 .recalc = &followparent_recalc,
1842 /* CORE_L4_ICK based clocks */
1844 static struct clk core_l4_ick = {
1845 .name = "core_l4_ick",
1847 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1848 PARENT_CONTROLS_CLOCK,
1849 .clkdm = { .name = "core_l4_clkdm" },
1850 .recalc = &followparent_recalc,
1853 static struct clk usbtll_ick = {
1854 .name = "usbtll_ick",
1855 .parent = &core_l4_ick,
1856 .prcm_mod = CORE_MOD,
1857 .enable_reg = CM_ICLKEN3,
1858 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1859 .idlest_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1860 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1861 .clkdm = { .name = "core_l4_clkdm" },
1862 .recalc = &followparent_recalc,
1865 static struct clk mmchs3_ick = {
1866 .name = "mmchs_ick",
1868 .parent = &core_l4_ick,
1869 .prcm_mod = CORE_MOD,
1870 .enable_reg = CM_ICLKEN1,
1871 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1872 .idlest_bit = OMAP3430ES2_ST_MMC3_SHIFT,
1873 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1874 .clkdm = { .name = "core_l4_clkdm" },
1875 .recalc = &followparent_recalc,
1878 /* Intersystem Communication Registers - chassis mode only */
1879 static struct clk icr_ick = {
1881 .parent = &core_l4_ick,
1882 .prcm_mod = CORE_MOD,
1883 .enable_reg = CM_ICLKEN1,
1884 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1885 .idlest_bit = OMAP3430_ST_ICR_SHIFT,
1886 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1887 .clkdm = { .name = "core_l4_clkdm" },
1888 .recalc = &followparent_recalc,
1891 static struct clk aes2_ick = {
1893 .parent = &core_l4_ick,
1894 .prcm_mod = CORE_MOD,
1895 .enable_reg = CM_ICLKEN1,
1896 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1897 .idlest_bit = OMAP3430_ST_AES2_SHIFT,
1898 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1899 .clkdm = { .name = "core_l4_clkdm" },
1900 .recalc = &followparent_recalc,
1903 static struct clk sha12_ick = {
1904 .name = "sha12_ick",
1905 .parent = &core_l4_ick,
1906 .prcm_mod = CORE_MOD,
1907 .enable_reg = CM_ICLKEN1,
1908 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1909 .idlest_bit = OMAP3430_ST_SHA12_SHIFT,
1910 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1911 .clkdm = { .name = "core_l4_clkdm" },
1912 .recalc = &followparent_recalc,
1915 static struct clk des2_ick = {
1917 .parent = &core_l4_ick,
1918 .prcm_mod = CORE_MOD,
1919 .enable_reg = CM_ICLKEN1,
1920 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1921 .idlest_bit = OMAP3430_ST_DES2_SHIFT,
1922 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1923 .clkdm = { .name = "core_l4_clkdm" },
1924 .recalc = &followparent_recalc,
1927 static struct clk mmchs2_ick = {
1928 .name = "mmchs_ick",
1930 .parent = &core_l4_ick,
1931 .prcm_mod = CORE_MOD,
1932 .enable_reg = CM_ICLKEN1,
1933 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1934 .idlest_bit = OMAP3430_ST_MMC2_SHIFT,
1935 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1936 .clkdm = { .name = "core_l4_clkdm" },
1937 .recalc = &followparent_recalc,
1940 static struct clk mmchs1_ick = {
1941 .name = "mmchs_ick",
1942 .parent = &core_l4_ick,
1943 .prcm_mod = CORE_MOD,
1944 .enable_reg = CM_ICLKEN1,
1945 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1946 .idlest_bit = OMAP3430_ST_MMC1_SHIFT,
1947 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1948 .clkdm = { .name = "core_l4_clkdm" },
1949 .recalc = &followparent_recalc,
1952 static struct clk mspro_ick = {
1953 .name = "mspro_ick",
1954 .parent = &core_l4_ick,
1955 .prcm_mod = CORE_MOD,
1956 .enable_reg = CM_ICLKEN1,
1957 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1958 .idlest_bit = OMAP3430_ST_MSPRO_SHIFT,
1959 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1960 .clkdm = { .name = "core_l4_clkdm" },
1961 .recalc = &followparent_recalc,
1964 static struct clk hdq_ick = {
1966 .parent = &core_l4_ick,
1967 .prcm_mod = CORE_MOD,
1968 .enable_reg = CM_ICLKEN1,
1969 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1970 .idlest_bit = OMAP3430_ST_HDQ_SHIFT,
1971 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1972 .clkdm = { .name = "core_l4_clkdm" },
1973 .recalc = &followparent_recalc,
1976 static struct clk mcspi4_ick = {
1977 .name = "mcspi_ick",
1979 .parent = &core_l4_ick,
1980 .prcm_mod = CORE_MOD,
1981 .enable_reg = CM_ICLKEN1,
1982 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1983 .idlest_bit = OMAP3430_ST_MCSPI4_SHIFT,
1984 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1985 .clkdm = { .name = "core_l4_clkdm" },
1986 .recalc = &followparent_recalc,
1989 static struct clk mcspi3_ick = {
1990 .name = "mcspi_ick",
1992 .parent = &core_l4_ick,
1993 .prcm_mod = CORE_MOD,
1994 .enable_reg = CM_ICLKEN1,
1995 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1996 .idlest_bit = OMAP3430_ST_MCSPI3_SHIFT,
1997 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1998 .clkdm = { .name = "core_l4_clkdm" },
1999 .recalc = &followparent_recalc,
2002 static struct clk mcspi2_ick = {
2003 .name = "mcspi_ick",
2005 .parent = &core_l4_ick,
2006 .prcm_mod = CORE_MOD,
2007 .enable_reg = CM_ICLKEN1,
2008 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
2009 .idlest_bit = OMAP3430_ST_MCSPI2_SHIFT,
2010 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2011 .clkdm = { .name = "core_l4_clkdm" },
2012 .recalc = &followparent_recalc,
2015 static struct clk mcspi1_ick = {
2016 .name = "mcspi_ick",
2018 .parent = &core_l4_ick,
2019 .prcm_mod = CORE_MOD,
2020 .enable_reg = CM_ICLKEN1,
2021 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
2022 .idlest_bit = OMAP3430_ST_MCSPI1_SHIFT,
2023 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2024 .clkdm = { .name = "core_l4_clkdm" },
2025 .recalc = &followparent_recalc,
2028 static struct clk i2c3_ick = {
2031 .parent = &core_l4_ick,
2032 .prcm_mod = CORE_MOD,
2033 .enable_reg = CM_ICLKEN1,
2034 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
2035 .idlest_bit = OMAP3430_ST_I2C3_SHIFT,
2036 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2037 .clkdm = { .name = "core_l4_clkdm" },
2038 .recalc = &followparent_recalc,
2041 static struct clk i2c2_ick = {
2044 .parent = &core_l4_ick,
2045 .prcm_mod = CORE_MOD,
2046 .enable_reg = CM_ICLKEN1,
2047 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
2048 .idlest_bit = OMAP3430_ST_I2C2_SHIFT,
2049 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2050 .clkdm = { .name = "core_l4_clkdm" },
2051 .recalc = &followparent_recalc,
2054 static struct clk i2c1_ick = {
2057 .parent = &core_l4_ick,
2058 .prcm_mod = CORE_MOD,
2059 .enable_reg = CM_ICLKEN1,
2060 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
2061 .idlest_bit = OMAP3430_ST_I2C1_SHIFT,
2062 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2063 .clkdm = { .name = "core_l4_clkdm" },
2064 .recalc = &followparent_recalc,
2067 static struct clk uart2_ick = {
2068 .name = "uart2_ick",
2069 .parent = &core_l4_ick,
2070 .prcm_mod = CORE_MOD,
2071 .enable_reg = CM_ICLKEN1,
2072 .enable_bit = OMAP3430_EN_UART2_SHIFT,
2073 .idlest_bit = OMAP3430_ST_UART2_SHIFT,
2074 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2075 .clkdm = { .name = "core_l4_clkdm" },
2076 .recalc = &followparent_recalc,
2079 static struct clk uart1_ick = {
2080 .name = "uart1_ick",
2081 .parent = &core_l4_ick,
2082 .prcm_mod = CORE_MOD,
2083 .enable_reg = CM_ICLKEN1,
2084 .enable_bit = OMAP3430_EN_UART1_SHIFT,
2085 .idlest_bit = OMAP3430_ST_UART1_SHIFT,
2086 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2087 .clkdm = { .name = "core_l4_clkdm" },
2088 .recalc = &followparent_recalc,
2091 static struct clk gpt11_ick = {
2092 .name = "gpt11_ick",
2093 .parent = &core_l4_ick,
2094 .prcm_mod = CORE_MOD,
2095 .enable_reg = CM_ICLKEN1,
2096 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
2097 .idlest_bit = OMAP3430_ST_GPT11_SHIFT,
2098 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2099 .clkdm = { .name = "core_l4_clkdm" },
2100 .recalc = &followparent_recalc,
2103 static struct clk gpt10_ick = {
2104 .name = "gpt10_ick",
2105 .parent = &core_l4_ick,
2106 .prcm_mod = CORE_MOD,
2107 .enable_reg = CM_ICLKEN1,
2108 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
2109 .idlest_bit = OMAP3430_ST_GPT10_SHIFT,
2110 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2111 .clkdm = { .name = "core_l4_clkdm" },
2112 .recalc = &followparent_recalc,
2115 static struct clk mcbsp5_ick = {
2116 .name = "mcbsp_ick",
2118 .parent = &core_l4_ick,
2119 .prcm_mod = CORE_MOD,
2120 .enable_reg = CM_ICLKEN1,
2121 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
2122 .idlest_bit = OMAP3430_ST_MCBSP5_SHIFT,
2123 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2124 .clkdm = { .name = "core_l4_clkdm" },
2125 .recalc = &followparent_recalc,
2128 static struct clk mcbsp1_ick = {
2129 .name = "mcbsp_ick",
2131 .parent = &core_l4_ick,
2132 .prcm_mod = CORE_MOD,
2133 .enable_reg = CM_ICLKEN1,
2134 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2135 .idlest_bit = OMAP3430_ST_MCBSP1_SHIFT,
2136 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2137 .clkdm = { .name = "core_l4_clkdm" },
2138 .recalc = &followparent_recalc,
2141 static struct clk fac_ick = {
2143 .parent = &core_l4_ick,
2144 .prcm_mod = CORE_MOD,
2145 .enable_reg = CM_ICLKEN1,
2146 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
2147 .idlest_bit = OMAP3430ES1_ST_FAC_SHIFT,
2148 .flags = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
2149 .clkdm = { .name = "core_l4_clkdm" },
2150 .recalc = &followparent_recalc,
2153 static struct clk mailboxes_ick = {
2154 .name = "mailboxes_ick",
2155 .parent = &core_l4_ick,
2156 .prcm_mod = CORE_MOD,
2157 .enable_reg = CM_ICLKEN1,
2158 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2159 .idlest_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2160 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2161 .clkdm = { .name = "core_l4_clkdm" },
2162 .recalc = &followparent_recalc,
2165 static struct clk omapctrl_ick = {
2166 .name = "omapctrl_ick",
2167 .parent = &core_l4_ick,
2168 .prcm_mod = CORE_MOD,
2169 .enable_reg = CM_ICLKEN1,
2170 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2171 .idlest_bit = OMAP3430_ST_OMAPCTRL_SHIFT,
2172 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT | WAIT_READY,
2173 .clkdm = { .name = "core_l4_clkdm" },
2174 .recalc = &followparent_recalc,
2177 /* SSI_L4_ICK based clocks */
2179 static struct clk ssi_l4_ick = {
2180 .name = "ssi_l4_ick",
2182 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2183 PARENT_CONTROLS_CLOCK,
2184 .clkdm = { .name = "core_l4_clkdm" },
2185 .recalc = &followparent_recalc,
2188 static struct clk ssi_ick_3430es1 = {
2190 .parent = &ssi_l4_ick,
2191 .prcm_mod = CORE_MOD,
2192 .enable_reg = CM_ICLKEN1,
2193 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2194 .flags = CLOCK_IN_OMAP3430ES1,
2195 .clkdm = { .name = "core_l4_clkdm" },
2196 .recalc = &followparent_recalc,
2199 static struct clk ssi_ick_3430es2 = {
2201 .parent = &ssi_l4_ick,
2202 .prcm_mod = CORE_MOD,
2203 .enable_reg = CM_ICLKEN1,
2204 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2205 .idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
2206 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2207 .clkdm = { .name = "core_l4_clkdm" },
2208 .recalc = &followparent_recalc,
2212 * REVISIT: Technically the TRM claims that this is CORE_CLK based,
2213 * but l4_ick makes more sense to me
2215 static const struct clksel usb_l4_clksel[] = {
2216 { .parent = &l4_ick, .rates = div2_rates },
2220 static struct clk usb_l4_ick = {
2221 .name = "usb_l4_ick",
2223 .prcm_mod = CORE_MOD,
2224 .init = &omap2_init_clksel_parent,
2225 .enable_reg = CM_ICLKEN1,
2226 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2227 .idlest_bit = OMAP3430ES1_ST_FSHOSTUSB_SHIFT,
2228 .clksel_reg = CM_CLKSEL,
2229 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2230 .clksel = usb_l4_clksel,
2231 .flags = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
2232 .clkdm = { .name = "core_l4_clkdm" },
2233 .recalc = &omap2_clksel_recalc,
2236 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2238 /* SECURITY_L4_ICK2 based clocks */
2240 static struct clk security_l4_ick2 = {
2241 .name = "security_l4_ick2",
2243 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2244 PARENT_CONTROLS_CLOCK,
2245 .clkdm = { .name = "core_l4_clkdm" },
2246 .recalc = &followparent_recalc,
2249 static struct clk aes1_ick = {
2251 .parent = &security_l4_ick2,
2252 .prcm_mod = CORE_MOD,
2253 .enable_reg = CM_ICLKEN2,
2254 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2255 .idlest_bit = OMAP3430_ST_AES1_SHIFT,
2256 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2257 .clkdm = { .name = "core_l4_clkdm" },
2258 .recalc = &followparent_recalc,
2261 static struct clk rng_ick = {
2263 .parent = &security_l4_ick2,
2264 .prcm_mod = CORE_MOD,
2265 .enable_reg = CM_ICLKEN2,
2266 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2267 .idlest_bit = OMAP3430_ST_RNG_SHIFT,
2268 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2269 .clkdm = { .name = "core_l4_clkdm" },
2270 .recalc = &followparent_recalc,
2273 static struct clk sha11_ick = {
2274 .name = "sha11_ick",
2275 .parent = &security_l4_ick2,
2276 .prcm_mod = CORE_MOD,
2277 .enable_reg = CM_ICLKEN2,
2278 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2279 .idlest_bit = OMAP3430_ST_SHA11_SHIFT,
2280 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2281 .clkdm = { .name = "core_l4_clkdm" },
2282 .recalc = &followparent_recalc,
2285 static struct clk des1_ick = {
2287 .parent = &security_l4_ick2,
2288 .prcm_mod = CORE_MOD,
2289 .enable_reg = CM_ICLKEN2,
2290 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2291 .idlest_bit = OMAP3430_ST_DES1_SHIFT,
2292 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2293 .clkdm = { .name = "core_l4_clkdm" },
2294 .recalc = &followparent_recalc,
2298 static struct clk dss1_alwon_fck_3430es1 = {
2299 .name = "dss1_alwon_fck",
2300 .parent = &dpll4_m4x2_ck,
2301 .prcm_mod = OMAP3430_DSS_MOD,
2302 .enable_reg = CM_FCLKEN,
2303 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2304 .flags = CLOCK_IN_OMAP3430ES1,
2305 .clkdm = { .name = "dss_clkdm" },
2306 .recalc = &followparent_recalc,
2309 static struct clk dss1_alwon_fck_3430es2 = {
2310 .name = "dss1_alwon_fck",
2311 .parent = &dpll4_m4x2_ck,
2312 .init = &omap2_init_clksel_parent,
2313 .prcm_mod = OMAP3430_DSS_MOD,
2314 .enable_reg = CM_FCLKEN,
2315 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2316 .idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
2317 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2318 .clkdm = { .name = "dss_clkdm" },
2319 .recalc = &followparent_recalc,
2322 static struct clk dss_tv_fck = {
2323 .name = "dss_tv_fck",
2324 .parent = &omap_54m_fck,
2325 .prcm_mod = OMAP3430_DSS_MOD,
2326 .enable_reg = CM_FCLKEN,
2327 .enable_bit = OMAP3430_EN_TV_SHIFT,
2328 .flags = CLOCK_IN_OMAP343X,
2329 .clkdm = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */
2330 .recalc = &followparent_recalc,
2333 static struct clk dss_96m_fck = {
2334 .name = "dss_96m_fck",
2335 .parent = &omap_96m_fck,
2336 .prcm_mod = OMAP3430_DSS_MOD,
2337 .enable_reg = CM_FCLKEN,
2338 .enable_bit = OMAP3430_EN_TV_SHIFT,
2339 .flags = CLOCK_IN_OMAP343X,
2340 .clkdm = { .name = "dss_clkdm" },
2341 .recalc = &followparent_recalc,
2344 static struct clk dss2_alwon_fck = {
2345 .name = "dss2_alwon_fck",
2347 .prcm_mod = OMAP3430_DSS_MOD,
2348 .enable_reg = CM_FCLKEN,
2349 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2350 .flags = CLOCK_IN_OMAP343X,
2351 .clkdm = { .name = "dss_clkdm" },
2352 .recalc = &followparent_recalc,
2355 static struct clk dss_ick_3430es1 = {
2356 /* Handles both L3 and L4 clocks */
2359 .prcm_mod = OMAP3430_DSS_MOD,
2360 .enable_reg = CM_ICLKEN,
2361 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2362 .flags = CLOCK_IN_OMAP3430ES1,
2363 .clkdm = { .name = "dss_clkdm" },
2364 .recalc = &followparent_recalc,
2367 static struct clk dss_ick_3430es2 = {
2368 /* Handles both L3 and L4 clocks */
2371 .prcm_mod = OMAP3430_DSS_MOD,
2372 .enable_reg = CM_ICLKEN,
2373 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2374 .idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
2375 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2376 .clkdm = { .name = "dss_clkdm" },
2377 .recalc = &followparent_recalc,
2382 static struct clk cam_mclk = {
2384 .parent = &dpll4_m5x2_ck,
2385 .prcm_mod = OMAP3430_CAM_MOD,
2386 .enable_reg = CM_FCLKEN,
2387 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2388 .flags = CLOCK_IN_OMAP343X,
2389 .clkdm = { .name = "cam_clkdm" },
2390 .recalc = &followparent_recalc,
2393 static struct clk cam_ick = {
2394 /* Handles both L3 and L4 clocks */
2397 .prcm_mod = OMAP3430_CAM_MOD,
2398 .enable_reg = CM_ICLKEN,
2399 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2400 .flags = CLOCK_IN_OMAP343X,
2401 .clkdm = { .name = "cam_clkdm" },
2402 .recalc = &followparent_recalc,
2405 static struct clk csi2_96m_fck = {
2406 .name = "csi2_96m_fck",
2407 .parent = &core_96m_fck,
2408 .prcm_mod = OMAP3430_CAM_MOD,
2409 .enable_reg = CM_FCLKEN,
2410 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
2411 .flags = CLOCK_IN_OMAP343X,
2412 .clkdm = { .name = "cam_clkdm" },
2413 .recalc = &followparent_recalc,
2416 /* USBHOST - 3430ES2 only */
2418 static struct clk usbhost_120m_fck = {
2419 .name = "usbhost_120m_fck",
2420 .parent = &dpll5_m2_ck,
2421 .prcm_mod = OMAP3430ES2_USBHOST_MOD,
2422 .enable_reg = CM_FCLKEN,
2423 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2424 .flags = CLOCK_IN_OMAP3430ES2,
2425 .clkdm = { .name = "usbhost_clkdm" },
2426 .recalc = &followparent_recalc,
2429 static struct clk usbhost_48m_fck = {
2430 .name = "usbhost_48m_fck",
2431 .parent = &omap_48m_fck,
2432 .prcm_mod = OMAP3430ES2_USBHOST_MOD,
2433 .enable_reg = CM_FCLKEN,
2434 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2435 .idlest_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
2436 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2437 .clkdm = { .name = "usbhost_clkdm" },
2438 .recalc = &followparent_recalc,
2441 static struct clk usbhost_ick = {
2442 /* Handles both L3 and L4 clocks */
2443 .name = "usbhost_ick",
2445 .prcm_mod = OMAP3430ES2_USBHOST_MOD,
2446 .enable_reg = CM_ICLKEN,
2447 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2448 .idlest_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
2449 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2450 .clkdm = { .name = "usbhost_clkdm" },
2451 .recalc = &followparent_recalc,
2456 static const struct clksel_rate usim_96m_rates[] = {
2457 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2458 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2459 { .div = 8, .val = 5, .flags = RATE_IN_343X },
2460 { .div = 10, .val = 6, .flags = RATE_IN_343X },
2464 static const struct clksel_rate usim_120m_rates[] = {
2465 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
2466 { .div = 8, .val = 8, .flags = RATE_IN_343X },
2467 { .div = 16, .val = 9, .flags = RATE_IN_343X },
2468 { .div = 20, .val = 10, .flags = RATE_IN_343X },
2472 static const struct clksel usim_clksel[] = {
2473 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2474 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
2475 { .parent = &sys_ck, .rates = div2_rates },
2480 static struct clk usim_fck = {
2482 .prcm_mod = WKUP_MOD,
2483 .init = &omap2_init_clksel_parent,
2484 .enable_reg = CM_FCLKEN,
2485 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2486 .idlest_bit = OMAP3430ES2_ST_USIMOCP_SHIFT,
2487 .clksel_reg = CM_CLKSEL,
2488 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2489 .clksel = usim_clksel,
2490 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2491 .clkdm = { .name = "prm_clkdm" },
2492 .recalc = &omap2_clksel_recalc,
2495 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2496 static struct clk gpt1_fck = {
2498 .prcm_mod = WKUP_MOD,
2499 .init = &omap2_init_clksel_parent,
2500 .enable_reg = CM_FCLKEN,
2501 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2502 .idlest_bit = OMAP3430_ST_GPT1_SHIFT,
2503 .clksel_reg = CM_CLKSEL,
2504 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2505 .clksel = omap343x_gpt_clksel,
2506 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2507 .clkdm = { .name = "prm_clkdm" },
2508 .recalc = &omap2_clksel_recalc,
2511 static struct clk wkup_32k_fck = {
2512 .name = "wkup_32k_fck",
2513 .parent = &omap_32k_fck,
2514 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2515 .clkdm = { .name = "prm_clkdm" },
2516 .recalc = &followparent_recalc,
2519 static struct clk gpio1_dbck = {
2520 .name = "gpio1_dbck",
2521 .parent = &wkup_32k_fck,
2522 .prcm_mod = WKUP_MOD,
2523 .enable_reg = CM_FCLKEN,
2524 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2525 .idlest_bit = OMAP3430_ST_GPIO1_SHIFT,
2526 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2527 .clkdm = { .name = "prm_clkdm" },
2528 .recalc = &followparent_recalc,
2531 static struct clk wdt2_fck = {
2533 .parent = &wkup_32k_fck,
2534 .prcm_mod = WKUP_MOD,
2535 .enable_reg = CM_FCLKEN,
2536 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2537 .idlest_bit = OMAP3430_ST_WDT2_SHIFT,
2538 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2539 .clkdm = { .name = "prm_clkdm" },
2540 .recalc = &followparent_recalc,
2543 static struct clk wkup_l4_ick = {
2544 .name = "wkup_l4_ick",
2546 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2547 .clkdm = { .name = "prm_clkdm" },
2548 .recalc = &followparent_recalc,
2551 static struct clk usim_ick = {
2553 .parent = &wkup_l4_ick,
2554 .prcm_mod = WKUP_MOD,
2555 .enable_reg = CM_ICLKEN,
2556 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2557 .idlest_bit = OMAP3430ES2_ST_USIMOCP_SHIFT,
2558 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2559 .clkdm = { .name = "prm_clkdm" },
2560 .recalc = &followparent_recalc,
2563 static struct clk wdt2_ick = {
2565 .parent = &wkup_l4_ick,
2566 .prcm_mod = WKUP_MOD,
2567 .enable_reg = CM_ICLKEN,
2568 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2569 .idlest_bit = OMAP3430_ST_WDT2_SHIFT,
2570 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2571 .clkdm = { .name = "prm_clkdm" },
2572 .recalc = &followparent_recalc,
2575 static struct clk wdt1_ick = {
2577 .parent = &wkup_l4_ick,
2578 .prcm_mod = WKUP_MOD,
2579 .enable_reg = CM_ICLKEN,
2580 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2581 .idlest_bit = OMAP3430_ST_WDT1_SHIFT,
2582 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2583 .clkdm = { .name = "prm_clkdm" },
2584 .recalc = &followparent_recalc,
2587 static struct clk gpio1_ick = {
2588 .name = "gpio1_ick",
2589 .parent = &wkup_l4_ick,
2590 .prcm_mod = WKUP_MOD,
2591 .enable_reg = CM_ICLKEN,
2592 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2593 .idlest_bit = OMAP3430_ST_GPIO1_SHIFT,
2594 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2595 .clkdm = { .name = "prm_clkdm" },
2596 .recalc = &followparent_recalc,
2599 static struct clk omap_32ksync_ick = {
2600 .name = "omap_32ksync_ick",
2601 .parent = &wkup_l4_ick,
2602 .prcm_mod = WKUP_MOD,
2603 .enable_reg = CM_ICLKEN,
2604 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2605 .idlest_bit = OMAP3430_ST_32KSYNC_SHIFT,
2606 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2607 .clkdm = { .name = "prm_clkdm" },
2608 .recalc = &followparent_recalc,
2611 static struct clk gpt12_ick = {
2612 .name = "gpt12_ick",
2613 .parent = &wkup_l4_ick,
2614 .prcm_mod = WKUP_MOD,
2615 .enable_reg = CM_ICLKEN,
2616 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2617 .idlest_bit = OMAP3430_ST_GPT12_SHIFT,
2618 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2619 .clkdm = { .name = "prm_clkdm" },
2620 .recalc = &followparent_recalc,
2623 static struct clk gpt1_ick = {
2625 .parent = &wkup_l4_ick,
2626 .prcm_mod = WKUP_MOD,
2627 .enable_reg = CM_ICLKEN,
2628 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2629 .idlest_bit = OMAP3430_ST_GPT1_SHIFT,
2630 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2631 .clkdm = { .name = "prm_clkdm" },
2632 .recalc = &followparent_recalc,
2637 /* PER clock domain */
2639 static struct clk per_96m_fck = {
2640 .name = "per_96m_fck",
2641 .parent = &omap_96m_alwon_fck,
2642 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2643 PARENT_CONTROLS_CLOCK,
2644 .clkdm = { .name = "per_clkdm" },
2645 .recalc = &followparent_recalc,
2648 static struct clk per_48m_fck = {
2649 .name = "per_48m_fck",
2650 .parent = &omap_48m_fck,
2651 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2652 PARENT_CONTROLS_CLOCK,
2653 .clkdm = { .name = "per_clkdm" },
2654 .recalc = &followparent_recalc,
2657 static struct clk uart3_fck = {
2658 .name = "uart3_fck",
2659 .parent = &per_48m_fck,
2660 .prcm_mod = OMAP3430_PER_MOD,
2661 .enable_reg = CM_FCLKEN,
2662 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2663 .idlest_bit = OMAP3430_ST_UART3_SHIFT,
2664 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2665 .clkdm = { .name = "per_clkdm" },
2666 .recalc = &followparent_recalc,
2669 static struct clk gpt2_fck = {
2671 .prcm_mod = OMAP3430_PER_MOD,
2672 .init = &omap2_init_clksel_parent,
2673 .enable_reg = CM_FCLKEN,
2674 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2675 .idlest_bit = OMAP3430_ST_GPT2_SHIFT,
2676 .clksel_reg = CM_CLKSEL,
2677 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2678 .clksel = omap343x_gpt_clksel,
2679 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2680 .clkdm = { .name = "per_clkdm" },
2681 .recalc = &omap2_clksel_recalc,
2684 static struct clk gpt3_fck = {
2686 .prcm_mod = OMAP3430_PER_MOD,
2687 .init = &omap2_init_clksel_parent,
2688 .enable_reg = CM_FCLKEN,
2689 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2690 .idlest_bit = OMAP3430_ST_GPT3_SHIFT,
2691 .clksel_reg = CM_CLKSEL,
2692 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2693 .clksel = omap343x_gpt_clksel,
2694 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2695 .clkdm = { .name = "per_clkdm" },
2696 .recalc = &omap2_clksel_recalc,
2699 static struct clk gpt4_fck = {
2701 .prcm_mod = OMAP3430_PER_MOD,
2702 .init = &omap2_init_clksel_parent,
2703 .enable_reg = CM_FCLKEN,
2704 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2705 .idlest_bit = OMAP3430_ST_GPT4_SHIFT,
2706 .clksel_reg = CM_CLKSEL,
2707 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2708 .clksel = omap343x_gpt_clksel,
2709 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2710 .clkdm = { .name = "per_clkdm" },
2711 .recalc = &omap2_clksel_recalc,
2714 static struct clk gpt5_fck = {
2716 .prcm_mod = OMAP3430_PER_MOD,
2717 .init = &omap2_init_clksel_parent,
2718 .enable_reg = CM_FCLKEN,
2719 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2720 .idlest_bit = OMAP3430_ST_GPT5_SHIFT,
2721 .clksel_reg = CM_CLKSEL,
2722 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2723 .clksel = omap343x_gpt_clksel,
2724 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2725 .clkdm = { .name = "per_clkdm" },
2726 .recalc = &omap2_clksel_recalc,
2729 static struct clk gpt6_fck = {
2731 .prcm_mod = OMAP3430_PER_MOD,
2732 .init = &omap2_init_clksel_parent,
2733 .enable_reg = CM_FCLKEN,
2734 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2735 .idlest_bit = OMAP3430_ST_GPT6_SHIFT,
2736 .clksel_reg = CM_CLKSEL,
2737 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2738 .clksel = omap343x_gpt_clksel,
2739 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2740 .clkdm = { .name = "per_clkdm" },
2741 .recalc = &omap2_clksel_recalc,
2744 static struct clk gpt7_fck = {
2746 .prcm_mod = OMAP3430_PER_MOD,
2747 .init = &omap2_init_clksel_parent,
2748 .enable_reg = CM_FCLKEN,
2749 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2750 .idlest_bit = OMAP3430_ST_GPT7_SHIFT,
2751 .clksel_reg = CM_CLKSEL,
2752 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2753 .clksel = omap343x_gpt_clksel,
2754 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2755 .clkdm = { .name = "per_clkdm" },
2756 .recalc = &omap2_clksel_recalc,
2759 static struct clk gpt8_fck = {
2761 .prcm_mod = OMAP3430_PER_MOD,
2762 .init = &omap2_init_clksel_parent,
2763 .enable_reg = CM_FCLKEN,
2764 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2765 .idlest_bit = OMAP3430_ST_GPT8_SHIFT,
2766 .clksel_reg = CM_CLKSEL,
2767 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2768 .clksel = omap343x_gpt_clksel,
2769 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2770 .clkdm = { .name = "per_clkdm" },
2771 .recalc = &omap2_clksel_recalc,
2774 static struct clk gpt9_fck = {
2776 .prcm_mod = OMAP3430_PER_MOD,
2777 .init = &omap2_init_clksel_parent,
2778 .enable_reg = CM_FCLKEN,
2779 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2780 .idlest_bit = OMAP3430_ST_GPT9_SHIFT,
2781 .clksel_reg = CM_CLKSEL,
2782 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2783 .clksel = omap343x_gpt_clksel,
2784 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2785 .clkdm = { .name = "per_clkdm" },
2786 .recalc = &omap2_clksel_recalc,
2789 static struct clk per_32k_alwon_fck = {
2790 .name = "per_32k_alwon_fck",
2791 .parent = &omap_32k_fck,
2792 .clkdm = { .name = "per_clkdm" },
2793 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2794 .recalc = &followparent_recalc,
2797 static struct clk gpio6_dbck = {
2798 .name = "gpio6_dbck",
2799 .parent = &per_32k_alwon_fck,
2800 .prcm_mod = OMAP3430_PER_MOD,
2801 .enable_reg = CM_FCLKEN,
2802 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2803 .idlest_bit = OMAP3430_ST_GPIO6_SHIFT,
2804 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2805 .clkdm = { .name = "per_clkdm" },
2806 .recalc = &followparent_recalc,
2809 static struct clk gpio5_dbck = {
2810 .name = "gpio5_dbck",
2811 .parent = &per_32k_alwon_fck,
2812 .prcm_mod = OMAP3430_PER_MOD,
2813 .enable_reg = CM_FCLKEN,
2814 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2815 .idlest_bit = OMAP3430_ST_GPIO5_SHIFT,
2816 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2817 .clkdm = { .name = "per_clkdm" },
2818 .recalc = &followparent_recalc,
2821 static struct clk gpio4_dbck = {
2822 .name = "gpio4_dbck",
2823 .parent = &per_32k_alwon_fck,
2824 .prcm_mod = OMAP3430_PER_MOD,
2825 .enable_reg = CM_FCLKEN,
2826 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2827 .idlest_bit = OMAP3430_ST_GPIO4_SHIFT,
2828 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2829 .clkdm = { .name = "per_clkdm" },
2830 .recalc = &followparent_recalc,
2833 static struct clk gpio3_dbck = {
2834 .name = "gpio3_dbck",
2835 .parent = &per_32k_alwon_fck,
2836 .prcm_mod = OMAP3430_PER_MOD,
2837 .enable_reg = CM_FCLKEN,
2838 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2839 .idlest_bit = OMAP3430_ST_GPIO3_SHIFT,
2840 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2841 .clkdm = { .name = "per_clkdm" },
2842 .recalc = &followparent_recalc,
2845 static struct clk gpio2_dbck = {
2846 .name = "gpio2_dbck",
2847 .parent = &per_32k_alwon_fck,
2848 .prcm_mod = OMAP3430_PER_MOD,
2849 .enable_reg = CM_FCLKEN,
2850 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2851 .idlest_bit = OMAP3430_ST_GPIO2_SHIFT,
2852 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2853 .clkdm = { .name = "per_clkdm" },
2854 .recalc = &followparent_recalc,
2857 static struct clk wdt3_fck = {
2859 .parent = &per_32k_alwon_fck,
2860 .prcm_mod = OMAP3430_PER_MOD,
2861 .enable_reg = CM_FCLKEN,
2862 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2863 .idlest_bit = OMAP3430_ST_WDT3_SHIFT,
2864 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2865 .clkdm = { .name = "per_clkdm" },
2866 .recalc = &followparent_recalc,
2869 static struct clk per_l4_ick = {
2870 .name = "per_l4_ick",
2872 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2873 PARENT_CONTROLS_CLOCK,
2874 .clkdm = { .name = "per_clkdm" },
2875 .recalc = &followparent_recalc,
2878 static struct clk gpio6_ick = {
2879 .name = "gpio6_ick",
2880 .parent = &per_l4_ick,
2881 .prcm_mod = OMAP3430_PER_MOD,
2882 .enable_reg = CM_ICLKEN,
2883 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2884 .idlest_bit = OMAP3430_ST_GPIO6_SHIFT,
2885 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2886 .clkdm = { .name = "per_clkdm" },
2887 .recalc = &followparent_recalc,
2890 static struct clk gpio5_ick = {
2891 .name = "gpio5_ick",
2892 .parent = &per_l4_ick,
2893 .prcm_mod = OMAP3430_PER_MOD,
2894 .enable_reg = CM_ICLKEN,
2895 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2896 .idlest_bit = OMAP3430_ST_GPIO5_SHIFT,
2897 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2898 .clkdm = { .name = "per_clkdm" },
2899 .recalc = &followparent_recalc,
2902 static struct clk gpio4_ick = {
2903 .name = "gpio4_ick",
2904 .parent = &per_l4_ick,
2905 .prcm_mod = OMAP3430_PER_MOD,
2906 .enable_reg = CM_ICLKEN,
2907 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2908 .idlest_bit = OMAP3430_ST_GPIO4_SHIFT,
2909 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2910 .clkdm = { .name = "per_clkdm" },
2911 .recalc = &followparent_recalc,
2914 static struct clk gpio3_ick = {
2915 .name = "gpio3_ick",
2916 .parent = &per_l4_ick,
2917 .prcm_mod = OMAP3430_PER_MOD,
2918 .enable_reg = CM_ICLKEN,
2919 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2920 .idlest_bit = OMAP3430_ST_GPIO3_SHIFT,
2921 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2922 .clkdm = { .name = "per_clkdm" },
2923 .recalc = &followparent_recalc,
2926 static struct clk gpio2_ick = {
2927 .name = "gpio2_ick",
2928 .parent = &per_l4_ick,
2929 .prcm_mod = OMAP3430_PER_MOD,
2930 .enable_reg = CM_ICLKEN,
2931 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2932 .idlest_bit = OMAP3430_ST_GPIO2_SHIFT,
2933 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2934 .clkdm = { .name = "per_clkdm" },
2935 .recalc = &followparent_recalc,
2938 static struct clk wdt3_ick = {
2940 .parent = &per_l4_ick,
2941 .prcm_mod = OMAP3430_PER_MOD,
2942 .enable_reg = CM_ICLKEN,
2943 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2944 .idlest_bit = OMAP3430_ST_WDT3_SHIFT,
2945 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2946 .clkdm = { .name = "per_clkdm" },
2947 .recalc = &followparent_recalc,
2950 static struct clk uart3_ick = {
2951 .name = "uart3_ick",
2952 .parent = &per_l4_ick,
2953 .prcm_mod = OMAP3430_PER_MOD,
2954 .enable_reg = CM_ICLKEN,
2955 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2956 .idlest_bit = OMAP3430_ST_UART3_SHIFT,
2957 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2958 .clkdm = { .name = "per_clkdm" },
2959 .recalc = &followparent_recalc,
2962 static struct clk gpt9_ick = {
2964 .parent = &per_l4_ick,
2965 .prcm_mod = OMAP3430_PER_MOD,
2966 .enable_reg = CM_ICLKEN,
2967 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2968 .idlest_bit = OMAP3430_ST_GPT9_SHIFT,
2969 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2970 .clkdm = { .name = "per_clkdm" },
2971 .recalc = &followparent_recalc,
2974 static struct clk gpt8_ick = {
2976 .parent = &per_l4_ick,
2977 .prcm_mod = OMAP3430_PER_MOD,
2978 .enable_reg = CM_ICLKEN,
2979 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2980 .idlest_bit = OMAP3430_ST_GPT8_SHIFT,
2981 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2982 .clkdm = { .name = "per_clkdm" },
2983 .recalc = &followparent_recalc,
2986 static struct clk gpt7_ick = {
2988 .parent = &per_l4_ick,
2989 .prcm_mod = OMAP3430_PER_MOD,
2990 .enable_reg = CM_ICLKEN,
2991 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2992 .idlest_bit = OMAP3430_ST_GPT7_SHIFT,
2993 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2994 .clkdm = { .name = "per_clkdm" },
2995 .recalc = &followparent_recalc,
2998 static struct clk gpt6_ick = {
3000 .parent = &per_l4_ick,
3001 .prcm_mod = OMAP3430_PER_MOD,
3002 .enable_reg = CM_ICLKEN,
3003 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
3004 .idlest_bit = OMAP3430_ST_GPT6_SHIFT,
3005 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3006 .clkdm = { .name = "per_clkdm" },
3007 .recalc = &followparent_recalc,
3010 static struct clk gpt5_ick = {
3012 .parent = &per_l4_ick,
3013 .prcm_mod = OMAP3430_PER_MOD,
3014 .enable_reg = CM_ICLKEN,
3015 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
3016 .idlest_bit = OMAP3430_ST_GPT5_SHIFT,
3017 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3018 .clkdm = { .name = "per_clkdm" },
3019 .recalc = &followparent_recalc,
3022 static struct clk gpt4_ick = {
3024 .parent = &per_l4_ick,
3025 .prcm_mod = OMAP3430_PER_MOD,
3026 .enable_reg = CM_ICLKEN,
3027 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
3028 .idlest_bit = OMAP3430_ST_GPT4_SHIFT,
3029 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3030 .clkdm = { .name = "per_clkdm" },
3031 .recalc = &followparent_recalc,
3034 static struct clk gpt3_ick = {
3036 .parent = &per_l4_ick,
3037 .prcm_mod = OMAP3430_PER_MOD,
3038 .enable_reg = CM_ICLKEN,
3039 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
3040 .idlest_bit = OMAP3430_ST_GPT3_SHIFT,
3041 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3042 .clkdm = { .name = "per_clkdm" },
3043 .recalc = &followparent_recalc,
3046 static struct clk gpt2_ick = {
3048 .parent = &per_l4_ick,
3049 .prcm_mod = OMAP3430_PER_MOD,
3050 .enable_reg = CM_ICLKEN,
3051 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
3052 .idlest_bit = OMAP3430_ST_GPT2_SHIFT,
3053 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3054 .clkdm = { .name = "per_clkdm" },
3055 .recalc = &followparent_recalc,
3058 static struct clk mcbsp2_ick = {
3059 .name = "mcbsp_ick",
3061 .parent = &per_l4_ick,
3062 .prcm_mod = OMAP3430_PER_MOD,
3063 .enable_reg = CM_ICLKEN,
3064 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
3065 .idlest_bit = OMAP3430_ST_MCBSP2_SHIFT,
3066 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3067 .clkdm = { .name = "per_clkdm" },
3068 .recalc = &followparent_recalc,
3071 static struct clk mcbsp3_ick = {
3072 .name = "mcbsp_ick",
3074 .parent = &per_l4_ick,
3075 .prcm_mod = OMAP3430_PER_MOD,
3076 .enable_reg = CM_ICLKEN,
3077 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
3078 .idlest_bit = OMAP3430_ST_MCBSP3_SHIFT,
3079 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3080 .clkdm = { .name = "per_clkdm" },
3081 .recalc = &followparent_recalc,
3084 static struct clk mcbsp4_ick = {
3085 .name = "mcbsp_ick",
3087 .parent = &per_l4_ick,
3088 .prcm_mod = OMAP3430_PER_MOD,
3089 .enable_reg = CM_ICLKEN,
3090 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
3091 .idlest_bit = OMAP3430_ST_MCBSP4_SHIFT,
3092 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3093 .clkdm = { .name = "per_clkdm" },
3094 .recalc = &followparent_recalc,
3097 static const struct clksel mcbsp_234_clksel[] = {
3098 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
3099 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
3103 static struct clk mcbsp2_src_fck = {
3104 .name = "mcbsp_src_fck",
3106 .prcm_mod = CLK_REG_IN_SCM,
3107 .init = &omap2_init_clksel_parent,
3108 .clksel_reg = OMAP2_CONTROL_DEVCONF0,
3109 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
3110 .clksel = mcbsp_234_clksel,
3111 .flags = CLOCK_IN_OMAP343X,
3112 .clkdm = { .name = "per_clkdm" },
3113 .recalc = &omap2_clksel_recalc,
3116 static struct clk mcbsp2_fck = {
3117 .name = "mcbsp_fck",
3119 .parent = &mcbsp2_src_fck,
3120 .prcm_mod = OMAP3430_PER_MOD,
3121 .enable_reg = CM_FCLKEN,
3122 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
3123 .idlest_bit = OMAP3430_ST_MCBSP2_SHIFT,
3124 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3125 .clkdm = { .name = "per_clkdm" },
3126 .recalc = &omap2_clksel_recalc,
3129 static struct clk mcbsp3_src_fck = {
3130 .name = "mcbsp_src_fck",
3132 .prcm_mod = CLK_REG_IN_SCM,
3133 .init = &omap2_init_clksel_parent,
3134 .clksel_reg = OMAP343X_CONTROL_DEVCONF1,
3135 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
3136 .clksel = mcbsp_234_clksel,
3137 .flags = CLOCK_IN_OMAP343X,
3138 .clkdm = { .name = "per_clkdm" },
3139 .recalc = &omap2_clksel_recalc,
3142 static struct clk mcbsp3_fck = {
3143 .name = "mcbsp_fck",
3145 .parent = &mcbsp3_src_fck,
3146 .prcm_mod = OMAP3430_PER_MOD,
3147 .enable_reg = CM_FCLKEN,
3148 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
3149 .idlest_bit = OMAP3430_ST_MCBSP3_SHIFT,
3150 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3151 .clkdm = { .name = "per_clkdm" },
3152 .recalc = &omap2_clksel_recalc,
3155 static struct clk mcbsp4_src_fck = {
3156 .name = "mcbsp_src_fck",
3158 .prcm_mod = CLK_REG_IN_SCM,
3159 .init = &omap2_init_clksel_parent,
3160 .clksel_reg = OMAP343X_CONTROL_DEVCONF1,
3161 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
3162 .clksel = mcbsp_234_clksel,
3163 .flags = CLOCK_IN_OMAP343X,
3164 .clkdm = { .name = "per_clkdm" },
3165 .recalc = &omap2_clksel_recalc,
3168 static struct clk mcbsp4_fck = {
3169 .name = "mcbsp_fck",
3171 .parent = &mcbsp4_src_fck,
3172 .prcm_mod = OMAP3430_PER_MOD,
3173 .enable_reg = CM_FCLKEN,
3174 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
3175 .idlest_bit = OMAP3430_ST_MCBSP4_SHIFT,
3176 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3177 .clkdm = { .name = "per_clkdm" },
3178 .recalc = &omap2_clksel_recalc,
3183 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
3185 static const struct clksel_rate emu_src_sys_rates[] = {
3186 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
3190 static const struct clksel_rate emu_src_core_rates[] = {
3191 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3195 static const struct clksel_rate emu_src_per_rates[] = {
3196 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3200 static const struct clksel_rate emu_src_mpu_rates[] = {
3201 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
3205 static const struct clksel emu_src_clksel[] = {
3206 { .parent = &sys_ck, .rates = emu_src_sys_rates },
3207 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
3208 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
3209 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
3214 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
3215 * to switch the source of some of the EMU clocks.
3216 * XXX Are there CLKEN bits for these EMU clks?
3218 static struct clk emu_src_ck = {
3219 .name = "emu_src_ck",
3220 .prcm_mod = OMAP3430_EMU_MOD,
3221 .init = &omap2_init_clksel_parent,
3222 .clksel_reg = CM_CLKSEL1,
3223 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
3224 .clksel = emu_src_clksel,
3225 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3226 .clkdm = { .name = "emu_clkdm" },
3227 .recalc = &omap2_clksel_recalc,
3230 static const struct clksel_rate pclk_emu_rates[] = {
3231 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3232 { .div = 3, .val = 3, .flags = RATE_IN_343X },
3233 { .div = 4, .val = 4, .flags = RATE_IN_343X },
3234 { .div = 6, .val = 6, .flags = RATE_IN_343X },
3238 static const struct clksel pclk_emu_clksel[] = {
3239 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
3243 static struct clk pclk_fck = {
3245 .prcm_mod = OMAP3430_EMU_MOD,
3246 .init = &omap2_init_clksel_parent,
3247 .clksel_reg = CM_CLKSEL1,
3248 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
3249 .clksel = pclk_emu_clksel,
3250 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3251 .clkdm = { .name = "emu_clkdm" },
3252 .recalc = &omap2_clksel_recalc,
3255 static const struct clksel_rate pclkx2_emu_rates[] = {
3256 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3257 { .div = 2, .val = 2, .flags = RATE_IN_343X },
3258 { .div = 3, .val = 3, .flags = RATE_IN_343X },
3262 static const struct clksel pclkx2_emu_clksel[] = {
3263 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
3267 static struct clk pclkx2_fck = {
3268 .name = "pclkx2_fck",
3269 .prcm_mod = OMAP3430_EMU_MOD,
3270 .init = &omap2_init_clksel_parent,
3271 .clksel_reg = CM_CLKSEL1,
3272 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
3273 .clksel = pclkx2_emu_clksel,
3274 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3275 .clkdm = { .name = "emu_clkdm" },
3276 .recalc = &omap2_clksel_recalc,
3279 static const struct clksel atclk_emu_clksel[] = {
3280 { .parent = &emu_src_ck, .rates = div2_rates },
3284 static struct clk atclk_fck = {
3285 .name = "atclk_fck",
3286 .prcm_mod = OMAP3430_EMU_MOD,
3287 .init = &omap2_init_clksel_parent,
3288 .clksel_reg = CM_CLKSEL1,
3289 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
3290 .clksel = atclk_emu_clksel,
3291 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3292 .clkdm = { .name = "emu_clkdm" },
3293 .recalc = &omap2_clksel_recalc,
3296 static struct clk traceclk_src_fck = {
3297 .name = "traceclk_src_fck",
3298 .prcm_mod = OMAP3430_EMU_MOD,
3299 .init = &omap2_init_clksel_parent,
3300 .clksel_reg = CM_CLKSEL1,
3301 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
3302 .clksel = emu_src_clksel,
3303 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3304 .clkdm = { .name = "emu_clkdm" },
3305 .recalc = &omap2_clksel_recalc,
3308 static const struct clksel_rate traceclk_rates[] = {
3309 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3310 { .div = 2, .val = 2, .flags = RATE_IN_343X },
3311 { .div = 4, .val = 4, .flags = RATE_IN_343X },
3315 static const struct clksel traceclk_clksel[] = {
3316 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3320 static struct clk traceclk_fck = {
3321 .name = "traceclk_fck",
3322 .prcm_mod = OMAP3430_EMU_MOD,
3323 .init = &omap2_init_clksel_parent,
3324 .clksel_reg = CM_CLKSEL1,
3325 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
3326 .clksel = traceclk_clksel,
3327 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3328 .clkdm = { .name = "emu_clkdm" },
3329 .recalc = &omap2_clksel_recalc,
3334 /* SmartReflex fclk (VDD1) */
3335 static struct clk sr1_fck = {
3338 .prcm_mod = WKUP_MOD,
3339 .enable_reg = CM_FCLKEN,
3340 .enable_bit = OMAP3430_EN_SR1_SHIFT,
3341 .idlest_bit = OMAP3430_ST_SR1_SHIFT,
3342 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | WAIT_READY,
3343 .clkdm = { .name = "prm_clkdm" },
3344 .recalc = &followparent_recalc,
3347 /* SmartReflex fclk (VDD2) */
3348 static struct clk sr2_fck = {
3351 .prcm_mod = WKUP_MOD,
3352 .enable_reg = CM_FCLKEN,
3353 .enable_bit = OMAP3430_EN_SR2_SHIFT,
3354 .idlest_bit = OMAP3430_ST_SR2_SHIFT,
3355 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | WAIT_READY,
3356 .clkdm = { .name = "prm_clkdm" },
3357 .recalc = &followparent_recalc,
3360 static struct clk sr_l4_ick = {
3361 .name = "sr_l4_ick",
3363 .flags = CLOCK_IN_OMAP343X,
3364 .clkdm = { .name = "core_l4_clkdm" },
3365 .recalc = &followparent_recalc,
3368 /* SECURE_32K_FCK clocks */
3370 /* XXX Make sure idlest_bit/wait_ready with no enable_bit works */
3371 static struct clk gpt12_fck = {
3372 .name = "gpt12_fck",
3373 .parent = &secure_32k_fck,
3374 .idlest_bit = OMAP3430_ST_GPT12_SHIFT,
3375 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | WAIT_READY,
3376 .clkdm = { .name = "prm_clkdm" },
3377 .recalc = &followparent_recalc,
3380 static struct clk wdt1_fck = {
3382 .parent = &secure_32k_fck,
3383 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3384 .clkdm = { .name = "prm_clkdm" },
3385 .recalc = &followparent_recalc,
3388 static struct clk *onchip_34xx_clks[] __initdata = {
3416 &omap_96m_alwon_fck,
3482 &ssi_ssr_fck_3430es1,
3483 &ssi_ssr_fck_3430es2,
3484 &ssi_sst_fck_3430es1,
3485 &ssi_sst_fck_3430es2,
3487 &hsotgusb_ick_3430es1,
3488 &hsotgusb_ick_3430es2,
3529 &dss1_alwon_fck_3430es1,
3530 &dss1_alwon_fck_3430es2,