arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  36 static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
  37
  38 /* Maximum DPLL multiplier, divider values for OMAP3 */
  39 #define OMAP3_MAX_DPLL_MULT             2048
  40 #define OMAP3_MAX_DPLL_DIV              128
  41
  42 /*
  43  * DPLL1 supplies clock to the MPU.
  44  * DPLL2 supplies clock to the IVA2.
  45  * DPLL3 supplies CORE domain clocks.
  46  * DPLL4 supplies peripheral clocks.
  47  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  48  */
  49
  50 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  51 #define DPLL_LOW_POWER_STOP             0x1
  52 #define DPLL_LOW_POWER_BYPASS           0x5
  53 #define DPLL_LOCKED                     0x7
  54
  55 /* PRM CLOCKS */
  56
  57 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  58 static struct clk omap_32k_fck = {
  59         .name           = "omap_32k_fck",
  60         .ops            = &clkops_null,
  61         .rate           = 32768,
  62         .flags          = RATE_FIXED | RATE_PROPAGATES,
  63 };
  64
  65 static struct clk secure_32k_fck = {
  66         .name           = "secure_32k_fck",
  67         .ops            = &clkops_null,
  68         .rate           = 32768,
  69         .flags          = RATE_FIXED | RATE_PROPAGATES,
  70 };
  71
  72 /* Virtual source clocks for osc_sys_ck */
  73 static struct clk virt_12m_ck = {
  74         .name           = "virt_12m_ck",
  75         .ops            = &clkops_null,
  76         .rate           = 12000000,
  77         .flags          = RATE_FIXED | RATE_PROPAGATES,
  78 };
  79
  80 static struct clk virt_13m_ck = {
  81         .name           = "virt_13m_ck",
  82         .ops            = &clkops_null,
  83         .rate           = 13000000,
  84         .flags          = RATE_FIXED | RATE_PROPAGATES,
  85 };
  86
  87 static struct clk virt_16_8m_ck = {
  88         .name           = "virt_16_8m_ck",
  89         .ops            = &clkops_null,
  90         .rate           = 16800000,
  91         .flags          = RATE_FIXED | RATE_PROPAGATES,
  92 };
  93
  94 static struct clk virt_19_2m_ck = {
  95         .name           = "virt_19_2m_ck",
  96         .ops            = &clkops_null,
  97         .rate           = 19200000,
  98         .flags          = RATE_FIXED | RATE_PROPAGATES,
  99 };
 100
 101 static struct clk virt_26m_ck = {
 102         .name           = "virt_26m_ck",
 103         .ops            = &clkops_null,
 104         .rate           = 26000000,
 105         .flags          = RATE_FIXED | RATE_PROPAGATES,
 106 };
 107
 108 static struct clk virt_38_4m_ck = {
 109         .name           = "virt_38_4m_ck",
 110         .ops            = &clkops_null,
 111         .rate           = 38400000,
 112         .flags          = RATE_FIXED | RATE_PROPAGATES,
 113 };
 114
 115 static const struct clksel_rate osc_sys_12m_rates[] = {
 116         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 117         { .div = 0 }
 118 };
 119
 120 static const struct clksel_rate osc_sys_13m_rates[] = {
 121         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 122         { .div = 0 }
 123 };
 124
 125 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 126         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 127         { .div = 0 }
 128 };
 129
 130 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 131         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 132         { .div = 0 }
 133 };
 134
 135 static const struct clksel_rate osc_sys_26m_rates[] = {
 136         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 137         { .div = 0 }
 138 };
 139
 140 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 141         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 142         { .div = 0 }
 143 };
 144
 145 static const struct clksel osc_sys_clksel[] = {
 146         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 147         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 148         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 149         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 150         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 151         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 152         { .parent = NULL },
 153 };
 154
 155 /* Oscillator clock */
 156 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 157 static struct clk osc_sys_ck = {
 158         .name           = "osc_sys_ck",
 159         .ops            = &clkops_null,
 160         .init           = &omap2_init_clksel_parent,
 161         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 162         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 163         .clksel         = osc_sys_clksel,
 164         /* REVISIT: deal with autoextclkmode? */
 165         .flags          = RATE_FIXED | RATE_PROPAGATES,
 166         .recalc         = &omap2_clksel_recalc,
 167 };
 168
 169 static const struct clksel_rate div2_rates[] = {
 170         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 171         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 172         { .div = 0 }
 173 };
 174
 175 static const struct clksel sys_clksel[] = {
 176         { .parent = &osc_sys_ck, .rates = div2_rates },
 177         { .parent = NULL }
 178 };
 179
 180 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 181 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 182 static struct clk sys_ck = {
 183         .name           = "sys_ck",
 184         .ops            = &clkops_null,
 185         .parent         = &osc_sys_ck,
 186         .init           = &omap2_init_clksel_parent,
 187         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 188         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 189         .clksel         = sys_clksel,
 190         .flags          = RATE_PROPAGATES,
 191         .recalc         = &omap2_clksel_recalc,
 192 };
 193
 194 static struct clk sys_altclk = {
 195         .name           = "sys_altclk",
 196         .ops            = &clkops_null,
 197         .flags          = RATE_PROPAGATES,
 198 };
 199
 200 /* Optional external clock input for some McBSPs */
 201 static struct clk mcbsp_clks = {
 202         .name           = "mcbsp_clks",
 203         .ops            = &clkops_null,
 204         .flags          = RATE_PROPAGATES,
 205 };
 206
 207 /* PRM EXTERNAL CLOCK OUTPUT */
 208
 209 static struct clk sys_clkout1 = {
 210         .name           = "sys_clkout1",
 211         .ops            = &clkops_omap2_dflt,
 212         .parent         = &osc_sys_ck,
 213         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 214         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 215         .recalc         = &followparent_recalc,
 216 };
 217
 218 /* DPLLS */
 219
 220 /* CM CLOCKS */
 221
 222 static const struct clksel_rate dpll_bypass_rates[] = {
 223         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 224         { .div = 0 }
 225 };
 226
 227 static const struct clksel_rate dpll_locked_rates[] = {
 228         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 229         { .div = 0 }
 230 };
 231
 232 static const struct clksel_rate div16_dpll_rates[] = {
 233         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 234         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 235         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 236         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 237         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 238         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 239         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 240         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 241         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 242         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 243         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 244         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 245         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 246         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 247         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 248         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 249         { .div = 0 }
 250 };
 251
 252 /* DPLL1 */
 253 /* MPU clock source */
 254 /* Type: DPLL */
 255 static struct dpll_data dpll1_dd = {
 256         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 257         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 258         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 259         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 260         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 261         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 262         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 263         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 264         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 265         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 266         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 267         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 268         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 269         .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
 270         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 271         .max_divider    = OMAP3_MAX_DPLL_DIV,
 272         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 273 };
 274
 275 static struct clk dpll1_ck = {
 276         .name           = "dpll1_ck",
 277         .ops            = &clkops_null,
 278         .parent         = &sys_ck,
 279         .dpll_data      = &dpll1_dd,
 280         .flags          = RATE_PROPAGATES,
 281         .round_rate     = &omap2_dpll_round_rate,
 282         .set_rate       = &omap3_noncore_dpll_set_rate,
 283         .recalc         = &omap3_dpll_recalc,
 284 };
 285
 286 /*
 287  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 288  * DPLL isn't bypassed.
 289  */
 290 static struct clk dpll1_x2_ck = {
 291         .name           = "dpll1_x2_ck",
 292         .ops            = &clkops_null,
 293         .parent         = &dpll1_ck,
 294         .flags          = RATE_PROPAGATES,
 295         .recalc         = &omap3_clkoutx2_recalc,
 296 };
 297
 298 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 299 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 300         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 301         { .parent = NULL }
 302 };
 303
 304 /*
 305  * Does not exist in the TRM - needed to separate the M2 divider from
 306  * bypass selection in mpu_ck
 307  */
 308 static struct clk dpll1_x2m2_ck = {
 309         .name           = "dpll1_x2m2_ck",
 310         .ops            = &clkops_null,
 311         .parent         = &dpll1_x2_ck,
 312         .init           = &omap2_init_clksel_parent,
 313         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 314         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 315         .clksel         = div16_dpll1_x2m2_clksel,
 316         .flags          = RATE_PROPAGATES,
 317         .recalc         = &omap2_clksel_recalc,
 318 };
 319
 320 /* DPLL2 */
 321 /* IVA2 clock source */
 322 /* Type: DPLL */
 323
 324 static struct dpll_data dpll2_dd = {
 325         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 326         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 327         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 328         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 329         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 330         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 331         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 332                                 (1 << DPLL_LOW_POWER_BYPASS),
 333         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 334         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 335         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 336         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 337         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 338         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 339         .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
 340         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 341         .max_divider    = OMAP3_MAX_DPLL_DIV,
 342         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 343 };
 344
 345 static struct clk dpll2_ck = {
 346         .name           = "dpll2_ck",
 347         .ops            = &clkops_noncore_dpll_ops,
 348         .parent         = &sys_ck,
 349         .dpll_data      = &dpll2_dd,
 350         .flags          = RATE_PROPAGATES,
 351         .round_rate     = &omap2_dpll_round_rate,
 352         .set_rate       = &omap3_noncore_dpll_set_rate,
 353         .recalc         = &omap3_dpll_recalc,
 354 };
 355
 356 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 357         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 358         { .parent = NULL }
 359 };
 360
 361 /*
 362  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 363  * or CLKOUTX2. CLKOUT seems most plausible.
 364  */
 365 static struct clk dpll2_m2_ck = {
 366         .name           = "dpll2_m2_ck",
 367         .ops            = &clkops_null,
 368         .parent         = &dpll2_ck,
 369         .init           = &omap2_init_clksel_parent,
 370         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 371                                           OMAP3430_CM_CLKSEL2_PLL),
 372         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 373         .clksel         = div16_dpll2_m2x2_clksel,
 374         .flags          = RATE_PROPAGATES,
 375         .recalc         = &omap2_clksel_recalc,
 376 };
 377
 378 /*
 379  * DPLL3
 380  * Source clock for all interfaces and for some device fclks
 381  * REVISIT: Also supports fast relock bypass - not included below
 382  */
 383 static struct dpll_data dpll3_dd = {
 384         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 385         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 386         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 387         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 388         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 389         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 390         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 391         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 392         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 393         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 394         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 395         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 396         .max_divider    = OMAP3_MAX_DPLL_DIV,
 397         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 398 };
 399
 400 static struct clk dpll3_ck = {
 401         .name           = "dpll3_ck",
 402         .ops            = &clkops_null,
 403         .parent         = &sys_ck,
 404         .dpll_data      = &dpll3_dd,
 405         .flags          = RATE_PROPAGATES,
 406         .round_rate     = &omap2_dpll_round_rate,
 407         .recalc         = &omap3_dpll_recalc,
 408 };
 409
 410 /*
 411  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 412  * DPLL isn't bypassed
 413  */
 414 static struct clk dpll3_x2_ck = {
 415         .name           = "dpll3_x2_ck",
 416         .ops            = &clkops_null,
 417         .parent         = &dpll3_ck,
 418         .flags          = RATE_PROPAGATES,
 419         .recalc         = &omap3_clkoutx2_recalc,
 420 };
 421
 422 static const struct clksel_rate div31_dpll3_rates[] = {
 423         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 424         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 425         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 426         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 427         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 428         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 429         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 430         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 431         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 432         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 433         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 434         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 435         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 436         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 437         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 438         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 439         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 440         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 441         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 442         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 443         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 444         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 445         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 446         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 447         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 448         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 449         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 450         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 451         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 452         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 453         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 454         { .div = 0 },
 455 };
 456
 457 static const struct clksel div31_dpll3m2_clksel[] = {
 458         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 459         { .parent = NULL }
 460 };
 461
 462 /*
 463  * DPLL3 output M2
 464  * REVISIT: This DPLL output divider must be changed in SRAM, so until
 465  * that code is ready, this should remain a 'read-only' clksel clock.
 466  */
 467 static struct clk dpll3_m2_ck = {
 468         .name           = "dpll3_m2_ck",
 469         .ops            = &clkops_null,
 470         .parent         = &dpll3_ck,
 471         .init           = &omap2_init_clksel_parent,
 472         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 473         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 474         .clksel         = div31_dpll3m2_clksel,
 475         .flags          = RATE_PROPAGATES,
 476         .recalc         = &omap2_clksel_recalc,
 477 };
 478
 479 static const struct clksel core_ck_clksel[] = {
 480         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 481         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 482         { .parent = NULL }
 483 };
 484
 485 static struct clk core_ck = {
 486         .name           = "core_ck",
 487         .ops            = &clkops_null,
 488         .init           = &omap2_init_clksel_parent,
 489         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 490         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 491         .clksel         = core_ck_clksel,
 492         .flags          = RATE_PROPAGATES,
 493         .recalc         = &omap2_clksel_recalc,
 494 };
 495
 496 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 497         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 498         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 499         { .parent = NULL }
 500 };
 501
 502 static struct clk dpll3_m2x2_ck = {
 503         .name           = "dpll3_m2x2_ck",
 504         .ops            = &clkops_null,
 505         .init           = &omap2_init_clksel_parent,
 506         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 507         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 508         .clksel         = dpll3_m2x2_ck_clksel,
 509         .flags          = RATE_PROPAGATES,
 510         .recalc         = &omap2_clksel_recalc,
 511 };
 512
 513 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 514 static const struct clksel div16_dpll3_clksel[] = {
 515         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 516         { .parent = NULL }
 517 };
 518
 519 /* This virtual clock is the source for dpll3_m3x2_ck */
 520 static struct clk dpll3_m3_ck = {
 521         .name           = "dpll3_m3_ck",
 522         .ops            = &clkops_null,
 523         .parent         = &dpll3_ck,
 524         .init           = &omap2_init_clksel_parent,
 525         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 526         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 527         .clksel         = div16_dpll3_clksel,
 528         .flags          = RATE_PROPAGATES,
 529         .recalc         = &omap2_clksel_recalc,
 530 };
 531
 532 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 533 static struct clk dpll3_m3x2_ck = {
 534         .name           = "dpll3_m3x2_ck",
 535         .ops            = &clkops_omap2_dflt_wait,
 536         .parent         = &dpll3_m3_ck,
 537         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 538         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 539         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 540         .recalc         = &omap3_clkoutx2_recalc,
 541 };
 542
 543 static const struct clksel emu_core_alwon_ck_clksel[] = {
 544         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 545         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 546         { .parent = NULL }
 547 };
 548
 549 static struct clk emu_core_alwon_ck = {
 550         .name           = "emu_core_alwon_ck",
 551         .ops            = &clkops_null,
 552         .parent         = &dpll3_m3x2_ck,
 553         .init           = &omap2_init_clksel_parent,
 554         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 555         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 556         .clksel         = emu_core_alwon_ck_clksel,
 557         .flags          = RATE_PROPAGATES,
 558         .recalc         = &omap2_clksel_recalc,
 559 };
 560
 561 /* DPLL4 */
 562 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 563 /* Type: DPLL */
 564 static struct dpll_data dpll4_dd = {
 565         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 566         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 567         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 568         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 569         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 570         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 571         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 572         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 573         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 574         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 575         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 576         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 577         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 578         .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
 579         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 580         .max_divider    = OMAP3_MAX_DPLL_DIV,
 581         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 582 };
 583
 584 static struct clk dpll4_ck = {
 585         .name           = "dpll4_ck",
 586         .ops            = &clkops_noncore_dpll_ops,
 587         .parent         = &sys_ck,
 588         .dpll_data      = &dpll4_dd,
 589         .flags          = RATE_PROPAGATES,
 590         .round_rate     = &omap2_dpll_round_rate,
 591         .set_rate       = &omap3_dpll4_set_rate,
 592         .recalc         = &omap3_dpll_recalc,
 593 };
 594
 595 /*
 596  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 597  * DPLL isn't bypassed --
 598  * XXX does this serve any downstream clocks?
 599  */
 600 static struct clk dpll4_x2_ck = {
 601         .name           = "dpll4_x2_ck",
 602         .ops            = &clkops_null,
 603         .parent         = &dpll4_ck,
 604         .flags          = RATE_PROPAGATES,
 605         .recalc         = &omap3_clkoutx2_recalc,
 606 };
 607
 608 static const struct clksel div16_dpll4_clksel[] = {
 609         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 610         { .parent = NULL }
 611 };
 612
 613 /* This virtual clock is the source for dpll4_m2x2_ck */
 614 static struct clk dpll4_m2_ck = {
 615         .name           = "dpll4_m2_ck",
 616         .ops            = &clkops_null,
 617         .parent         = &dpll4_ck,
 618         .init           = &omap2_init_clksel_parent,
 619         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 620         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 621         .clksel         = div16_dpll4_clksel,
 622         .flags          = RATE_PROPAGATES,
 623         .recalc         = &omap2_clksel_recalc,
 624 };
 625
 626 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 627 static struct clk dpll4_m2x2_ck = {
 628         .name           = "dpll4_m2x2_ck",
 629         .ops            = &clkops_omap2_dflt_wait,
 630         .parent         = &dpll4_m2_ck,
 631         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 632         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 633         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 634         .recalc         = &omap3_clkoutx2_recalc,
 635 };
 636
 637 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 638         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 639         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 640         { .parent = NULL }
 641 };
 642
 643 /*
 644  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 645  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 646  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 647  * CM_96K_(F)CLK.
 648  */
 649 static struct clk omap_96m_alwon_fck = {
 650         .name           = "omap_96m_alwon_fck",
 651         .ops            = &clkops_null,
 652         .parent         = &dpll4_m2x2_ck,
 653         .init           = &omap2_init_clksel_parent,
 654         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 655         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 656         .clksel         = omap_96m_alwon_fck_clksel,
 657         .flags          = RATE_PROPAGATES,
 658         .recalc         = &omap2_clksel_recalc,
 659 };
 660
 661 static struct clk cm_96m_fck = {
 662         .name           = "cm_96m_fck",
 663         .ops            = &clkops_null,
 664         .parent         = &omap_96m_alwon_fck,
 665         .flags          = RATE_PROPAGATES,
 666         .recalc         = &followparent_recalc,
 667 };
 668
 669 static const struct clksel_rate omap_96m_dpll_rates[] = {
 670         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 671         { .div = 0 }
 672 };
 673
 674 static const struct clksel_rate omap_96m_sys_rates[] = {
 675         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 676         { .div = 0 }
 677 };
 678
 679 static const struct clksel omap_96m_fck_clksel[] = {
 680         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 681         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 682         { .parent = NULL }
 683 };
 684
 685 static struct clk omap_96m_fck = {
 686         .name           = "omap_96m_fck",
 687         .ops            = &clkops_null,
 688         .parent         = &sys_ck,
 689         .init           = &omap2_init_clksel_parent,
 690         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 691         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 692         .clksel         = omap_96m_fck_clksel,
 693         .flags          = RATE_PROPAGATES,
 694         .recalc         = &omap2_clksel_recalc,
 695 };
 696
 697 /* This virtual clock is the source for dpll4_m3x2_ck */
 698 static struct clk dpll4_m3_ck = {
 699         .name           = "dpll4_m3_ck",
 700         .ops            = &clkops_null,
 701         .parent         = &dpll4_ck,
 702         .init           = &omap2_init_clksel_parent,
 703         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 704         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 705         .clksel         = div16_dpll4_clksel,
 706         .flags          = RATE_PROPAGATES,
 707         .recalc         = &omap2_clksel_recalc,
 708 };
 709
 710 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 711 static struct clk dpll4_m3x2_ck = {
 712         .name           = "dpll4_m3x2_ck",
 713         .ops            = &clkops_omap2_dflt_wait,
 714         .parent         = &dpll4_m3_ck,
 715         .init           = &omap2_init_clksel_parent,
 716         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 717         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 718         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 719         .recalc         = &omap3_clkoutx2_recalc,
 720 };
 721
 722 static const struct clksel virt_omap_54m_fck_clksel[] = {
 723         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 724         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 725         { .parent = NULL }
 726 };
 727
 728 static struct clk virt_omap_54m_fck = {
 729         .name           = "virt_omap_54m_fck",
 730         .ops            = &clkops_null,
 731         .parent         = &dpll4_m3x2_ck,
 732         .init           = &omap2_init_clksel_parent,
 733         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 734         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 735         .clksel         = virt_omap_54m_fck_clksel,
 736         .flags          = RATE_PROPAGATES,
 737         .recalc         = &omap2_clksel_recalc,
 738 };
 739
 740 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 741         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 742         { .div = 0 }
 743 };
 744
 745 static const struct clksel_rate omap_54m_alt_rates[] = {
 746         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 747         { .div = 0 }
 748 };
 749
 750 static const struct clksel omap_54m_clksel[] = {
 751         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 752         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 753         { .parent = NULL }
 754 };
 755
 756 static struct clk omap_54m_fck = {
 757         .name           = "omap_54m_fck",
 758         .ops            = &clkops_null,
 759         .init           = &omap2_init_clksel_parent,
 760         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 761         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 762         .clksel         = omap_54m_clksel,
 763         .flags          = RATE_PROPAGATES,
 764         .recalc         = &omap2_clksel_recalc,
 765 };
 766
 767 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 768         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 769         { .div = 0 }
 770 };
 771
 772 static const struct clksel_rate omap_48m_alt_rates[] = {
 773         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 774         { .div = 0 }
 775 };
 776
 777 static const struct clksel omap_48m_clksel[] = {
 778         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 779         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 780         { .parent = NULL }
 781 };
 782
 783 static struct clk omap_48m_fck = {
 784         .name           = "omap_48m_fck",
 785         .ops            = &clkops_null,
 786         .init           = &omap2_init_clksel_parent,
 787         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 788         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 789         .clksel         = omap_48m_clksel,
 790         .flags          = RATE_PROPAGATES,
 791         .recalc         = &omap2_clksel_recalc,
 792 };
 793
 794 static struct clk omap_12m_fck = {
 795         .name           = "omap_12m_fck",
 796         .ops            = &clkops_null,
 797         .parent         = &omap_48m_fck,
 798         .fixed_div      = 4,
 799         .flags          = RATE_PROPAGATES,
 800         .recalc         = &omap2_fixed_divisor_recalc,
 801 };
 802
 803 /* This virstual clock is the source for dpll4_m4x2_ck */
 804 static struct clk dpll4_m4_ck = {
 805         .name           = "dpll4_m4_ck",
 806         .ops            = &clkops_null,
 807         .parent         = &dpll4_ck,
 808         .init           = &omap2_init_clksel_parent,
 809         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 810         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 811         .clksel         = div16_dpll4_clksel,
 812         .flags          = RATE_PROPAGATES,
 813         .recalc         = &omap2_clksel_recalc,
 814         .set_rate       = &omap2_clksel_set_rate,
 815         .round_rate     = &omap2_clksel_round_rate,
 816 };
 817
 818 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 819 static struct clk dpll4_m4x2_ck = {
 820         .name           = "dpll4_m4x2_ck",
 821         .ops            = &clkops_omap2_dflt_wait,
 822         .parent         = &dpll4_m4_ck,
 823         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 824         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 825         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 826         .recalc         = &omap3_clkoutx2_recalc,
 827 };
 828
 829 /* This virtual clock is the source for dpll4_m5x2_ck */
 830 static struct clk dpll4_m5_ck = {
 831         .name           = "dpll4_m5_ck",
 832         .ops            = &clkops_null,
 833         .parent         = &dpll4_ck,
 834         .init           = &omap2_init_clksel_parent,
 835         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 836         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 837         .clksel         = div16_dpll4_clksel,
 838         .flags          = RATE_PROPAGATES,
 839         .recalc         = &omap2_clksel_recalc,
 840 };
 841
 842 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 843 static struct clk dpll4_m5x2_ck = {
 844         .name           = "dpll4_m5x2_ck",
 845         .ops            = &clkops_omap2_dflt_wait,
 846         .parent         = &dpll4_m5_ck,
 847         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 848         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 849         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 850         .recalc         = &omap3_clkoutx2_recalc,
 851 };
 852
 853 /* This virtual clock is the source for dpll4_m6x2_ck */
 854 static struct clk dpll4_m6_ck = {
 855         .name           = "dpll4_m6_ck",
 856         .ops            = &clkops_null,
 857         .parent         = &dpll4_ck,
 858         .init           = &omap2_init_clksel_parent,
 859         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 860         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 861         .clksel         = div16_dpll4_clksel,
 862         .flags          = RATE_PROPAGATES,
 863         .recalc         = &omap2_clksel_recalc,
 864 };
 865
 866 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 867 static struct clk dpll4_m6x2_ck = {
 868         .name           = "dpll4_m6x2_ck",
 869         .ops            = &clkops_omap2_dflt_wait,
 870         .parent         = &dpll4_m6_ck,
 871         .init           = &omap2_init_clksel_parent,
 872         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 873         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 874         .flags          = RATE_PROPAGATES | INVERT_ENABLE,
 875         .recalc         = &omap3_clkoutx2_recalc,
 876 };
 877
 878 static struct clk emu_per_alwon_ck = {
 879         .name           = "emu_per_alwon_ck",
 880         .ops            = &clkops_null,
 881         .parent         = &dpll4_m6x2_ck,
 882         .flags          = RATE_PROPAGATES,
 883         .recalc         = &followparent_recalc,
 884 };
 885
 886 /* DPLL5 */
 887 /* Supplies 120MHz clock, USIM source clock */
 888 /* Type: DPLL */
 889 /* 3430ES2 only */
 890 static struct dpll_data dpll5_dd = {
 891         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 892         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 893         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 894         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 895         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 896         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 897         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 898         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 899         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 900         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 901         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 902         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 903         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 904         .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
 905         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 906         .max_divider    = OMAP3_MAX_DPLL_DIV,
 907         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 908 };
 909
 910 static struct clk dpll5_ck = {
 911         .name           = "dpll5_ck",
 912         .ops            = &clkops_noncore_dpll_ops,
 913         .parent         = &sys_ck,
 914         .dpll_data      = &dpll5_dd,
 915         .flags          = RATE_PROPAGATES,
 916         .round_rate     = &omap2_dpll_round_rate,
 917         .set_rate       = &omap3_noncore_dpll_set_rate,
 918         .recalc         = &omap3_dpll_recalc,
 919 };
 920
 921 static const struct clksel div16_dpll5_clksel[] = {
 922         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 923         { .parent = NULL }
 924 };
 925
 926 static struct clk dpll5_m2_ck = {
 927         .name           = "dpll5_m2_ck",
 928         .ops            = &clkops_null,
 929         .parent         = &dpll5_ck,
 930         .init           = &omap2_init_clksel_parent,
 931         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 932         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 933         .clksel         = div16_dpll5_clksel,
 934         .flags          = RATE_PROPAGATES,
 935         .recalc         = &omap2_clksel_recalc,
 936 };
 937
 938 static const struct clksel omap_120m_fck_clksel[] = {
 939         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 940         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
 941         { .parent = NULL }
 942 };
 943
 944 static struct clk omap_120m_fck = {
 945         .name           = "omap_120m_fck",
 946         .ops            = &clkops_null,
 947         .parent         = &dpll5_m2_ck,
 948         .init           = &omap2_init_clksel_parent,
 949         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 950         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 951         .clksel         = omap_120m_fck_clksel,
 952         .flags          = RATE_PROPAGATES,
 953         .recalc         = &omap2_clksel_recalc,
 954 };
 955
 956 /* CM EXTERNAL CLOCK OUTPUTS */
 957
 958 static const struct clksel_rate clkout2_src_core_rates[] = {
 959         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 960         { .div = 0 }
 961 };
 962
 963 static const struct clksel_rate clkout2_src_sys_rates[] = {
 964         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 965         { .div = 0 }
 966 };
 967
 968 static const struct clksel_rate clkout2_src_96m_rates[] = {
 969         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 970         { .div = 0 }
 971 };
 972
 973 static const struct clksel_rate clkout2_src_54m_rates[] = {
 974         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 975         { .div = 0 }
 976 };
 977
 978 static const struct clksel clkout2_src_clksel[] = {
 979         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
 980         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
 981         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
 982         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
 983         { .parent = NULL }
 984 };
 985
 986 static struct clk clkout2_src_ck = {
 987         .name           = "clkout2_src_ck",
 988         .ops            = &clkops_omap2_dflt,
 989         .init           = &omap2_init_clksel_parent,
 990         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
 991         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 992         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 993         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 994         .clksel         = clkout2_src_clksel,
 995         .flags          = RATE_PROPAGATES,
 996         .recalc         = &omap2_clksel_recalc,
 997 };
 998
 999 static const struct clksel_rate sys_clkout2_rates[] = {
1000         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1001         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1002         { .div = 4, .val = 2, .flags = RATE_IN_343X },
1003         { .div = 8, .val = 3, .flags = RATE_IN_343X },
1004         { .div = 16, .val = 4, .flags = RATE_IN_343X },
1005         { .div = 0 },
1006 };
1007
1008 static const struct clksel sys_clkout2_clksel[] = {
1009         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1010         { .parent = NULL },
1011 };
1012
1013 static struct clk sys_clkout2 = {
1014         .name           = "sys_clkout2",
1015         .ops            = &clkops_null,
1016         .init           = &omap2_init_clksel_parent,
1017         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
1018         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1019         .clksel         = sys_clkout2_clksel,
1020         .recalc         = &omap2_clksel_recalc,
1021 };
1022
1023 /* CM OUTPUT CLOCKS */
1024
1025 static struct clk corex2_fck = {
1026         .name           = "corex2_fck",
1027         .ops            = &clkops_null,
1028         .parent         = &dpll3_m2x2_ck,
1029         .flags          = RATE_PROPAGATES,
1030         .recalc         = &followparent_recalc,
1031 };
1032
1033 /* DPLL power domain clock controls */
1034
1035 static const struct clksel div2_core_clksel[] = {
1036         { .parent = &core_ck, .rates = div2_rates },
1037         { .parent = NULL }
1038 };
1039
1040 /*
1041  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1042  * may be inconsistent here?
1043  */
1044 static struct clk dpll1_fck = {
1045         .name           = "dpll1_fck",
1046         .ops            = &clkops_null,
1047         .parent         = &core_ck,
1048         .init           = &omap2_init_clksel_parent,
1049         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1050         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1051         .clksel         = div2_core_clksel,
1052         .flags          = RATE_PROPAGATES,
1053         .recalc         = &omap2_clksel_recalc,
1054 };
1055
1056 /*
1057  * MPU clksel:
1058  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1059  * derives from the high-frequency bypass clock originating from DPLL3,
1060  * called 'dpll1_fck'
1061  */
1062 static const struct clksel mpu_clksel[] = {
1063         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1064         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1065         { .parent = NULL }
1066 };
1067
1068 static struct clk mpu_ck = {
1069         .name           = "mpu_ck",
1070         .ops            = &clkops_null,
1071         .parent         = &dpll1_x2m2_ck,
1072         .init           = &omap2_init_clksel_parent,
1073         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1074         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1075         .clksel         = mpu_clksel,
1076         .flags          = RATE_PROPAGATES,
1077         .clkdm_name     = "mpu_clkdm",
1078         .recalc         = &omap2_clksel_recalc,
1079 };
1080
1081 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1082 static const struct clksel_rate arm_fck_rates[] = {
1083         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1084         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1085         { .div = 0 },
1086 };
1087
1088 static const struct clksel arm_fck_clksel[] = {
1089         { .parent = &mpu_ck, .rates = arm_fck_rates },
1090         { .parent = NULL }
1091 };
1092
1093 static struct clk arm_fck = {
1094         .name           = "arm_fck",
1095         .ops            = &clkops_null,
1096         .parent         = &mpu_ck,
1097         .init           = &omap2_init_clksel_parent,
1098         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1099         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1100         .clksel         = arm_fck_clksel,
1101         .flags          = RATE_PROPAGATES,
1102         .recalc         = &omap2_clksel_recalc,
1103 };
1104
1105 /* XXX What about neon_clkdm ? */
1106
1107 /*
1108  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1109  * although it is referenced - so this is a guess
1110  */
1111 static struct clk emu_mpu_alwon_ck = {
1112         .name           = "emu_mpu_alwon_ck",
1113         .ops            = &clkops_null,
1114         .parent         = &mpu_ck,
1115         .flags          = RATE_PROPAGATES,
1116         .recalc         = &followparent_recalc,
1117 };
1118
1119 static struct clk dpll2_fck = {
1120         .name           = "dpll2_fck",
1121         .ops            = &clkops_null,
1122         .parent         = &core_ck,
1123         .init           = &omap2_init_clksel_parent,
1124         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1125         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1126         .clksel         = div2_core_clksel,
1127         .flags          = RATE_PROPAGATES,
1128         .recalc         = &omap2_clksel_recalc,
1129 };
1130
1131 /*
1132  * IVA2 clksel:
1133  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1134  * derives from the high-frequency bypass clock originating from DPLL3,
1135  * called 'dpll2_fck'
1136  */
1137
1138 static const struct clksel iva2_clksel[] = {
1139         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1140         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1141         { .parent = NULL }
1142 };
1143
1144 static struct clk iva2_ck = {
1145         .name           = "iva2_ck",
1146         .ops            = &clkops_omap2_dflt_wait,
1147         .parent         = &dpll2_m2_ck,
1148         .init           = &omap2_init_clksel_parent,
1149         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1150         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1151         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1152                                           OMAP3430_CM_IDLEST_PLL),
1153         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1154         .clksel         = iva2_clksel,
1155         .flags          = RATE_PROPAGATES,
1156         .clkdm_name     = "iva2_clkdm",
1157         .recalc         = &omap2_clksel_recalc,
1158 };
1159
1160 /* Common interface clocks */
1161
1162 static struct clk l3_ick = {
1163         .name           = "l3_ick",
1164         .ops            = &clkops_null,
1165         .parent         = &core_ck,
1166         .init           = &omap2_init_clksel_parent,
1167         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1168         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1169         .clksel         = div2_core_clksel,
1170         .flags          = RATE_PROPAGATES,
1171         .clkdm_name     = "core_l3_clkdm",
1172         .recalc         = &omap2_clksel_recalc,
1173 };
1174
1175 static const struct clksel div2_l3_clksel[] = {
1176         { .parent = &l3_ick, .rates = div2_rates },
1177         { .parent = NULL }
1178 };
1179
1180 static struct clk l4_ick = {
1181         .name           = "l4_ick",
1182         .ops            = &clkops_null,
1183         .parent         = &l3_ick,
1184         .init           = &omap2_init_clksel_parent,
1185         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1186         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1187         .clksel         = div2_l3_clksel,
1188         .flags          = RATE_PROPAGATES,
1189         .clkdm_name     = "core_l4_clkdm",
1190         .recalc         = &omap2_clksel_recalc,
1191
1192 };
1193
1194 static const struct clksel div2_l4_clksel[] = {
1195         { .parent = &l4_ick, .rates = div2_rates },
1196         { .parent = NULL }
1197 };
1198
1199 static struct clk rm_ick = {
1200         .name           = "rm_ick",
1201         .ops            = &clkops_null,
1202         .parent         = &l4_ick,
1203         .init           = &omap2_init_clksel_parent,
1204         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1205         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1206         .clksel         = div2_l4_clksel,
1207         .recalc         = &omap2_clksel_recalc,
1208 };
1209
1210 /* GFX power domain */
1211
1212 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1213
1214 static const struct clksel gfx_l3_clksel[] = {
1215         { .parent = &l3_ick, .rates = gfx_l3_rates },
1216         { .parent = NULL }
1217 };
1218
1219 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1220 static struct clk gfx_l3_ck = {
1221         .name           = "gfx_l3_ck",
1222         .ops            = &clkops_omap2_dflt_wait,
1223         .parent         = &l3_ick,
1224         .init           = &omap2_init_clksel_parent,
1225         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1226         .enable_bit     = OMAP_EN_GFX_SHIFT,
1227         .recalc         = &followparent_recalc,
1228 };
1229
1230 static struct clk gfx_l3_fck = {
1231         .name           = "gfx_l3_fck",
1232         .ops            = &clkops_null,
1233         .parent         = &gfx_l3_ck,
1234         .init           = &omap2_init_clksel_parent,
1235         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1236         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1237         .clksel         = gfx_l3_clksel,
1238         .flags          = RATE_PROPAGATES,
1239         .clkdm_name     = "gfx_3430es1_clkdm",
1240         .recalc         = &omap2_clksel_recalc,
1241 };
1242
1243 static struct clk gfx_l3_ick = {
1244         .name           = "gfx_l3_ick",
1245         .ops            = &clkops_null,
1246         .parent         = &gfx_l3_ck,
1247         .clkdm_name     = "gfx_3430es1_clkdm",
1248         .recalc         = &followparent_recalc,
1249 };
1250
1251 static struct clk gfx_cg1_ck = {
1252         .name           = "gfx_cg1_ck",
1253         .ops            = &clkops_omap2_dflt_wait,
1254         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1255         .init           = &omap2_init_clk_clkdm,
1256         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1257         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1258         .clkdm_name     = "gfx_3430es1_clkdm",
1259         .recalc         = &followparent_recalc,
1260 };
1261
1262 static struct clk gfx_cg2_ck = {
1263         .name           = "gfx_cg2_ck",
1264         .ops            = &clkops_omap2_dflt_wait,
1265         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1266         .init           = &omap2_init_clk_clkdm,
1267         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1268         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1269         .clkdm_name     = "gfx_3430es1_clkdm",
1270         .recalc         = &followparent_recalc,
1271 };
1272
1273 /* SGX power domain - 3430ES2 only */
1274
1275 static const struct clksel_rate sgx_core_rates[] = {
1276         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1277         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1278         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1279         { .div = 0 },
1280 };
1281
1282 static const struct clksel_rate sgx_96m_rates[] = {
1283         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1284         { .div = 0 },
1285 };
1286
1287 static const struct clksel sgx_clksel[] = {
1288         { .parent = &core_ck,    .rates = sgx_core_rates },
1289         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1290         { .parent = NULL },
1291 };
1292
1293 static struct clk sgx_fck = {
1294         .name           = "sgx_fck",
1295         .ops            = &clkops_omap2_dflt_wait,
1296         .init           = &omap2_init_clksel_parent,
1297         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1298         .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1299         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1300         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1301         .clksel         = sgx_clksel,
1302         .clkdm_name     = "sgx_clkdm",
1303         .recalc         = &omap2_clksel_recalc,
1304 };
1305
1306 static struct clk sgx_ick = {
1307         .name           = "sgx_ick",
1308         .ops            = &clkops_omap2_dflt_wait,
1309         .parent         = &l3_ick,
1310         .init           = &omap2_init_clk_clkdm,
1311         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1312         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1313         .clkdm_name     = "sgx_clkdm",
1314         .recalc         = &followparent_recalc,
1315 };
1316
1317 /* CORE power domain */
1318
1319 static struct clk d2d_26m_fck = {
1320         .name           = "d2d_26m_fck",
1321         .ops            = &clkops_omap2_dflt_wait,
1322         .parent         = &sys_ck,
1323         .init           = &omap2_init_clk_clkdm,
1324         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1325         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1326         .clkdm_name     = "d2d_clkdm",
1327         .recalc         = &followparent_recalc,
1328 };
1329
1330 static const struct clksel omap343x_gpt_clksel[] = {
1331         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1332         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1333         { .parent = NULL}
1334 };
1335
1336 static struct clk gpt10_fck = {
1337         .name           = "gpt10_fck",
1338         .ops            = &clkops_omap2_dflt_wait,
1339         .parent         = &sys_ck,
1340         .init           = &omap2_init_clksel_parent,
1341         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1342         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1343         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1344         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1345         .clksel         = omap343x_gpt_clksel,
1346         .clkdm_name     = "core_l4_clkdm",
1347         .recalc         = &omap2_clksel_recalc,
1348 };
1349
1350 static struct clk gpt11_fck = {
1351         .name           = "gpt11_fck",
1352         .ops            = &clkops_omap2_dflt_wait,
1353         .parent         = &sys_ck,
1354         .init           = &omap2_init_clksel_parent,
1355         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1356         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1357         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1358         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1359         .clksel         = omap343x_gpt_clksel,
1360         .clkdm_name     = "core_l4_clkdm",
1361         .recalc         = &omap2_clksel_recalc,
1362 };
1363
1364 static struct clk cpefuse_fck = {
1365         .name           = "cpefuse_fck",
1366         .ops            = &clkops_omap2_dflt,
1367         .parent         = &sys_ck,
1368         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1369         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1370         .recalc         = &followparent_recalc,
1371 };
1372
1373 static struct clk ts_fck = {
1374         .name           = "ts_fck",
1375         .ops            = &clkops_omap2_dflt,
1376         .parent         = &omap_32k_fck,
1377         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1378         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1379         .recalc         = &followparent_recalc,
1380 };
1381
1382 static struct clk usbtll_fck = {
1383         .name           = "usbtll_fck",
1384         .ops            = &clkops_omap2_dflt,
1385         .parent         = &omap_120m_fck,
1386         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1387         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1388         .recalc         = &followparent_recalc,
1389 };
1390
1391 /* CORE 96M FCLK-derived clocks */
1392
1393 static struct clk core_96m_fck = {
1394         .name           = "core_96m_fck",
1395         .ops            = &clkops_null,
1396         .parent         = &omap_96m_fck,
1397         .flags          = RATE_PROPAGATES,
1398         .clkdm_name     = "core_l4_clkdm",
1399         .recalc         = &followparent_recalc,
1400 };
1401
1402 static struct clk mmchs3_fck = {
1403         .name           = "mmchs_fck",
1404         .ops            = &clkops_omap2_dflt_wait,
1405         .id             = 2,
1406         .parent         = &core_96m_fck,
1407         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1408         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1409         .clkdm_name     = "core_l4_clkdm",
1410         .recalc         = &followparent_recalc,
1411 };
1412
1413 static struct clk mmchs2_fck = {
1414         .name           = "mmchs_fck",
1415         .ops            = &clkops_omap2_dflt_wait,
1416         .id             = 1,
1417         .parent         = &core_96m_fck,
1418         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1419         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1420         .clkdm_name     = "core_l4_clkdm",
1421         .recalc         = &followparent_recalc,
1422 };
1423
1424 static struct clk mspro_fck = {
1425         .name           = "mspro_fck",
1426         .ops            = &clkops_omap2_dflt_wait,
1427         .parent         = &core_96m_fck,
1428         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1429         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1430         .clkdm_name     = "core_l4_clkdm",
1431         .recalc         = &followparent_recalc,
1432 };
1433
1434 static struct clk mmchs1_fck = {
1435         .name           = "mmchs_fck",
1436         .ops            = &clkops_omap2_dflt_wait,
1437         .parent         = &core_96m_fck,
1438         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1439         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1440         .clkdm_name     = "core_l4_clkdm",
1441         .recalc         = &followparent_recalc,
1442 };
1443
1444 static struct clk i2c3_fck = {
1445         .name           = "i2c_fck",
1446         .ops            = &clkops_omap2_dflt_wait,
1447         .id             = 3,
1448         .parent         = &core_96m_fck,
1449         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1450         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1451         .clkdm_name     = "core_l4_clkdm",
1452         .recalc         = &followparent_recalc,
1453 };
1454
1455 static struct clk i2c2_fck = {
1456         .name           = "i2c_fck",
1457         .ops            = &clkops_omap2_dflt_wait,
1458         .id             = 2,
1459         .parent         = &core_96m_fck,
1460         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1461         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1462         .clkdm_name     = "core_l4_clkdm",
1463         .recalc         = &followparent_recalc,
1464 };
1465
1466 static struct clk i2c1_fck = {
1467         .name           = "i2c_fck",
1468         .ops            = &clkops_omap2_dflt_wait,
1469         .id             = 1,
1470         .parent         = &core_96m_fck,
1471         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1472         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1473         .clkdm_name     = "core_l4_clkdm",
1474         .recalc         = &followparent_recalc,
1475 };
1476
1477 /*
1478  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1479  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1480  */
1481 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1482         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1483         { .div = 0 }
1484 };
1485
1486 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1487         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1488         { .div = 0 }
1489 };
1490
1491 static const struct clksel mcbsp_15_clksel[] = {
1492         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1493         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1494         { .parent = NULL }
1495 };
1496
1497 static struct clk mcbsp5_fck = {
1498         .name           = "mcbsp_fck",
1499         .ops            = &clkops_omap2_dflt_wait,
1500         .id             = 5,
1501         .init           = &omap2_init_clksel_parent,
1502         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1503         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1504         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1505         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1506         .clksel         = mcbsp_15_clksel,
1507         .clkdm_name     = "core_l4_clkdm",
1508         .recalc         = &omap2_clksel_recalc,
1509 };
1510
1511 static struct clk mcbsp1_fck = {
1512         .name           = "mcbsp_fck",
1513         .ops            = &clkops_omap2_dflt_wait,
1514         .id             = 1,
1515         .init           = &omap2_init_clksel_parent,
1516         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1517         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1518         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1519         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1520         .clksel         = mcbsp_15_clksel,
1521         .clkdm_name     = "core_l4_clkdm",
1522         .recalc         = &omap2_clksel_recalc,
1523 };
1524
1525 /* CORE_48M_FCK-derived clocks */
1526
1527 static struct clk core_48m_fck = {
1528         .name           = "core_48m_fck",
1529         .ops            = &clkops_null,
1530         .parent         = &omap_48m_fck,
1531         .flags          = RATE_PROPAGATES,
1532         .clkdm_name     = "core_l4_clkdm",
1533         .recalc         = &followparent_recalc,
1534 };
1535
1536 static struct clk mcspi4_fck = {
1537         .name           = "mcspi_fck",
1538         .ops            = &clkops_omap2_dflt_wait,
1539         .id             = 4,
1540         .parent         = &core_48m_fck,
1541         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1542         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1543         .recalc         = &followparent_recalc,
1544 };
1545
1546 static struct clk mcspi3_fck = {
1547         .name           = "mcspi_fck",
1548         .ops            = &clkops_omap2_dflt_wait,
1549         .id             = 3,
1550         .parent         = &core_48m_fck,
1551         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1552         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1553         .recalc         = &followparent_recalc,
1554 };
1555
1556 static struct clk mcspi2_fck = {
1557         .name           = "mcspi_fck",
1558         .ops            = &clkops_omap2_dflt_wait,
1559         .id             = 2,
1560         .parent         = &core_48m_fck,
1561         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1562         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1563         .recalc         = &followparent_recalc,
1564 };
1565
1566 static struct clk mcspi1_fck = {
1567         .name           = "mcspi_fck",
1568         .ops            = &clkops_omap2_dflt_wait,
1569         .id             = 1,
1570         .parent         = &core_48m_fck,
1571         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1572         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1573         .recalc         = &followparent_recalc,
1574 };
1575
1576 static struct clk uart2_fck = {
1577         .name           = "uart2_fck",
1578         .ops            = &clkops_omap2_dflt_wait,
1579         .parent         = &core_48m_fck,
1580         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1581         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1582         .recalc         = &followparent_recalc,
1583 };
1584
1585 static struct clk uart1_fck = {
1586         .name           = "uart1_fck",
1587         .ops            = &clkops_omap2_dflt_wait,
1588         .parent         = &core_48m_fck,
1589         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1590         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1591         .recalc         = &followparent_recalc,
1592 };
1593
1594 static struct clk fshostusb_fck = {
1595         .name           = "fshostusb_fck",
1596         .ops            = &clkops_omap2_dflt_wait,
1597         .parent         = &core_48m_fck,
1598         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1599         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1600         .recalc         = &followparent_recalc,
1601 };
1602
1603 /* CORE_12M_FCK based clocks */
1604
1605 static struct clk core_12m_fck = {
1606         .name           = "core_12m_fck",
1607         .ops            = &clkops_null,
1608         .parent         = &omap_12m_fck,
1609         .flags          = RATE_PROPAGATES,
1610         .clkdm_name     = "core_l4_clkdm",
1611         .recalc         = &followparent_recalc,
1612 };
1613
1614 static struct clk hdq_fck = {
1615         .name           = "hdq_fck",
1616         .ops            = &clkops_omap2_dflt_wait,
1617         .parent         = &core_12m_fck,
1618         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1619         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1620         .recalc         = &followparent_recalc,
1621 };
1622
1623 /* DPLL3-derived clock */
1624
1625 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1626         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1627         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1628         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1629         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1630         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1631         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1632         { .div = 0 }
1633 };
1634
1635 static const struct clksel ssi_ssr_clksel[] = {
1636         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1637         { .parent = NULL }
1638 };
1639
1640 static struct clk ssi_ssr_fck = {
1641         .name           = "ssi_ssr_fck",
1642         .ops            = &clkops_omap2_dflt,
1643         .init           = &omap2_init_clksel_parent,
1644         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1645         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1646         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1647         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1648         .clksel         = ssi_ssr_clksel,
1649         .flags          = RATE_PROPAGATES,
1650         .clkdm_name     = "core_l4_clkdm",
1651         .recalc         = &omap2_clksel_recalc,
1652 };
1653
1654 static struct clk ssi_sst_fck = {
1655         .name           = "ssi_sst_fck",
1656         .ops            = &clkops_null,
1657         .parent         = &ssi_ssr_fck,
1658         .fixed_div      = 2,
1659         .recalc         = &omap2_fixed_divisor_recalc,
1660 };
1661
1662
1663
1664 /* CORE_L3_ICK based clocks */
1665
1666 /*
1667  * XXX must add clk_enable/clk_disable for these if standard code won't
1668  * handle it
1669  */
1670 static struct clk core_l3_ick = {
1671         .name           = "core_l3_ick",
1672         .ops            = &clkops_null,
1673         .parent         = &l3_ick,
1674         .init           = &omap2_init_clk_clkdm,
1675         .flags          = RATE_PROPAGATES,
1676         .clkdm_name     = "core_l3_clkdm",
1677         .recalc         = &followparent_recalc,
1678 };
1679
1680 static struct clk hsotgusb_ick = {
1681         .name           = "hsotgusb_ick",
1682         .ops            = &clkops_omap2_dflt_wait,
1683         .parent         = &core_l3_ick,
1684         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1685         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1686         .clkdm_name     = "core_l3_clkdm",
1687         .recalc         = &followparent_recalc,
1688 };
1689
1690 static struct clk sdrc_ick = {
1691         .name           = "sdrc_ick",
1692         .ops            = &clkops_omap2_dflt_wait,
1693         .parent         = &core_l3_ick,
1694         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1695         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1696         .flags          = ENABLE_ON_INIT,
1697         .clkdm_name     = "core_l3_clkdm",
1698         .recalc         = &followparent_recalc,
1699 };
1700
1701 static struct clk gpmc_fck = {
1702         .name           = "gpmc_fck",
1703         .ops            = &clkops_null,
1704         .parent         = &core_l3_ick,
1705         .flags          = ENABLE_ON_INIT, /* huh? */
1706         .clkdm_name     = "core_l3_clkdm",
1707         .recalc         = &followparent_recalc,
1708 };
1709
1710 /* SECURITY_L3_ICK based clocks */
1711
1712 static struct clk security_l3_ick = {
1713         .name           = "security_l3_ick",
1714         .ops            = &clkops_null,
1715         .parent         = &l3_ick,
1716         .flags          = RATE_PROPAGATES,
1717         .recalc         = &followparent_recalc,
1718 };
1719
1720 static struct clk pka_ick = {
1721         .name           = "pka_ick",
1722         .ops            = &clkops_omap2_dflt_wait,
1723         .parent         = &security_l3_ick,
1724         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1725         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1726         .recalc         = &followparent_recalc,
1727 };
1728
1729 /* CORE_L4_ICK based clocks */
1730
1731 static struct clk core_l4_ick = {
1732         .name           = "core_l4_ick",
1733         .ops            = &clkops_null,
1734         .parent         = &l4_ick,
1735         .init           = &omap2_init_clk_clkdm,
1736         .flags          = RATE_PROPAGATES,
1737         .clkdm_name     = "core_l4_clkdm",
1738         .recalc         = &followparent_recalc,
1739 };
1740
1741 static struct clk usbtll_ick = {
1742         .name           = "usbtll_ick",
1743         .ops            = &clkops_omap2_dflt_wait,
1744         .parent         = &core_l4_ick,
1745         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1746         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1747         .clkdm_name     = "core_l4_clkdm",
1748         .recalc         = &followparent_recalc,
1749 };
1750
1751 static struct clk mmchs3_ick = {
1752         .name           = "mmchs_ick",
1753         .ops            = &clkops_omap2_dflt_wait,
1754         .id             = 2,
1755         .parent         = &core_l4_ick,
1756         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1757         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1758         .clkdm_name     = "core_l4_clkdm",
1759         .recalc         = &followparent_recalc,
1760 };
1761
1762 /* Intersystem Communication Registers - chassis mode only */
1763 static struct clk icr_ick = {
1764         .name           = "icr_ick",
1765         .ops            = &clkops_omap2_dflt_wait,
1766         .parent         = &core_l4_ick,
1767         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1768         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1769         .clkdm_name     = "core_l4_clkdm",
1770         .recalc         = &followparent_recalc,
1771 };
1772
1773 static struct clk aes2_ick = {
1774         .name           = "aes2_ick",
1775         .ops            = &clkops_omap2_dflt_wait,
1776         .parent         = &core_l4_ick,
1777         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1778         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1779         .clkdm_name     = "core_l4_clkdm",
1780         .recalc         = &followparent_recalc,
1781 };
1782
1783 static struct clk sha12_ick = {
1784         .name           = "sha12_ick",
1785         .ops            = &clkops_omap2_dflt_wait,
1786         .parent         = &core_l4_ick,
1787         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1788         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1789         .clkdm_name     = "core_l4_clkdm",
1790         .recalc         = &followparent_recalc,
1791 };
1792
1793 static struct clk des2_ick = {
1794         .name           = "des2_ick",
1795         .ops            = &clkops_omap2_dflt_wait,
1796         .parent         = &core_l4_ick,
1797         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1798         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1799         .clkdm_name     = "core_l4_clkdm",
1800         .recalc         = &followparent_recalc,
1801 };
1802
1803 static struct clk mmchs2_ick = {
1804         .name           = "mmchs_ick",
1805         .ops            = &clkops_omap2_dflt_wait,
1806         .id             = 1,
1807         .parent         = &core_l4_ick,
1808         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1809         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1810         .clkdm_name     = "core_l4_clkdm",
1811         .recalc         = &followparent_recalc,
1812 };
1813
1814 static struct clk mmchs1_ick = {
1815         .name           = "mmchs_ick",
1816         .ops            = &clkops_omap2_dflt_wait,
1817         .parent         = &core_l4_ick,
1818         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1819         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1820         .clkdm_name     = "core_l4_clkdm",
1821         .recalc         = &followparent_recalc,
1822 };
1823
1824 static struct clk mspro_ick = {
1825         .name           = "mspro_ick",
1826         .ops            = &clkops_omap2_dflt_wait,
1827         .parent         = &core_l4_ick,
1828         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1829         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1830         .clkdm_name     = "core_l4_clkdm",
1831         .recalc         = &followparent_recalc,
1832 };
1833
1834 static struct clk hdq_ick = {
1835         .name           = "hdq_ick",
1836         .ops            = &clkops_omap2_dflt_wait,
1837         .parent         = &core_l4_ick,
1838         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1839         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1840         .clkdm_name     = "core_l4_clkdm",
1841         .recalc         = &followparent_recalc,
1842 };
1843
1844 static struct clk mcspi4_ick = {
1845         .name           = "mcspi_ick",
1846         .ops            = &clkops_omap2_dflt_wait,
1847         .id             = 4,
1848         .parent         = &core_l4_ick,
1849         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1850         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1851         .clkdm_name     = "core_l4_clkdm",
1852         .recalc         = &followparent_recalc,
1853 };
1854
1855 static struct clk mcspi3_ick = {
1856         .name           = "mcspi_ick",
1857         .ops            = &clkops_omap2_dflt_wait,
1858         .id             = 3,
1859         .parent         = &core_l4_ick,
1860         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1861         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1862         .clkdm_name     = "core_l4_clkdm",
1863         .recalc         = &followparent_recalc,
1864 };
1865
1866 static struct clk mcspi2_ick = {
1867         .name           = "mcspi_ick",
1868         .ops            = &clkops_omap2_dflt_wait,
1869         .id             = 2,
1870         .parent         = &core_l4_ick,
1871         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1872         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1873         .clkdm_name     = "core_l4_clkdm",
1874         .recalc         = &followparent_recalc,
1875 };
1876
1877 static struct clk mcspi1_ick = {
1878         .name           = "mcspi_ick",
1879         .ops            = &clkops_omap2_dflt_wait,
1880         .id             = 1,
1881         .parent         = &core_l4_ick,
1882         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1883         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1884         .clkdm_name     = "core_l4_clkdm",
1885         .recalc         = &followparent_recalc,
1886 };
1887
1888 static struct clk i2c3_ick = {
1889         .name           = "i2c_ick",
1890         .ops            = &clkops_omap2_dflt_wait,
1891         .id             = 3,
1892         .parent         = &core_l4_ick,
1893         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1894         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1895         .clkdm_name     = "core_l4_clkdm",
1896         .recalc         = &followparent_recalc,
1897 };
1898
1899 static struct clk i2c2_ick = {
1900         .name           = "i2c_ick",
1901         .ops            = &clkops_omap2_dflt_wait,
1902         .id             = 2,
1903         .parent         = &core_l4_ick,
1904         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1905         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1906         .clkdm_name     = "core_l4_clkdm",
1907         .recalc         = &followparent_recalc,
1908 };
1909
1910 static struct clk i2c1_ick = {
1911         .name           = "i2c_ick",
1912         .ops            = &clkops_omap2_dflt_wait,
1913         .id             = 1,
1914         .parent         = &core_l4_ick,
1915         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1916         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1917         .clkdm_name     = "core_l4_clkdm",
1918         .recalc         = &followparent_recalc,
1919 };
1920
1921 static struct clk uart2_ick = {
1922         .name           = "uart2_ick",
1923         .ops            = &clkops_omap2_dflt_wait,
1924         .parent         = &core_l4_ick,
1925         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1926         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1927         .clkdm_name     = "core_l4_clkdm",
1928         .recalc         = &followparent_recalc,
1929 };
1930
1931 static struct clk uart1_ick = {
1932         .name           = "uart1_ick",
1933         .ops            = &clkops_omap2_dflt_wait,
1934         .parent         = &core_l4_ick,
1935         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1936         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1937         .clkdm_name     = "core_l4_clkdm",
1938         .recalc         = &followparent_recalc,
1939 };
1940
1941 static struct clk gpt11_ick = {
1942         .name           = "gpt11_ick",
1943         .ops            = &clkops_omap2_dflt_wait,
1944         .parent         = &core_l4_ick,
1945         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1946         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1947         .clkdm_name     = "core_l4_clkdm",
1948         .recalc         = &followparent_recalc,
1949 };
1950
1951 static struct clk gpt10_ick = {
1952         .name           = "gpt10_ick",
1953         .ops            = &clkops_omap2_dflt_wait,
1954         .parent         = &core_l4_ick,
1955         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1956         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1957         .clkdm_name     = "core_l4_clkdm",
1958         .recalc         = &followparent_recalc,
1959 };
1960
1961 static struct clk mcbsp5_ick = {
1962         .name           = "mcbsp_ick",
1963         .ops            = &clkops_omap2_dflt_wait,
1964         .id             = 5,
1965         .parent         = &core_l4_ick,
1966         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1967         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1968         .clkdm_name     = "core_l4_clkdm",
1969         .recalc         = &followparent_recalc,
1970 };
1971
1972 static struct clk mcbsp1_ick = {
1973         .name           = "mcbsp_ick",
1974         .ops            = &clkops_omap2_dflt_wait,
1975         .id             = 1,
1976         .parent         = &core_l4_ick,
1977         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1978         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1979         .clkdm_name     = "core_l4_clkdm",
1980         .recalc         = &followparent_recalc,
1981 };
1982
1983 static struct clk fac_ick = {
1984         .name           = "fac_ick",
1985         .ops            = &clkops_omap2_dflt_wait,
1986         .parent         = &core_l4_ick,
1987         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1988         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1989         .clkdm_name     = "core_l4_clkdm",
1990         .recalc         = &followparent_recalc,
1991 };
1992
1993 static struct clk mailboxes_ick = {
1994         .name           = "mailboxes_ick",
1995         .ops            = &clkops_omap2_dflt_wait,
1996         .parent         = &core_l4_ick,
1997         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1998         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
1999         .clkdm_name     = "core_l4_clkdm",
2000         .recalc         = &followparent_recalc,
2001 };
2002
2003 static struct clk omapctrl_ick = {
2004         .name           = "omapctrl_ick",
2005         .ops            = &clkops_omap2_dflt_wait,
2006         .parent         = &core_l4_ick,
2007         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2008         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2009         .flags          = ENABLE_ON_INIT,
2010         .recalc         = &followparent_recalc,
2011 };
2012
2013 /* SSI_L4_ICK based clocks */
2014
2015 static struct clk ssi_l4_ick = {
2016         .name           = "ssi_l4_ick",
2017         .ops            = &clkops_null,
2018         .parent         = &l4_ick,
2019         .flags          = RATE_PROPAGATES,
2020         .clkdm_name     = "core_l4_clkdm",
2021         .recalc         = &followparent_recalc,
2022 };
2023
2024 static struct clk ssi_ick = {
2025         .name           = "ssi_ick",
2026         .ops            = &clkops_omap2_dflt,
2027         .parent         = &ssi_l4_ick,
2028         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2029         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2030         .clkdm_name     = "core_l4_clkdm",
2031         .recalc         = &followparent_recalc,
2032 };
2033
2034 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2035  * but l4_ick makes more sense to me */
2036
2037 static const struct clksel usb_l4_clksel[] = {
2038         { .parent = &l4_ick, .rates = div2_rates },
2039         { .parent = NULL },
2040 };
2041
2042 static struct clk usb_l4_ick = {
2043         .name           = "usb_l4_ick",
2044         .ops            = &clkops_omap2_dflt_wait,
2045         .parent         = &l4_ick,
2046         .init           = &omap2_init_clksel_parent,
2047         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2048         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2049         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2050         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2051         .clksel         = usb_l4_clksel,
2052         .recalc         = &omap2_clksel_recalc,
2053 };
2054
2055 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2056
2057 /* SECURITY_L4_ICK2 based clocks */
2058
2059 static struct clk security_l4_ick2 = {
2060         .name           = "security_l4_ick2",
2061         .ops            = &clkops_null,
2062         .parent         = &l4_ick,
2063         .flags          = RATE_PROPAGATES,
2064         .recalc         = &followparent_recalc,
2065 };
2066
2067 static struct clk aes1_ick = {
2068         .name           = "aes1_ick",
2069         .ops            = &clkops_omap2_dflt_wait,
2070         .parent         = &security_l4_ick2,
2071         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2072         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2073         .recalc         = &followparent_recalc,
2074 };
2075
2076 static struct clk rng_ick = {
2077         .name           = "rng_ick",
2078         .ops            = &clkops_omap2_dflt_wait,
2079         .parent         = &security_l4_ick2,
2080         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2081         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2082         .recalc         = &followparent_recalc,
2083 };
2084
2085 static struct clk sha11_ick = {
2086         .name           = "sha11_ick",
2087         .ops            = &clkops_omap2_dflt_wait,
2088         .parent         = &security_l4_ick2,
2089         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2090         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2091         .recalc         = &followparent_recalc,
2092 };
2093
2094 static struct clk des1_ick = {
2095         .name           = "des1_ick",
2096         .ops            = &clkops_omap2_dflt_wait,
2097         .parent         = &security_l4_ick2,
2098         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2099         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2100         .recalc         = &followparent_recalc,
2101 };
2102
2103 /* DSS */
2104 static const struct clksel dss1_alwon_fck_clksel[] = {
2105         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2106         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2107         { .parent = NULL }
2108 };
2109
2110 static struct clk dss1_alwon_fck = {
2111         .name           = "dss1_alwon_fck",
2112         .ops            = &clkops_omap2_dflt,
2113         .parent         = &dpll4_m4x2_ck,
2114         .init           = &omap2_init_clksel_parent,
2115         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2116         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2117         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2118         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2119         .clksel         = dss1_alwon_fck_clksel,
2120         .clkdm_name     = "dss_clkdm",
2121         .recalc         = &omap2_clksel_recalc,
2122 };
2123
2124 static struct clk dss_tv_fck = {
2125         .name           = "dss_tv_fck",
2126         .ops            = &clkops_omap2_dflt,
2127         .parent         = &omap_54m_fck,
2128         .init           = &omap2_init_clk_clkdm,
2129         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2130         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2131         .clkdm_name     = "dss_clkdm",
2132         .recalc         = &followparent_recalc,
2133 };
2134
2135 static struct clk dss_96m_fck = {
2136         .name           = "dss_96m_fck",
2137         .ops            = &clkops_omap2_dflt,
2138         .parent         = &omap_96m_fck,
2139         .init           = &omap2_init_clk_clkdm,
2140         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2141         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2142         .clkdm_name     = "dss_clkdm",
2143         .recalc         = &followparent_recalc,
2144 };
2145
2146 static struct clk dss2_alwon_fck = {
2147         .name           = "dss2_alwon_fck",
2148         .ops            = &clkops_omap2_dflt,
2149         .parent         = &sys_ck,
2150         .init           = &omap2_init_clk_clkdm,
2151         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2152         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2153         .clkdm_name     = "dss_clkdm",
2154         .recalc         = &followparent_recalc,
2155 };
2156
2157 static struct clk dss_ick = {
2158         /* Handles both L3 and L4 clocks */
2159         .name           = "dss_ick",
2160         .ops            = &clkops_omap2_dflt,
2161         .parent         = &l4_ick,
2162         .init           = &omap2_init_clk_clkdm,
2163         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2164         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2165         .clkdm_name     = "dss_clkdm",
2166         .recalc         = &followparent_recalc,
2167 };
2168
2169 /* CAM */
2170
2171 static const struct clksel cam_mclk_clksel[] = {
2172         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2173         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2174         { .parent = NULL }
2175 };
2176
2177 static struct clk cam_mclk = {
2178         .name           = "cam_mclk",
2179         .ops            = &clkops_omap2_dflt_wait,
2180         .parent         = &dpll4_m5x2_ck,
2181         .init           = &omap2_init_clksel_parent,
2182         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2183         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2184         .clksel         = cam_mclk_clksel,
2185         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2186         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2187         .clkdm_name     = "cam_clkdm",
2188         .recalc         = &omap2_clksel_recalc,
2189 };
2190
2191 static struct clk cam_ick = {
2192         /* Handles both L3 and L4 clocks */
2193         .name           = "cam_ick",
2194         .ops            = &clkops_omap2_dflt_wait,
2195         .parent         = &l4_ick,
2196         .init           = &omap2_init_clk_clkdm,
2197         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2198         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2199         .clkdm_name     = "cam_clkdm",
2200         .recalc         = &followparent_recalc,
2201 };
2202
2203 static struct clk csi2_96m_fck = {
2204         .name           = "csi2_96m_fck",
2205         .ops            = &clkops_omap2_dflt_wait,
2206         .parent         = &core_96m_fck,
2207         .init           = &omap2_init_clk_clkdm,
2208         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2209         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2210         .clkdm_name     = "cam_clkdm",
2211         .recalc         = &followparent_recalc,
2212 };
2213
2214 /* USBHOST - 3430ES2 only */
2215
2216 static struct clk usbhost_120m_fck = {
2217         .name           = "usbhost_120m_fck",
2218         .ops            = &clkops_omap2_dflt_wait,
2219         .parent         = &omap_120m_fck,
2220         .init           = &omap2_init_clk_clkdm,
2221         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2222         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2223         .clkdm_name     = "usbhost_clkdm",
2224         .recalc         = &followparent_recalc,
2225 };
2226
2227 static struct clk usbhost_48m_fck = {
2228         .name           = "usbhost_48m_fck",
2229         .ops            = &clkops_omap2_dflt_wait,
2230         .parent         = &omap_48m_fck,
2231         .init           = &omap2_init_clk_clkdm,
2232         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2233         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2234         .clkdm_name     = "usbhost_clkdm",
2235         .recalc         = &followparent_recalc,
2236 };
2237
2238 static struct clk usbhost_ick = {
2239         /* Handles both L3 and L4 clocks */
2240         .name           = "usbhost_ick",
2241         .ops            = &clkops_omap2_dflt_wait,
2242         .parent         = &l4_ick,
2243         .init           = &omap2_init_clk_clkdm,
2244         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2245         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2246         .clkdm_name     = "usbhost_clkdm",
2247         .recalc         = &followparent_recalc,
2248 };
2249
2250 /* WKUP */
2251
2252 static const struct clksel_rate usim_96m_rates[] = {
2253         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2254         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2255         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2256         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2257         { .div = 0 },
2258 };
2259
2260 static const struct clksel_rate usim_120m_rates[] = {
2261         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2262         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2263         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2264         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2265         { .div = 0 },
2266 };
2267
2268 static const struct clksel usim_clksel[] = {
2269         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2270         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2271         { .parent = &sys_ck,            .rates = div2_rates },
2272         { .parent = NULL },
2273 };
2274
2275 /* 3430ES2 only */
2276 static struct clk usim_fck = {
2277         .name           = "usim_fck",
2278         .ops            = &clkops_omap2_dflt_wait,
2279         .init           = &omap2_init_clksel_parent,
2280         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2281         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2282         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2283         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2284         .clksel         = usim_clksel,
2285         .recalc         = &omap2_clksel_recalc,
2286 };
2287
2288 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2289 static struct clk gpt1_fck = {
2290         .name           = "gpt1_fck",
2291         .ops            = &clkops_omap2_dflt_wait,
2292         .init           = &omap2_init_clksel_parent,
2293         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2294         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2295         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2296         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2297         .clksel         = omap343x_gpt_clksel,
2298         .clkdm_name     = "wkup_clkdm",
2299         .recalc         = &omap2_clksel_recalc,
2300 };
2301
2302 static struct clk wkup_32k_fck = {
2303         .name           = "wkup_32k_fck",
2304         .ops            = &clkops_null,
2305         .init           = &omap2_init_clk_clkdm,
2306         .parent         = &omap_32k_fck,
2307         .flags          = RATE_PROPAGATES,
2308         .clkdm_name     = "wkup_clkdm",
2309         .recalc         = &followparent_recalc,
2310 };
2311
2312 static struct clk gpio1_dbck = {
2313         .name           = "gpio1_dbck",
2314         .ops            = &clkops_omap2_dflt_wait,
2315         .parent         = &wkup_32k_fck,
2316         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2317         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2318         .clkdm_name     = "wkup_clkdm",
2319         .recalc         = &followparent_recalc,
2320 };
2321
2322 static struct clk wdt2_fck = {
2323         .name           = "wdt2_fck",
2324         .ops            = &clkops_omap2_dflt_wait,
2325         .parent         = &wkup_32k_fck,
2326         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2327         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2328         .clkdm_name     = "wkup_clkdm",
2329         .recalc         = &followparent_recalc,
2330 };
2331
2332 static struct clk wkup_l4_ick = {
2333         .name           = "wkup_l4_ick",
2334         .ops            = &clkops_null,
2335         .parent         = &sys_ck,
2336         .flags          = RATE_PROPAGATES,
2337         .clkdm_name     = "wkup_clkdm",
2338         .recalc         = &followparent_recalc,
2339 };
2340
2341 /* 3430ES2 only */
2342 /* Never specifically named in the TRM, so we have to infer a likely name */
2343 static struct clk usim_ick = {
2344         .name           = "usim_ick",
2345         .ops            = &clkops_omap2_dflt_wait,
2346         .parent         = &wkup_l4_ick,
2347         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2348         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2349         .clkdm_name     = "wkup_clkdm",
2350         .recalc         = &followparent_recalc,
2351 };
2352
2353 static struct clk wdt2_ick = {
2354         .name           = "wdt2_ick",
2355         .ops            = &clkops_omap2_dflt_wait,
2356         .parent         = &wkup_l4_ick,
2357         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2358         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2359         .clkdm_name     = "wkup_clkdm",
2360         .recalc         = &followparent_recalc,
2361 };
2362
2363 static struct clk wdt1_ick = {
2364         .name           = "wdt1_ick",
2365         .ops            = &clkops_omap2_dflt_wait,
2366         .parent         = &wkup_l4_ick,
2367         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2368         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2369         .clkdm_name     = "wkup_clkdm",
2370         .recalc         = &followparent_recalc,
2371 };
2372
2373 static struct clk gpio1_ick = {
2374         .name           = "gpio1_ick",
2375         .ops            = &clkops_omap2_dflt_wait,
2376         .parent         = &wkup_l4_ick,
2377         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2378         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2379         .clkdm_name     = "wkup_clkdm",
2380         .recalc         = &followparent_recalc,
2381 };
2382
2383 static struct clk omap_32ksync_ick = {
2384         .name           = "omap_32ksync_ick",
2385         .ops            = &clkops_omap2_dflt_wait,
2386         .parent         = &wkup_l4_ick,
2387         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2388         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2389         .clkdm_name     = "wkup_clkdm",
2390         .recalc         = &followparent_recalc,
2391 };
2392
2393 /* XXX This clock no longer exists in 3430 TRM rev F */
2394 static struct clk gpt12_ick = {
2395         .name           = "gpt12_ick",
2396         .ops            = &clkops_omap2_dflt_wait,
2397         .parent         = &wkup_l4_ick,
2398         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2399         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2400         .clkdm_name     = "wkup_clkdm",
2401         .recalc         = &followparent_recalc,
2402 };
2403
2404 static struct clk gpt1_ick = {
2405         .name           = "gpt1_ick",
2406         .ops            = &clkops_omap2_dflt_wait,
2407         .parent         = &wkup_l4_ick,
2408         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2409         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2410         .clkdm_name     = "wkup_clkdm",
2411         .recalc         = &followparent_recalc,
2412 };
2413
2414
2415
2416 /* PER clock domain */
2417
2418 static struct clk per_96m_fck = {
2419         .name           = "per_96m_fck",
2420         .ops            = &clkops_null,
2421         .parent         = &omap_96m_alwon_fck,
2422         .init           = &omap2_init_clk_clkdm,
2423         .flags          = RATE_PROPAGATES,
2424         .clkdm_name     = "per_clkdm",
2425         .recalc         = &followparent_recalc,
2426 };
2427
2428 static struct clk per_48m_fck = {
2429         .name           = "per_48m_fck",
2430         .ops            = &clkops_null,
2431         .parent         = &omap_48m_fck,
2432         .init           = &omap2_init_clk_clkdm,
2433         .flags          = RATE_PROPAGATES,
2434         .clkdm_name     = "per_clkdm",
2435         .recalc         = &followparent_recalc,
2436 };
2437
2438 static struct clk uart3_fck = {
2439         .name           = "uart3_fck",
2440         .ops            = &clkops_omap2_dflt_wait,
2441         .parent         = &per_48m_fck,
2442         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2443         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2444         .clkdm_name     = "per_clkdm",
2445         .recalc         = &followparent_recalc,
2446 };
2447
2448 static struct clk gpt2_fck = {
2449         .name           = "gpt2_fck",
2450         .ops            = &clkops_omap2_dflt_wait,
2451         .init           = &omap2_init_clksel_parent,
2452         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2453         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2454         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2455         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2456         .clksel         = omap343x_gpt_clksel,
2457         .clkdm_name     = "per_clkdm",
2458         .recalc         = &omap2_clksel_recalc,
2459 };
2460
2461 static struct clk gpt3_fck = {
2462         .name           = "gpt3_fck",
2463         .ops            = &clkops_omap2_dflt_wait,
2464         .init           = &omap2_init_clksel_parent,
2465         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2466         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2467         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2468         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2469         .clksel         = omap343x_gpt_clksel,
2470         .clkdm_name     = "per_clkdm",
2471         .recalc         = &omap2_clksel_recalc,
2472 };
2473
2474 static struct clk gpt4_fck = {
2475         .name           = "gpt4_fck",
2476         .ops            = &clkops_omap2_dflt_wait,
2477         .init           = &omap2_init_clksel_parent,
2478         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2479         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2480         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2481         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2482         .clksel         = omap343x_gpt_clksel,
2483         .clkdm_name     = "per_clkdm",
2484         .recalc         = &omap2_clksel_recalc,
2485 };
2486
2487 static struct clk gpt5_fck = {
2488         .name           = "gpt5_fck",
2489         .ops            = &clkops_omap2_dflt_wait,
2490         .init           = &omap2_init_clksel_parent,
2491         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2492         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2493         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2494         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2495         .clksel         = omap343x_gpt_clksel,
2496         .clkdm_name     = "per_clkdm",
2497         .recalc         = &omap2_clksel_recalc,
2498 };
2499
2500 static struct clk gpt6_fck = {
2501         .name           = "gpt6_fck",
2502         .ops            = &clkops_omap2_dflt_wait,
2503         .init           = &omap2_init_clksel_parent,
2504         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2505         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2506         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2507         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2508         .clksel         = omap343x_gpt_clksel,
2509         .clkdm_name     = "per_clkdm",
2510         .recalc         = &omap2_clksel_recalc,
2511 };
2512
2513 static struct clk gpt7_fck = {
2514         .name           = "gpt7_fck",
2515         .ops            = &clkops_omap2_dflt_wait,
2516         .init           = &omap2_init_clksel_parent,
2517         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2518         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2519         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2520         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2521         .clksel         = omap343x_gpt_clksel,
2522         .clkdm_name     = "per_clkdm",
2523         .recalc         = &omap2_clksel_recalc,
2524 };
2525
2526 static struct clk gpt8_fck = {
2527         .name           = "gpt8_fck",
2528         .ops            = &clkops_omap2_dflt_wait,
2529         .init           = &omap2_init_clksel_parent,
2530         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2531         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2532         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2533         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2534         .clksel         = omap343x_gpt_clksel,
2535         .clkdm_name     = "per_clkdm",
2536         .recalc         = &omap2_clksel_recalc,
2537 };
2538
2539 static struct clk gpt9_fck = {
2540         .name           = "gpt9_fck",
2541         .ops            = &clkops_omap2_dflt_wait,
2542         .init           = &omap2_init_clksel_parent,
2543         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2544         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2545         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2546         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2547         .clksel         = omap343x_gpt_clksel,
2548         .clkdm_name     = "per_clkdm",
2549         .recalc         = &omap2_clksel_recalc,
2550 };
2551
2552 static struct clk per_32k_alwon_fck = {
2553         .name           = "per_32k_alwon_fck",
2554         .ops            = &clkops_null,
2555         .parent         = &omap_32k_fck,
2556         .clkdm_name     = "per_clkdm",
2557         .flags          = RATE_PROPAGATES,
2558         .recalc         = &followparent_recalc,
2559 };
2560
2561 static struct clk gpio6_dbck = {
2562         .name           = "gpio6_dbck",
2563         .ops            = &clkops_omap2_dflt_wait,
2564         .parent         = &per_32k_alwon_fck,
2565         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2566         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2567         .clkdm_name     = "per_clkdm",
2568         .recalc         = &followparent_recalc,
2569 };
2570
2571 static struct clk gpio5_dbck = {
2572         .name           = "gpio5_dbck",
2573         .ops            = &clkops_omap2_dflt_wait,
2574         .parent         = &per_32k_alwon_fck,
2575         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2576         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2577         .clkdm_name     = "per_clkdm",
2578         .recalc         = &followparent_recalc,
2579 };
2580
2581 static struct clk gpio4_dbck = {
2582         .name           = "gpio4_dbck",
2583         .ops            = &clkops_omap2_dflt_wait,
2584         .parent         = &per_32k_alwon_fck,
2585         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2586         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2587         .clkdm_name     = "per_clkdm",
2588         .recalc         = &followparent_recalc,
2589 };
2590
2591 static struct clk gpio3_dbck = {
2592         .name           = "gpio3_dbck",
2593         .ops            = &clkops_omap2_dflt_wait,
2594         .parent         = &per_32k_alwon_fck,
2595         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2596         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2597         .clkdm_name     = "per_clkdm",
2598         .recalc         = &followparent_recalc,
2599 };
2600
2601 static struct clk gpio2_dbck = {
2602         .name           = "gpio2_dbck",
2603         .ops            = &clkops_omap2_dflt_wait,
2604         .parent         = &per_32k_alwon_fck,
2605         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2606         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2607         .clkdm_name     = "per_clkdm",
2608         .recalc         = &followparent_recalc,
2609 };
2610
2611 static struct clk wdt3_fck = {
2612         .name           = "wdt3_fck",
2613         .ops            = &clkops_omap2_dflt_wait,
2614         .parent         = &per_32k_alwon_fck,
2615         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2616         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2617         .clkdm_name     = "per_clkdm",
2618         .recalc         = &followparent_recalc,
2619 };
2620
2621 static struct clk per_l4_ick = {
2622         .name           = "per_l4_ick",
2623         .ops            = &clkops_null,
2624         .parent         = &l4_ick,
2625         .flags          = RATE_PROPAGATES,
2626         .clkdm_name     = "per_clkdm",
2627         .recalc         = &followparent_recalc,
2628 };
2629
2630 static struct clk gpio6_ick = {
2631         .name           = "gpio6_ick",
2632         .ops            = &clkops_omap2_dflt_wait,
2633         .parent         = &per_l4_ick,
2634         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2635         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2636         .clkdm_name     = "per_clkdm",
2637         .recalc         = &followparent_recalc,
2638 };
2639
2640 static struct clk gpio5_ick = {
2641         .name           = "gpio5_ick",
2642         .ops            = &clkops_omap2_dflt_wait,
2643         .parent         = &per_l4_ick,
2644         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2645         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2646         .clkdm_name     = "per_clkdm",
2647         .recalc         = &followparent_recalc,
2648 };
2649
2650 static struct clk gpio4_ick = {
2651         .name           = "gpio4_ick",
2652         .ops            = &clkops_omap2_dflt_wait,
2653         .parent         = &per_l4_ick,
2654         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2655         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2656         .clkdm_name     = "per_clkdm",
2657         .recalc         = &followparent_recalc,
2658 };
2659
2660 static struct clk gpio3_ick = {
2661         .name           = "gpio3_ick",
2662         .ops            = &clkops_omap2_dflt_wait,
2663         .parent         = &per_l4_ick,
2664         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2665         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2666         .clkdm_name     = "per_clkdm",
2667         .recalc         = &followparent_recalc,
2668 };
2669
2670 static struct clk gpio2_ick = {
2671         .name           = "gpio2_ick",
2672         .ops            = &clkops_omap2_dflt_wait,
2673         .parent         = &per_l4_ick,
2674         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2675         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2676         .clkdm_name     = "per_clkdm",
2677         .recalc         = &followparent_recalc,
2678 };
2679
2680 static struct clk wdt3_ick = {
2681         .name           = "wdt3_ick",
2682         .ops            = &clkops_omap2_dflt_wait,
2683         .parent         = &per_l4_ick,
2684         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2685         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2686         .clkdm_name     = "per_clkdm",
2687         .recalc         = &followparent_recalc,
2688 };
2689
2690 static struct clk uart3_ick = {
2691         .name           = "uart3_ick",
2692         .ops            = &clkops_omap2_dflt_wait,
2693         .parent         = &per_l4_ick,
2694         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2695         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2696         .clkdm_name     = "per_clkdm",
2697         .recalc         = &followparent_recalc,
2698 };
2699
2700 static struct clk gpt9_ick = {
2701         .name           = "gpt9_ick",
2702         .ops            = &clkops_omap2_dflt_wait,
2703         .parent         = &per_l4_ick,
2704         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2705         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2706         .clkdm_name     = "per_clkdm",
2707         .recalc         = &followparent_recalc,
2708 };
2709
2710 static struct clk gpt8_ick = {
2711         .name           = "gpt8_ick",
2712         .ops            = &clkops_omap2_dflt_wait,
2713         .parent         = &per_l4_ick,
2714         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2715         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2716         .clkdm_name     = "per_clkdm",
2717         .recalc         = &followparent_recalc,
2718 };
2719
2720 static struct clk gpt7_ick = {
2721         .name           = "gpt7_ick",
2722         .ops            = &clkops_omap2_dflt_wait,
2723         .parent         = &per_l4_ick,
2724         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2725         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2726         .clkdm_name     = "per_clkdm",
2727         .recalc         = &followparent_recalc,
2728 };
2729
2730 static struct clk gpt6_ick = {
2731         .name           = "gpt6_ick",
2732         .ops            = &clkops_omap2_dflt_wait,
2733         .parent         = &per_l4_ick,
2734         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2735         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2736         .clkdm_name     = "per_clkdm",
2737         .recalc         = &followparent_recalc,
2738 };
2739
2740 static struct clk gpt5_ick = {
2741         .name           = "gpt5_ick",
2742         .ops            = &clkops_omap2_dflt_wait,
2743         .parent         = &per_l4_ick,
2744         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2745         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2746         .clkdm_name     = "per_clkdm",
2747         .recalc         = &followparent_recalc,
2748 };
2749
2750 static struct clk gpt4_ick = {
2751         .name           = "gpt4_ick",
2752         .ops            = &clkops_omap2_dflt_wait,
2753         .parent         = &per_l4_ick,
2754         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2755         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2756         .clkdm_name     = "per_clkdm",
2757         .recalc         = &followparent_recalc,
2758 };
2759
2760 static struct clk gpt3_ick = {
2761         .name           = "gpt3_ick",
2762         .ops            = &clkops_omap2_dflt_wait,
2763         .parent         = &per_l4_ick,
2764         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2765         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2766         .clkdm_name     = "per_clkdm",
2767         .recalc         = &followparent_recalc,
2768 };
2769
2770 static struct clk gpt2_ick = {
2771         .name           = "gpt2_ick",
2772         .ops            = &clkops_omap2_dflt_wait,
2773         .parent         = &per_l4_ick,
2774         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2775         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2776         .clkdm_name     = "per_clkdm",
2777         .recalc         = &followparent_recalc,
2778 };
2779
2780 static struct clk mcbsp2_ick = {
2781         .name           = "mcbsp_ick",
2782         .ops            = &clkops_omap2_dflt_wait,
2783         .id             = 2,
2784         .parent         = &per_l4_ick,
2785         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2786         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2787         .clkdm_name     = "per_clkdm",
2788         .recalc         = &followparent_recalc,
2789 };
2790
2791 static struct clk mcbsp3_ick = {
2792         .name           = "mcbsp_ick",
2793         .ops            = &clkops_omap2_dflt_wait,
2794         .id             = 3,
2795         .parent         = &per_l4_ick,
2796         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2797         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2798         .clkdm_name     = "per_clkdm",
2799         .recalc         = &followparent_recalc,
2800 };
2801
2802 static struct clk mcbsp4_ick = {
2803         .name           = "mcbsp_ick",
2804         .ops            = &clkops_omap2_dflt_wait,
2805         .id             = 4,
2806         .parent         = &per_l4_ick,
2807         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2808         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2809         .clkdm_name     = "per_clkdm",
2810         .recalc         = &followparent_recalc,
2811 };
2812
2813 static const struct clksel mcbsp_234_clksel[] = {
2814         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2815         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2816         { .parent = NULL }
2817 };
2818
2819 static struct clk mcbsp2_fck = {
2820         .name           = "mcbsp_fck",
2821         .ops            = &clkops_omap2_dflt_wait,
2822         .id             = 2,
2823         .init           = &omap2_init_clksel_parent,
2824         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2825         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2826         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2827         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2828         .clksel         = mcbsp_234_clksel,
2829         .clkdm_name     = "per_clkdm",
2830         .recalc         = &omap2_clksel_recalc,
2831 };
2832
2833 static struct clk mcbsp3_fck = {
2834         .name           = "mcbsp_fck",
2835         .ops            = &clkops_omap2_dflt_wait,
2836         .id             = 3,
2837         .init           = &omap2_init_clksel_parent,
2838         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2839         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2840         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2841         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2842         .clksel         = mcbsp_234_clksel,
2843         .clkdm_name     = "per_clkdm",
2844         .recalc         = &omap2_clksel_recalc,
2845 };
2846
2847 static struct clk mcbsp4_fck = {
2848         .name           = "mcbsp_fck",
2849         .ops            = &clkops_omap2_dflt_wait,
2850         .id             = 4,
2851         .init           = &omap2_init_clksel_parent,
2852         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2853         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2854         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2855         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2856         .clksel         = mcbsp_234_clksel,
2857         .clkdm_name     = "per_clkdm",
2858         .recalc         = &omap2_clksel_recalc,
2859 };
2860
2861 /* EMU clocks */
2862
2863 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2864
2865 static const struct clksel_rate emu_src_sys_rates[] = {
2866         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2867         { .div = 0 },
2868 };
2869
2870 static const struct clksel_rate emu_src_core_rates[] = {
2871         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2872         { .div = 0 },
2873 };
2874
2875 static const struct clksel_rate emu_src_per_rates[] = {
2876         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2877         { .div = 0 },
2878 };
2879
2880 static const struct clksel_rate emu_src_mpu_rates[] = {
2881         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2882         { .div = 0 },
2883 };
2884
2885 static const struct clksel emu_src_clksel[] = {
2886         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2887         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2888         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2889         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2890         { .parent = NULL },
2891 };
2892
2893 /*
2894  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2895  * to switch the source of some of the EMU clocks.
2896  * XXX Are there CLKEN bits for these EMU clks?
2897  */
2898 static struct clk emu_src_ck = {
2899         .name           = "emu_src_ck",
2900         .ops            = &clkops_null,
2901         .init           = &omap2_init_clksel_parent,
2902         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2903         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2904         .clksel         = emu_src_clksel,
2905         .flags          = RATE_PROPAGATES,
2906         .clkdm_name     = "emu_clkdm",
2907         .recalc         = &omap2_clksel_recalc,
2908 };
2909
2910 static const struct clksel_rate pclk_emu_rates[] = {
2911         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2912         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2913         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2914         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2915         { .div = 0 },
2916 };
2917
2918 static const struct clksel pclk_emu_clksel[] = {
2919         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2920         { .parent = NULL },
2921 };
2922
2923 static struct clk pclk_fck = {
2924         .name           = "pclk_fck",
2925         .ops            = &clkops_null,
2926         .init           = &omap2_init_clksel_parent,
2927         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2928         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2929         .clksel         = pclk_emu_clksel,
2930         .flags          = RATE_PROPAGATES,
2931         .clkdm_name     = "emu_clkdm",
2932         .recalc         = &omap2_clksel_recalc,
2933 };
2934
2935 static const struct clksel_rate pclkx2_emu_rates[] = {
2936         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2937         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2938         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2939         { .div = 0 },
2940 };
2941
2942 static const struct clksel pclkx2_emu_clksel[] = {
2943         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2944         { .parent = NULL },
2945 };
2946
2947 static struct clk pclkx2_fck = {
2948         .name           = "pclkx2_fck",
2949         .ops            = &clkops_null,
2950         .init           = &omap2_init_clksel_parent,
2951         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2952         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2953         .clksel         = pclkx2_emu_clksel,
2954         .flags          = RATE_PROPAGATES,
2955         .clkdm_name     = "emu_clkdm",
2956         .recalc         = &omap2_clksel_recalc,
2957 };
2958
2959 static const struct clksel atclk_emu_clksel[] = {
2960         { .parent = &emu_src_ck, .rates = div2_rates },
2961         { .parent = NULL },
2962 };
2963
2964 static struct clk atclk_fck = {
2965         .name           = "atclk_fck",
2966         .ops            = &clkops_null,
2967         .init           = &omap2_init_clksel_parent,
2968         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2969         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2970         .clksel         = atclk_emu_clksel,
2971         .flags          = RATE_PROPAGATES,
2972         .clkdm_name     = "emu_clkdm",
2973         .recalc         = &omap2_clksel_recalc,
2974 };
2975
2976 static struct clk traceclk_src_fck = {
2977         .name           = "traceclk_src_fck",
2978         .ops            = &clkops_null,
2979         .init           = &omap2_init_clksel_parent,
2980         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2981         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2982         .clksel         = emu_src_clksel,
2983         .flags          = RATE_PROPAGATES,
2984         .clkdm_name     = "emu_clkdm",
2985         .recalc         = &omap2_clksel_recalc,
2986 };
2987
2988 static const struct clksel_rate traceclk_rates[] = {
2989         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2990         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2991         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2992         { .div = 0 },
2993 };
2994
2995 static const struct clksel traceclk_clksel[] = {
2996         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2997         { .parent = NULL },
2998 };
2999
3000 static struct clk traceclk_fck = {
3001         .name           = "traceclk_fck",
3002         .ops            = &clkops_null,
3003         .init           = &omap2_init_clksel_parent,
3004         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3005         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3006         .clksel         = traceclk_clksel,
3007         .clkdm_name     = "emu_clkdm",
3008         .recalc         = &omap2_clksel_recalc,
3009 };
3010
3011 /* SR clocks */
3012
3013 /* SmartReflex fclk (VDD1) */
3014 static struct clk sr1_fck = {
3015         .name           = "sr1_fck",
3016         .ops            = &clkops_omap2_dflt_wait,
3017         .parent         = &sys_ck,
3018         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3019         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3020         .flags          = RATE_PROPAGATES,
3021         .recalc         = &followparent_recalc,
3022 };
3023
3024 /* SmartReflex fclk (VDD2) */
3025 static struct clk sr2_fck = {
3026         .name           = "sr2_fck",
3027         .ops            = &clkops_omap2_dflt_wait,
3028         .parent         = &sys_ck,
3029         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3030         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3031         .flags          = RATE_PROPAGATES,
3032         .recalc         = &followparent_recalc,
3033 };
3034
3035 static struct clk sr_l4_ick = {
3036         .name           = "sr_l4_ick",
3037         .ops            = &clkops_null, /* RMK: missing? */
3038         .parent         = &l4_ick,
3039         .clkdm_name     = "core_l4_clkdm",
3040         .recalc         = &followparent_recalc,
3041 };
3042
3043 /* SECURE_32K_FCK clocks */
3044
3045 /* XXX This clock no longer exists in 3430 TRM rev F */
3046 static struct clk gpt12_fck = {
3047         .name           = "gpt12_fck",
3048         .ops            = &clkops_null,
3049         .parent         = &secure_32k_fck,
3050         .recalc         = &followparent_recalc,
3051 };
3052
3053 static struct clk wdt1_fck = {
3054         .name           = "wdt1_fck",
3055         .ops            = &clkops_null,
3056         .parent         = &secure_32k_fck,
3057         .recalc         = &followparent_recalc,
3058 };
3059
3060 #endif