arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_enable(struct clk *clk);
  36 static void omap3_noncore_dpll_disable(struct clk *clk);
  37 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  38 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
  39
  40 /* Maximum DPLL multiplier, divider values for OMAP3 */
  41 #define OMAP3_MAX_DPLL_MULT             2048
  42 #define OMAP3_MAX_DPLL_DIV              128
  43
  44 /*
  45  * DPLL1 supplies clock to the MPU.
  46  * DPLL2 supplies clock to the IVA2.
  47  * DPLL3 supplies CORE domain clocks.
  48  * DPLL4 supplies peripheral clocks.
  49  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  50  */
  51
  52 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  53 #define DPLL_LOW_POWER_STOP             0x1
  54 #define DPLL_LOW_POWER_BYPASS           0x5
  55 #define DPLL_LOCKED                     0x7
  56
  57 #define _OMAP34XX_PRM_REGADDR(module, reg)                              \
  58         ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
  59
  60 #define OMAP3430_PRM_CLKSRC_CTRL                                        \
  61         _OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, OMAP3_PRM_CLKSRC_CTRL_OFFSET)
  62
  63 #define OMAP3430_PRM_CLKSEL                                             \
  64         _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKSEL_OFFSET)
  65
  66 #define OMAP3430_PRM_CLKOUT_CTRL                                        \
  67         _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKOUT_CTRL_OFFSET)
  68
  69 /* PRM CLOCKS */
  70
  71 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  72 static struct clk omap_32k_fck = {
  73         .name           = "omap_32k_fck",
  74         .rate           = 32768,
  75         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  76                                 ALWAYS_ENABLED,
  77         .recalc         = &propagate_rate,
  78 };
  79
  80 static struct clk secure_32k_fck = {
  81         .name           = "secure_32k_fck",
  82         .rate           = 32768,
  83         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  84                                 ALWAYS_ENABLED,
  85         .recalc         = &propagate_rate,
  86 };
  87
  88 /* Virtual source clocks for osc_sys_ck */
  89 static struct clk virt_12m_ck = {
  90         .name           = "virt_12m_ck",
  91         .rate           = 12000000,
  92         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  93                                 ALWAYS_ENABLED,
  94         .recalc         = &propagate_rate,
  95 };
  96
  97 static struct clk virt_13m_ck = {
  98         .name           = "virt_13m_ck",
  99         .rate           = 13000000,
 100         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 101                                 ALWAYS_ENABLED,
 102         .recalc         = &propagate_rate,
 103 };
 104
 105 static struct clk virt_16_8m_ck = {
 106         .name           = "virt_16_8m_ck",
 107         .rate           = 16800000,
 108         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
 109                                 ALWAYS_ENABLED,
 110         .recalc         = &propagate_rate,
 111 };
 112
 113 static struct clk virt_19_2m_ck = {
 114         .name           = "virt_19_2m_ck",
 115         .rate           = 19200000,
 116         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 117                                 ALWAYS_ENABLED,
 118         .recalc         = &propagate_rate,
 119 };
 120
 121 static struct clk virt_26m_ck = {
 122         .name           = "virt_26m_ck",
 123         .rate           = 26000000,
 124         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 125                                 ALWAYS_ENABLED,
 126         .recalc         = &propagate_rate,
 127 };
 128
 129 static struct clk virt_38_4m_ck = {
 130         .name           = "virt_38_4m_ck",
 131         .rate           = 38400000,
 132         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 133                                 ALWAYS_ENABLED,
 134         .recalc         = &propagate_rate,
 135 };
 136
 137 static const struct clksel_rate osc_sys_12m_rates[] = {
 138         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 139         { .div = 0 }
 140 };
 141
 142 static const struct clksel_rate osc_sys_13m_rates[] = {
 143         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 144         { .div = 0 }
 145 };
 146
 147 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 148         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 149         { .div = 0 }
 150 };
 151
 152 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 153         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 154         { .div = 0 }
 155 };
 156
 157 static const struct clksel_rate osc_sys_26m_rates[] = {
 158         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 159         { .div = 0 }
 160 };
 161
 162 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 163         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 164         { .div = 0 }
 165 };
 166
 167 static const struct clksel osc_sys_clksel[] = {
 168         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 169         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 170         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 171         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 172         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 173         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 174         { .parent = NULL },
 175 };
 176
 177 /* Oscillator clock */
 178 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 179 static struct clk osc_sys_ck = {
 180         .name           = "osc_sys_ck",
 181         .init           = &omap2_init_clksel_parent,
 182         .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSEL,
 183         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 184         .clksel         = osc_sys_clksel,
 185         /* REVISIT: deal with autoextclkmode? */
 186         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 187                                 ALWAYS_ENABLED,
 188         .recalc         = &omap2_clksel_recalc,
 189 };
 190
 191 static const struct clksel_rate div2_rates[] = {
 192         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 193         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 194         { .div = 0 }
 195 };
 196
 197 static const struct clksel sys_clksel[] = {
 198         { .parent = &osc_sys_ck, .rates = div2_rates },
 199         { .parent = NULL }
 200 };
 201
 202 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 203 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 204 static struct clk sys_ck = {
 205         .name           = "sys_ck",
 206         .parent         = &osc_sys_ck,
 207         .init           = &omap2_init_clksel_parent,
 208         .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSRC_CTRL,
 209         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 210         .clksel         = sys_clksel,
 211         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 212         .recalc         = &omap2_clksel_recalc,
 213 };
 214
 215 static struct clk sys_altclk = {
 216         .name           = "sys_altclk",
 217         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 218         .recalc         = &propagate_rate,
 219 };
 220
 221 /* Optional external clock input for some McBSPs */
 222 static struct clk mcbsp_clks = {
 223         .name           = "mcbsp_clks",
 224         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 225         .recalc         = &propagate_rate,
 226 };
 227
 228 /* PRM EXTERNAL CLOCK OUTPUT */
 229
 230 static struct clk sys_clkout1 = {
 231         .name           = "sys_clkout1",
 232         .parent         = &osc_sys_ck,
 233         .enable_reg     = (__force void __iomem *)OMAP3430_PRM_CLKOUT_CTRL,
 234         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 235         .flags          = CLOCK_IN_OMAP343X,
 236         .recalc         = &followparent_recalc,
 237 };
 238
 239 /* DPLLS */
 240
 241 /* CM CLOCKS */
 242
 243 static const struct clksel_rate dpll_bypass_rates[] = {
 244         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 245         { .div = 0 }
 246 };
 247
 248 static const struct clksel_rate dpll_locked_rates[] = {
 249         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 250         { .div = 0 }
 251 };
 252
 253 static const struct clksel_rate div16_dpll_rates[] = {
 254         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 255         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 256         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 257         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 258         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 259         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 260         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 261         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 262         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 263         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 264         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 265         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 266         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 267         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 268         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 269         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 270         { .div = 0 }
 271 };
 272
 273 #define _OMAP34XX_CM_REGADDR(module, reg)                               \
 274         ((__force void __iomem *)(OMAP34XX_CM_REGADDR((module), (reg))))
 275
 276 #define _OMAP34XX_PRM_REGADDR(module, reg)                              \
 277         ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
 278
 279 /* DPLL1 */
 280 /* MPU clock source */
 281 /* Type: DPLL */
 282 static struct dpll_data dpll1_dd = {
 283         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 284         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 285         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 286         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 287         .control_reg    = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 288         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 289         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 290         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 291         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 292         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 293         .autoidle_reg   = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 294         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 295         .idlest_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 296         .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
 297         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 298         .max_divider    = OMAP3_MAX_DPLL_DIV,
 299         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 300 };
 301
 302 static struct clk dpll1_ck = {
 303         .name           = "dpll1_ck",
 304         .parent         = &sys_ck,
 305         .dpll_data      = &dpll1_dd,
 306         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 307         .round_rate     = &omap2_dpll_round_rate,
 308         .set_rate       = &omap3_noncore_dpll_set_rate,
 309         .recalc         = &omap3_dpll_recalc,
 310 };
 311
 312 /*
 313  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 314  * DPLL isn't bypassed.
 315  */
 316 static struct clk dpll1_x2_ck = {
 317         .name           = "dpll1_x2_ck",
 318         .parent         = &dpll1_ck,
 319         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 320                                 PARENT_CONTROLS_CLOCK,
 321         .recalc         = &omap3_clkoutx2_recalc,
 322 };
 323
 324 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 325 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 326         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 327         { .parent = NULL }
 328 };
 329
 330 /*
 331  * Does not exist in the TRM - needed to separate the M2 divider from
 332  * bypass selection in mpu_ck
 333  */
 334 static struct clk dpll1_x2m2_ck = {
 335         .name           = "dpll1_x2m2_ck",
 336         .parent         = &dpll1_x2_ck,
 337         .init           = &omap2_init_clksel_parent,
 338         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 339         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 340         .clksel         = div16_dpll1_x2m2_clksel,
 341         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 342                                 PARENT_CONTROLS_CLOCK,
 343         .recalc         = &omap2_clksel_recalc,
 344 };
 345
 346 /* DPLL2 */
 347 /* IVA2 clock source */
 348 /* Type: DPLL */
 349
 350 static struct dpll_data dpll2_dd = {
 351         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 352         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 353         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 354         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 355         .control_reg    = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 356         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 357         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 358                                 (1 << DPLL_LOW_POWER_BYPASS),
 359         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 360         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 361         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 362         .autoidle_reg   = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 363         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 364         .idlest_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 365         .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
 366         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 367         .max_divider    = OMAP3_MAX_DPLL_DIV,
 368         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 369 };
 370
 371 static struct clk dpll2_ck = {
 372         .name           = "dpll2_ck",
 373         .parent         = &sys_ck,
 374         .dpll_data      = &dpll2_dd,
 375         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 376         .enable         = &omap3_noncore_dpll_enable,
 377         .disable        = &omap3_noncore_dpll_disable,
 378         .round_rate     = &omap2_dpll_round_rate,
 379         .set_rate       = &omap3_noncore_dpll_set_rate,
 380         .recalc         = &omap3_dpll_recalc,
 381 };
 382
 383 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 384         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 385         { .parent = NULL }
 386 };
 387
 388 /*
 389  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 390  * or CLKOUTX2. CLKOUT seems most plausible.
 391  */
 392 static struct clk dpll2_m2_ck = {
 393         .name           = "dpll2_m2_ck",
 394         .parent         = &dpll2_ck,
 395         .init           = &omap2_init_clksel_parent,
 396         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
 397                                           OMAP3430_CM_CLKSEL2_PLL),
 398         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 399         .clksel         = div16_dpll2_m2x2_clksel,
 400         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 401                                 PARENT_CONTROLS_CLOCK,
 402         .recalc         = &omap2_clksel_recalc,
 403 };
 404
 405 /*
 406  * DPLL3
 407  * Source clock for all interfaces and for some device fclks
 408  * REVISIT: Also supports fast relock bypass - not included below
 409  */
 410 static struct dpll_data dpll3_dd = {
 411         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 412         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 413         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 414         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 415         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 416         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 417         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 418         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 419         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 420         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 421         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 422         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 423         .max_divider    = OMAP3_MAX_DPLL_DIV,
 424         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 425 };
 426
 427 static struct clk dpll3_ck = {
 428         .name           = "dpll3_ck",
 429         .parent         = &sys_ck,
 430         .dpll_data      = &dpll3_dd,
 431         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 432         .round_rate     = &omap2_dpll_round_rate,
 433         .recalc         = &omap3_dpll_recalc,
 434 };
 435
 436 /*
 437  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 438  * DPLL isn't bypassed
 439  */
 440 static struct clk dpll3_x2_ck = {
 441         .name           = "dpll3_x2_ck",
 442         .parent         = &dpll3_ck,
 443         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 444                                 PARENT_CONTROLS_CLOCK,
 445         .recalc         = &omap3_clkoutx2_recalc,
 446 };
 447
 448 static const struct clksel_rate div31_dpll3_rates[] = {
 449         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 450         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 451         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 452         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 453         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 454         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 455         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 456         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 457         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 458         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 459         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 460         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 461         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 462         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 463         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 464         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 465         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 466         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 467         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 468         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 469         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 470         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 471         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 472         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 473         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 474         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 475         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 476         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 477         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 478         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 479         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 480         { .div = 0 },
 481 };
 482
 483 static const struct clksel div31_dpll3m2_clksel[] = {
 484         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 485         { .parent = NULL }
 486 };
 487
 488 /* DPLL3 output M2 - primary control point for CORE speed */
 489 static struct clk dpll3_m2_ck = {
 490         .name           = "dpll3_m2_ck",
 491         .parent         = &dpll3_ck,
 492         .init           = &omap2_init_clksel_parent,
 493         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 494         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 495         .clksel         = div31_dpll3m2_clksel,
 496         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 497                                 PARENT_CONTROLS_CLOCK,
 498         .round_rate     = &omap2_clksel_round_rate,
 499         .set_rate       = &omap3_core_dpll_m2_set_rate,
 500         .recalc         = &omap2_clksel_recalc,
 501 };
 502
 503 static const struct clksel core_ck_clksel[] = {
 504         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 505         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 506         { .parent = NULL }
 507 };
 508
 509 static struct clk core_ck = {
 510         .name           = "core_ck",
 511         .init           = &omap2_init_clksel_parent,
 512         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 513         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 514         .clksel         = core_ck_clksel,
 515         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 516                                 PARENT_CONTROLS_CLOCK,
 517         .recalc         = &omap2_clksel_recalc,
 518 };
 519
 520 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 521         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 522         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 523         { .parent = NULL }
 524 };
 525
 526 static struct clk dpll3_m2x2_ck = {
 527         .name           = "dpll3_m2x2_ck",
 528         .init           = &omap2_init_clksel_parent,
 529         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 530         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 531         .clksel         = dpll3_m2x2_ck_clksel,
 532         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 533                                 PARENT_CONTROLS_CLOCK,
 534         .recalc         = &omap2_clksel_recalc,
 535 };
 536
 537 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 538 static const struct clksel div16_dpll3_clksel[] = {
 539         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 540         { .parent = NULL }
 541 };
 542
 543 /* This virtual clock is the source for dpll3_m3x2_ck */
 544 static struct clk dpll3_m3_ck = {
 545         .name           = "dpll3_m3_ck",
 546         .parent         = &dpll3_ck,
 547         .init           = &omap2_init_clksel_parent,
 548         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 549         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 550         .clksel         = div16_dpll3_clksel,
 551         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 552                                 PARENT_CONTROLS_CLOCK,
 553         .recalc         = &omap2_clksel_recalc,
 554 };
 555
 556 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 557 static struct clk dpll3_m3x2_ck = {
 558         .name           = "dpll3_m3x2_ck",
 559         .parent         = &dpll3_m3_ck,
 560         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 561         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 562         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 563         .recalc         = &omap3_clkoutx2_recalc,
 564 };
 565
 566 static const struct clksel emu_core_alwon_ck_clksel[] = {
 567         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 568         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 569         { .parent = NULL }
 570 };
 571
 572 static struct clk emu_core_alwon_ck = {
 573         .name           = "emu_core_alwon_ck",
 574         .parent         = &dpll3_m3x2_ck,
 575         .init           = &omap2_init_clksel_parent,
 576         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 577         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 578         .clksel         = emu_core_alwon_ck_clksel,
 579         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 580                                 PARENT_CONTROLS_CLOCK,
 581         .recalc         = &omap2_clksel_recalc,
 582 };
 583
 584 /* DPLL4 */
 585 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 586 /* Type: DPLL */
 587 static struct dpll_data dpll4_dd = {
 588         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 589         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 590         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 591         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 592         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 593         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 594         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 595         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 596         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 597         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 598         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 599         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 600         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 601         .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
 602         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 603         .max_divider    = OMAP3_MAX_DPLL_DIV,
 604         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 605 };
 606
 607 static struct clk dpll4_ck = {
 608         .name           = "dpll4_ck",
 609         .parent         = &sys_ck,
 610         .dpll_data      = &dpll4_dd,
 611         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 612         .enable         = &omap3_noncore_dpll_enable,
 613         .disable        = &omap3_noncore_dpll_disable,
 614         .round_rate     = &omap2_dpll_round_rate,
 615         .set_rate       = &omap3_noncore_dpll_set_rate,
 616         .recalc         = &omap3_dpll_recalc,
 617 };
 618
 619 /*
 620  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 621  * DPLL isn't bypassed --
 622  * XXX does this serve any downstream clocks?
 623  */
 624 static struct clk dpll4_x2_ck = {
 625         .name           = "dpll4_x2_ck",
 626         .parent         = &dpll4_ck,
 627         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 628                                 PARENT_CONTROLS_CLOCK,
 629         .recalc         = &omap3_clkoutx2_recalc,
 630 };
 631
 632 static const struct clksel div16_dpll4_clksel[] = {
 633         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 634         { .parent = NULL }
 635 };
 636
 637 /* This virtual clock is the source for dpll4_m2x2_ck */
 638 static struct clk dpll4_m2_ck = {
 639         .name           = "dpll4_m2_ck",
 640         .parent         = &dpll4_ck,
 641         .init           = &omap2_init_clksel_parent,
 642         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 643         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 644         .clksel         = div16_dpll4_clksel,
 645         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 646                                 PARENT_CONTROLS_CLOCK,
 647         .recalc         = &omap2_clksel_recalc,
 648 };
 649
 650 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 651 static struct clk dpll4_m2x2_ck = {
 652         .name           = "dpll4_m2x2_ck",
 653         .parent         = &dpll4_m2_ck,
 654         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 655         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 656         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 657         .recalc         = &omap3_clkoutx2_recalc,
 658 };
 659
 660 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 661         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 662         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 663         { .parent = NULL }
 664 };
 665
 666 /*
 667  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 668  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 669  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 670  * CM_96K_(F)CLK.
 671  */
 672 static struct clk omap_96m_alwon_fck = {
 673         .name           = "omap_96m_alwon_fck",
 674         .parent         = &dpll4_m2x2_ck,
 675         .init           = &omap2_init_clksel_parent,
 676         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 677         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 678         .clksel         = omap_96m_alwon_fck_clksel,
 679         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 680                                 PARENT_CONTROLS_CLOCK,
 681         .recalc         = &omap2_clksel_recalc,
 682 };
 683
 684 static struct clk cm_96m_fck = {
 685         .name           = "cm_96m_fck",
 686         .parent         = &omap_96m_alwon_fck,
 687         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 688                                 PARENT_CONTROLS_CLOCK,
 689         .recalc         = &followparent_recalc,
 690 };
 691
 692 static const struct clksel_rate omap_96m_dpll_rates[] = {
 693         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 694         { .div = 0 }
 695 };
 696
 697 static const struct clksel_rate omap_96m_sys_rates[] = {
 698         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 699         { .div = 0 }
 700 };
 701
 702 static const struct clksel omap_96m_fck_clksel[] = {
 703         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 704         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 705         { .parent = NULL }
 706 };
 707
 708 static struct clk omap_96m_fck = {
 709         .name           = "omap_96m_fck",
 710         .parent         = &sys_ck,
 711         .init           = &omap2_init_clksel_parent,
 712         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 713         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 714         .clksel         = omap_96m_fck_clksel,
 715         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 716                                 PARENT_CONTROLS_CLOCK,
 717         .recalc         = &omap2_clksel_recalc,
 718 };
 719
 720 /* This virtual clock is the source for dpll4_m3x2_ck */
 721 static struct clk dpll4_m3_ck = {
 722         .name           = "dpll4_m3_ck",
 723         .parent         = &dpll4_ck,
 724         .init           = &omap2_init_clksel_parent,
 725         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 726         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 727         .clksel         = div16_dpll4_clksel,
 728         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 729                                 PARENT_CONTROLS_CLOCK,
 730         .recalc         = &omap2_clksel_recalc,
 731 };
 732
 733 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 734 static struct clk dpll4_m3x2_ck = {
 735         .name           = "dpll4_m3x2_ck",
 736         .parent         = &dpll4_m3_ck,
 737         .init           = &omap2_init_clksel_parent,
 738         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 739         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 740         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 741         .recalc         = &omap3_clkoutx2_recalc,
 742 };
 743
 744 static const struct clksel virt_omap_54m_fck_clksel[] = {
 745         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 746         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 747         { .parent = NULL }
 748 };
 749
 750 static struct clk virt_omap_54m_fck = {
 751         .name           = "virt_omap_54m_fck",
 752         .parent         = &dpll4_m3x2_ck,
 753         .init           = &omap2_init_clksel_parent,
 754         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
 755         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 756         .clksel         = virt_omap_54m_fck_clksel,
 757         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 758                                 PARENT_CONTROLS_CLOCK,
 759         .recalc         = &omap2_clksel_recalc,
 760 };
 761
 762 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 763         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 764         { .div = 0 }
 765 };
 766
 767 static const struct clksel_rate omap_54m_alt_rates[] = {
 768         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 769         { .div = 0 }
 770 };
 771
 772 static const struct clksel omap_54m_clksel[] = {
 773         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 774         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 775         { .parent = NULL }
 776 };
 777
 778 static struct clk omap_54m_fck = {
 779         .name           = "omap_54m_fck",
 780         .init           = &omap2_init_clksel_parent,
 781         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 782         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 783         .clksel         = omap_54m_clksel,
 784         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 785                                 PARENT_CONTROLS_CLOCK,
 786         .recalc         = &omap2_clksel_recalc,
 787 };
 788
 789 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 790         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 791         { .div = 0 }
 792 };
 793
 794 static const struct clksel_rate omap_48m_alt_rates[] = {
 795         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 796         { .div = 0 }
 797 };
 798
 799 static const struct clksel omap_48m_clksel[] = {
 800         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 801         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 802         { .parent = NULL }
 803 };
 804
 805 static struct clk omap_48m_fck = {
 806         .name           = "omap_48m_fck",
 807         .init           = &omap2_init_clksel_parent,
 808         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 809         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 810         .clksel         = omap_48m_clksel,
 811         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 812                                 PARENT_CONTROLS_CLOCK,
 813         .recalc         = &omap2_clksel_recalc,
 814 };
 815
 816 static struct clk omap_12m_fck = {
 817         .name           = "omap_12m_fck",
 818         .parent         = &omap_48m_fck,
 819         .fixed_div      = 4,
 820         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 821                                 PARENT_CONTROLS_CLOCK,
 822         .recalc         = &omap2_fixed_divisor_recalc,
 823 };
 824
 825 /* This virstual clock is the source for dpll4_m4x2_ck */
 826 static struct clk dpll4_m4_ck = {
 827         .name           = "dpll4_m4_ck",
 828         .parent         = &dpll4_ck,
 829         .init           = &omap2_init_clksel_parent,
 830         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 831         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 832         .clksel         = div16_dpll4_clksel,
 833         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 834                                 PARENT_CONTROLS_CLOCK,
 835         .recalc         = &omap2_clksel_recalc,
 836 };
 837
 838 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 839 static struct clk dpll4_m4x2_ck = {
 840         .name           = "dpll4_m4x2_ck",
 841         .parent         = &dpll4_m4_ck,
 842         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 843         .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
 844         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 845         .recalc         = &omap3_clkoutx2_recalc,
 846 };
 847
 848 /* This virtual clock is the source for dpll4_m5x2_ck */
 849 static struct clk dpll4_m5_ck = {
 850         .name           = "dpll4_m5_ck",
 851         .parent         = &dpll4_ck,
 852         .init           = &omap2_init_clksel_parent,
 853         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 854         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 855         .clksel         = div16_dpll4_clksel,
 856         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 857                                 PARENT_CONTROLS_CLOCK,
 858         .recalc         = &omap2_clksel_recalc,
 859 };
 860
 861 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 862 static struct clk dpll4_m5x2_ck = {
 863         .name           = "dpll4_m5x2_ck",
 864         .parent         = &dpll4_m5_ck,
 865         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 866         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 867         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 868         .recalc         = &omap3_clkoutx2_recalc,
 869 };
 870
 871 /* This virtual clock is the source for dpll4_m6x2_ck */
 872 static struct clk dpll4_m6_ck = {
 873         .name           = "dpll4_m6_ck",
 874         .parent         = &dpll4_ck,
 875         .init           = &omap2_init_clksel_parent,
 876         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 877         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 878         .clksel         = div16_dpll4_clksel,
 879         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 880                                 PARENT_CONTROLS_CLOCK,
 881         .recalc         = &omap2_clksel_recalc,
 882 };
 883
 884 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 885 static struct clk dpll4_m6x2_ck = {
 886         .name           = "dpll4_m6x2_ck",
 887         .parent         = &dpll4_m6_ck,
 888         .init           = &omap2_init_clksel_parent,
 889         .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
 890         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 891         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 892         .recalc         = &omap3_clkoutx2_recalc,
 893 };
 894
 895 static struct clk emu_per_alwon_ck = {
 896         .name           = "emu_per_alwon_ck",
 897         .parent         = &dpll4_m6x2_ck,
 898         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 899                                 PARENT_CONTROLS_CLOCK,
 900         .recalc         = &followparent_recalc,
 901 };
 902
 903 /* DPLL5 */
 904 /* Supplies 120MHz clock, USIM source clock */
 905 /* Type: DPLL */
 906 /* 3430ES2 only */
 907 static struct dpll_data dpll5_dd = {
 908         .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 909         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 910         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 911         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 912         .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 913         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 914         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 915         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 916         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 917         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 918         .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 919         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 920         .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 921         .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
 922         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 923         .max_divider    = OMAP3_MAX_DPLL_DIV,
 924         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 925 };
 926
 927 static struct clk dpll5_ck = {
 928         .name           = "dpll5_ck",
 929         .parent         = &sys_ck,
 930         .dpll_data      = &dpll5_dd,
 931         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 932         .enable         = &omap3_noncore_dpll_enable,
 933         .disable        = &omap3_noncore_dpll_disable,
 934         .round_rate     = &omap2_dpll_round_rate,
 935         .set_rate       = &omap3_noncore_dpll_set_rate,
 936         .recalc         = &omap3_dpll_recalc,
 937 };
 938
 939 static const struct clksel div16_dpll5_clksel[] = {
 940         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 941         { .parent = NULL }
 942 };
 943
 944 static struct clk dpll5_m2_ck = {
 945         .name           = "dpll5_m2_ck",
 946         .parent         = &dpll5_ck,
 947         .init           = &omap2_init_clksel_parent,
 948         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 949         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 950         .clksel         = div16_dpll5_clksel,
 951         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 952                                 PARENT_CONTROLS_CLOCK,
 953         .recalc         = &omap2_clksel_recalc,
 954 };
 955
 956 static const struct clksel omap_120m_fck_clksel[] = {
 957         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 958         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
 959         { .parent = NULL }
 960 };
 961
 962 static struct clk omap_120m_fck = {
 963         .name           = "omap_120m_fck",
 964         .parent         = &dpll5_m2_ck,
 965         .init           = &omap2_init_clksel_parent,
 966         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 967         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 968         .clksel         = omap_120m_fck_clksel,
 969         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 970                                 PARENT_CONTROLS_CLOCK,
 971         .recalc         = &omap2_clksel_recalc,
 972 };
 973
 974 /* CM EXTERNAL CLOCK OUTPUTS */
 975
 976 static const struct clksel_rate clkout2_src_core_rates[] = {
 977         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 978         { .div = 0 }
 979 };
 980
 981 static const struct clksel_rate clkout2_src_sys_rates[] = {
 982         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 983         { .div = 0 }
 984 };
 985
 986 static const struct clksel_rate clkout2_src_96m_rates[] = {
 987         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 988         { .div = 0 }
 989 };
 990
 991 static const struct clksel_rate clkout2_src_54m_rates[] = {
 992         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 993         { .div = 0 }
 994 };
 995
 996 static const struct clksel clkout2_src_clksel[] = {
 997         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
 998         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
 999         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
1000         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
1001         { .parent = NULL }
1002 };
1003
1004 static struct clk clkout2_src_ck = {
1005         .name           = "clkout2_src_ck",
1006         .init           = &omap2_init_clksel_parent,
1007         .enable_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1008         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
1009         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1010         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
1011         .clksel         = clkout2_src_clksel,
1012         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1013         .clkdm          = { .name = "core_l4_clkdm" },
1014         .recalc         = &omap2_clksel_recalc,
1015 };
1016
1017 static const struct clksel_rate sys_clkout2_rates[] = {
1018         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1019         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1020         { .div = 4, .val = 2, .flags = RATE_IN_343X },
1021         { .div = 8, .val = 3, .flags = RATE_IN_343X },
1022         { .div = 16, .val = 4, .flags = RATE_IN_343X },
1023         { .div = 0 },
1024 };
1025
1026 static const struct clksel sys_clkout2_clksel[] = {
1027         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1028         { .parent = NULL },
1029 };
1030
1031 static struct clk sys_clkout2 = {
1032         .name           = "sys_clkout2",
1033         .init           = &omap2_init_clksel_parent,
1034         .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
1035         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1036         .clksel         = sys_clkout2_clksel,
1037         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1038         .recalc         = &omap2_clksel_recalc,
1039 };
1040
1041 /* CM OUTPUT CLOCKS */
1042
1043 static struct clk corex2_fck = {
1044         .name           = "corex2_fck",
1045         .parent         = &dpll3_m2x2_ck,
1046         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1047                                 PARENT_CONTROLS_CLOCK,
1048         .recalc         = &followparent_recalc,
1049 };
1050
1051 /* DPLL power domain clock controls */
1052
1053 static const struct clksel_rate div4_rates[] = {
1054         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1055         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1056         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1057         { .div = 0 }
1058 };
1059
1060 static const struct clksel div4_core_clksel[] = {
1061         { .parent = &core_ck, .rates = div4_rates },
1062         { .parent = NULL }
1063 };
1064
1065 /*
1066  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1067  * may be inconsistent here?
1068  */
1069 static struct clk dpll1_fck = {
1070         .name           = "dpll1_fck",
1071         .parent         = &core_ck,
1072         .init           = &omap2_init_clksel_parent,
1073         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1074         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1075         .clksel         = div4_core_clksel,
1076         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1077                                 PARENT_CONTROLS_CLOCK,
1078         .recalc         = &omap2_clksel_recalc,
1079 };
1080
1081 /*
1082  * MPU clksel:
1083  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1084  * derives from the high-frequency bypass clock originating from DPLL3,
1085  * called 'dpll1_fck'
1086  */
1087 static const struct clksel mpu_clksel[] = {
1088         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1089         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1090         { .parent = NULL }
1091 };
1092
1093 static struct clk mpu_ck = {
1094         .name           = "mpu_ck",
1095         .parent         = &dpll1_x2m2_ck,
1096         .init           = &omap2_init_clksel_parent,
1097         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1098         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1099         .clksel         = mpu_clksel,
1100         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1101                                 PARENT_CONTROLS_CLOCK,
1102         .clkdm          = { .name = "mpu_clkdm" },
1103         .recalc         = &omap2_clksel_recalc,
1104 };
1105
1106 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1107 static const struct clksel_rate arm_fck_rates[] = {
1108         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1109         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1110         { .div = 0 },
1111 };
1112
1113 static const struct clksel arm_fck_clksel[] = {
1114         { .parent = &mpu_ck, .rates = arm_fck_rates },
1115         { .parent = NULL }
1116 };
1117
1118 static struct clk arm_fck = {
1119         .name           = "arm_fck",
1120         .parent         = &mpu_ck,
1121         .init           = &omap2_init_clksel_parent,
1122         .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1123         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1124         .clksel         = arm_fck_clksel,
1125         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1126                                 PARENT_CONTROLS_CLOCK,
1127         .recalc         = &omap2_clksel_recalc,
1128 };
1129
1130 /* XXX What about neon_clkdm ? */
1131
1132 /*
1133  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1134  * although it is referenced - so this is a guess
1135  */
1136 static struct clk emu_mpu_alwon_ck = {
1137         .name           = "emu_mpu_alwon_ck",
1138         .parent         = &mpu_ck,
1139         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1140                                 PARENT_CONTROLS_CLOCK,
1141         .recalc         = &followparent_recalc,
1142 };
1143
1144 static struct clk dpll2_fck = {
1145         .name           = "dpll2_fck",
1146         .parent         = &core_ck,
1147         .init           = &omap2_init_clksel_parent,
1148         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1149         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1150         .clksel         = div4_core_clksel,
1151         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1152                                 PARENT_CONTROLS_CLOCK,
1153         .recalc         = &omap2_clksel_recalc,
1154 };
1155
1156 /*
1157  * IVA2 clksel:
1158  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1159  * derives from the high-frequency bypass clock originating from DPLL3,
1160  * called 'dpll2_fck'
1161  */
1162
1163 static const struct clksel iva2_clksel[] = {
1164         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1165         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1166         { .parent = NULL }
1167 };
1168
1169 static struct clk iva2_ck = {
1170         .name           = "iva2_ck",
1171         .parent         = &dpll2_m2_ck,
1172         .init           = &omap2_init_clksel_parent,
1173         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1174         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1175         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
1176                                           OMAP3430_CM_IDLEST_PLL),
1177         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1178         .clksel         = iva2_clksel,
1179         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1180         .clkdm          = { .name = "iva2_clkdm" },
1181         .recalc         = &omap2_clksel_recalc,
1182 };
1183
1184 /* Common interface clocks */
1185
1186 static const struct clksel div2_core_clksel[] = {
1187         { .parent = &core_ck, .rates = div2_rates },
1188         { .parent = NULL }
1189 };
1190
1191 static struct clk l3_ick = {
1192         .name           = "l3_ick",
1193         .parent         = &core_ck,
1194         .init           = &omap2_init_clksel_parent,
1195         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1196         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1197         .clksel         = div2_core_clksel,
1198         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1199                                 PARENT_CONTROLS_CLOCK,
1200         .clkdm          = { .name = "core_l3_clkdm" },
1201         .recalc         = &omap2_clksel_recalc,
1202 };
1203
1204 static const struct clksel div2_l3_clksel[] = {
1205         { .parent = &l3_ick, .rates = div2_rates },
1206         { .parent = NULL }
1207 };
1208
1209 static struct clk l4_ick = {
1210         .name           = "l4_ick",
1211         .parent         = &l3_ick,
1212         .init           = &omap2_init_clksel_parent,
1213         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1214         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1215         .clksel         = div2_l3_clksel,
1216         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1217                                 PARENT_CONTROLS_CLOCK,
1218         .clkdm          = { .name = "core_l4_clkdm" },
1219         .recalc         = &omap2_clksel_recalc,
1220
1221 };
1222
1223 static const struct clksel div2_l4_clksel[] = {
1224         { .parent = &l4_ick, .rates = div2_rates },
1225         { .parent = NULL }
1226 };
1227
1228 static struct clk rm_ick = {
1229         .name           = "rm_ick",
1230         .parent         = &l4_ick,
1231         .init           = &omap2_init_clksel_parent,
1232         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1233         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1234         .clksel         = div2_l4_clksel,
1235         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1236         .recalc         = &omap2_clksel_recalc,
1237 };
1238
1239 /* GFX power domain */
1240
1241 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1242
1243 static const struct clksel gfx_l3_clksel[] = {
1244         { .parent = &l3_ick, .rates = gfx_l3_rates },
1245         { .parent = NULL }
1246 };
1247
1248 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1249 static struct clk gfx_l3_ck = {
1250         .name           = "gfx_l3_ck",
1251         .parent         = &l3_ick,
1252         .init           = &omap2_init_clksel_parent,
1253         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1254         .enable_bit     = OMAP_EN_GFX_SHIFT,
1255         .flags          = CLOCK_IN_OMAP3430ES1,
1256         .recalc         = &followparent_recalc,
1257 };
1258
1259 static struct clk gfx_l3_fck = {
1260         .name           = "gfx_l3_fck",
1261         .parent         = &gfx_l3_ck,
1262         .init           = &omap2_init_clksel_parent,
1263         .clksel_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1264         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1265         .clksel         = gfx_l3_clksel,
1266         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1267                                 PARENT_CONTROLS_CLOCK,
1268         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1269         .recalc         = &omap2_clksel_recalc,
1270 };
1271
1272 static struct clk gfx_l3_ick = {
1273         .name           = "gfx_l3_ick",
1274         .parent         = &gfx_l3_ck,
1275         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1276         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1277         .recalc         = &followparent_recalc,
1278 };
1279
1280 static struct clk gfx_cg1_ck = {
1281         .name           = "gfx_cg1_ck",
1282         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1283         .init           = &omap2_init_clk_clkdm,
1284         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1285         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1286         .flags          = CLOCK_IN_OMAP3430ES1,
1287         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1288         .recalc         = &followparent_recalc,
1289 };
1290
1291 static struct clk gfx_cg2_ck = {
1292         .name           = "gfx_cg2_ck",
1293         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1294         .init           = &omap2_init_clk_clkdm,
1295         .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1296         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1297         .flags          = CLOCK_IN_OMAP3430ES1,
1298         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1299         .recalc         = &followparent_recalc,
1300 };
1301
1302 /* SGX power domain - 3430ES2 only */
1303
1304 static const struct clksel_rate sgx_core_rates[] = {
1305         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1306         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1307         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1308         { .div = 0 },
1309 };
1310
1311 static const struct clksel_rate sgx_96m_rates[] = {
1312         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1313         { .div = 0 },
1314 };
1315
1316 static const struct clksel sgx_clksel[] = {
1317         { .parent = &core_ck,    .rates = sgx_core_rates },
1318         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1319         { .parent = NULL },
1320 };
1321
1322 static struct clk sgx_fck = {
1323         .name           = "sgx_fck",
1324         .init           = &omap2_init_clksel_parent,
1325         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1326         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1327         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1328         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1329         .clksel         = sgx_clksel,
1330         .flags          = CLOCK_IN_OMAP3430ES2,
1331         .clkdm          = { .name = "sgx_clkdm" },
1332         .recalc         = &omap2_clksel_recalc,
1333 };
1334
1335 static struct clk sgx_ick = {
1336         .name           = "sgx_ick",
1337         .parent         = &l3_ick,
1338         .init           = &omap2_init_clk_clkdm,
1339         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1340         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1341         .flags          = CLOCK_IN_OMAP3430ES2,
1342         .clkdm          = { .name = "sgx_clkdm" },
1343         .recalc         = &followparent_recalc,
1344 };
1345
1346 /* CORE power domain */
1347
1348 static struct clk d2d_26m_fck = {
1349         .name           = "d2d_26m_fck",
1350         .parent         = &sys_ck,
1351         .init           = &omap2_init_clk_clkdm,
1352         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1353         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1354         .flags          = CLOCK_IN_OMAP3430ES1,
1355         .clkdm          = { .name = "d2d_clkdm" },
1356         .recalc         = &followparent_recalc,
1357 };
1358
1359 static const struct clksel omap343x_gpt_clksel[] = {
1360         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1361         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1362         { .parent = NULL}
1363 };
1364
1365 static struct clk gpt10_fck = {
1366         .name           = "gpt10_fck",
1367         .parent         = &sys_ck,
1368         .init           = &omap2_init_clksel_parent,
1369         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1370         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1371         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1372         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1373         .clksel         = omap343x_gpt_clksel,
1374         .flags          = CLOCK_IN_OMAP343X,
1375         .clkdm          = { .name = "core_l4_clkdm" },
1376         .recalc         = &omap2_clksel_recalc,
1377 };
1378
1379 static struct clk gpt11_fck = {
1380         .name           = "gpt11_fck",
1381         .parent         = &sys_ck,
1382         .init           = &omap2_init_clksel_parent,
1383         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1384         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1385         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1386         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1387         .clksel         = omap343x_gpt_clksel,
1388         .flags          = CLOCK_IN_OMAP343X,
1389         .clkdm          = { .name = "core_l4_clkdm" },
1390         .recalc         = &omap2_clksel_recalc,
1391 };
1392
1393 static struct clk cpefuse_fck = {
1394         .name           = "cpefuse_fck",
1395         .parent         = &sys_ck,
1396         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1397         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1398         .flags          = CLOCK_IN_OMAP3430ES2,
1399         .recalc         = &followparent_recalc,
1400 };
1401
1402 static struct clk ts_fck = {
1403         .name           = "ts_fck",
1404         .parent         = &omap_32k_fck,
1405         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1406         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1407         .flags          = CLOCK_IN_OMAP3430ES2,
1408         .recalc         = &followparent_recalc,
1409 };
1410
1411 static struct clk usbtll_fck = {
1412         .name           = "usbtll_fck",
1413         .parent         = &omap_120m_fck,
1414         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1415         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1416         .flags          = CLOCK_IN_OMAP3430ES2,
1417         .recalc         = &followparent_recalc,
1418 };
1419
1420 /* CORE 96M FCLK-derived clocks */
1421
1422 static struct clk core_96m_fck = {
1423         .name           = "core_96m_fck",
1424         .parent         = &omap_96m_fck,
1425         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1426                                 PARENT_CONTROLS_CLOCK,
1427         .clkdm          = { .name = "core_l4_clkdm" },
1428         .recalc         = &followparent_recalc,
1429 };
1430
1431 static struct clk mmchs3_fck = {
1432         .name           = "mmchs_fck",
1433         .id             = 3,
1434         .parent         = &core_96m_fck,
1435         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1436         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1437         .flags          = CLOCK_IN_OMAP3430ES2,
1438         .clkdm          = { .name = "core_l4_clkdm" },
1439         .recalc         = &followparent_recalc,
1440 };
1441
1442 static struct clk mmchs2_fck = {
1443         .name           = "mmchs_fck",
1444         .id             = 2,
1445         .parent         = &core_96m_fck,
1446         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1447         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1448         .flags          = CLOCK_IN_OMAP343X,
1449         .clkdm          = { .name = "core_l4_clkdm" },
1450         .recalc         = &followparent_recalc,
1451 };
1452
1453 static struct clk mspro_fck = {
1454         .name           = "mspro_fck",
1455         .parent         = &core_96m_fck,
1456         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1457         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1458         .flags          = CLOCK_IN_OMAP343X,
1459         .clkdm          = { .name = "core_l4_clkdm" },
1460         .recalc         = &followparent_recalc,
1461 };
1462
1463 static struct clk mmchs1_fck = {
1464         .name           = "mmchs_fck",
1465         .id             = 1,
1466         .parent         = &core_96m_fck,
1467         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1468         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1469         .flags          = CLOCK_IN_OMAP343X,
1470         .clkdm          = { .name = "core_l4_clkdm" },
1471         .recalc         = &followparent_recalc,
1472 };
1473
1474 static struct clk i2c3_fck = {
1475         .name           = "i2c_fck",
1476         .id             = 3,
1477         .parent         = &core_96m_fck,
1478         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1479         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1480         .flags          = CLOCK_IN_OMAP343X,
1481         .clkdm          = { .name = "core_l4_clkdm" },
1482         .recalc         = &followparent_recalc,
1483 };
1484
1485 static struct clk i2c2_fck = {
1486         .name           = "i2c_fck",
1487         .id             = 2,
1488         .parent         = &core_96m_fck,
1489         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1490         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1491         .flags          = CLOCK_IN_OMAP343X,
1492         .clkdm          = { .name = "core_l4_clkdm" },
1493         .recalc         = &followparent_recalc,
1494 };
1495
1496 static struct clk i2c1_fck = {
1497         .name           = "i2c_fck",
1498         .id             = 1,
1499         .parent         = &core_96m_fck,
1500         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1501         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1502         .flags          = CLOCK_IN_OMAP343X,
1503         .clkdm          = { .name = "core_l4_clkdm" },
1504         .recalc         = &followparent_recalc,
1505 };
1506
1507 /*
1508  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1509  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1510  */
1511 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1512         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1513         { .div = 0 }
1514 };
1515
1516 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1517         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1518         { .div = 0 }
1519 };
1520
1521 static const struct clksel mcbsp_15_clksel[] = {
1522         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1523         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1524         { .parent = NULL }
1525 };
1526
1527 static struct clk mcbsp5_fck = {
1528         .name           = "mcbsp_fck",
1529         .id             = 5,
1530         .init           = &omap2_init_clksel_parent,
1531         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1532         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1533         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1534         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1535         .clksel         = mcbsp_15_clksel,
1536         .flags          = CLOCK_IN_OMAP343X,
1537         .clkdm          = { .name = "core_l4_clkdm" },
1538         .recalc         = &omap2_clksel_recalc,
1539 };
1540
1541 static struct clk mcbsp1_fck = {
1542         .name           = "mcbsp_fck",
1543         .id             = 1,
1544         .init           = &omap2_init_clksel_parent,
1545         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1546         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1547         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1548         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1549         .clksel         = mcbsp_15_clksel,
1550         .flags          = CLOCK_IN_OMAP343X,
1551         .clkdm          = { .name = "core_l4_clkdm" },
1552         .recalc         = &omap2_clksel_recalc,
1553 };
1554
1555 /* CORE_48M_FCK-derived clocks */
1556
1557 static struct clk core_48m_fck = {
1558         .name           = "core_48m_fck",
1559         .parent         = &omap_48m_fck,
1560         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1561                                 PARENT_CONTROLS_CLOCK,
1562         .clkdm          = { .name = "core_l4_clkdm" },
1563         .recalc         = &followparent_recalc,
1564 };
1565
1566 static struct clk mcspi4_fck = {
1567         .name           = "mcspi_fck",
1568         .id             = 4,
1569         .parent         = &core_48m_fck,
1570         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1571         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1572         .flags          = CLOCK_IN_OMAP343X,
1573         .recalc         = &followparent_recalc,
1574 };
1575
1576 static struct clk mcspi3_fck = {
1577         .name           = "mcspi_fck",
1578         .id             = 3,
1579         .parent         = &core_48m_fck,
1580         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1581         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1582         .flags          = CLOCK_IN_OMAP343X,
1583         .recalc         = &followparent_recalc,
1584 };
1585
1586 static struct clk mcspi2_fck = {
1587         .name           = "mcspi_fck",
1588         .id             = 2,
1589         .parent         = &core_48m_fck,
1590         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1591         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1592         .flags          = CLOCK_IN_OMAP343X,
1593         .recalc         = &followparent_recalc,
1594 };
1595
1596 static struct clk mcspi1_fck = {
1597         .name           = "mcspi_fck",
1598         .id             = 1,
1599         .parent         = &core_48m_fck,
1600         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1601         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1602         .flags          = CLOCK_IN_OMAP343X,
1603         .recalc         = &followparent_recalc,
1604 };
1605
1606 static struct clk uart2_fck = {
1607         .name           = "uart2_fck",
1608         .parent         = &core_48m_fck,
1609         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1610         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1611         .flags          = CLOCK_IN_OMAP343X,
1612         .recalc         = &followparent_recalc,
1613 };
1614
1615 static struct clk uart1_fck = {
1616         .name           = "uart1_fck",
1617         .parent         = &core_48m_fck,
1618         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1619         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1620         .flags          = CLOCK_IN_OMAP343X,
1621         .recalc         = &followparent_recalc,
1622 };
1623
1624 static struct clk fshostusb_fck = {
1625         .name           = "fshostusb_fck",
1626         .parent         = &core_48m_fck,
1627         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1628         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1629         .flags          = CLOCK_IN_OMAP3430ES1,
1630         .recalc         = &followparent_recalc,
1631 };
1632
1633 /* CORE_12M_FCK based clocks */
1634
1635 static struct clk core_12m_fck = {
1636         .name           = "core_12m_fck",
1637         .parent         = &omap_12m_fck,
1638         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1639                                 PARENT_CONTROLS_CLOCK,
1640         .clkdm          = { .name = "core_l4_clkdm" },
1641         .recalc         = &followparent_recalc,
1642 };
1643
1644 static struct clk hdq_fck = {
1645         .name           = "hdq_fck",
1646         .parent         = &core_12m_fck,
1647         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1648         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1649         .flags          = CLOCK_IN_OMAP343X,
1650         .recalc         = &followparent_recalc,
1651 };
1652
1653 /* DPLL3-derived clock */
1654
1655 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1656         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1657         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1658         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1659         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1660         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1661         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1662         { .div = 0 }
1663 };
1664
1665 static const struct clksel ssi_ssr_clksel[] = {
1666         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1667         { .parent = NULL }
1668 };
1669
1670 static struct clk ssi_ssr_fck = {
1671         .name           = "ssi_ssr_fck",
1672         .init           = &omap2_init_clksel_parent,
1673         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1674         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1675         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1676         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1677         .clksel         = ssi_ssr_clksel,
1678         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1679         .clkdm          = { .name = "core_l4_clkdm" },
1680         .recalc         = &omap2_clksel_recalc,
1681 };
1682
1683 static struct clk ssi_sst_fck = {
1684         .name           = "ssi_sst_fck",
1685         .parent         = &ssi_ssr_fck,
1686         .fixed_div      = 2,
1687         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1688         .recalc         = &omap2_fixed_divisor_recalc,
1689 };
1690
1691
1692
1693 /* CORE_L3_ICK based clocks */
1694
1695 /*
1696  * XXX must add clk_enable/clk_disable for these if standard code won't
1697  * handle it
1698  */
1699 static struct clk core_l3_ick = {
1700         .name           = "core_l3_ick",
1701         .parent         = &l3_ick,
1702         .init           = &omap2_init_clk_clkdm,
1703         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1704                                 PARENT_CONTROLS_CLOCK,
1705         .clkdm          = { .name = "core_l3_clkdm" },
1706         .recalc         = &followparent_recalc,
1707 };
1708
1709 static struct clk hsotgusb_ick = {
1710         .name           = "hsotgusb_ick",
1711         .parent         = &core_l3_ick,
1712         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1713         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1714         .flags          = CLOCK_IN_OMAP343X,
1715         .clkdm          = { .name = "core_l3_clkdm" },
1716         .recalc         = &followparent_recalc,
1717 };
1718
1719 static struct clk sdrc_ick = {
1720         .name           = "sdrc_ick",
1721         .parent         = &core_l3_ick,
1722         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1723         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1724         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1725         .clkdm          = { .name = "core_l3_clkdm" },
1726         .recalc         = &followparent_recalc,
1727 };
1728
1729 static struct clk gpmc_fck = {
1730         .name           = "gpmc_fck",
1731         .parent         = &core_l3_ick,
1732         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1733                                 ENABLE_ON_INIT,
1734         .clkdm          = { .name = "core_l3_clkdm" },
1735         .recalc         = &followparent_recalc,
1736 };
1737
1738 /* SECURITY_L3_ICK based clocks */
1739
1740 static struct clk security_l3_ick = {
1741         .name           = "security_l3_ick",
1742         .parent         = &l3_ick,
1743         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1744                                 PARENT_CONTROLS_CLOCK,
1745         .recalc         = &followparent_recalc,
1746 };
1747
1748 static struct clk pka_ick = {
1749         .name           = "pka_ick",
1750         .parent         = &security_l3_ick,
1751         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1752         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1753         .flags          = CLOCK_IN_OMAP343X,
1754         .recalc         = &followparent_recalc,
1755 };
1756
1757 /* CORE_L4_ICK based clocks */
1758
1759 static struct clk core_l4_ick = {
1760         .name           = "core_l4_ick",
1761         .parent         = &l4_ick,
1762         .init           = &omap2_init_clk_clkdm,
1763         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1764                                 PARENT_CONTROLS_CLOCK,
1765         .clkdm          = { .name = "core_l4_clkdm" },
1766         .recalc         = &followparent_recalc,
1767 };
1768
1769 static struct clk usbtll_ick = {
1770         .name           = "usbtll_ick",
1771         .parent         = &core_l4_ick,
1772         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1773         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1774         .flags          = CLOCK_IN_OMAP3430ES2,
1775         .clkdm          = { .name = "core_l4_clkdm" },
1776         .recalc         = &followparent_recalc,
1777 };
1778
1779 static struct clk mmchs3_ick = {
1780         .name           = "mmchs_ick",
1781         .id             = 3,
1782         .parent         = &core_l4_ick,
1783         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1784         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1785         .flags          = CLOCK_IN_OMAP3430ES2,
1786         .clkdm          = { .name = "core_l4_clkdm" },
1787         .recalc         = &followparent_recalc,
1788 };
1789
1790 /* Intersystem Communication Registers - chassis mode only */
1791 static struct clk icr_ick = {
1792         .name           = "icr_ick",
1793         .parent         = &core_l4_ick,
1794         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1795         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1796         .flags          = CLOCK_IN_OMAP343X,
1797         .clkdm          = { .name = "core_l4_clkdm" },
1798         .recalc         = &followparent_recalc,
1799 };
1800
1801 static struct clk aes2_ick = {
1802         .name           = "aes2_ick",
1803         .parent         = &core_l4_ick,
1804         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1805         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1806         .flags          = CLOCK_IN_OMAP343X,
1807         .clkdm          = { .name = "core_l4_clkdm" },
1808         .recalc         = &followparent_recalc,
1809 };
1810
1811 static struct clk sha12_ick = {
1812         .name           = "sha12_ick",
1813         .parent         = &core_l4_ick,
1814         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1815         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1816         .flags          = CLOCK_IN_OMAP343X,
1817         .clkdm          = { .name = "core_l4_clkdm" },
1818         .recalc         = &followparent_recalc,
1819 };
1820
1821 static struct clk des2_ick = {
1822         .name           = "des2_ick",
1823         .parent         = &core_l4_ick,
1824         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1825         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1826         .flags          = CLOCK_IN_OMAP343X,
1827         .clkdm          = { .name = "core_l4_clkdm" },
1828         .recalc         = &followparent_recalc,
1829 };
1830
1831 static struct clk mmchs2_ick = {
1832         .name           = "mmchs_ick",
1833         .id             = 2,
1834         .parent         = &core_l4_ick,
1835         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1836         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1837         .flags          = CLOCK_IN_OMAP343X,
1838         .clkdm          = { .name = "core_l4_clkdm" },
1839         .recalc         = &followparent_recalc,
1840 };
1841
1842 static struct clk mmchs1_ick = {
1843         .name           = "mmchs_ick",
1844         .id             = 1,
1845         .parent         = &core_l4_ick,
1846         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1847         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1848         .flags          = CLOCK_IN_OMAP343X,
1849         .clkdm          = { .name = "core_l4_clkdm" },
1850         .recalc         = &followparent_recalc,
1851 };
1852
1853 static struct clk mspro_ick = {
1854         .name           = "mspro_ick",
1855         .parent         = &core_l4_ick,
1856         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1857         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1858         .flags          = CLOCK_IN_OMAP343X,
1859         .clkdm          = { .name = "core_l4_clkdm" },
1860         .recalc         = &followparent_recalc,
1861 };
1862
1863 static struct clk hdq_ick = {
1864         .name           = "hdq_ick",
1865         .parent         = &core_l4_ick,
1866         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1867         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1868         .flags          = CLOCK_IN_OMAP343X,
1869         .clkdm          = { .name = "core_l4_clkdm" },
1870         .recalc         = &followparent_recalc,
1871 };
1872
1873 static struct clk mcspi4_ick = {
1874         .name           = "mcspi_ick",
1875         .id             = 4,
1876         .parent         = &core_l4_ick,
1877         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1878         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1879         .flags          = CLOCK_IN_OMAP343X,
1880         .clkdm          = { .name = "core_l4_clkdm" },
1881         .recalc         = &followparent_recalc,
1882 };
1883
1884 static struct clk mcspi3_ick = {
1885         .name           = "mcspi_ick",
1886         .id             = 3,
1887         .parent         = &core_l4_ick,
1888         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1889         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1890         .flags          = CLOCK_IN_OMAP343X,
1891         .clkdm          = { .name = "core_l4_clkdm" },
1892         .recalc         = &followparent_recalc,
1893 };
1894
1895 static struct clk mcspi2_ick = {
1896         .name           = "mcspi_ick",
1897         .id             = 2,
1898         .parent         = &core_l4_ick,
1899         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1900         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1901         .flags          = CLOCK_IN_OMAP343X,
1902         .clkdm          = { .name = "core_l4_clkdm" },
1903         .recalc         = &followparent_recalc,
1904 };
1905
1906 static struct clk mcspi1_ick = {
1907         .name           = "mcspi_ick",
1908         .id             = 1,
1909         .parent         = &core_l4_ick,
1910         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1911         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1912         .flags          = CLOCK_IN_OMAP343X,
1913         .clkdm          = { .name = "core_l4_clkdm" },
1914         .recalc         = &followparent_recalc,
1915 };
1916
1917 static struct clk i2c3_ick = {
1918         .name           = "i2c_ick",
1919         .id             = 3,
1920         .parent         = &core_l4_ick,
1921         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1922         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1923         .flags          = CLOCK_IN_OMAP343X,
1924         .clkdm          = { .name = "core_l4_clkdm" },
1925         .recalc         = &followparent_recalc,
1926 };
1927
1928 static struct clk i2c2_ick = {
1929         .name           = "i2c_ick",
1930         .id             = 2,
1931         .parent         = &core_l4_ick,
1932         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1933         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1934         .flags          = CLOCK_IN_OMAP343X,
1935         .clkdm          = { .name = "core_l4_clkdm" },
1936         .recalc         = &followparent_recalc,
1937 };
1938
1939 static struct clk i2c1_ick = {
1940         .name           = "i2c_ick",
1941         .id             = 1,
1942         .parent         = &core_l4_ick,
1943         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1944         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1945         .flags          = CLOCK_IN_OMAP343X,
1946         .clkdm          = { .name = "core_l4_clkdm" },
1947         .recalc         = &followparent_recalc,
1948 };
1949
1950 static struct clk uart2_ick = {
1951         .name           = "uart2_ick",
1952         .parent         = &core_l4_ick,
1953         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1954         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1955         .flags          = CLOCK_IN_OMAP343X,
1956         .clkdm          = { .name = "core_l4_clkdm" },
1957         .recalc         = &followparent_recalc,
1958 };
1959
1960 static struct clk uart1_ick = {
1961         .name           = "uart1_ick",
1962         .parent         = &core_l4_ick,
1963         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1964         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1965         .flags          = CLOCK_IN_OMAP343X,
1966         .clkdm          = { .name = "core_l4_clkdm" },
1967         .recalc         = &followparent_recalc,
1968 };
1969
1970 static struct clk gpt11_ick = {
1971         .name           = "gpt11_ick",
1972         .parent         = &core_l4_ick,
1973         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1974         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1975         .flags          = CLOCK_IN_OMAP343X,
1976         .clkdm          = { .name = "core_l4_clkdm" },
1977         .recalc         = &followparent_recalc,
1978 };
1979
1980 static struct clk gpt10_ick = {
1981         .name           = "gpt10_ick",
1982         .parent         = &core_l4_ick,
1983         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1984         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1985         .flags          = CLOCK_IN_OMAP343X,
1986         .clkdm          = { .name = "core_l4_clkdm" },
1987         .recalc         = &followparent_recalc,
1988 };
1989
1990 static struct clk mcbsp5_ick = {
1991         .name           = "mcbsp_ick",
1992         .id             = 5,
1993         .parent         = &core_l4_ick,
1994         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1995         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1996         .flags          = CLOCK_IN_OMAP343X,
1997         .clkdm          = { .name = "core_l4_clkdm" },
1998         .recalc         = &followparent_recalc,
1999 };
2000
2001 static struct clk mcbsp1_ick = {
2002         .name           = "mcbsp_ick",
2003         .id             = 1,
2004         .parent         = &core_l4_ick,
2005         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2006         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2007         .flags          = CLOCK_IN_OMAP343X,
2008         .clkdm          = { .name = "core_l4_clkdm" },
2009         .recalc         = &followparent_recalc,
2010 };
2011
2012 static struct clk fac_ick = {
2013         .name           = "fac_ick",
2014         .parent         = &core_l4_ick,
2015         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2016         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
2017         .flags          = CLOCK_IN_OMAP3430ES1,
2018         .clkdm          = { .name = "core_l4_clkdm" },
2019         .recalc         = &followparent_recalc,
2020 };
2021
2022 static struct clk mailboxes_ick = {
2023         .name           = "mailboxes_ick",
2024         .parent         = &core_l4_ick,
2025         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2026         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2027         .flags          = CLOCK_IN_OMAP343X,
2028         .clkdm          = { .name = "core_l4_clkdm" },
2029         .recalc         = &followparent_recalc,
2030 };
2031
2032 static struct clk omapctrl_ick = {
2033         .name           = "omapctrl_ick",
2034         .parent         = &core_l4_ick,
2035         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2036         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2037         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
2038         .recalc         = &followparent_recalc,
2039 };
2040
2041 /* SSI_L4_ICK based clocks */
2042
2043 static struct clk ssi_l4_ick = {
2044         .name           = "ssi_l4_ick",
2045         .parent         = &l4_ick,
2046         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2047                                 PARENT_CONTROLS_CLOCK,
2048         .clkdm          = { .name = "core_l4_clkdm" },
2049         .recalc         = &followparent_recalc,
2050 };
2051
2052 static struct clk ssi_ick = {
2053         .name           = "ssi_ick",
2054         .parent         = &ssi_l4_ick,
2055         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2056         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2057         .flags          = CLOCK_IN_OMAP343X,
2058         .clkdm          = { .name = "core_l4_clkdm" },
2059         .recalc         = &followparent_recalc,
2060 };
2061
2062 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2063  * but l4_ick makes more sense to me */
2064
2065 static const struct clksel usb_l4_clksel[] = {
2066         { .parent = &l4_ick, .rates = div2_rates },
2067         { .parent = NULL },
2068 };
2069
2070 static struct clk usb_l4_ick = {
2071         .name           = "usb_l4_ick",
2072         .parent         = &l4_ick,
2073         .init           = &omap2_init_clksel_parent,
2074         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2075         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2076         .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2077         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2078         .clksel         = usb_l4_clksel,
2079         .flags          = CLOCK_IN_OMAP3430ES1,
2080         .recalc         = &omap2_clksel_recalc,
2081 };
2082
2083 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2084
2085 /* SECURITY_L4_ICK2 based clocks */
2086
2087 static struct clk security_l4_ick2 = {
2088         .name           = "security_l4_ick2",
2089         .parent         = &l4_ick,
2090         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2091                                 PARENT_CONTROLS_CLOCK,
2092         .recalc         = &followparent_recalc,
2093 };
2094
2095 static struct clk aes1_ick = {
2096         .name           = "aes1_ick",
2097         .parent         = &security_l4_ick2,
2098         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2099         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2100         .flags          = CLOCK_IN_OMAP343X,
2101         .recalc         = &followparent_recalc,
2102 };
2103
2104 static struct clk rng_ick = {
2105         .name           = "rng_ick",
2106         .parent         = &security_l4_ick2,
2107         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2108         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2109         .flags          = CLOCK_IN_OMAP343X,
2110         .recalc         = &followparent_recalc,
2111 };
2112
2113 static struct clk sha11_ick = {
2114         .name           = "sha11_ick",
2115         .parent         = &security_l4_ick2,
2116         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2117         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2118         .flags          = CLOCK_IN_OMAP343X,
2119         .recalc         = &followparent_recalc,
2120 };
2121
2122 static struct clk des1_ick = {
2123         .name           = "des1_ick",
2124         .parent         = &security_l4_ick2,
2125         .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2126         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2127         .flags          = CLOCK_IN_OMAP343X,
2128         .recalc         = &followparent_recalc,
2129 };
2130
2131 /* DSS */
2132 static const struct clksel dss1_alwon_fck_clksel[] = {
2133         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2134         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2135         { .parent = NULL }
2136 };
2137
2138 static struct clk dss1_alwon_fck = {
2139         .name           = "dss1_alwon_fck",
2140         .parent         = &dpll4_m4x2_ck,
2141         .init           = &omap2_init_clksel_parent,
2142         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2143         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2144         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
2145         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2146         .clksel         = dss1_alwon_fck_clksel,
2147         .flags          = CLOCK_IN_OMAP343X,
2148         .clkdm          = { .name = "dss_clkdm" },
2149         .recalc         = &omap2_clksel_recalc,
2150 };
2151
2152 static struct clk dss_tv_fck = {
2153         .name           = "dss_tv_fck",
2154         .parent         = &omap_54m_fck,
2155         .init           = &omap2_init_clk_clkdm,
2156         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2157         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2158         .flags          = CLOCK_IN_OMAP343X,
2159         .clkdm          = { .name = "dss_clkdm" },
2160         .recalc         = &followparent_recalc,
2161 };
2162
2163 static struct clk dss_96m_fck = {
2164         .name           = "dss_96m_fck",
2165         .parent         = &omap_96m_fck,
2166         .init           = &omap2_init_clk_clkdm,
2167         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2168         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2169         .flags          = CLOCK_IN_OMAP343X,
2170         .clkdm          = { .name = "dss_clkdm" },
2171         .recalc         = &followparent_recalc,
2172 };
2173
2174 static struct clk dss2_alwon_fck = {
2175         .name           = "dss2_alwon_fck",
2176         .parent         = &sys_ck,
2177         .init           = &omap2_init_clk_clkdm,
2178         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2179         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2180         .flags          = CLOCK_IN_OMAP343X,
2181         .clkdm          = { .name = "dss_clkdm" },
2182         .recalc         = &followparent_recalc,
2183 };
2184
2185 static struct clk dss_ick = {
2186         /* Handles both L3 and L4 clocks */
2187         .name           = "dss_ick",
2188         .parent         = &l4_ick,
2189         .init           = &omap2_init_clk_clkdm,
2190         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2191         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2192         .flags          = CLOCK_IN_OMAP343X,
2193         .clkdm          = { .name = "dss_clkdm" },
2194         .recalc         = &followparent_recalc,
2195 };
2196
2197 /* CAM */
2198
2199 static const struct clksel cam_mclk_clksel[] = {
2200         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2201         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2202         { .parent = NULL }
2203 };
2204
2205 static struct clk cam_mclk = {
2206         .name           = "cam_mclk",
2207         .parent         = &dpll4_m5x2_ck,
2208         .init           = &omap2_init_clksel_parent,
2209         .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
2210         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2211         .clksel         = cam_mclk_clksel,
2212         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2213         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2214         .flags          = CLOCK_IN_OMAP343X,
2215         .clkdm          = { .name = "cam_clkdm" },
2216         .recalc         = &omap2_clksel_recalc,
2217 };
2218
2219 static struct clk cam_ick = {
2220         /* Handles both L3 and L4 clocks */
2221         .name           = "cam_ick",
2222         .parent         = &l4_ick,
2223         .init           = &omap2_init_clk_clkdm,
2224         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2225         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2226         .flags          = CLOCK_IN_OMAP343X,
2227         .clkdm          = { .name = "cam_clkdm" },
2228         .recalc         = &followparent_recalc,
2229 };
2230
2231 static struct clk csi2_96m_fck = {
2232         .name           = "csi2_96m_fck",
2233         .parent         = &core_96m_fck,
2234         .init           = &omap2_init_clk_clkdm,
2235         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2236         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2237         .flags          = CLOCK_IN_OMAP343X,
2238         .clkdm          = { .name = "cam_clkdm" },
2239         .recalc         = &followparent_recalc,
2240 };
2241
2242 /* USBHOST - 3430ES2 only */
2243
2244 static struct clk usbhost_120m_fck = {
2245         .name           = "usbhost_120m_fck",
2246         .parent         = &omap_120m_fck,
2247         .init           = &omap2_init_clk_clkdm,
2248         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2249         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2250         .flags          = CLOCK_IN_OMAP3430ES2,
2251         .clkdm          = { .name = "usbhost_clkdm" },
2252         .recalc         = &followparent_recalc,
2253 };
2254
2255 static struct clk usbhost_48m_fck = {
2256         .name           = "usbhost_48m_fck",
2257         .parent         = &omap_48m_fck,
2258         .init           = &omap2_init_clk_clkdm,
2259         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2260         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2261         .flags          = CLOCK_IN_OMAP3430ES2,
2262         .clkdm          = { .name = "usbhost_clkdm" },
2263         .recalc         = &followparent_recalc,
2264 };
2265
2266 static struct clk usbhost_ick = {
2267         /* Handles both L3 and L4 clocks */
2268         .name           = "usbhost_ick",
2269         .parent         = &l4_ick,
2270         .init           = &omap2_init_clk_clkdm,
2271         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2272         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2273         .flags          = CLOCK_IN_OMAP3430ES2,
2274         .clkdm          = { .name = "usbhost_clkdm" },
2275         .recalc         = &followparent_recalc,
2276 };
2277
2278 /* WKUP */
2279
2280 static const struct clksel_rate usim_96m_rates[] = {
2281         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2282         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2283         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2284         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2285         { .div = 0 },
2286 };
2287
2288 static const struct clksel_rate usim_120m_rates[] = {
2289         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2290         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2291         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2292         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2293         { .div = 0 },
2294 };
2295
2296 static const struct clksel usim_clksel[] = {
2297         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2298         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2299         { .parent = &sys_ck,            .rates = div2_rates },
2300         { .parent = NULL },
2301 };
2302
2303 /* 3430ES2 only */
2304 static struct clk usim_fck = {
2305         .name           = "usim_fck",
2306         .init           = &omap2_init_clksel_parent,
2307         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2308         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2309         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2310         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2311         .clksel         = usim_clksel,
2312         .flags          = CLOCK_IN_OMAP3430ES2,
2313         .recalc         = &omap2_clksel_recalc,
2314 };
2315
2316 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2317 static struct clk gpt1_fck = {
2318         .name           = "gpt1_fck",
2319         .init           = &omap2_init_clksel_parent,
2320         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2321         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2322         .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2323         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2324         .clksel         = omap343x_gpt_clksel,
2325         .flags          = CLOCK_IN_OMAP343X,
2326         .clkdm          = { .name = "wkup_clkdm" },
2327         .recalc         = &omap2_clksel_recalc,
2328 };
2329
2330 static struct clk wkup_32k_fck = {
2331         .name           = "wkup_32k_fck",
2332         .init           = &omap2_init_clk_clkdm,
2333         .parent         = &omap_32k_fck,
2334         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2335         .clkdm          = { .name = "wkup_clkdm" },
2336         .recalc         = &followparent_recalc,
2337 };
2338
2339 static struct clk gpio1_fck = {
2340         .name           = "gpio1_fck",
2341         .parent         = &wkup_32k_fck,
2342         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2343         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2344         .flags          = CLOCK_IN_OMAP343X,
2345         .clkdm          = { .name = "wkup_clkdm" },
2346         .recalc         = &followparent_recalc,
2347 };
2348
2349 static struct clk wdt2_fck = {
2350         .name           = "wdt2_fck",
2351         .parent         = &wkup_32k_fck,
2352         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2353         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2354         .flags          = CLOCK_IN_OMAP343X,
2355         .clkdm          = { .name = "wkup_clkdm" },
2356         .recalc         = &followparent_recalc,
2357 };
2358
2359 static struct clk wkup_l4_ick = {
2360         .name           = "wkup_l4_ick",
2361         .parent         = &sys_ck,
2362         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2363         .clkdm          = { .name = "wkup_clkdm" },
2364         .recalc         = &followparent_recalc,
2365 };
2366
2367 /* 3430ES2 only */
2368 /* Never specifically named in the TRM, so we have to infer a likely name */
2369 static struct clk usim_ick = {
2370         .name           = "usim_ick",
2371         .parent         = &wkup_l4_ick,
2372         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2373         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2374         .flags          = CLOCK_IN_OMAP3430ES2,
2375         .clkdm          = { .name = "wkup_clkdm" },
2376         .recalc         = &followparent_recalc,
2377 };
2378
2379 static struct clk wdt2_ick = {
2380         .name           = "wdt2_ick",
2381         .parent         = &wkup_l4_ick,
2382         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2383         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2384         .flags          = CLOCK_IN_OMAP343X,
2385         .clkdm          = { .name = "wkup_clkdm" },
2386         .recalc         = &followparent_recalc,
2387 };
2388
2389 static struct clk wdt1_ick = {
2390         .name           = "wdt1_ick",
2391         .parent         = &wkup_l4_ick,
2392         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2393         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2394         .flags          = CLOCK_IN_OMAP343X,
2395         .clkdm          = { .name = "wkup_clkdm" },
2396         .recalc         = &followparent_recalc,
2397 };
2398
2399 static struct clk gpio1_ick = {
2400         .name           = "gpio1_ick",
2401         .parent         = &wkup_l4_ick,
2402         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2403         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2404         .flags          = CLOCK_IN_OMAP343X,
2405         .clkdm          = { .name = "wkup_clkdm" },
2406         .recalc         = &followparent_recalc,
2407 };
2408
2409 static struct clk omap_32ksync_ick = {
2410         .name           = "omap_32ksync_ick",
2411         .parent         = &wkup_l4_ick,
2412         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2413         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2414         .flags          = CLOCK_IN_OMAP343X,
2415         .clkdm          = { .name = "wkup_clkdm" },
2416         .recalc         = &followparent_recalc,
2417 };
2418
2419 /* XXX This clock no longer exists in 3430 TRM rev F */
2420 static struct clk gpt12_ick = {
2421         .name           = "gpt12_ick",
2422         .parent         = &wkup_l4_ick,
2423         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2424         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2425         .flags          = CLOCK_IN_OMAP343X,
2426         .clkdm          = { .name = "wkup_clkdm" },
2427         .recalc         = &followparent_recalc,
2428 };
2429
2430 static struct clk gpt1_ick = {
2431         .name           = "gpt1_ick",
2432         .parent         = &wkup_l4_ick,
2433         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2434         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2435         .flags          = CLOCK_IN_OMAP343X,
2436         .clkdm          = { .name = "wkup_clkdm" },
2437         .recalc         = &followparent_recalc,
2438 };
2439
2440
2441
2442 /* PER clock domain */
2443
2444 static struct clk per_96m_fck = {
2445         .name           = "per_96m_fck",
2446         .parent         = &omap_96m_alwon_fck,
2447         .init           = &omap2_init_clk_clkdm,
2448         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2449                                 PARENT_CONTROLS_CLOCK,
2450         .clkdm          = { .name = "per_clkdm" },
2451         .recalc         = &followparent_recalc,
2452 };
2453
2454 static struct clk per_48m_fck = {
2455         .name           = "per_48m_fck",
2456         .parent         = &omap_48m_fck,
2457         .init           = &omap2_init_clk_clkdm,
2458         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2459                                 PARENT_CONTROLS_CLOCK,
2460         .clkdm          = { .name = "per_clkdm" },
2461         .recalc         = &followparent_recalc,
2462 };
2463
2464 static struct clk uart3_fck = {
2465         .name           = "uart3_fck",
2466         .parent         = &per_48m_fck,
2467         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2468         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2469         .flags          = CLOCK_IN_OMAP343X,
2470         .clkdm          = { .name = "per_clkdm" },
2471         .recalc         = &followparent_recalc,
2472 };
2473
2474 static struct clk gpt2_fck = {
2475         .name           = "gpt2_fck",
2476         .init           = &omap2_init_clksel_parent,
2477         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2478         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2479         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2480         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2481         .clksel         = omap343x_gpt_clksel,
2482         .flags          = CLOCK_IN_OMAP343X,
2483         .clkdm          = { .name = "per_clkdm" },
2484         .recalc         = &omap2_clksel_recalc,
2485 };
2486
2487 static struct clk gpt3_fck = {
2488         .name           = "gpt3_fck",
2489         .init           = &omap2_init_clksel_parent,
2490         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2491         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2492         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2493         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2494         .clksel         = omap343x_gpt_clksel,
2495         .flags          = CLOCK_IN_OMAP343X,
2496         .clkdm          = { .name = "per_clkdm" },
2497         .recalc         = &omap2_clksel_recalc,
2498 };
2499
2500 static struct clk gpt4_fck = {
2501         .name           = "gpt4_fck",
2502         .init           = &omap2_init_clksel_parent,
2503         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2504         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2505         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2506         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2507         .clksel         = omap343x_gpt_clksel,
2508         .flags          = CLOCK_IN_OMAP343X,
2509         .clkdm          = { .name = "per_clkdm" },
2510         .recalc         = &omap2_clksel_recalc,
2511 };
2512
2513 static struct clk gpt5_fck = {
2514         .name           = "gpt5_fck",
2515         .init           = &omap2_init_clksel_parent,
2516         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2517         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2518         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2519         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2520         .clksel         = omap343x_gpt_clksel,
2521         .flags          = CLOCK_IN_OMAP343X,
2522         .clkdm          = { .name = "per_clkdm" },
2523         .recalc         = &omap2_clksel_recalc,
2524 };
2525
2526 static struct clk gpt6_fck = {
2527         .name           = "gpt6_fck",
2528         .init           = &omap2_init_clksel_parent,
2529         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2530         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2531         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2532         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2533         .clksel         = omap343x_gpt_clksel,
2534         .flags          = CLOCK_IN_OMAP343X,
2535         .clkdm          = { .name = "per_clkdm" },
2536         .recalc         = &omap2_clksel_recalc,
2537 };
2538
2539 static struct clk gpt7_fck = {
2540         .name           = "gpt7_fck",
2541         .init           = &omap2_init_clksel_parent,
2542         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2543         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2544         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2545         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2546         .clksel         = omap343x_gpt_clksel,
2547         .flags          = CLOCK_IN_OMAP343X,
2548         .clkdm          = { .name = "per_clkdm" },
2549         .recalc         = &omap2_clksel_recalc,
2550 };
2551
2552 static struct clk gpt8_fck = {
2553         .name           = "gpt8_fck",
2554         .init           = &omap2_init_clksel_parent,
2555         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2556         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2557         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2558         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2559         .clksel         = omap343x_gpt_clksel,
2560         .flags          = CLOCK_IN_OMAP343X,
2561         .clkdm          = { .name = "per_clkdm" },
2562         .recalc         = &omap2_clksel_recalc,
2563 };
2564
2565 static struct clk gpt9_fck = {
2566         .name           = "gpt9_fck",
2567         .init           = &omap2_init_clksel_parent,
2568         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2569         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2570         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2571         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2572         .clksel         = omap343x_gpt_clksel,
2573         .flags          = CLOCK_IN_OMAP343X,
2574         .clkdm          = { .name = "per_clkdm" },
2575         .recalc         = &omap2_clksel_recalc,
2576 };
2577
2578 static struct clk per_32k_alwon_fck = {
2579         .name           = "per_32k_alwon_fck",
2580         .parent         = &omap_32k_fck,
2581         .clkdm          = { .name = "per_clkdm" },
2582         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2583         .recalc         = &followparent_recalc,
2584 };
2585
2586 static struct clk gpio6_fck = {
2587         .name           = "gpio6_fck",
2588         .parent         = &per_32k_alwon_fck,
2589         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2590         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2591         .flags          = CLOCK_IN_OMAP343X,
2592         .clkdm          = { .name = "per_clkdm" },
2593         .recalc         = &followparent_recalc,
2594 };
2595
2596 static struct clk gpio5_fck = {
2597         .name           = "gpio5_fck",
2598         .parent         = &per_32k_alwon_fck,
2599         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2600         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2601         .flags          = CLOCK_IN_OMAP343X,
2602         .clkdm          = { .name = "per_clkdm" },
2603         .recalc         = &followparent_recalc,
2604 };
2605
2606 static struct clk gpio4_fck = {
2607         .name           = "gpio4_fck",
2608         .parent         = &per_32k_alwon_fck,
2609         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2610         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2611         .flags          = CLOCK_IN_OMAP343X,
2612         .clkdm          = { .name = "per_clkdm" },
2613         .recalc         = &followparent_recalc,
2614 };
2615
2616 static struct clk gpio3_fck = {
2617         .name           = "gpio3_fck",
2618         .parent         = &per_32k_alwon_fck,
2619         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2620         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2621         .flags          = CLOCK_IN_OMAP343X,
2622         .clkdm          = { .name = "per_clkdm" },
2623         .recalc         = &followparent_recalc,
2624 };
2625
2626 static struct clk gpio2_fck = {
2627         .name           = "gpio2_fck",
2628         .parent         = &per_32k_alwon_fck,
2629         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2630         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2631         .flags          = CLOCK_IN_OMAP343X,
2632         .clkdm          = { .name = "per_clkdm" },
2633         .recalc         = &followparent_recalc,
2634 };
2635
2636 static struct clk wdt3_fck = {
2637         .name           = "wdt3_fck",
2638         .parent         = &per_32k_alwon_fck,
2639         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2640         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2641         .flags          = CLOCK_IN_OMAP343X,
2642         .clkdm          = { .name = "per_clkdm" },
2643         .recalc         = &followparent_recalc,
2644 };
2645
2646 static struct clk per_l4_ick = {
2647         .name           = "per_l4_ick",
2648         .parent         = &l4_ick,
2649         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2650                                 PARENT_CONTROLS_CLOCK,
2651         .clkdm          = { .name = "per_clkdm" },
2652         .recalc         = &followparent_recalc,
2653 };
2654
2655 static struct clk gpio6_ick = {
2656         .name           = "gpio6_ick",
2657         .parent         = &per_l4_ick,
2658         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2659         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2660         .flags          = CLOCK_IN_OMAP343X,
2661         .clkdm          = { .name = "per_clkdm" },
2662         .recalc         = &followparent_recalc,
2663 };
2664
2665 static struct clk gpio5_ick = {
2666         .name           = "gpio5_ick",
2667         .parent         = &per_l4_ick,
2668         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2669         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2670         .flags          = CLOCK_IN_OMAP343X,
2671         .clkdm          = { .name = "per_clkdm" },
2672         .recalc         = &followparent_recalc,
2673 };
2674
2675 static struct clk gpio4_ick = {
2676         .name           = "gpio4_ick",
2677         .parent         = &per_l4_ick,
2678         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2679         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2680         .flags          = CLOCK_IN_OMAP343X,
2681         .clkdm          = { .name = "per_clkdm" },
2682         .recalc         = &followparent_recalc,
2683 };
2684
2685 static struct clk gpio3_ick = {
2686         .name           = "gpio3_ick",
2687         .parent         = &per_l4_ick,
2688         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2689         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2690         .flags          = CLOCK_IN_OMAP343X,
2691         .clkdm          = { .name = "per_clkdm" },
2692         .recalc         = &followparent_recalc,
2693 };
2694
2695 static struct clk gpio2_ick = {
2696         .name           = "gpio2_ick",
2697         .parent         = &per_l4_ick,
2698         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2699         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2700         .flags          = CLOCK_IN_OMAP343X,
2701         .clkdm          = { .name = "per_clkdm" },
2702         .recalc         = &followparent_recalc,
2703 };
2704
2705 static struct clk wdt3_ick = {
2706         .name           = "wdt3_ick",
2707         .parent         = &per_l4_ick,
2708         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2709         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2710         .flags          = CLOCK_IN_OMAP343X,
2711         .clkdm          = { .name = "per_clkdm" },
2712         .recalc         = &followparent_recalc,
2713 };
2714
2715 static struct clk uart3_ick = {
2716         .name           = "uart3_ick",
2717         .parent         = &per_l4_ick,
2718         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2719         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2720         .flags          = CLOCK_IN_OMAP343X,
2721         .clkdm          = { .name = "per_clkdm" },
2722         .recalc         = &followparent_recalc,
2723 };
2724
2725 static struct clk gpt9_ick = {
2726         .name           = "gpt9_ick",
2727         .parent         = &per_l4_ick,
2728         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2729         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2730         .flags          = CLOCK_IN_OMAP343X,
2731         .clkdm          = { .name = "per_clkdm" },
2732         .recalc         = &followparent_recalc,
2733 };
2734
2735 static struct clk gpt8_ick = {
2736         .name           = "gpt8_ick",
2737         .parent         = &per_l4_ick,
2738         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2739         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2740         .flags          = CLOCK_IN_OMAP343X,
2741         .clkdm          = { .name = "per_clkdm" },
2742         .recalc         = &followparent_recalc,
2743 };
2744
2745 static struct clk gpt7_ick = {
2746         .name           = "gpt7_ick",
2747         .parent         = &per_l4_ick,
2748         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2749         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2750         .flags          = CLOCK_IN_OMAP343X,
2751         .clkdm          = { .name = "per_clkdm" },
2752         .recalc         = &followparent_recalc,
2753 };
2754
2755 static struct clk gpt6_ick = {
2756         .name           = "gpt6_ick",
2757         .parent         = &per_l4_ick,
2758         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2759         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2760         .flags          = CLOCK_IN_OMAP343X,
2761         .clkdm          = { .name = "per_clkdm" },
2762         .recalc         = &followparent_recalc,
2763 };
2764
2765 static struct clk gpt5_ick = {
2766         .name           = "gpt5_ick",
2767         .parent         = &per_l4_ick,
2768         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2769         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2770         .flags          = CLOCK_IN_OMAP343X,
2771         .clkdm          = { .name = "per_clkdm" },
2772         .recalc         = &followparent_recalc,
2773 };
2774
2775 static struct clk gpt4_ick = {
2776         .name           = "gpt4_ick",
2777         .parent         = &per_l4_ick,
2778         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2779         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2780         .flags          = CLOCK_IN_OMAP343X,
2781         .clkdm          = { .name = "per_clkdm" },
2782         .recalc         = &followparent_recalc,
2783 };
2784
2785 static struct clk gpt3_ick = {
2786         .name           = "gpt3_ick",
2787         .parent         = &per_l4_ick,
2788         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2789         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2790         .flags          = CLOCK_IN_OMAP343X,
2791         .clkdm          = { .name = "per_clkdm" },
2792         .recalc         = &followparent_recalc,
2793 };
2794
2795 static struct clk gpt2_ick = {
2796         .name           = "gpt2_ick",
2797         .parent         = &per_l4_ick,
2798         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2799         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2800         .flags          = CLOCK_IN_OMAP343X,
2801         .clkdm          = { .name = "per_clkdm" },
2802         .recalc         = &followparent_recalc,
2803 };
2804
2805 static struct clk mcbsp2_ick = {
2806         .name           = "mcbsp_ick",
2807         .id             = 2,
2808         .parent         = &per_l4_ick,
2809         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2810         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2811         .flags          = CLOCK_IN_OMAP343X,
2812         .clkdm          = { .name = "per_clkdm" },
2813         .recalc         = &followparent_recalc,
2814 };
2815
2816 static struct clk mcbsp3_ick = {
2817         .name           = "mcbsp_ick",
2818         .id             = 3,
2819         .parent         = &per_l4_ick,
2820         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2821         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2822         .flags          = CLOCK_IN_OMAP343X,
2823         .clkdm          = { .name = "per_clkdm" },
2824         .recalc         = &followparent_recalc,
2825 };
2826
2827 static struct clk mcbsp4_ick = {
2828         .name           = "mcbsp_ick",
2829         .id             = 4,
2830         .parent         = &per_l4_ick,
2831         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2832         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2833         .flags          = CLOCK_IN_OMAP343X,
2834         .clkdm          = { .name = "per_clkdm" },
2835         .recalc         = &followparent_recalc,
2836 };
2837
2838 static const struct clksel mcbsp_234_clksel[] = {
2839         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2840         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2841         { .parent = NULL }
2842 };
2843
2844 static struct clk mcbsp2_fck = {
2845         .name           = "mcbsp_fck",
2846         .id             = 2,
2847         .init           = &omap2_init_clksel_parent,
2848         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2849         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2850         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2851         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2852         .clksel         = mcbsp_234_clksel,
2853         .flags          = CLOCK_IN_OMAP343X,
2854         .clkdm          = { .name = "per_clkdm" },
2855         .recalc         = &omap2_clksel_recalc,
2856 };
2857
2858 static struct clk mcbsp3_fck = {
2859         .name           = "mcbsp_fck",
2860         .id             = 3,
2861         .init           = &omap2_init_clksel_parent,
2862         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2863         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2864         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2865         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2866         .clksel         = mcbsp_234_clksel,
2867         .flags          = CLOCK_IN_OMAP343X,
2868         .clkdm          = { .name = "per_clkdm" },
2869         .recalc         = &omap2_clksel_recalc,
2870 };
2871
2872 static struct clk mcbsp4_fck = {
2873         .name           = "mcbsp_fck",
2874         .id             = 4,
2875         .init           = &omap2_init_clksel_parent,
2876         .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2877         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2878         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2879         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2880         .clksel         = mcbsp_234_clksel,
2881         .flags          = CLOCK_IN_OMAP343X,
2882         .clkdm          = { .name = "per_clkdm" },
2883         .recalc         = &omap2_clksel_recalc,
2884 };
2885
2886 /* EMU clocks */
2887
2888 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2889
2890 static const struct clksel_rate emu_src_sys_rates[] = {
2891         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2892         { .div = 0 },
2893 };
2894
2895 static const struct clksel_rate emu_src_core_rates[] = {
2896         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2897         { .div = 0 },
2898 };
2899
2900 static const struct clksel_rate emu_src_per_rates[] = {
2901         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2902         { .div = 0 },
2903 };
2904
2905 static const struct clksel_rate emu_src_mpu_rates[] = {
2906         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2907         { .div = 0 },
2908 };
2909
2910 static const struct clksel emu_src_clksel[] = {
2911         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2912         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2913         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2914         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2915         { .parent = NULL },
2916 };
2917
2918 /*
2919  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2920  * to switch the source of some of the EMU clocks.
2921  * XXX Are there CLKEN bits for these EMU clks?
2922  */
2923 static struct clk emu_src_ck = {
2924         .name           = "emu_src_ck",
2925         .init           = &omap2_init_clksel_parent,
2926         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2927         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2928         .clksel         = emu_src_clksel,
2929         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2930         .clkdm          = { .name = "emu_clkdm" },
2931         .recalc         = &omap2_clksel_recalc,
2932 };
2933
2934 static const struct clksel_rate pclk_emu_rates[] = {
2935         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2936         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2937         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2938         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2939         { .div = 0 },
2940 };
2941
2942 static const struct clksel pclk_emu_clksel[] = {
2943         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2944         { .parent = NULL },
2945 };
2946
2947 static struct clk pclk_fck = {
2948         .name           = "pclk_fck",
2949         .init           = &omap2_init_clksel_parent,
2950         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2951         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2952         .clksel         = pclk_emu_clksel,
2953         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2954         .clkdm          = { .name = "emu_clkdm" },
2955         .recalc         = &omap2_clksel_recalc,
2956 };
2957
2958 static const struct clksel_rate pclkx2_emu_rates[] = {
2959         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2960         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2961         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2962         { .div = 0 },
2963 };
2964
2965 static const struct clksel pclkx2_emu_clksel[] = {
2966         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2967         { .parent = NULL },
2968 };
2969
2970 static struct clk pclkx2_fck = {
2971         .name           = "pclkx2_fck",
2972         .init           = &omap2_init_clksel_parent,
2973         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2974         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2975         .clksel         = pclkx2_emu_clksel,
2976         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2977         .clkdm          = { .name = "emu_clkdm" },
2978         .recalc         = &omap2_clksel_recalc,
2979 };
2980
2981 static const struct clksel atclk_emu_clksel[] = {
2982         { .parent = &emu_src_ck, .rates = div2_rates },
2983         { .parent = NULL },
2984 };
2985
2986 static struct clk atclk_fck = {
2987         .name           = "atclk_fck",
2988         .init           = &omap2_init_clksel_parent,
2989         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2990         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2991         .clksel         = atclk_emu_clksel,
2992         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2993         .clkdm          = { .name = "emu_clkdm" },
2994         .recalc         = &omap2_clksel_recalc,
2995 };
2996
2997 static struct clk traceclk_src_fck = {
2998         .name           = "traceclk_src_fck",
2999         .init           = &omap2_init_clksel_parent,
3000         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3001         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
3002         .clksel         = emu_src_clksel,
3003         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3004         .clkdm          = { .name = "emu_clkdm" },
3005         .recalc         = &omap2_clksel_recalc,
3006 };
3007
3008 static const struct clksel_rate traceclk_rates[] = {
3009         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3010         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3011         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3012         { .div = 0 },
3013 };
3014
3015 static const struct clksel traceclk_clksel[] = {
3016         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3017         { .parent = NULL },
3018 };
3019
3020 static struct clk traceclk_fck = {
3021         .name           = "traceclk_fck",
3022         .init           = &omap2_init_clksel_parent,
3023         .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3024         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3025         .clksel         = traceclk_clksel,
3026         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3027         .clkdm          = { .name = "emu_clkdm" },
3028         .recalc         = &omap2_clksel_recalc,
3029 };
3030
3031 /* SR clocks */
3032
3033 /* SmartReflex fclk (VDD1) */
3034 static struct clk sr1_fck = {
3035         .name           = "sr1_fck",
3036         .parent         = &sys_ck,
3037         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3038         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3039         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3040         .recalc         = &followparent_recalc,
3041 };
3042
3043 /* SmartReflex fclk (VDD2) */
3044 static struct clk sr2_fck = {
3045         .name           = "sr2_fck",
3046         .parent         = &sys_ck,
3047         .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3048         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3049         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3050         .recalc         = &followparent_recalc,
3051 };
3052
3053 static struct clk sr_l4_ick = {
3054         .name           = "sr_l4_ick",
3055         .parent         = &l4_ick,
3056         .flags          = CLOCK_IN_OMAP343X,
3057         .clkdm          = { .name = "core_l4_clkdm" },
3058         .recalc         = &followparent_recalc,
3059 };
3060
3061 /* SECURE_32K_FCK clocks */
3062
3063 /* XXX This clock no longer exists in 3430 TRM rev F */
3064 static struct clk gpt12_fck = {
3065         .name           = "gpt12_fck",
3066         .parent         = &secure_32k_fck,
3067         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3068         .recalc         = &followparent_recalc,
3069 };
3070
3071 static struct clk wdt1_fck = {
3072         .name           = "wdt1_fck",
3073         .parent         = &secure_32k_fck,
3074         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3075         .recalc         = &followparent_recalc,
3076 };
3077
3078 static struct clk *onchip_34xx_clks[] __initdata = {
3079         &omap_32k_fck,
3080         &virt_12m_ck,
3081         &virt_13m_ck,
3082         &virt_16_8m_ck,
3083         &virt_19_2m_ck,
3084         &virt_26m_ck,
3085         &virt_38_4m_ck,
3086         &osc_sys_ck,
3087         &sys_ck,
3088         &sys_altclk,
3089         &mcbsp_clks,
3090         &sys_clkout1,
3091         &dpll1_ck,
3092         &dpll1_x2_ck,
3093         &dpll1_x2m2_ck,
3094         &dpll2_ck,
3095         &dpll2_m2_ck,
3096         &dpll3_ck,
3097         &core_ck,
3098         &dpll3_x2_ck,
3099         &dpll3_m2_ck,
3100         &dpll3_m2x2_ck,
3101         &dpll3_m3_ck,
3102         &dpll3_m3x2_ck,
3103         &emu_core_alwon_ck,
3104         &dpll4_ck,
3105         &dpll4_x2_ck,
3106         &omap_96m_alwon_fck,
3107         &omap_96m_fck,
3108         &cm_96m_fck,
3109         &virt_omap_54m_fck,
3110         &omap_54m_fck,
3111         &omap_48m_fck,
3112         &omap_12m_fck,
3113         &dpll4_m2_ck,
3114         &dpll4_m2x2_ck,
3115         &dpll4_m3_ck,
3116         &dpll4_m3x2_ck,
3117         &dpll4_m4_ck,
3118         &dpll4_m4x2_ck,
3119         &dpll4_m5_ck,
3120         &dpll4_m5x2_ck,
3121         &dpll4_m6_ck,
3122         &dpll4_m6x2_ck,
3123         &emu_per_alwon_ck,
3124         &dpll5_ck,
3125         &dpll5_m2_ck,
3126         &omap_120m_fck,
3127         &clkout2_src_ck,
3128         &sys_clkout2,
3129         &corex2_fck,
3130         &dpll1_fck,
3131         &mpu_ck,
3132         &arm_fck,
3133         &emu_mpu_alwon_ck,
3134         &dpll2_fck,
3135         &iva2_ck,
3136         &l3_ick,
3137         &l4_ick,
3138         &rm_ick,
3139         &gfx_l3_ck,
3140         &gfx_l3_fck,
3141         &gfx_l3_ick,
3142         &gfx_cg1_ck,
3143         &gfx_cg2_ck,
3144         &sgx_fck,
3145         &sgx_ick,
3146         &d2d_26m_fck,
3147         &gpt10_fck,
3148         &gpt11_fck,
3149         &cpefuse_fck,
3150         &ts_fck,
3151         &usbtll_fck,
3152         &core_96m_fck,
3153         &mmchs3_fck,
3154         &mmchs2_fck,
3155         &mspro_fck,
3156         &mmchs1_fck,
3157         &i2c3_fck,
3158         &i2c2_fck,
3159         &i2c1_fck,
3160         &mcbsp5_fck,
3161         &mcbsp1_fck,
3162         &core_48m_fck,
3163         &mcspi4_fck,
3164         &mcspi3_fck,
3165         &mcspi2_fck,
3166         &mcspi1_fck,
3167         &uart2_fck,
3168         &uart1_fck,
3169         &fshostusb_fck,
3170         &core_12m_fck,
3171         &hdq_fck,
3172         &ssi_ssr_fck,
3173         &ssi_sst_fck,
3174         &core_l3_ick,
3175         &hsotgusb_ick,
3176         &sdrc_ick,
3177         &gpmc_fck,
3178         &security_l3_ick,
3179         &pka_ick,
3180         &core_l4_ick,
3181         &usbtll_ick,
3182         &mmchs3_ick,
3183         &icr_ick,
3184         &aes2_ick,
3185         &sha12_ick,
3186         &des2_ick,
3187         &mmchs2_ick,
3188         &mmchs1_ick,
3189         &mspro_ick,
3190         &hdq_ick,
3191         &mcspi4_ick,
3192         &mcspi3_ick,
3193         &mcspi2_ick,
3194         &mcspi1_ick,
3195         &i2c3_ick,
3196         &i2c2_ick,
3197         &i2c1_ick,
3198         &uart2_ick,
3199         &uart1_ick,
3200         &gpt11_ick,
3201         &gpt10_ick,
3202         &mcbsp5_ick,
3203         &mcbsp1_ick,
3204         &fac_ick,
3205         &mailboxes_ick,
3206         &omapctrl_ick,
3207         &ssi_l4_ick,
3208         &ssi_ick,
3209         &usb_l4_ick,
3210         &security_l4_ick2,
3211         &aes1_ick,
3212         &rng_ick,
3213         &sha11_ick,
3214         &des1_ick,
3215         &dss1_alwon_fck,
3216         &dss_tv_fck,
3217         &dss_96m_fck,
3218         &dss2_alwon_fck,
3219         &dss_ick,
3220         &cam_mclk,
3221         &cam_ick,
3222         &csi2_96m_fck,
3223         &usbhost_120m_fck,
3224         &usbhost_48m_fck,
3225         &usbhost_ick,
3226         &usim_fck,
3227         &gpt1_fck,
3228         &wkup_32k_fck,
3229         &gpio1_fck,
3230         &wdt2_fck,
3231         &wkup_l4_ick,
3232         &usim_ick,
3233         &wdt2_ick,
3234         &wdt1_ick,
3235         &gpio1_ick,
3236         &omap_32ksync_ick,
3237         &gpt12_ick,
3238         &gpt1_ick,
3239         &per_96m_fck,
3240         &per_48m_fck,
3241         &uart3_fck,
3242         &gpt2_fck,
3243         &gpt3_fck,
3244         &gpt4_fck,
3245         &gpt5_fck,
3246         &gpt6_fck,
3247         &gpt7_fck,
3248         &gpt8_fck,
3249         &gpt9_fck,
3250         &per_32k_alwon_fck,
3251         &gpio6_fck,
3252         &gpio5_fck,
3253         &gpio4_fck,
3254         &gpio3_fck,
3255         &gpio2_fck,
3256         &wdt3_fck,
3257         &per_l4_ick,
3258         &gpio6_ick,
3259         &gpio5_ick,
3260         &gpio4_ick,
3261         &gpio3_ick,
3262         &gpio2_ick,
3263         &wdt3_ick,
3264         &uart3_ick,
3265         &gpt9_ick,
3266         &gpt8_ick,
3267         &gpt7_ick,
3268         &gpt6_ick,
3269         &gpt5_ick,
3270         &gpt4_ick,
3271         &gpt3_ick,
3272         &gpt2_ick,
3273         &mcbsp2_ick,
3274         &mcbsp3_ick,
3275         &mcbsp4_ick,
3276         &mcbsp2_fck,
3277         &mcbsp3_fck,
3278         &mcbsp4_fck,
3279         &emu_src_ck,
3280         &pclk_fck,
3281         &pclkx2_fck,
3282         &atclk_fck,
3283         &traceclk_src_fck,
3284         &traceclk_fck,
3285         &sr1_fck,
3286         &sr2_fck,
3287         &sr_l4_ick,
3288         &secure_32k_fck,
3289         &gpt12_fck,
3290         &wdt1_fck,
3291 };
3292
3293 #endif