2 * OMAP3 clock framework
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
22 #include <mach/control.h>
26 #include "cm-regbits-34xx.h"
28 #include "prm-regbits-34xx.h"
30 static void omap3_dpll_recalc(struct clk *clk);
31 static void omap3_clkoutx2_recalc(struct clk *clk);
32 static void omap3_dpll_allow_idle(struct clk *clk);
33 static void omap3_dpll_deny_idle(struct clk *clk);
34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
35 static int omap3_noncore_dpll_enable(struct clk *clk);
36 static void omap3_noncore_dpll_disable(struct clk *clk);
37 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
38 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
40 /* Maximum DPLL multiplier, divider values for OMAP3 */
41 #define OMAP3_MAX_DPLL_MULT 2048
42 #define OMAP3_MAX_DPLL_DIV 128
45 * DPLL1 supplies clock to the MPU.
46 * DPLL2 supplies clock to the IVA2.
47 * DPLL3 supplies CORE domain clocks.
48 * DPLL4 supplies peripheral clocks.
49 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
52 /* Forward declarations for DPLL bypass clocks */
53 static struct clk dpll1_fck;
54 static struct clk dpll2_fck;
56 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
57 #define DPLL_LOW_POWER_STOP 0x1
58 #define DPLL_LOW_POWER_BYPASS 0x5
59 #define DPLL_LOCKED 0x7
63 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
64 static struct clk omap_32k_fck = {
65 .name = "omap_32k_fck",
67 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
69 .clkdm = { .name = "prm_clkdm" },
70 .recalc = &propagate_rate,
73 static struct clk secure_32k_fck = {
74 .name = "secure_32k_fck",
76 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
78 .clkdm = { .name = "prm_clkdm" },
79 .recalc = &propagate_rate,
82 /* Virtual source clocks for osc_sys_ck */
83 static struct clk virt_12m_ck = {
84 .name = "virt_12m_ck",
86 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
88 .clkdm = { .name = "prm_clkdm" },
89 .recalc = &propagate_rate,
92 static struct clk virt_13m_ck = {
93 .name = "virt_13m_ck",
95 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
97 .clkdm = { .name = "prm_clkdm" },
98 .recalc = &propagate_rate,
101 static struct clk virt_16_8m_ck = {
102 .name = "virt_16_8m_ck",
104 .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
106 .clkdm = { .name = "prm_clkdm" },
107 .recalc = &propagate_rate,
110 static struct clk virt_19_2m_ck = {
111 .name = "virt_19_2m_ck",
113 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
115 .clkdm = { .name = "prm_clkdm" },
116 .recalc = &propagate_rate,
119 static struct clk virt_26m_ck = {
120 .name = "virt_26m_ck",
122 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
124 .clkdm = { .name = "prm_clkdm" },
125 .recalc = &propagate_rate,
128 static struct clk virt_38_4m_ck = {
129 .name = "virt_38_4m_ck",
131 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
133 .clkdm = { .name = "prm_clkdm" },
134 .recalc = &propagate_rate,
137 static const struct clksel_rate osc_sys_12m_rates[] = {
138 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
142 static const struct clksel_rate osc_sys_13m_rates[] = {
143 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
147 static const struct clksel_rate osc_sys_16_8m_rates[] = {
148 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
152 static const struct clksel_rate osc_sys_19_2m_rates[] = {
153 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
157 static const struct clksel_rate osc_sys_26m_rates[] = {
158 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
162 static const struct clksel_rate osc_sys_38_4m_rates[] = {
163 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
167 static const struct clksel osc_sys_clksel[] = {
168 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
169 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
170 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
171 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
172 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
173 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
177 /* Oscillator clock */
178 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
179 static struct clk osc_sys_ck = {
180 .name = "osc_sys_ck",
181 .prcm_mod = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
182 .init = &omap2_init_clksel_parent,
183 .clksel_reg = OMAP3_PRM_CLKSEL_OFFSET,
184 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
185 .clksel = osc_sys_clksel,
186 /* REVISIT: deal with autoextclkmode? */
187 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
189 .clkdm = { .name = "prm_clkdm" },
190 .recalc = &omap2_clksel_recalc,
193 static const struct clksel_rate div2_rates[] = {
194 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
195 { .div = 2, .val = 2, .flags = RATE_IN_343X },
199 static const struct clksel sys_clksel[] = {
200 { .parent = &osc_sys_ck, .rates = div2_rates },
204 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
205 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
206 static struct clk sys_ck = {
208 .parent = &osc_sys_ck,
209 .prcm_mod = OMAP3430_GR_MOD | CLK_REG_IN_PRM,
210 .init = &omap2_init_clksel_parent,
211 .clksel_reg = OMAP3_PRM_CLKSRC_CTRL_OFFSET,
212 .clksel_mask = OMAP_SYSCLKDIV_MASK,
213 .clksel = sys_clksel,
214 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
215 .clkdm = { .name = "prm_clkdm" },
216 .recalc = &omap2_clksel_recalc,
219 static struct clk sys_altclk = {
220 .name = "sys_altclk",
221 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
222 .clkdm = { .name = "cm_clkdm" },
223 .recalc = &propagate_rate,
227 * Optional external clock input for some McBSPs
228 * Apparently this is not really in prm_clkdm, but rather is fed into
229 * both CORE and PER separately.
231 static struct clk mcbsp_clks = {
232 .name = "mcbsp_clks",
233 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
234 .clkdm = { .name = "prm_clkdm" },
235 .recalc = &propagate_rate,
238 /* PRM EXTERNAL CLOCK OUTPUT */
240 static struct clk sys_clkout1 = {
241 .name = "sys_clkout1",
242 .parent = &osc_sys_ck,
243 .prcm_mod = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
244 .enable_reg = OMAP3_PRM_CLKOUT_CTRL_OFFSET,
245 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
246 .flags = CLOCK_IN_OMAP343X,
247 .clkdm = { .name = "prm_clkdm" },
248 .recalc = &followparent_recalc,
255 static const struct clksel_rate div16_dpll_rates[] = {
256 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
257 { .div = 2, .val = 2, .flags = RATE_IN_343X },
258 { .div = 3, .val = 3, .flags = RATE_IN_343X },
259 { .div = 4, .val = 4, .flags = RATE_IN_343X },
260 { .div = 5, .val = 5, .flags = RATE_IN_343X },
261 { .div = 6, .val = 6, .flags = RATE_IN_343X },
262 { .div = 7, .val = 7, .flags = RATE_IN_343X },
263 { .div = 8, .val = 8, .flags = RATE_IN_343X },
264 { .div = 9, .val = 9, .flags = RATE_IN_343X },
265 { .div = 10, .val = 10, .flags = RATE_IN_343X },
266 { .div = 11, .val = 11, .flags = RATE_IN_343X },
267 { .div = 12, .val = 12, .flags = RATE_IN_343X },
268 { .div = 13, .val = 13, .flags = RATE_IN_343X },
269 { .div = 14, .val = 14, .flags = RATE_IN_343X },
270 { .div = 15, .val = 15, .flags = RATE_IN_343X },
271 { .div = 16, .val = 16, .flags = RATE_IN_343X },
276 /* MPU clock source */
278 static struct dpll_data dpll1_dd = {
279 .mult_div1_reg = OMAP3430_CM_CLKSEL1_PLL,
280 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
281 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
282 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
283 .control_reg = OMAP3430_CM_CLKEN_PLL,
284 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
285 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
286 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
287 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
288 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
289 .autoidle_reg = OMAP3430_CM_AUTOIDLE_PLL,
290 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
291 .idlest_reg = OMAP3430_CM_IDLEST_PLL,
292 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
293 .bypass_clk = &dpll1_fck,
294 .max_multiplier = OMAP3_MAX_DPLL_MULT,
295 .max_divider = OMAP3_MAX_DPLL_DIV,
296 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
299 static struct clk dpll1_ck = {
303 .dpll_data = &dpll1_dd,
304 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
305 .round_rate = &omap2_dpll_round_rate,
306 .set_rate = &omap3_noncore_dpll_set_rate,
307 .clkdm = { .name = "dpll1_clkdm" },
308 .recalc = &omap3_dpll_recalc,
312 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
313 * DPLL isn't bypassed.
315 static struct clk dpll1_x2_ck = {
316 .name = "dpll1_x2_ck",
318 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
319 PARENT_CONTROLS_CLOCK,
320 .clkdm = { .name = "dpll1_clkdm" },
321 .recalc = &omap3_clkoutx2_recalc,
324 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
325 static const struct clksel div16_dpll1_x2m2_clksel[] = {
326 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
331 * Does not exist in the TRM - needed to separate the M2 divider from
332 * bypass selection in mpu_ck
334 static struct clk dpll1_x2m2_ck = {
335 .name = "dpll1_x2m2_ck",
336 .parent = &dpll1_x2_ck,
338 .init = &omap2_init_clksel_parent,
339 .clksel_reg = OMAP3430_CM_CLKSEL2_PLL,
340 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
341 .clksel = div16_dpll1_x2m2_clksel,
342 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
343 PARENT_CONTROLS_CLOCK,
344 .clkdm = { .name = "dpll1_clkdm" },
345 .recalc = &omap2_clksel_recalc,
349 /* IVA2 clock source */
352 static struct dpll_data dpll2_dd = {
353 .mult_div1_reg = OMAP3430_CM_CLKSEL1_PLL,
354 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
355 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
356 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
357 .control_reg = OMAP3430_CM_CLKEN_PLL,
358 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
359 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
360 (1 << DPLL_LOW_POWER_BYPASS),
361 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
362 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
363 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
364 .autoidle_reg = OMAP3430_CM_AUTOIDLE_PLL,
365 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
366 .idlest_reg = OMAP3430_CM_IDLEST_PLL,
367 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
368 .bypass_clk = &dpll2_fck,
369 .max_multiplier = OMAP3_MAX_DPLL_MULT,
370 .max_divider = OMAP3_MAX_DPLL_DIV,
371 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
374 static struct clk dpll2_ck = {
377 .prcm_mod = OMAP3430_IVA2_MOD,
378 .dpll_data = &dpll2_dd,
379 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
380 .enable = &omap3_noncore_dpll_enable,
381 .disable = &omap3_noncore_dpll_disable,
382 .round_rate = &omap2_dpll_round_rate,
383 .set_rate = &omap3_noncore_dpll_set_rate,
384 .clkdm = { .name = "dpll2_clkdm" },
385 .recalc = &omap3_dpll_recalc,
388 static const struct clksel div16_dpll2_m2x2_clksel[] = {
389 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
394 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
395 * or CLKOUTX2. CLKOUT seems most plausible.
397 static struct clk dpll2_m2_ck = {
398 .name = "dpll2_m2_ck",
400 .prcm_mod = OMAP3430_IVA2_MOD,
401 .init = &omap2_init_clksel_parent,
402 .clksel_reg = OMAP3430_CM_CLKSEL2_PLL,
403 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
404 .clksel = div16_dpll2_m2x2_clksel,
405 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
406 PARENT_CONTROLS_CLOCK,
407 .clkdm = { .name = "dpll2_clkdm" },
408 .recalc = &omap2_clksel_recalc,
413 * Source clock for all interfaces and for some device fclks
414 * REVISIT: Also supports fast relock bypass - not included below
416 static struct dpll_data dpll3_dd = {
417 .mult_div1_reg = CM_CLKSEL1,
418 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
419 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
420 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
421 .control_reg = CM_CLKEN,
422 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
423 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
424 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
425 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
426 .autoidle_reg = CM_AUTOIDLE,
427 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
428 .idlest_reg = CM_IDLEST,
429 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
430 .bypass_clk = &sys_ck,
431 .max_multiplier = OMAP3_MAX_DPLL_MULT,
432 .max_divider = OMAP3_MAX_DPLL_DIV,
433 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
436 static struct clk dpll3_ck = {
440 .dpll_data = &dpll3_dd,
441 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
442 .round_rate = &omap2_dpll_round_rate,
443 .clkdm = { .name = "dpll3_clkdm" },
444 .recalc = &omap3_dpll_recalc,
448 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
449 * DPLL isn't bypassed
451 static struct clk dpll3_x2_ck = {
452 .name = "dpll3_x2_ck",
454 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
455 PARENT_CONTROLS_CLOCK,
456 .clkdm = { .name = "dpll3_clkdm" },
457 .recalc = &omap3_clkoutx2_recalc,
460 static const struct clksel_rate div31_dpll3_rates[] = {
461 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
462 { .div = 2, .val = 2, .flags = RATE_IN_343X },
463 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
464 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
465 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
466 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
467 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
468 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
469 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
470 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
471 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
472 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
473 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
474 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
475 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
476 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
477 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
478 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
479 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
480 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
481 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
482 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
483 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
484 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
485 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
486 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
487 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
488 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
489 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
490 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
491 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
495 static const struct clksel div31_dpll3m2_clksel[] = {
496 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
500 /* DPLL3 output M2 - primary control point for CORE speed */
501 static struct clk dpll3_m2_ck = {
502 .name = "dpll3_m2_ck",
505 .init = &omap2_init_clksel_parent,
506 .clksel_reg = CM_CLKSEL1,
507 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
508 .clksel = div31_dpll3m2_clksel,
509 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
510 PARENT_CONTROLS_CLOCK,
511 .clkdm = { .name = "dpll3_clkdm" },
512 .round_rate = &omap2_clksel_round_rate,
513 .set_rate = &omap3_core_dpll_m2_set_rate,
514 .recalc = &omap2_clksel_recalc,
517 static struct clk core_ck = {
519 .parent = &dpll3_m2_ck,
520 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
521 PARENT_CONTROLS_CLOCK,
522 .clkdm = { .name = "cm_clkdm" },
523 .recalc = &followparent_recalc,
526 static struct clk dpll3_m2x2_ck = {
527 .name = "dpll3_m2x2_ck",
528 .parent = &dpll3_x2_ck,
529 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
530 PARENT_CONTROLS_CLOCK,
531 .clkdm = { .name = "dpll3_clkdm" },
532 .recalc = &followparent_recalc,
535 /* The PWRDN bit is apparently only available on 3430ES2 and above */
536 static const struct clksel div16_dpll3_clksel[] = {
537 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
541 /* This virtual clock is the source for dpll3_m3x2_ck */
542 static struct clk dpll3_m3_ck = {
543 .name = "dpll3_m3_ck",
545 .prcm_mod = OMAP3430_EMU_MOD,
546 .init = &omap2_init_clksel_parent,
547 .clksel_reg = CM_CLKSEL1,
548 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
549 .clksel = div16_dpll3_clksel,
550 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
551 PARENT_CONTROLS_CLOCK,
552 .clkdm = { .name = "dpll3_clkdm" },
553 .recalc = &omap2_clksel_recalc,
556 /* The PWRDN bit is apparently only available on 3430ES2 and above */
557 static struct clk dpll3_m3x2_ck = {
558 .name = "dpll3_m3x2_ck",
559 .parent = &dpll3_m3_ck,
561 .enable_reg = CM_CLKEN,
562 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
563 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
564 .clkdm = { .name = "dpll3_clkdm" },
565 .recalc = &omap3_clkoutx2_recalc,
568 static struct clk emu_core_alwon_ck = {
569 .name = "emu_core_alwon_ck",
570 .parent = &dpll3_m3x2_ck,
571 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
572 PARENT_CONTROLS_CLOCK,
573 .clkdm = { .name = "dpll3_clkdm" },
574 .recalc = &followparent_recalc,
578 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
580 static struct dpll_data dpll4_dd = {
581 .mult_div1_reg = CM_CLKSEL2,
582 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
583 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
584 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
585 .control_reg = CM_CLKEN,
586 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
587 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
588 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
589 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
590 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
591 .autoidle_reg = CM_AUTOIDLE,
592 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
593 .idlest_reg = CM_IDLEST,
594 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
595 .bypass_clk = &sys_ck,
596 .max_multiplier = OMAP3_MAX_DPLL_MULT,
597 .max_divider = OMAP3_MAX_DPLL_DIV,
598 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
601 static struct clk dpll4_ck = {
605 .dpll_data = &dpll4_dd,
606 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
607 .enable = &omap3_noncore_dpll_enable,
608 .disable = &omap3_noncore_dpll_disable,
609 .round_rate = &omap2_dpll_round_rate,
610 .set_rate = &omap3_noncore_dpll_set_rate,
611 .clkdm = { .name = "dpll4_clkdm" },
612 .recalc = &omap3_dpll_recalc,
616 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
617 * DPLL isn't bypassed --
618 * XXX does this serve any downstream clocks?
620 static struct clk dpll4_x2_ck = {
621 .name = "dpll4_x2_ck",
623 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
624 PARENT_CONTROLS_CLOCK,
625 .clkdm = { .name = "dpll4_clkdm" },
626 .recalc = &omap3_clkoutx2_recalc,
629 static const struct clksel div16_dpll4_clksel[] = {
630 { .parent = &dpll4_ck, .rates = div16_dpll_rates },
634 /* This virtual clock is the source for dpll4_m2x2_ck */
635 static struct clk dpll4_m2_ck = {
636 .name = "dpll4_m2_ck",
639 .init = &omap2_init_clksel_parent,
640 .clksel_reg = OMAP3430_CM_CLKSEL3,
641 .clksel_mask = OMAP3430_DIV_96M_MASK,
642 .clksel = div16_dpll4_clksel,
643 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
644 PARENT_CONTROLS_CLOCK,
645 .clkdm = { .name = "dpll4_clkdm" },
646 .recalc = &omap2_clksel_recalc,
649 /* The PWRDN bit is apparently only available on 3430ES2 and above */
650 static struct clk dpll4_m2x2_ck = {
651 .name = "dpll4_m2x2_ck",
652 .parent = &dpll4_m2_ck,
654 .enable_reg = CM_CLKEN,
655 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
656 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
657 .clkdm = { .name = "dpll4_clkdm" },
658 .recalc = &omap3_clkoutx2_recalc,
662 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
663 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
664 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
667 static struct clk omap_96m_alwon_fck = {
668 .name = "omap_96m_alwon_fck",
669 .parent = &dpll4_m2x2_ck,
670 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
671 PARENT_CONTROLS_CLOCK,
672 .clkdm = { .name = "prm_clkdm" },
673 .recalc = &followparent_recalc,
676 static struct clk cm_96m_fck = {
677 .name = "cm_96m_fck",
678 .parent = &omap_96m_alwon_fck,
679 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
680 PARENT_CONTROLS_CLOCK,
681 .clkdm = { .name = "cm_clkdm" },
682 .recalc = &followparent_recalc,
685 static const struct clksel_rate omap_96m_dpll_rates[] = {
686 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
690 static const struct clksel_rate omap_96m_sys_rates[] = {
691 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
695 static const struct clksel omap_96m_fck_clksel[] = {
696 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
697 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
701 static struct clk omap_96m_fck = {
702 .name = "omap_96m_fck",
705 .init = &omap2_init_clksel_parent,
706 .clksel_reg = CM_CLKSEL1,
707 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
708 .clksel = omap_96m_fck_clksel,
709 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
710 PARENT_CONTROLS_CLOCK,
711 .clkdm = { .name = "cm_clkdm" },
712 .recalc = &omap2_clksel_recalc,
715 /* This virtual clock is the source for dpll4_m3x2_ck */
716 static struct clk dpll4_m3_ck = {
717 .name = "dpll4_m3_ck",
719 .prcm_mod = OMAP3430_DSS_MOD,
720 .init = &omap2_init_clksel_parent,
721 .clksel_reg = CM_CLKSEL,
722 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
723 .clksel = div16_dpll4_clksel,
724 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
725 PARENT_CONTROLS_CLOCK,
726 .clkdm = { .name = "dpll4_clkdm" },
727 .recalc = &omap2_clksel_recalc,
730 /* The PWRDN bit is apparently only available on 3430ES2 and above */
731 static struct clk dpll4_m3x2_ck = {
732 .name = "dpll4_m3x2_ck",
733 .parent = &dpll4_m3_ck,
735 .init = &omap2_init_clksel_parent,
736 .enable_reg = CM_CLKEN,
737 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
738 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
739 .clkdm = { .name = "dpll4_clkdm" },
740 .recalc = &omap3_clkoutx2_recalc,
743 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
744 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
748 static const struct clksel_rate omap_54m_alt_rates[] = {
749 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
753 static const struct clksel omap_54m_clksel[] = {
754 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
755 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
759 static struct clk omap_54m_fck = {
760 .name = "omap_54m_fck",
762 .init = &omap2_init_clksel_parent,
763 .clksel_reg = CM_CLKSEL1,
764 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
765 .clksel = omap_54m_clksel,
766 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
767 PARENT_CONTROLS_CLOCK,
768 .clkdm = { .name = "cm_clkdm" },
769 .recalc = &omap2_clksel_recalc,
772 static const struct clksel_rate omap_48m_cm96m_rates[] = {
773 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
777 static const struct clksel_rate omap_48m_alt_rates[] = {
778 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
782 static const struct clksel omap_48m_clksel[] = {
783 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
784 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
788 static struct clk omap_48m_fck = {
789 .name = "omap_48m_fck",
791 .init = &omap2_init_clksel_parent,
792 .clksel_reg = CM_CLKSEL1,
793 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
794 .clksel = omap_48m_clksel,
795 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
796 PARENT_CONTROLS_CLOCK,
797 .clkdm = { .name = "cm_clkdm" },
798 .recalc = &omap2_clksel_recalc,
801 static struct clk omap_12m_fck = {
802 .name = "omap_12m_fck",
803 .parent = &omap_48m_fck,
805 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
806 PARENT_CONTROLS_CLOCK,
807 .clkdm = { .name = "cm_clkdm" },
808 .recalc = &omap2_fixed_divisor_recalc,
811 /* This virstual clock is the source for dpll4_m4x2_ck */
812 static struct clk dpll4_m4_ck = {
813 .name = "dpll4_m4_ck",
815 .prcm_mod = OMAP3430_DSS_MOD,
816 .init = &omap2_init_clksel_parent,
817 .clksel_reg = CM_CLKSEL,
818 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
819 .clksel = div16_dpll4_clksel,
820 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
821 PARENT_CONTROLS_CLOCK,
822 .clkdm = { .name = "dpll4_clkdm" },
823 .recalc = &omap2_clksel_recalc,
826 /* The PWRDN bit is apparently only available on 3430ES2 and above */
827 static struct clk dpll4_m4x2_ck = {
828 .name = "dpll4_m4x2_ck",
829 .parent = &dpll4_m4_ck,
831 .enable_reg = CM_CLKEN,
832 .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
833 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
834 .clkdm = { .name = "dpll4_clkdm" },
835 .recalc = &omap3_clkoutx2_recalc,
838 /* This virtual clock is the source for dpll4_m5x2_ck */
839 static struct clk dpll4_m5_ck = {
840 .name = "dpll4_m5_ck",
842 .prcm_mod = OMAP3430_CAM_MOD,
843 .init = &omap2_init_clksel_parent,
844 .clksel_reg = CM_CLKSEL,
845 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
846 .clksel = div16_dpll4_clksel,
847 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
848 PARENT_CONTROLS_CLOCK,
849 .clkdm = { .name = "dpll4_clkdm" },
850 .recalc = &omap2_clksel_recalc,
853 /* The PWRDN bit is apparently only available on 3430ES2 and above */
854 static struct clk dpll4_m5x2_ck = {
855 .name = "dpll4_m5x2_ck",
856 .parent = &dpll4_m5_ck,
858 .enable_reg = CM_CLKEN,
859 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
860 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
861 .clkdm = { .name = "dpll4_clkdm" },
862 .recalc = &omap3_clkoutx2_recalc,
865 /* This virtual clock is the source for dpll4_m6x2_ck */
866 static struct clk dpll4_m6_ck = {
867 .name = "dpll4_m6_ck",
869 .prcm_mod = OMAP3430_EMU_MOD,
870 .init = &omap2_init_clksel_parent,
871 .clksel_reg = CM_CLKSEL1,
872 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
873 .clksel = div16_dpll4_clksel,
874 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
875 PARENT_CONTROLS_CLOCK,
876 .clkdm = { .name = "dpll4_clkdm" },
877 .recalc = &omap2_clksel_recalc,
880 /* The PWRDN bit is apparently only available on 3430ES2 and above */
881 static struct clk dpll4_m6x2_ck = {
882 .name = "dpll4_m6x2_ck",
883 .parent = &dpll4_m6_ck,
885 .init = &omap2_init_clksel_parent,
886 .enable_reg = CM_CLKEN,
887 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
888 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
889 .clkdm = { .name = "dpll4_clkdm" },
890 .recalc = &omap3_clkoutx2_recalc,
893 static struct clk emu_per_alwon_ck = {
894 .name = "emu_per_alwon_ck",
895 .parent = &dpll4_m6x2_ck,
896 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
897 PARENT_CONTROLS_CLOCK,
898 .clkdm = { .name = "dpll4_clkdm" },
899 .recalc = &followparent_recalc,
903 /* Supplies 120MHz clock, USIM source clock */
906 static struct dpll_data dpll5_dd = {
907 .mult_div1_reg = OMAP3430ES2_CM_CLKSEL4,
908 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
909 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
910 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
911 .control_reg = OMAP3430ES2_CM_CLKEN2,
912 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
913 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
914 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
915 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
916 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
917 .autoidle_reg = OMAP3430ES2_CM_AUTOIDLE2_PLL,
918 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
919 .idlest_reg = CM_IDLEST2,
920 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
921 .bypass_clk = &sys_ck,
922 .max_multiplier = OMAP3_MAX_DPLL_MULT,
923 .max_divider = OMAP3_MAX_DPLL_DIV,
924 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
927 static struct clk dpll5_ck = {
931 .dpll_data = &dpll5_dd,
932 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
933 .enable = &omap3_noncore_dpll_enable,
934 .disable = &omap3_noncore_dpll_disable,
935 .round_rate = &omap2_dpll_round_rate,
936 .set_rate = &omap3_noncore_dpll_set_rate,
937 .clkdm = { .name = "dpll5_clkdm" },
938 .recalc = &omap3_dpll_recalc,
941 static const struct clksel div16_dpll5_clksel[] = {
942 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
946 static struct clk dpll5_m2_ck = {
947 .name = "dpll5_m2_ck",
950 .init = &omap2_init_clksel_parent,
951 .clksel_reg = OMAP3430ES2_CM_CLKSEL5,
952 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
953 .clksel = div16_dpll5_clksel,
954 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
955 PARENT_CONTROLS_CLOCK,
956 .clkdm = { .name = "dpll5_clkdm" },
957 .recalc = &omap2_clksel_recalc,
960 /* CM EXTERNAL CLOCK OUTPUTS */
962 static const struct clksel_rate clkout2_src_core_rates[] = {
963 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
967 static const struct clksel_rate clkout2_src_sys_rates[] = {
968 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
972 static const struct clksel_rate clkout2_src_96m_rates[] = {
973 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
977 static const struct clksel_rate clkout2_src_54m_rates[] = {
978 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
982 static const struct clksel clkout2_src_clksel[] = {
983 { .parent = &core_ck, .rates = clkout2_src_core_rates },
984 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
985 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
986 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
990 static struct clk clkout2_src_ck = {
991 .name = "clkout2_src_ck",
992 .prcm_mod = OMAP3430_CCR_MOD,
993 .init = &omap2_init_clksel_parent,
994 .enable_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
995 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
996 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
997 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
998 .clksel = clkout2_src_clksel,
999 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1000 .clkdm = { .name = "cm_clkdm" },
1001 .recalc = &omap2_clksel_recalc,
1004 static const struct clksel_rate sys_clkout2_rates[] = {
1005 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1006 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1007 { .div = 4, .val = 2, .flags = RATE_IN_343X },
1008 { .div = 8, .val = 3, .flags = RATE_IN_343X },
1009 { .div = 16, .val = 4, .flags = RATE_IN_343X },
1013 static const struct clksel sys_clkout2_clksel[] = {
1014 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1018 static struct clk sys_clkout2 = {
1019 .name = "sys_clkout2",
1020 .prcm_mod = OMAP3430_CCR_MOD,
1021 .init = &omap2_init_clksel_parent,
1022 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
1023 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
1024 .clksel = sys_clkout2_clksel,
1025 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1026 .clkdm = { .name = "cm_clkdm" },
1027 .recalc = &omap2_clksel_recalc,
1030 /* CM OUTPUT CLOCKS */
1032 static struct clk corex2_fck = {
1033 .name = "corex2_fck",
1034 .parent = &dpll3_m2x2_ck,
1035 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1036 PARENT_CONTROLS_CLOCK,
1037 .clkdm = { .name = "cm_clkdm" },
1038 .recalc = &followparent_recalc,
1041 /* DPLL power domain clock controls */
1043 static const struct clksel_rate div4_rates[] = {
1044 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1045 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1046 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1050 static const struct clksel div4_core_clksel[] = {
1051 { .parent = &core_ck, .rates = div4_rates },
1055 static struct clk dpll1_fck = {
1056 .name = "dpll1_fck",
1058 .prcm_mod = MPU_MOD,
1059 .init = &omap2_init_clksel_parent,
1060 .clksel_reg = OMAP3430_CM_CLKSEL1_PLL,
1061 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1062 .clksel = div4_core_clksel,
1063 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1064 PARENT_CONTROLS_CLOCK,
1065 .clkdm = { .name = "cm_clkdm" },
1066 .recalc = &omap2_clksel_recalc,
1069 static struct clk mpu_ck = {
1071 .parent = &dpll1_x2m2_ck,
1072 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1073 PARENT_CONTROLS_CLOCK,
1074 .clkdm = { .name = "mpu_clkdm" },
1075 .recalc = &followparent_recalc,
1078 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1079 static const struct clksel_rate arm_fck_rates[] = {
1080 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1081 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1085 static const struct clksel arm_fck_clksel[] = {
1086 { .parent = &mpu_ck, .rates = arm_fck_rates },
1090 static struct clk arm_fck = {
1093 .prcm_mod = MPU_MOD,
1094 .init = &omap2_init_clksel_parent,
1095 .clksel_reg = OMAP3430_CM_IDLEST_PLL,
1096 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1097 .clksel = arm_fck_clksel,
1098 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1099 PARENT_CONTROLS_CLOCK,
1100 .clkdm = { .name = "mpu_clkdm" },
1101 .recalc = &omap2_clksel_recalc,
1104 /* XXX What about neon_clkdm ? */
1107 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1108 * although it is referenced - so this is a guess
1110 static struct clk emu_mpu_alwon_ck = {
1111 .name = "emu_mpu_alwon_ck",
1113 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1114 PARENT_CONTROLS_CLOCK,
1115 .clkdm = { .name = "mpu_clkdm" },
1116 .recalc = &followparent_recalc,
1119 static struct clk dpll2_fck = {
1120 .name = "dpll2_fck",
1122 .prcm_mod = OMAP3430_IVA2_MOD,
1123 .init = &omap2_init_clksel_parent,
1124 .clksel_reg = OMAP3430_CM_CLKSEL1_PLL,
1125 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1126 .clksel = div4_core_clksel,
1127 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1128 PARENT_CONTROLS_CLOCK,
1129 .clkdm = { .name = "cm_clkdm" },
1130 .recalc = &omap2_clksel_recalc,
1133 static struct clk iva2_ck = {
1135 .parent = &dpll2_m2_ck,
1136 .prcm_mod = OMAP3430_IVA2_MOD,
1137 .init = &omap2_init_clksel_parent,
1138 .enable_reg = CM_FCLKEN,
1139 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1140 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1141 .clkdm = { .name = "iva2_clkdm" },
1142 .recalc = &followparent_recalc,
1145 /* Common interface clocks */
1147 static const struct clksel div2_core_clksel[] = {
1148 { .parent = &core_ck, .rates = div2_rates },
1152 static struct clk l3_ick = {
1155 .prcm_mod = CORE_MOD,
1156 .init = &omap2_init_clksel_parent,
1157 .clksel_reg = CM_CLKSEL,
1158 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1159 .clksel = div2_core_clksel,
1160 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1161 PARENT_CONTROLS_CLOCK,
1162 .clkdm = { .name = "core_l3_clkdm" },
1163 .recalc = &omap2_clksel_recalc,
1166 static const struct clksel div2_l3_clksel[] = {
1167 { .parent = &l3_ick, .rates = div2_rates },
1171 static struct clk l4_ick = {
1174 .prcm_mod = CORE_MOD,
1175 .init = &omap2_init_clksel_parent,
1176 .clksel_reg = CM_CLKSEL,
1177 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1178 .clksel = div2_l3_clksel,
1179 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1180 PARENT_CONTROLS_CLOCK,
1181 .clkdm = { .name = "core_l4_clkdm" },
1182 .recalc = &omap2_clksel_recalc,
1186 static const struct clksel div2_l4_clksel[] = {
1187 { .parent = &l4_ick, .rates = div2_rates },
1191 static struct clk rm_ick = {
1194 .prcm_mod = WKUP_MOD,
1195 .init = &omap2_init_clksel_parent,
1196 .clksel_reg = CM_CLKSEL,
1197 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1198 .clksel = div2_l4_clksel,
1199 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1200 .clkdm = { .name = "cm_clkdm" },
1201 .recalc = &omap2_clksel_recalc,
1204 /* GFX power domain */
1206 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1208 static const struct clksel gfx_l3_clksel[] = {
1209 { .parent = &l3_ick, .rates = gfx_l3_rates },
1213 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1214 static struct clk gfx_l3_ck = {
1215 .name = "gfx_l3_ck",
1217 .prcm_mod = GFX_MOD,
1218 .init = &omap2_init_clksel_parent,
1219 .enable_reg = CM_ICLKEN,
1220 .enable_bit = OMAP_EN_GFX_SHIFT,
1221 .flags = CLOCK_IN_OMAP3430ES1,
1222 .clkdm = { .name = "gfx_3430es1_clkdm" },
1223 .recalc = &followparent_recalc,
1226 static struct clk gfx_l3_fck = {
1227 .name = "gfx_l3_fck",
1228 .parent = &gfx_l3_ck,
1229 .prcm_mod = GFX_MOD,
1230 .init = &omap2_init_clksel_parent,
1231 .clksel_reg = CM_CLKSEL,
1232 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1233 .clksel = gfx_l3_clksel,
1234 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1235 PARENT_CONTROLS_CLOCK,
1236 .clkdm = { .name = "gfx_3430es1_clkdm" },
1237 .recalc = &omap2_clksel_recalc,
1240 static struct clk gfx_l3_ick = {
1241 .name = "gfx_l3_ick",
1242 .parent = &gfx_l3_ck,
1243 .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1244 .clkdm = { .name = "gfx_3430es1_clkdm" },
1245 .recalc = &followparent_recalc,
1248 static struct clk gfx_cg1_ck = {
1249 .name = "gfx_cg1_ck",
1250 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1251 .prcm_mod = GFX_MOD,
1252 .enable_reg = CM_FCLKEN,
1253 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1254 .flags = CLOCK_IN_OMAP3430ES1,
1255 .clkdm = { .name = "gfx_3430es1_clkdm" },
1256 .recalc = &followparent_recalc,
1259 static struct clk gfx_cg2_ck = {
1260 .name = "gfx_cg2_ck",
1261 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1262 .prcm_mod = GFX_MOD,
1263 .enable_reg = CM_FCLKEN,
1264 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1265 .flags = CLOCK_IN_OMAP3430ES1,
1266 .clkdm = { .name = "gfx_3430es1_clkdm" },
1267 .recalc = &followparent_recalc,
1270 /* SGX power domain - 3430ES2 only */
1272 static const struct clksel_rate sgx_core_rates[] = {
1273 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1274 { .div = 4, .val = 1, .flags = RATE_IN_343X },
1275 { .div = 6, .val = 2, .flags = RATE_IN_343X },
1279 static const struct clksel_rate sgx_96m_rates[] = {
1280 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1284 static const struct clksel sgx_clksel[] = {
1285 { .parent = &core_ck, .rates = sgx_core_rates },
1286 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1290 static struct clk sgx_fck = {
1292 .init = &omap2_init_clksel_parent,
1293 .prcm_mod = OMAP3430ES2_SGX_MOD,
1294 .enable_reg = CM_FCLKEN,
1295 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1296 .clksel_reg = CM_CLKSEL,
1297 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1298 .clksel = sgx_clksel,
1299 .flags = CLOCK_IN_OMAP3430ES2,
1300 .clkdm = { .name = "sgx_clkdm" },
1301 .recalc = &omap2_clksel_recalc,
1304 static struct clk sgx_ick = {
1307 .prcm_mod = OMAP3430ES2_SGX_MOD,
1308 .enable_reg = CM_ICLKEN,
1309 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1310 .flags = CLOCK_IN_OMAP3430ES2,
1311 .clkdm = { .name = "sgx_clkdm" },
1312 .recalc = &followparent_recalc,
1315 /* CORE power domain */
1317 static struct clk d2d_26m_fck = {
1318 .name = "d2d_26m_fck",
1320 .prcm_mod = CORE_MOD,
1321 .enable_reg = CM_FCLKEN1,
1322 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1323 .flags = CLOCK_IN_OMAP3430ES1,
1324 .clkdm = { .name = "d2d_clkdm" },
1325 .recalc = &followparent_recalc,
1328 static const struct clksel omap343x_gpt_clksel[] = {
1329 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1330 { .parent = &sys_ck, .rates = gpt_sys_rates },
1334 static struct clk gpt10_fck = {
1335 .name = "gpt10_fck",
1337 .prcm_mod = CORE_MOD,
1338 .init = &omap2_init_clksel_parent,
1339 .enable_reg = CM_FCLKEN1,
1340 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1341 .idlest_bit = OMAP3430_ST_GPT10_SHIFT,
1342 .clksel_reg = CM_CLKSEL,
1343 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1344 .clksel = omap343x_gpt_clksel,
1345 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1346 .clkdm = { .name = "core_l4_clkdm" },
1347 .recalc = &omap2_clksel_recalc,
1350 static struct clk gpt11_fck = {
1351 .name = "gpt11_fck",
1353 .prcm_mod = CORE_MOD,
1354 .init = &omap2_init_clksel_parent,
1355 .enable_reg = CM_FCLKEN1,
1356 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1357 .idlest_bit = OMAP3430_ST_GPT11_SHIFT,
1358 .clksel_reg = CM_CLKSEL,
1359 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1360 .clksel = omap343x_gpt_clksel,
1361 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1362 .clkdm = { .name = "core_l4_clkdm" },
1363 .recalc = &omap2_clksel_recalc,
1366 static struct clk cpefuse_fck = {
1367 .name = "cpefuse_fck",
1369 .prcm_mod = CORE_MOD,
1370 .enable_reg = OMAP3430ES2_CM_FCLKEN3,
1371 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1372 .idlest_bit = OMAP3430ES2_ST_CPEFUSE_SHIFT,
1373 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1374 .clkdm = { .name = "cm_clkdm" },
1375 .recalc = &followparent_recalc,
1378 static struct clk ts_fck = {
1380 .parent = &omap_32k_fck,
1381 .prcm_mod = CORE_MOD,
1382 .enable_reg = OMAP3430ES2_CM_FCLKEN3,
1383 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1384 .flags = CLOCK_IN_OMAP3430ES2,
1385 .clkdm = { .name = "core_l4_clkdm" },
1386 .recalc = &followparent_recalc,
1389 static struct clk usbtll_fck = {
1390 .name = "usbtll_fck",
1391 .parent = &dpll5_m2_ck,
1392 .prcm_mod = CORE_MOD,
1393 .enable_reg = OMAP3430ES2_CM_FCLKEN3,
1394 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1395 .idlest_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1396 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1397 .clkdm = { .name = "core_l4_clkdm" },
1398 .recalc = &followparent_recalc,
1401 /* CORE 96M FCLK-derived clocks */
1403 static struct clk core_96m_fck = {
1404 .name = "core_96m_fck",
1405 .parent = &omap_96m_fck,
1406 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1407 PARENT_CONTROLS_CLOCK,
1408 .clkdm = { .name = "core_l4_clkdm" },
1409 .recalc = &followparent_recalc,
1412 static struct clk mmchs3_fck = {
1413 .name = "mmchs_fck",
1415 .parent = &core_96m_fck,
1416 .prcm_mod = CORE_MOD,
1417 .enable_reg = CM_FCLKEN1,
1418 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1419 .idlest_bit = OMAP3430ES2_ST_MMC3_SHIFT,
1420 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1421 .clkdm = { .name = "core_l4_clkdm" },
1422 .recalc = &followparent_recalc,
1425 static struct clk mmchs2_fck = {
1426 .name = "mmchs_fck",
1428 .parent = &core_96m_fck,
1429 .prcm_mod = CORE_MOD,
1430 .enable_reg = CM_FCLKEN1,
1431 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1432 .idlest_bit = OMAP3430_ST_MMC2_SHIFT,
1433 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1434 .clkdm = { .name = "core_l4_clkdm" },
1435 .recalc = &followparent_recalc,
1438 static struct clk mspro_fck = {
1439 .name = "mspro_fck",
1440 .parent = &core_96m_fck,
1441 .prcm_mod = CORE_MOD,
1442 .enable_reg = CM_FCLKEN1,
1443 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1444 .idlest_bit = OMAP3430_ST_MSPRO_SHIFT,
1445 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1446 .clkdm = { .name = "core_l4_clkdm" },
1447 .recalc = &followparent_recalc,
1450 static struct clk mmchs1_fck = {
1451 .name = "mmchs_fck",
1453 .parent = &core_96m_fck,
1454 .prcm_mod = CORE_MOD,
1455 .enable_reg = CM_FCLKEN1,
1456 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1457 .idlest_bit = OMAP3430_ST_MMC1_SHIFT,
1458 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1459 .clkdm = { .name = "core_l4_clkdm" },
1460 .recalc = &followparent_recalc,
1463 static struct clk i2c3_fck = {
1466 .parent = &core_96m_fck,
1467 .prcm_mod = CORE_MOD,
1468 .enable_reg = CM_FCLKEN1,
1469 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1470 .idlest_bit = OMAP3430_ST_I2C3_SHIFT,
1471 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1472 .clkdm = { .name = "core_l4_clkdm" },
1473 .recalc = &followparent_recalc,
1476 static struct clk i2c2_fck = {
1479 .parent = &core_96m_fck,
1480 .prcm_mod = CORE_MOD,
1481 .enable_reg = CM_FCLKEN1,
1482 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1483 .idlest_bit = OMAP3430_ST_I2C2_SHIFT,
1484 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1485 .clkdm = { .name = "core_l4_clkdm" },
1486 .recalc = &followparent_recalc,
1489 static struct clk i2c1_fck = {
1492 .parent = &core_96m_fck,
1493 .prcm_mod = CORE_MOD,
1494 .enable_reg = CM_FCLKEN1,
1495 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1496 .idlest_bit = OMAP3430_ST_I2C1_SHIFT,
1497 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1498 .clkdm = { .name = "core_l4_clkdm" },
1499 .recalc = &followparent_recalc,
1503 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1504 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1506 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1507 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1511 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1512 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1516 static const struct clksel mcbsp_15_clksel[] = {
1517 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1518 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1522 static struct clk mcbsp5_src_fck = {
1523 .name = "mcbsp_src_fck",
1525 .prcm_mod = CLK_REG_IN_SCM,
1526 .init = &omap2_init_clksel_parent,
1527 .clksel_reg = OMAP343X_CONTROL_DEVCONF1,
1528 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1529 .clksel = mcbsp_15_clksel,
1530 .flags = CLOCK_IN_OMAP343X,
1531 .clkdm = { .name = "core_l4_clkdm" },
1532 .recalc = &omap2_clksel_recalc,
1535 static struct clk mcbsp5_fck = {
1536 .name = "mcbsp_fck",
1538 .parent = &mcbsp5_src_fck,
1539 .prcm_mod = CORE_MOD,
1540 .enable_reg = CM_FCLKEN1,
1541 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1542 .idlest_bit = OMAP3430_ST_MCBSP5_SHIFT,
1543 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1544 .clkdm = { .name = "core_l4_clkdm" },
1545 .recalc = &followparent_recalc,
1548 static struct clk mcbsp1_src_fck = {
1549 .name = "mcbsp_src_fck",
1551 .prcm_mod = CLK_REG_IN_SCM,
1552 .init = &omap2_init_clksel_parent,
1553 .clksel_reg = OMAP2_CONTROL_DEVCONF0,
1554 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1555 .clksel = mcbsp_15_clksel,
1556 .flags = CLOCK_IN_OMAP343X,
1557 .clkdm = { .name = "core_l4_clkdm" },
1558 .recalc = &omap2_clksel_recalc,
1561 static struct clk mcbsp1_fck = {
1562 .name = "mcbsp_fck",
1564 .parent = &mcbsp1_src_fck,
1565 .prcm_mod = CORE_MOD,
1566 .enable_reg = CM_FCLKEN1,
1567 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1568 .idlest_bit = OMAP3430_ST_MCBSP1_SHIFT,
1569 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1570 .clkdm = { .name = "core_l4_clkdm" },
1571 .recalc = &followparent_recalc,
1574 /* CORE_48M_FCK-derived clocks */
1576 static struct clk core_48m_fck = {
1577 .name = "core_48m_fck",
1578 .parent = &omap_48m_fck,
1579 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1580 PARENT_CONTROLS_CLOCK,
1581 .clkdm = { .name = "core_l4_clkdm" },
1582 .recalc = &followparent_recalc,
1585 static struct clk mcspi4_fck = {
1586 .name = "mcspi_fck",
1588 .parent = &core_48m_fck,
1589 .prcm_mod = CORE_MOD,
1590 .enable_reg = CM_FCLKEN1,
1591 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1592 .idlest_bit = OMAP3430_ST_MCSPI4_SHIFT,
1593 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1594 .clkdm = { .name = "core_l4_clkdm" },
1595 .recalc = &followparent_recalc,
1598 static struct clk mcspi3_fck = {
1599 .name = "mcspi_fck",
1601 .parent = &core_48m_fck,
1602 .prcm_mod = CORE_MOD,
1603 .enable_reg = CM_FCLKEN1,
1604 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1605 .idlest_bit = OMAP3430_ST_MCSPI3_SHIFT,
1606 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1607 .clkdm = { .name = "core_l4_clkdm" },
1608 .recalc = &followparent_recalc,
1611 static struct clk mcspi2_fck = {
1612 .name = "mcspi_fck",
1614 .parent = &core_48m_fck,
1615 .prcm_mod = CORE_MOD,
1616 .enable_reg = CM_FCLKEN1,
1617 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1618 .idlest_bit = OMAP3430_ST_MCSPI2_SHIFT,
1619 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1620 .clkdm = { .name = "core_l4_clkdm" },
1621 .recalc = &followparent_recalc,
1624 static struct clk mcspi1_fck = {
1625 .name = "mcspi_fck",
1627 .parent = &core_48m_fck,
1628 .prcm_mod = CORE_MOD,
1629 .enable_reg = CM_FCLKEN1,
1630 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1631 .idlest_bit = OMAP3430_ST_MCSPI1_SHIFT,
1632 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1633 .clkdm = { .name = "core_l4_clkdm" },
1634 .recalc = &followparent_recalc,
1637 static struct clk uart2_fck = {
1638 .name = "uart2_fck",
1639 .parent = &core_48m_fck,
1640 .prcm_mod = CORE_MOD,
1641 .enable_reg = CM_FCLKEN1,
1642 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1643 .idlest_bit = OMAP3430_ST_UART2_SHIFT,
1644 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1645 .clkdm = { .name = "core_l4_clkdm" },
1646 .recalc = &followparent_recalc,
1649 static struct clk uart1_fck = {
1650 .name = "uart1_fck",
1651 .parent = &core_48m_fck,
1652 .prcm_mod = CORE_MOD,
1653 .enable_reg = CM_FCLKEN1,
1654 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1655 .idlest_bit = OMAP3430_ST_UART1_SHIFT,
1656 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1657 .clkdm = { .name = "core_l4_clkdm" },
1658 .recalc = &followparent_recalc,
1661 /* XXX doublecheck: is this idle or standby? */
1662 static struct clk fshostusb_fck = {
1663 .name = "fshostusb_fck",
1664 .parent = &core_48m_fck,
1665 .prcm_mod = CORE_MOD,
1666 .enable_reg = CM_FCLKEN1,
1667 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1668 .idlest_bit = OMAP3430ES1_ST_FSHOSTUSB_SHIFT,
1669 .flags = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
1670 .clkdm = { .name = "core_l4_clkdm" },
1671 .recalc = &followparent_recalc,
1674 /* CORE_12M_FCK based clocks */
1676 static struct clk core_12m_fck = {
1677 .name = "core_12m_fck",
1678 .parent = &omap_12m_fck,
1679 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1680 PARENT_CONTROLS_CLOCK,
1681 .clkdm = { .name = "core_l4_clkdm" },
1682 .recalc = &followparent_recalc,
1685 static struct clk hdq_fck = {
1687 .parent = &core_12m_fck,
1688 .prcm_mod = CORE_MOD,
1689 .enable_reg = CM_FCLKEN1,
1690 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1691 .idlest_bit = OMAP3430_ST_HDQ_SHIFT,
1692 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1693 .clkdm = { .name = "core_l4_clkdm" },
1694 .recalc = &followparent_recalc,
1697 /* DPLL3-derived clock */
1699 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1700 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1701 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1702 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1703 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1704 { .div = 6, .val = 6, .flags = RATE_IN_343X },
1705 { .div = 8, .val = 8, .flags = RATE_IN_343X },
1709 static const struct clksel ssi_ssr_clksel[] = {
1710 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1714 static struct clk ssi_ssr_fck_3430es1 = {
1715 .name = "ssi_ssr_fck",
1716 .init = &omap2_init_clksel_parent,
1717 .prcm_mod = CORE_MOD,
1718 .enable_reg = CM_FCLKEN1,
1719 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1720 .clksel_reg = CM_CLKSEL,
1721 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1722 .clksel = ssi_ssr_clksel,
1723 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
1724 .clkdm = { .name = "core_l4_clkdm" },
1725 .recalc = &omap2_clksel_recalc,
1728 static struct clk ssi_ssr_fck_3430es2 = {
1729 .name = "ssi_ssr_fck",
1730 .init = &omap2_init_clksel_parent,
1731 .prcm_mod = CORE_MOD,
1732 .enable_reg = CM_FCLKEN1,
1733 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1734 .idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
1735 .clksel_reg = CM_CLKSEL,
1736 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1737 .clksel = ssi_ssr_clksel,
1738 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | WAIT_READY,
1739 .clkdm = { .name = "core_l4_clkdm" },
1740 .recalc = &omap2_clksel_recalc,
1743 /* It's unfortunate that we need to duplicate this clock. */
1744 static struct clk ssi_sst_fck_3430es1 = {
1745 .name = "ssi_sst_fck",
1746 .parent = &ssi_ssr_fck_3430es1,
1748 .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1749 .clkdm = { .name = "core_l4_clkdm" },
1750 .recalc = &omap2_fixed_divisor_recalc,
1753 static struct clk ssi_sst_fck_3430es2 = {
1754 .name = "ssi_sst_fck",
1755 .parent = &ssi_ssr_fck_3430es2,
1757 .flags = CLOCK_IN_OMAP3430ES2 | PARENT_CONTROLS_CLOCK,
1758 .clkdm = { .name = "core_l4_clkdm" },
1759 .recalc = &omap2_fixed_divisor_recalc,
1764 /* CORE_L3_ICK based clocks */
1767 * XXX must add clk_enable/clk_disable for these if standard code won't
1770 static struct clk core_l3_ick = {
1771 .name = "core_l3_ick",
1773 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1774 PARENT_CONTROLS_CLOCK,
1775 .clkdm = { .name = "core_l3_clkdm" },
1776 .recalc = &followparent_recalc,
1779 static struct clk hsotgusb_ick_3430es1 = {
1780 .name = "hsotgusb_ick",
1781 .parent = &core_l3_ick,
1782 .prcm_mod = CORE_MOD,
1783 .enable_reg = CM_ICLKEN1,
1784 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1785 .flags = CLOCK_IN_OMAP3430ES1,
1786 .clkdm = { .name = "core_l3_clkdm" },
1787 .recalc = &followparent_recalc,
1790 static struct clk hsotgusb_ick_3430es2 = {
1791 .name = "hsotgusb_ick",
1792 .parent = &core_l3_ick,
1793 .prcm_mod = CORE_MOD,
1794 .enable_reg = CM_ICLKEN1,
1795 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1796 .idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1797 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1798 .clkdm = { .name = "core_l3_clkdm" },
1799 .recalc = &followparent_recalc,
1802 static struct clk sdrc_ick = {
1804 .parent = &core_l3_ick,
1805 .prcm_mod = CORE_MOD,
1806 .enable_reg = CM_ICLKEN1,
1807 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1808 .idlest_bit = OMAP3430_ST_SDRC_SHIFT,
1809 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT | WAIT_READY,
1810 .clkdm = { .name = "core_l3_clkdm" },
1811 .recalc = &followparent_recalc,
1814 static struct clk gpmc_fck = {
1816 .parent = &core_l3_ick,
1817 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1819 .clkdm = { .name = "core_l3_clkdm" },
1820 .recalc = &followparent_recalc,
1823 /* SECURITY_L3_ICK based clocks */
1825 static struct clk security_l3_ick = {
1826 .name = "security_l3_ick",
1828 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1829 PARENT_CONTROLS_CLOCK,
1830 .clkdm = { .name = "core_l3_clkdm" },
1831 .recalc = &followparent_recalc,
1834 static struct clk pka_ick = {
1836 .parent = &security_l3_ick,
1837 .prcm_mod = CORE_MOD,
1838 .enable_reg = CM_ICLKEN2,
1839 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1840 .idlest_bit = OMAP3430_ST_PKA_SHIFT,
1841 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1842 .clkdm = { .name = "core_l3_clkdm" },
1843 .recalc = &followparent_recalc,
1846 /* CORE_L4_ICK based clocks */
1848 static struct clk core_l4_ick = {
1849 .name = "core_l4_ick",
1851 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1852 PARENT_CONTROLS_CLOCK,
1853 .clkdm = { .name = "core_l4_clkdm" },
1854 .recalc = &followparent_recalc,
1857 static struct clk usbtll_ick = {
1858 .name = "usbtll_ick",
1859 .parent = &core_l4_ick,
1860 .prcm_mod = CORE_MOD,
1861 .enable_reg = CM_ICLKEN3,
1862 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1863 .idlest_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1864 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1865 .clkdm = { .name = "core_l4_clkdm" },
1866 .recalc = &followparent_recalc,
1869 static struct clk mmchs3_ick = {
1870 .name = "mmchs_ick",
1872 .parent = &core_l4_ick,
1873 .prcm_mod = CORE_MOD,
1874 .enable_reg = CM_ICLKEN1,
1875 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1876 .idlest_bit = OMAP3430ES2_ST_MMC3_SHIFT,
1877 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1878 .clkdm = { .name = "core_l4_clkdm" },
1879 .recalc = &followparent_recalc,
1882 /* Intersystem Communication Registers - chassis mode only */
1883 static struct clk icr_ick = {
1885 .parent = &core_l4_ick,
1886 .prcm_mod = CORE_MOD,
1887 .enable_reg = CM_ICLKEN1,
1888 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1889 .idlest_bit = OMAP3430_ST_ICR_SHIFT,
1890 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1891 .clkdm = { .name = "core_l4_clkdm" },
1892 .recalc = &followparent_recalc,
1895 static struct clk aes2_ick = {
1897 .parent = &core_l4_ick,
1898 .prcm_mod = CORE_MOD,
1899 .enable_reg = CM_ICLKEN1,
1900 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1901 .idlest_bit = OMAP3430_ST_AES2_SHIFT,
1902 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1903 .clkdm = { .name = "core_l4_clkdm" },
1904 .recalc = &followparent_recalc,
1907 static struct clk sha12_ick = {
1908 .name = "sha12_ick",
1909 .parent = &core_l4_ick,
1910 .prcm_mod = CORE_MOD,
1911 .enable_reg = CM_ICLKEN1,
1912 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1913 .idlest_bit = OMAP3430_ST_SHA12_SHIFT,
1914 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1915 .clkdm = { .name = "core_l4_clkdm" },
1916 .recalc = &followparent_recalc,
1919 static struct clk des2_ick = {
1921 .parent = &core_l4_ick,
1922 .prcm_mod = CORE_MOD,
1923 .enable_reg = CM_ICLKEN1,
1924 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1925 .idlest_bit = OMAP3430_ST_DES2_SHIFT,
1926 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1927 .clkdm = { .name = "core_l4_clkdm" },
1928 .recalc = &followparent_recalc,
1931 static struct clk mmchs2_ick = {
1932 .name = "mmchs_ick",
1934 .parent = &core_l4_ick,
1935 .prcm_mod = CORE_MOD,
1936 .enable_reg = CM_ICLKEN1,
1937 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1938 .idlest_bit = OMAP3430_ST_MMC2_SHIFT,
1939 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1940 .clkdm = { .name = "core_l4_clkdm" },
1941 .recalc = &followparent_recalc,
1944 static struct clk mmchs1_ick = {
1945 .name = "mmchs_ick",
1947 .parent = &core_l4_ick,
1948 .prcm_mod = CORE_MOD,
1949 .enable_reg = CM_ICLKEN1,
1950 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1951 .idlest_bit = OMAP3430_ST_MMC1_SHIFT,
1952 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1953 .clkdm = { .name = "core_l4_clkdm" },
1954 .recalc = &followparent_recalc,
1957 static struct clk mspro_ick = {
1958 .name = "mspro_ick",
1959 .parent = &core_l4_ick,
1960 .prcm_mod = CORE_MOD,
1961 .enable_reg = CM_ICLKEN1,
1962 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1963 .idlest_bit = OMAP3430_ST_MSPRO_SHIFT,
1964 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1965 .clkdm = { .name = "core_l4_clkdm" },
1966 .recalc = &followparent_recalc,
1969 static struct clk hdq_ick = {
1971 .parent = &core_l4_ick,
1972 .prcm_mod = CORE_MOD,
1973 .enable_reg = CM_ICLKEN1,
1974 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1975 .idlest_bit = OMAP3430_ST_HDQ_SHIFT,
1976 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1977 .clkdm = { .name = "core_l4_clkdm" },
1978 .recalc = &followparent_recalc,
1981 static struct clk mcspi4_ick = {
1982 .name = "mcspi_ick",
1984 .parent = &core_l4_ick,
1985 .prcm_mod = CORE_MOD,
1986 .enable_reg = CM_ICLKEN1,
1987 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1988 .idlest_bit = OMAP3430_ST_MCSPI4_SHIFT,
1989 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
1990 .clkdm = { .name = "core_l4_clkdm" },
1991 .recalc = &followparent_recalc,
1994 static struct clk mcspi3_ick = {
1995 .name = "mcspi_ick",
1997 .parent = &core_l4_ick,
1998 .prcm_mod = CORE_MOD,
1999 .enable_reg = CM_ICLKEN1,
2000 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
2001 .idlest_bit = OMAP3430_ST_MCSPI3_SHIFT,
2002 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2003 .clkdm = { .name = "core_l4_clkdm" },
2004 .recalc = &followparent_recalc,
2007 static struct clk mcspi2_ick = {
2008 .name = "mcspi_ick",
2010 .parent = &core_l4_ick,
2011 .prcm_mod = CORE_MOD,
2012 .enable_reg = CM_ICLKEN1,
2013 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
2014 .idlest_bit = OMAP3430_ST_MCSPI2_SHIFT,
2015 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2016 .clkdm = { .name = "core_l4_clkdm" },
2017 .recalc = &followparent_recalc,
2020 static struct clk mcspi1_ick = {
2021 .name = "mcspi_ick",
2023 .parent = &core_l4_ick,
2024 .prcm_mod = CORE_MOD,
2025 .enable_reg = CM_ICLKEN1,
2026 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
2027 .idlest_bit = OMAP3430_ST_MCSPI1_SHIFT,
2028 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2029 .clkdm = { .name = "core_l4_clkdm" },
2030 .recalc = &followparent_recalc,
2033 static struct clk i2c3_ick = {
2036 .parent = &core_l4_ick,
2037 .prcm_mod = CORE_MOD,
2038 .enable_reg = CM_ICLKEN1,
2039 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
2040 .idlest_bit = OMAP3430_ST_I2C3_SHIFT,
2041 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2042 .clkdm = { .name = "core_l4_clkdm" },
2043 .recalc = &followparent_recalc,
2046 static struct clk i2c2_ick = {
2049 .parent = &core_l4_ick,
2050 .prcm_mod = CORE_MOD,
2051 .enable_reg = CM_ICLKEN1,
2052 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
2053 .idlest_bit = OMAP3430_ST_I2C2_SHIFT,
2054 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2055 .clkdm = { .name = "core_l4_clkdm" },
2056 .recalc = &followparent_recalc,
2059 static struct clk i2c1_ick = {
2062 .parent = &core_l4_ick,
2063 .prcm_mod = CORE_MOD,
2064 .enable_reg = CM_ICLKEN1,
2065 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
2066 .idlest_bit = OMAP3430_ST_I2C1_SHIFT,
2067 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2068 .clkdm = { .name = "core_l4_clkdm" },
2069 .recalc = &followparent_recalc,
2072 static struct clk uart2_ick = {
2073 .name = "uart2_ick",
2074 .parent = &core_l4_ick,
2075 .prcm_mod = CORE_MOD,
2076 .enable_reg = CM_ICLKEN1,
2077 .enable_bit = OMAP3430_EN_UART2_SHIFT,
2078 .idlest_bit = OMAP3430_ST_UART2_SHIFT,
2079 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2080 .clkdm = { .name = "core_l4_clkdm" },
2081 .recalc = &followparent_recalc,
2084 static struct clk uart1_ick = {
2085 .name = "uart1_ick",
2086 .parent = &core_l4_ick,
2087 .prcm_mod = CORE_MOD,
2088 .enable_reg = CM_ICLKEN1,
2089 .enable_bit = OMAP3430_EN_UART1_SHIFT,
2090 .idlest_bit = OMAP3430_ST_UART1_SHIFT,
2091 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2092 .clkdm = { .name = "core_l4_clkdm" },
2093 .recalc = &followparent_recalc,
2096 static struct clk gpt11_ick = {
2097 .name = "gpt11_ick",
2098 .parent = &core_l4_ick,
2099 .prcm_mod = CORE_MOD,
2100 .enable_reg = CM_ICLKEN1,
2101 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
2102 .idlest_bit = OMAP3430_ST_GPT11_SHIFT,
2103 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2104 .clkdm = { .name = "core_l4_clkdm" },
2105 .recalc = &followparent_recalc,
2108 static struct clk gpt10_ick = {
2109 .name = "gpt10_ick",
2110 .parent = &core_l4_ick,
2111 .prcm_mod = CORE_MOD,
2112 .enable_reg = CM_ICLKEN1,
2113 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
2114 .idlest_bit = OMAP3430_ST_GPT10_SHIFT,
2115 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2116 .clkdm = { .name = "core_l4_clkdm" },
2117 .recalc = &followparent_recalc,
2120 static struct clk mcbsp5_ick = {
2121 .name = "mcbsp_ick",
2123 .parent = &core_l4_ick,
2124 .prcm_mod = CORE_MOD,
2125 .enable_reg = CM_ICLKEN1,
2126 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
2127 .idlest_bit = OMAP3430_ST_MCBSP5_SHIFT,
2128 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2129 .clkdm = { .name = "core_l4_clkdm" },
2130 .recalc = &followparent_recalc,
2133 static struct clk mcbsp1_ick = {
2134 .name = "mcbsp_ick",
2136 .parent = &core_l4_ick,
2137 .prcm_mod = CORE_MOD,
2138 .enable_reg = CM_ICLKEN1,
2139 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2140 .idlest_bit = OMAP3430_ST_MCBSP1_SHIFT,
2141 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2142 .clkdm = { .name = "core_l4_clkdm" },
2143 .recalc = &followparent_recalc,
2146 static struct clk fac_ick = {
2148 .parent = &core_l4_ick,
2149 .prcm_mod = CORE_MOD,
2150 .enable_reg = CM_ICLKEN1,
2151 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
2152 .idlest_bit = OMAP3430ES1_ST_FAC_SHIFT,
2153 .flags = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
2154 .clkdm = { .name = "core_l4_clkdm" },
2155 .recalc = &followparent_recalc,
2158 static struct clk mailboxes_ick = {
2159 .name = "mailboxes_ick",
2160 .parent = &core_l4_ick,
2161 .prcm_mod = CORE_MOD,
2162 .enable_reg = CM_ICLKEN1,
2163 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2164 .idlest_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2165 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2166 .clkdm = { .name = "core_l4_clkdm" },
2167 .recalc = &followparent_recalc,
2170 static struct clk omapctrl_ick = {
2171 .name = "omapctrl_ick",
2172 .parent = &core_l4_ick,
2173 .prcm_mod = CORE_MOD,
2174 .enable_reg = CM_ICLKEN1,
2175 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2176 .idlest_bit = OMAP3430_ST_OMAPCTRL_SHIFT,
2177 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT | WAIT_READY,
2178 .clkdm = { .name = "core_l4_clkdm" },
2179 .recalc = &followparent_recalc,
2182 /* SSI_L4_ICK based clocks */
2184 static struct clk ssi_l4_ick = {
2185 .name = "ssi_l4_ick",
2187 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2188 PARENT_CONTROLS_CLOCK,
2189 .clkdm = { .name = "core_l4_clkdm" },
2190 .recalc = &followparent_recalc,
2193 static struct clk ssi_ick_3430es1 = {
2195 .parent = &ssi_l4_ick,
2196 .prcm_mod = CORE_MOD,
2197 .enable_reg = CM_ICLKEN1,
2198 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2199 .flags = CLOCK_IN_OMAP3430ES1,
2200 .clkdm = { .name = "core_l4_clkdm" },
2201 .recalc = &followparent_recalc,
2204 static struct clk ssi_ick_3430es2 = {
2206 .parent = &ssi_l4_ick,
2207 .prcm_mod = CORE_MOD,
2208 .enable_reg = CM_ICLKEN1,
2209 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2210 .idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
2211 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2212 .clkdm = { .name = "core_l4_clkdm" },
2213 .recalc = &followparent_recalc,
2217 * REVISIT: Technically the TRM claims that this is CORE_CLK based,
2218 * but l4_ick makes more sense to me
2220 static const struct clksel usb_l4_clksel[] = {
2221 { .parent = &l4_ick, .rates = div2_rates },
2225 static struct clk usb_l4_ick = {
2226 .name = "usb_l4_ick",
2228 .prcm_mod = CORE_MOD,
2229 .init = &omap2_init_clksel_parent,
2230 .enable_reg = CM_ICLKEN1,
2231 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2232 .idlest_bit = OMAP3430ES1_ST_FSHOSTUSB_SHIFT,
2233 .clksel_reg = CM_CLKSEL,
2234 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2235 .clksel = usb_l4_clksel,
2236 .flags = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
2237 .clkdm = { .name = "core_l4_clkdm" },
2238 .recalc = &omap2_clksel_recalc,
2241 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2243 /* SECURITY_L4_ICK2 based clocks */
2245 static struct clk security_l4_ick2 = {
2246 .name = "security_l4_ick2",
2248 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2249 PARENT_CONTROLS_CLOCK,
2250 .clkdm = { .name = "core_l4_clkdm" },
2251 .recalc = &followparent_recalc,
2254 static struct clk aes1_ick = {
2256 .parent = &security_l4_ick2,
2257 .prcm_mod = CORE_MOD,
2258 .enable_reg = CM_ICLKEN2,
2259 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2260 .idlest_bit = OMAP3430_ST_AES1_SHIFT,
2261 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2262 .clkdm = { .name = "core_l4_clkdm" },
2263 .recalc = &followparent_recalc,
2266 static struct clk rng_ick = {
2268 .parent = &security_l4_ick2,
2269 .prcm_mod = CORE_MOD,
2270 .enable_reg = CM_ICLKEN2,
2271 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2272 .idlest_bit = OMAP3430_ST_RNG_SHIFT,
2273 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2274 .clkdm = { .name = "core_l4_clkdm" },
2275 .recalc = &followparent_recalc,
2278 static struct clk sha11_ick = {
2279 .name = "sha11_ick",
2280 .parent = &security_l4_ick2,
2281 .prcm_mod = CORE_MOD,
2282 .enable_reg = CM_ICLKEN2,
2283 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2284 .idlest_bit = OMAP3430_ST_SHA11_SHIFT,
2285 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2286 .clkdm = { .name = "core_l4_clkdm" },
2287 .recalc = &followparent_recalc,
2290 static struct clk des1_ick = {
2292 .parent = &security_l4_ick2,
2293 .prcm_mod = CORE_MOD,
2294 .enable_reg = CM_ICLKEN2,
2295 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2296 .idlest_bit = OMAP3430_ST_DES1_SHIFT,
2297 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2298 .clkdm = { .name = "core_l4_clkdm" },
2299 .recalc = &followparent_recalc,
2303 static struct clk dss1_alwon_fck_3430es1 = {
2304 .name = "dss1_alwon_fck",
2305 .parent = &dpll4_m4x2_ck,
2306 .prcm_mod = OMAP3430_DSS_MOD,
2307 .enable_reg = CM_FCLKEN,
2308 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2309 .flags = CLOCK_IN_OMAP343X,
2310 .clkdm = { .name = "dss_clkdm" },
2311 .recalc = &followparent_recalc,
2314 static struct clk dss1_alwon_fck_3430es2 = {
2315 .name = "dss1_alwon_fck",
2316 .parent = &dpll4_m4x2_ck,
2317 .init = &omap2_init_clksel_parent,
2318 .prcm_mod = OMAP3430_DSS_MOD,
2319 .enable_reg = CM_FCLKEN,
2320 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2321 .idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
2322 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2323 .clkdm = { .name = "dss_clkdm" },
2324 .recalc = &followparent_recalc,
2327 static struct clk dss_tv_fck = {
2328 .name = "dss_tv_fck",
2329 .parent = &omap_54m_fck,
2330 .prcm_mod = OMAP3430_DSS_MOD,
2331 .enable_reg = CM_FCLKEN,
2332 .enable_bit = OMAP3430_EN_TV_SHIFT,
2333 .flags = CLOCK_IN_OMAP343X,
2334 .clkdm = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */
2335 .recalc = &followparent_recalc,
2338 static struct clk dss_96m_fck = {
2339 .name = "dss_96m_fck",
2340 .parent = &omap_96m_fck,
2341 .prcm_mod = OMAP3430_DSS_MOD,
2342 .enable_reg = CM_FCLKEN,
2343 .enable_bit = OMAP3430_EN_TV_SHIFT,
2344 .flags = CLOCK_IN_OMAP343X,
2345 .clkdm = { .name = "dss_clkdm" },
2346 .recalc = &followparent_recalc,
2349 static struct clk dss2_alwon_fck = {
2350 .name = "dss2_alwon_fck",
2352 .prcm_mod = OMAP3430_DSS_MOD,
2353 .enable_reg = CM_FCLKEN,
2354 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2355 .flags = CLOCK_IN_OMAP343X,
2356 .clkdm = { .name = "dss_clkdm" },
2357 .recalc = &followparent_recalc,
2360 static struct clk dss_ick_3430es1 = {
2361 /* Handles both L3 and L4 clocks */
2364 .prcm_mod = OMAP3430_DSS_MOD,
2365 .enable_reg = CM_ICLKEN,
2366 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2367 .flags = CLOCK_IN_OMAP3430ES1,
2368 .clkdm = { .name = "dss_clkdm" },
2369 .recalc = &followparent_recalc,
2372 static struct clk dss_ick_3430es2 = {
2373 /* Handles both L3 and L4 clocks */
2376 .prcm_mod = OMAP3430_DSS_MOD,
2377 .enable_reg = CM_ICLKEN,
2378 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2379 .idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
2380 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2381 .clkdm = { .name = "dss_clkdm" },
2382 .recalc = &followparent_recalc,
2387 static struct clk cam_mclk = {
2389 .parent = &dpll4_m5x2_ck,
2390 .prcm_mod = OMAP3430_CAM_MOD,
2391 .enable_reg = CM_FCLKEN,
2392 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2393 .flags = CLOCK_IN_OMAP343X,
2394 .clkdm = { .name = "cam_clkdm" },
2395 .recalc = &followparent_recalc,
2398 static struct clk cam_ick = {
2399 /* Handles both L3 and L4 clocks */
2402 .prcm_mod = OMAP3430_CAM_MOD,
2403 .enable_reg = CM_ICLKEN,
2404 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2405 .flags = CLOCK_IN_OMAP343X,
2406 .clkdm = { .name = "cam_clkdm" },
2407 .recalc = &followparent_recalc,
2410 static struct clk csi2_96m_fck = {
2411 .name = "csi2_96m_fck",
2412 .parent = &core_96m_fck,
2413 .prcm_mod = OMAP3430_CAM_MOD,
2414 .enable_reg = CM_FCLKEN,
2415 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
2416 .flags = CLOCK_IN_OMAP343X,
2417 .clkdm = { .name = "cam_clkdm" },
2418 .recalc = &followparent_recalc,
2421 /* USBHOST - 3430ES2 only */
2423 static struct clk usbhost_120m_fck = {
2424 .name = "usbhost_120m_fck",
2425 .parent = &dpll5_m2_ck,
2426 .prcm_mod = OMAP3430ES2_USBHOST_MOD,
2427 .enable_reg = CM_FCLKEN,
2428 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2429 .flags = CLOCK_IN_OMAP3430ES2,
2430 .clkdm = { .name = "usbhost_clkdm" },
2431 .recalc = &followparent_recalc,
2434 static struct clk usbhost_48m_fck = {
2435 .name = "usbhost_48m_fck",
2436 .parent = &omap_48m_fck,
2437 .prcm_mod = OMAP3430ES2_USBHOST_MOD,
2438 .enable_reg = CM_FCLKEN,
2439 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2440 .idlest_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
2441 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2442 .clkdm = { .name = "usbhost_clkdm" },
2443 .recalc = &followparent_recalc,
2446 static struct clk usbhost_ick = {
2447 /* Handles both L3 and L4 clocks */
2448 .name = "usbhost_ick",
2450 .prcm_mod = OMAP3430ES2_USBHOST_MOD,
2451 .enable_reg = CM_ICLKEN,
2452 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2453 .idlest_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
2454 .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2455 .clkdm = { .name = "usbhost_clkdm" },
2456 .recalc = &followparent_recalc,
2461 static const struct clksel_rate usim_96m_rates[] = {
2462 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2463 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2464 { .div = 8, .val = 5, .flags = RATE_IN_343X },
2465 { .div = 10, .val = 6, .flags = RATE_IN_343X },
2469 static const struct clksel_rate usim_120m_rates[] = {
2470 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
2471 { .div = 8, .val = 8, .flags = RATE_IN_343X },
2472 { .div = 16, .val = 9, .flags = RATE_IN_343X },
2473 { .div = 20, .val = 10, .flags = RATE_IN_343X },
2477 static const struct clksel usim_clksel[] = {
2478 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2479 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
2480 { .parent = &sys_ck, .rates = div2_rates },
2485 static struct clk usim_fck = {
2487 .prcm_mod = WKUP_MOD,
2488 .init = &omap2_init_clksel_parent,
2489 .enable_reg = CM_FCLKEN,
2490 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2491 .clksel_reg = CM_CLKSEL,
2492 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2493 .clksel = usim_clksel,
2494 .flags = CLOCK_IN_OMAP3430ES2,
2495 .clkdm = { .name = "prm_clkdm" },
2496 .recalc = &omap2_clksel_recalc,
2499 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2500 static struct clk gpt1_fck = {
2502 .prcm_mod = WKUP_MOD,
2503 .init = &omap2_init_clksel_parent,
2504 .enable_reg = CM_FCLKEN,
2505 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2506 .idlest_bit = OMAP3430_ST_GPT1_SHIFT,
2507 .clksel_reg = CM_CLKSEL,
2508 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2509 .clksel = omap343x_gpt_clksel,
2510 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2511 .clkdm = { .name = "prm_clkdm" },
2512 .recalc = &omap2_clksel_recalc,
2515 static struct clk wkup_32k_fck = {
2516 .name = "wkup_32k_fck",
2517 .parent = &omap_32k_fck,
2518 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2519 .clkdm = { .name = "prm_clkdm" },
2520 .recalc = &followparent_recalc,
2523 static struct clk gpio1_fck = {
2524 .name = "gpio1_fck",
2525 .parent = &wkup_32k_fck,
2526 .prcm_mod = WKUP_MOD,
2527 .enable_reg = CM_FCLKEN,
2528 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2529 .idlest_bit = OMAP3430_ST_GPIO1_SHIFT,
2530 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2531 .clkdm = { .name = "prm_clkdm" },
2532 .recalc = &followparent_recalc,
2535 static struct clk wdt2_fck = {
2537 .parent = &wkup_32k_fck,
2538 .prcm_mod = WKUP_MOD,
2539 .enable_reg = CM_FCLKEN,
2540 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2541 .idlest_bit = OMAP3430_ST_WDT2_SHIFT,
2542 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2543 .clkdm = { .name = "prm_clkdm" },
2544 .recalc = &followparent_recalc,
2547 static struct clk wkup_l4_ick = {
2548 .name = "wkup_l4_ick",
2550 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2551 .clkdm = { .name = "prm_clkdm" },
2552 .recalc = &followparent_recalc,
2556 /* Never specifically named in the TRM, so we have to infer a likely name */
2557 static struct clk usim_ick = {
2559 .parent = &wkup_l4_ick,
2560 .prcm_mod = WKUP_MOD,
2561 .enable_reg = CM_ICLKEN,
2562 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2563 .flags = CLOCK_IN_OMAP3430ES2,
2564 .clkdm = { .name = "prm_clkdm" },
2565 .recalc = &followparent_recalc,
2568 static struct clk wdt2_ick = {
2570 .parent = &wkup_l4_ick,
2571 .prcm_mod = WKUP_MOD,
2572 .enable_reg = CM_ICLKEN,
2573 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2574 .idlest_bit = OMAP3430_ST_WDT2_SHIFT,
2575 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2576 .clkdm = { .name = "prm_clkdm" },
2577 .recalc = &followparent_recalc,
2580 static struct clk wdt1_ick = {
2582 .parent = &wkup_l4_ick,
2583 .prcm_mod = WKUP_MOD,
2584 .enable_reg = CM_ICLKEN,
2585 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2586 .idlest_bit = OMAP3430_ST_WDT1_SHIFT,
2587 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2588 .clkdm = { .name = "prm_clkdm" },
2589 .recalc = &followparent_recalc,
2592 static struct clk gpio1_ick = {
2593 .name = "gpio1_ick",
2594 .parent = &wkup_l4_ick,
2595 .prcm_mod = WKUP_MOD,
2596 .enable_reg = CM_ICLKEN,
2597 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2598 .idlest_bit = OMAP3430_ST_GPIO1_SHIFT,
2599 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2600 .clkdm = { .name = "prm_clkdm" },
2601 .recalc = &followparent_recalc,
2604 static struct clk omap_32ksync_ick = {
2605 .name = "omap_32ksync_ick",
2606 .parent = &wkup_l4_ick,
2607 .prcm_mod = WKUP_MOD,
2608 .enable_reg = CM_ICLKEN,
2609 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2610 .idlest_bit = OMAP3430_ST_32KSYNC_SHIFT,
2611 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2612 .clkdm = { .name = "prm_clkdm" },
2613 .recalc = &followparent_recalc,
2616 static struct clk gpt12_ick = {
2617 .name = "gpt12_ick",
2618 .parent = &wkup_l4_ick,
2619 .prcm_mod = WKUP_MOD,
2620 .enable_reg = CM_ICLKEN,
2621 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2622 .idlest_bit = OMAP3430_ST_GPT12_SHIFT,
2623 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2624 .clkdm = { .name = "prm_clkdm" },
2625 .recalc = &followparent_recalc,
2628 static struct clk gpt1_ick = {
2630 .parent = &wkup_l4_ick,
2631 .prcm_mod = WKUP_MOD,
2632 .enable_reg = CM_ICLKEN,
2633 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2634 .idlest_bit = OMAP3430_ST_GPT1_SHIFT,
2635 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2636 .clkdm = { .name = "prm_clkdm" },
2637 .recalc = &followparent_recalc,
2642 /* PER clock domain */
2644 static struct clk per_96m_fck = {
2645 .name = "per_96m_fck",
2646 .parent = &omap_96m_alwon_fck,
2647 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2648 PARENT_CONTROLS_CLOCK,
2649 .clkdm = { .name = "per_clkdm" },
2650 .recalc = &followparent_recalc,
2653 static struct clk per_48m_fck = {
2654 .name = "per_48m_fck",
2655 .parent = &omap_48m_fck,
2656 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2657 PARENT_CONTROLS_CLOCK,
2658 .clkdm = { .name = "per_clkdm" },
2659 .recalc = &followparent_recalc,
2662 static struct clk uart3_fck = {
2663 .name = "uart3_fck",
2664 .parent = &per_48m_fck,
2665 .prcm_mod = OMAP3430_PER_MOD,
2666 .enable_reg = CM_FCLKEN,
2667 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2668 .idlest_bit = OMAP3430_ST_UART3_SHIFT,
2669 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2670 .clkdm = { .name = "per_clkdm" },
2671 .recalc = &followparent_recalc,
2674 static struct clk gpt2_fck = {
2676 .prcm_mod = OMAP3430_PER_MOD,
2677 .init = &omap2_init_clksel_parent,
2678 .enable_reg = CM_FCLKEN,
2679 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2680 .idlest_bit = OMAP3430_ST_GPT2_SHIFT,
2681 .clksel_reg = CM_CLKSEL,
2682 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2683 .clksel = omap343x_gpt_clksel,
2684 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2685 .clkdm = { .name = "per_clkdm" },
2686 .recalc = &omap2_clksel_recalc,
2689 static struct clk gpt3_fck = {
2691 .prcm_mod = OMAP3430_PER_MOD,
2692 .init = &omap2_init_clksel_parent,
2693 .enable_reg = CM_FCLKEN,
2694 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2695 .idlest_bit = OMAP3430_ST_GPT3_SHIFT,
2696 .clksel_reg = CM_CLKSEL,
2697 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2698 .clksel = omap343x_gpt_clksel,
2699 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2700 .clkdm = { .name = "per_clkdm" },
2701 .recalc = &omap2_clksel_recalc,
2704 static struct clk gpt4_fck = {
2706 .prcm_mod = OMAP3430_PER_MOD,
2707 .init = &omap2_init_clksel_parent,
2708 .enable_reg = CM_FCLKEN,
2709 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2710 .idlest_bit = OMAP3430_ST_GPT4_SHIFT,
2711 .clksel_reg = CM_CLKSEL,
2712 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2713 .clksel = omap343x_gpt_clksel,
2714 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2715 .clkdm = { .name = "per_clkdm" },
2716 .recalc = &omap2_clksel_recalc,
2719 static struct clk gpt5_fck = {
2721 .prcm_mod = OMAP3430_PER_MOD,
2722 .init = &omap2_init_clksel_parent,
2723 .enable_reg = CM_FCLKEN,
2724 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2725 .idlest_bit = OMAP3430_ST_GPT5_SHIFT,
2726 .clksel_reg = CM_CLKSEL,
2727 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2728 .clksel = omap343x_gpt_clksel,
2729 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2730 .clkdm = { .name = "per_clkdm" },
2731 .recalc = &omap2_clksel_recalc,
2734 static struct clk gpt6_fck = {
2736 .prcm_mod = OMAP3430_PER_MOD,
2737 .init = &omap2_init_clksel_parent,
2738 .enable_reg = CM_FCLKEN,
2739 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2740 .idlest_bit = OMAP3430_ST_GPT6_SHIFT,
2741 .clksel_reg = CM_CLKSEL,
2742 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2743 .clksel = omap343x_gpt_clksel,
2744 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2745 .clkdm = { .name = "per_clkdm" },
2746 .recalc = &omap2_clksel_recalc,
2749 static struct clk gpt7_fck = {
2751 .prcm_mod = OMAP3430_PER_MOD,
2752 .init = &omap2_init_clksel_parent,
2753 .enable_reg = CM_FCLKEN,
2754 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2755 .idlest_bit = OMAP3430_ST_GPT7_SHIFT,
2756 .clksel_reg = CM_CLKSEL,
2757 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2758 .clksel = omap343x_gpt_clksel,
2759 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2760 .clkdm = { .name = "per_clkdm" },
2761 .recalc = &omap2_clksel_recalc,
2764 static struct clk gpt8_fck = {
2766 .prcm_mod = OMAP3430_PER_MOD,
2767 .init = &omap2_init_clksel_parent,
2768 .enable_reg = CM_FCLKEN,
2769 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2770 .idlest_bit = OMAP3430_ST_GPT8_SHIFT,
2771 .clksel_reg = CM_CLKSEL,
2772 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2773 .clksel = omap343x_gpt_clksel,
2774 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2775 .clkdm = { .name = "per_clkdm" },
2776 .recalc = &omap2_clksel_recalc,
2779 static struct clk gpt9_fck = {
2781 .prcm_mod = OMAP3430_PER_MOD,
2782 .init = &omap2_init_clksel_parent,
2783 .enable_reg = CM_FCLKEN,
2784 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2785 .idlest_bit = OMAP3430_ST_GPT9_SHIFT,
2786 .clksel_reg = CM_CLKSEL,
2787 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2788 .clksel = omap343x_gpt_clksel,
2789 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2790 .clkdm = { .name = "per_clkdm" },
2791 .recalc = &omap2_clksel_recalc,
2794 static struct clk per_32k_alwon_fck = {
2795 .name = "per_32k_alwon_fck",
2796 .parent = &omap_32k_fck,
2797 .clkdm = { .name = "per_clkdm" },
2798 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2799 .recalc = &followparent_recalc,
2802 static struct clk gpio6_fck = {
2803 .name = "gpio6_fck",
2804 .parent = &per_32k_alwon_fck,
2805 .prcm_mod = OMAP3430_PER_MOD,
2806 .enable_reg = CM_FCLKEN,
2807 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2808 .idlest_bit = OMAP3430_ST_GPIO6_SHIFT,
2809 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2810 .clkdm = { .name = "per_clkdm" },
2811 .recalc = &followparent_recalc,
2814 static struct clk gpio5_fck = {
2815 .name = "gpio5_fck",
2816 .parent = &per_32k_alwon_fck,
2817 .prcm_mod = OMAP3430_PER_MOD,
2818 .enable_reg = CM_FCLKEN,
2819 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2820 .idlest_bit = OMAP3430_ST_GPIO5_SHIFT,
2821 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2822 .clkdm = { .name = "per_clkdm" },
2823 .recalc = &followparent_recalc,
2826 static struct clk gpio4_fck = {
2827 .name = "gpio4_fck",
2828 .parent = &per_32k_alwon_fck,
2829 .prcm_mod = OMAP3430_PER_MOD,
2830 .enable_reg = CM_FCLKEN,
2831 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2832 .idlest_bit = OMAP3430_ST_GPIO4_SHIFT,
2833 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2834 .clkdm = { .name = "per_clkdm" },
2835 .recalc = &followparent_recalc,
2838 static struct clk gpio3_fck = {
2839 .name = "gpio3_fck",
2840 .parent = &per_32k_alwon_fck,
2841 .prcm_mod = OMAP3430_PER_MOD,
2842 .enable_reg = CM_FCLKEN,
2843 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2844 .idlest_bit = OMAP3430_ST_GPIO3_SHIFT,
2845 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2846 .clkdm = { .name = "per_clkdm" },
2847 .recalc = &followparent_recalc,
2850 static struct clk gpio2_fck = {
2851 .name = "gpio2_fck",
2852 .parent = &per_32k_alwon_fck,
2853 .prcm_mod = OMAP3430_PER_MOD,
2854 .enable_reg = CM_FCLKEN,
2855 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2856 .idlest_bit = OMAP3430_ST_GPIO2_SHIFT,
2857 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2858 .clkdm = { .name = "per_clkdm" },
2859 .recalc = &followparent_recalc,
2862 static struct clk wdt3_fck = {
2864 .parent = &per_32k_alwon_fck,
2865 .prcm_mod = OMAP3430_PER_MOD,
2866 .enable_reg = CM_FCLKEN,
2867 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2868 .idlest_bit = OMAP3430_ST_WDT3_SHIFT,
2869 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2870 .clkdm = { .name = "per_clkdm" },
2871 .recalc = &followparent_recalc,
2874 static struct clk per_l4_ick = {
2875 .name = "per_l4_ick",
2877 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2878 PARENT_CONTROLS_CLOCK,
2879 .clkdm = { .name = "per_clkdm" },
2880 .recalc = &followparent_recalc,
2883 static struct clk gpio6_ick = {
2884 .name = "gpio6_ick",
2885 .parent = &per_l4_ick,
2886 .prcm_mod = OMAP3430_PER_MOD,
2887 .enable_reg = CM_ICLKEN,
2888 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2889 .idlest_bit = OMAP3430_ST_GPIO6_SHIFT,
2890 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2891 .clkdm = { .name = "per_clkdm" },
2892 .recalc = &followparent_recalc,
2895 static struct clk gpio5_ick = {
2896 .name = "gpio5_ick",
2897 .parent = &per_l4_ick,
2898 .prcm_mod = OMAP3430_PER_MOD,
2899 .enable_reg = CM_ICLKEN,
2900 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2901 .idlest_bit = OMAP3430_ST_GPIO5_SHIFT,
2902 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2903 .clkdm = { .name = "per_clkdm" },
2904 .recalc = &followparent_recalc,
2907 static struct clk gpio4_ick = {
2908 .name = "gpio4_ick",
2909 .parent = &per_l4_ick,
2910 .prcm_mod = OMAP3430_PER_MOD,
2911 .enable_reg = CM_ICLKEN,
2912 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2913 .idlest_bit = OMAP3430_ST_GPIO4_SHIFT,
2914 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2915 .clkdm = { .name = "per_clkdm" },
2916 .recalc = &followparent_recalc,
2919 static struct clk gpio3_ick = {
2920 .name = "gpio3_ick",
2921 .parent = &per_l4_ick,
2922 .prcm_mod = OMAP3430_PER_MOD,
2923 .enable_reg = CM_ICLKEN,
2924 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2925 .idlest_bit = OMAP3430_ST_GPIO3_SHIFT,
2926 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2927 .clkdm = { .name = "per_clkdm" },
2928 .recalc = &followparent_recalc,
2931 static struct clk gpio2_ick = {
2932 .name = "gpio2_ick",
2933 .parent = &per_l4_ick,
2934 .prcm_mod = OMAP3430_PER_MOD,
2935 .enable_reg = CM_ICLKEN,
2936 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2937 .idlest_bit = OMAP3430_ST_GPIO2_SHIFT,
2938 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2939 .clkdm = { .name = "per_clkdm" },
2940 .recalc = &followparent_recalc,
2943 static struct clk wdt3_ick = {
2945 .parent = &per_l4_ick,
2946 .prcm_mod = OMAP3430_PER_MOD,
2947 .enable_reg = CM_ICLKEN,
2948 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2949 .idlest_bit = OMAP3430_ST_WDT3_SHIFT,
2950 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2951 .clkdm = { .name = "per_clkdm" },
2952 .recalc = &followparent_recalc,
2955 static struct clk uart3_ick = {
2956 .name = "uart3_ick",
2957 .parent = &per_l4_ick,
2958 .prcm_mod = OMAP3430_PER_MOD,
2959 .enable_reg = CM_ICLKEN,
2960 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2961 .idlest_bit = OMAP3430_ST_UART3_SHIFT,
2962 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2963 .clkdm = { .name = "per_clkdm" },
2964 .recalc = &followparent_recalc,
2967 static struct clk gpt9_ick = {
2969 .parent = &per_l4_ick,
2970 .prcm_mod = OMAP3430_PER_MOD,
2971 .enable_reg = CM_ICLKEN,
2972 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2973 .idlest_bit = OMAP3430_ST_GPT9_SHIFT,
2974 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2975 .clkdm = { .name = "per_clkdm" },
2976 .recalc = &followparent_recalc,
2979 static struct clk gpt8_ick = {
2981 .parent = &per_l4_ick,
2982 .prcm_mod = OMAP3430_PER_MOD,
2983 .enable_reg = CM_ICLKEN,
2984 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2985 .idlest_bit = OMAP3430_ST_GPT8_SHIFT,
2986 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2987 .clkdm = { .name = "per_clkdm" },
2988 .recalc = &followparent_recalc,
2991 static struct clk gpt7_ick = {
2993 .parent = &per_l4_ick,
2994 .prcm_mod = OMAP3430_PER_MOD,
2995 .enable_reg = CM_ICLKEN,
2996 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2997 .idlest_bit = OMAP3430_ST_GPT7_SHIFT,
2998 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
2999 .clkdm = { .name = "per_clkdm" },
3000 .recalc = &followparent_recalc,
3003 static struct clk gpt6_ick = {
3005 .parent = &per_l4_ick,
3006 .prcm_mod = OMAP3430_PER_MOD,
3007 .enable_reg = CM_ICLKEN,
3008 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
3009 .idlest_bit = OMAP3430_ST_GPT6_SHIFT,
3010 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3011 .clkdm = { .name = "per_clkdm" },
3012 .recalc = &followparent_recalc,
3015 static struct clk gpt5_ick = {
3017 .parent = &per_l4_ick,
3018 .prcm_mod = OMAP3430_PER_MOD,
3019 .enable_reg = CM_ICLKEN,
3020 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
3021 .idlest_bit = OMAP3430_ST_GPT5_SHIFT,
3022 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3023 .clkdm = { .name = "per_clkdm" },
3024 .recalc = &followparent_recalc,
3027 static struct clk gpt4_ick = {
3029 .parent = &per_l4_ick,
3030 .prcm_mod = OMAP3430_PER_MOD,
3031 .enable_reg = CM_ICLKEN,
3032 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
3033 .idlest_bit = OMAP3430_ST_GPT4_SHIFT,
3034 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3035 .clkdm = { .name = "per_clkdm" },
3036 .recalc = &followparent_recalc,
3039 static struct clk gpt3_ick = {
3041 .parent = &per_l4_ick,
3042 .prcm_mod = OMAP3430_PER_MOD,
3043 .enable_reg = CM_ICLKEN,
3044 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
3045 .idlest_bit = OMAP3430_ST_GPT3_SHIFT,
3046 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3047 .clkdm = { .name = "per_clkdm" },
3048 .recalc = &followparent_recalc,
3051 static struct clk gpt2_ick = {
3053 .parent = &per_l4_ick,
3054 .prcm_mod = OMAP3430_PER_MOD,
3055 .enable_reg = CM_ICLKEN,
3056 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
3057 .idlest_bit = OMAP3430_ST_GPT2_SHIFT,
3058 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3059 .clkdm = { .name = "per_clkdm" },
3060 .recalc = &followparent_recalc,
3063 static struct clk mcbsp2_ick = {
3064 .name = "mcbsp_ick",
3066 .parent = &per_l4_ick,
3067 .prcm_mod = OMAP3430_PER_MOD,
3068 .enable_reg = CM_ICLKEN,
3069 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
3070 .idlest_bit = OMAP3430_ST_MCBSP2_SHIFT,
3071 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3072 .clkdm = { .name = "per_clkdm" },
3073 .recalc = &followparent_recalc,
3076 static struct clk mcbsp3_ick = {
3077 .name = "mcbsp_ick",
3079 .parent = &per_l4_ick,
3080 .prcm_mod = OMAP3430_PER_MOD,
3081 .enable_reg = CM_ICLKEN,
3082 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
3083 .idlest_bit = OMAP3430_ST_MCBSP3_SHIFT,
3084 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3085 .clkdm = { .name = "per_clkdm" },
3086 .recalc = &followparent_recalc,
3089 static struct clk mcbsp4_ick = {
3090 .name = "mcbsp_ick",
3092 .parent = &per_l4_ick,
3093 .prcm_mod = OMAP3430_PER_MOD,
3094 .enable_reg = CM_ICLKEN,
3095 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
3096 .idlest_bit = OMAP3430_ST_MCBSP4_SHIFT,
3097 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3098 .clkdm = { .name = "per_clkdm" },
3099 .recalc = &followparent_recalc,
3102 static const struct clksel mcbsp_234_clksel[] = {
3103 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
3104 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
3108 static struct clk mcbsp2_src_fck = {
3109 .name = "mcbsp_src_fck",
3111 .prcm_mod = CLK_REG_IN_SCM,
3112 .init = &omap2_init_clksel_parent,
3113 .clksel_reg = OMAP2_CONTROL_DEVCONF0,
3114 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
3115 .clksel = mcbsp_234_clksel,
3116 .flags = CLOCK_IN_OMAP343X,
3117 .clkdm = { .name = "per_clkdm" },
3118 .recalc = &omap2_clksel_recalc,
3121 static struct clk mcbsp2_fck = {
3122 .name = "mcbsp_fck",
3124 .parent = &mcbsp2_src_fck,
3125 .prcm_mod = OMAP3430_PER_MOD,
3126 .enable_reg = CM_FCLKEN,
3127 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
3128 .idlest_bit = OMAP3430_ST_MCBSP2_SHIFT,
3129 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3130 .clkdm = { .name = "per_clkdm" },
3131 .recalc = &omap2_clksel_recalc,
3134 static struct clk mcbsp3_src_fck = {
3135 .name = "mcbsp_src_fck",
3137 .prcm_mod = CLK_REG_IN_SCM,
3138 .init = &omap2_init_clksel_parent,
3139 .clksel_reg = OMAP343X_CONTROL_DEVCONF1,
3140 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
3141 .clksel = mcbsp_234_clksel,
3142 .flags = CLOCK_IN_OMAP343X,
3143 .clkdm = { .name = "per_clkdm" },
3144 .recalc = &omap2_clksel_recalc,
3147 static struct clk mcbsp3_fck = {
3148 .name = "mcbsp_fck",
3150 .parent = &mcbsp3_src_fck,
3151 .prcm_mod = OMAP3430_PER_MOD,
3152 .enable_reg = CM_FCLKEN,
3153 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
3154 .idlest_bit = OMAP3430_ST_MCBSP3_SHIFT,
3155 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3156 .clkdm = { .name = "per_clkdm" },
3157 .recalc = &omap2_clksel_recalc,
3160 static struct clk mcbsp4_src_fck = {
3161 .name = "mcbsp_src_fck",
3163 .prcm_mod = CLK_REG_IN_SCM,
3164 .init = &omap2_init_clksel_parent,
3165 .clksel_reg = OMAP343X_CONTROL_DEVCONF1,
3166 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
3167 .clksel = mcbsp_234_clksel,
3168 .flags = CLOCK_IN_OMAP343X,
3169 .clkdm = { .name = "per_clkdm" },
3170 .recalc = &omap2_clksel_recalc,
3173 static struct clk mcbsp4_fck = {
3174 .name = "mcbsp_fck",
3176 .parent = &mcbsp4_src_fck,
3177 .prcm_mod = OMAP3430_PER_MOD,
3178 .enable_reg = CM_FCLKEN,
3179 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
3180 .idlest_bit = OMAP3430_ST_MCBSP4_SHIFT,
3181 .flags = CLOCK_IN_OMAP343X | WAIT_READY,
3182 .clkdm = { .name = "per_clkdm" },
3183 .recalc = &omap2_clksel_recalc,
3188 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
3190 static const struct clksel_rate emu_src_sys_rates[] = {
3191 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
3195 static const struct clksel_rate emu_src_core_rates[] = {
3196 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3200 static const struct clksel_rate emu_src_per_rates[] = {
3201 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3205 static const struct clksel_rate emu_src_mpu_rates[] = {
3206 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
3210 static const struct clksel emu_src_clksel[] = {
3211 { .parent = &sys_ck, .rates = emu_src_sys_rates },
3212 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
3213 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
3214 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
3219 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
3220 * to switch the source of some of the EMU clocks.
3221 * XXX Are there CLKEN bits for these EMU clks?
3223 static struct clk emu_src_ck = {
3224 .name = "emu_src_ck",
3225 .prcm_mod = OMAP3430_EMU_MOD,
3226 .init = &omap2_init_clksel_parent,
3227 .clksel_reg = CM_CLKSEL1,
3228 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
3229 .clksel = emu_src_clksel,
3230 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3231 .clkdm = { .name = "emu_clkdm" },
3232 .recalc = &omap2_clksel_recalc,
3235 static const struct clksel_rate pclk_emu_rates[] = {
3236 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3237 { .div = 3, .val = 3, .flags = RATE_IN_343X },
3238 { .div = 4, .val = 4, .flags = RATE_IN_343X },
3239 { .div = 6, .val = 6, .flags = RATE_IN_343X },
3243 static const struct clksel pclk_emu_clksel[] = {
3244 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
3248 static struct clk pclk_fck = {
3250 .prcm_mod = OMAP3430_EMU_MOD,
3251 .init = &omap2_init_clksel_parent,
3252 .clksel_reg = CM_CLKSEL1,
3253 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
3254 .clksel = pclk_emu_clksel,
3255 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3256 .clkdm = { .name = "emu_clkdm" },
3257 .recalc = &omap2_clksel_recalc,
3260 static const struct clksel_rate pclkx2_emu_rates[] = {
3261 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3262 { .div = 2, .val = 2, .flags = RATE_IN_343X },
3263 { .div = 3, .val = 3, .flags = RATE_IN_343X },
3267 static const struct clksel pclkx2_emu_clksel[] = {
3268 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
3272 static struct clk pclkx2_fck = {
3273 .name = "pclkx2_fck",
3274 .prcm_mod = OMAP3430_EMU_MOD,
3275 .init = &omap2_init_clksel_parent,
3276 .clksel_reg = CM_CLKSEL1,
3277 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
3278 .clksel = pclkx2_emu_clksel,
3279 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3280 .clkdm = { .name = "emu_clkdm" },
3281 .recalc = &omap2_clksel_recalc,
3284 static const struct clksel atclk_emu_clksel[] = {
3285 { .parent = &emu_src_ck, .rates = div2_rates },
3289 static struct clk atclk_fck = {
3290 .name = "atclk_fck",
3291 .prcm_mod = OMAP3430_EMU_MOD,
3292 .init = &omap2_init_clksel_parent,
3293 .clksel_reg = CM_CLKSEL1,
3294 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
3295 .clksel = atclk_emu_clksel,
3296 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3297 .clkdm = { .name = "emu_clkdm" },
3298 .recalc = &omap2_clksel_recalc,
3301 static struct clk traceclk_src_fck = {
3302 .name = "traceclk_src_fck",
3303 .prcm_mod = OMAP3430_EMU_MOD,
3304 .init = &omap2_init_clksel_parent,
3305 .clksel_reg = CM_CLKSEL1,
3306 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
3307 .clksel = emu_src_clksel,
3308 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3309 .clkdm = { .name = "emu_clkdm" },
3310 .recalc = &omap2_clksel_recalc,
3313 static const struct clksel_rate traceclk_rates[] = {
3314 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3315 { .div = 2, .val = 2, .flags = RATE_IN_343X },
3316 { .div = 4, .val = 4, .flags = RATE_IN_343X },
3320 static const struct clksel traceclk_clksel[] = {
3321 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3325 static struct clk traceclk_fck = {
3326 .name = "traceclk_fck",
3327 .prcm_mod = OMAP3430_EMU_MOD,
3328 .init = &omap2_init_clksel_parent,
3329 .clksel_reg = CM_CLKSEL1,
3330 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
3331 .clksel = traceclk_clksel,
3332 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3333 .clkdm = { .name = "emu_clkdm" },
3334 .recalc = &omap2_clksel_recalc,
3339 /* SmartReflex fclk (VDD1) */
3340 static struct clk sr1_fck = {
3343 .prcm_mod = WKUP_MOD,
3344 .enable_reg = CM_FCLKEN,
3345 .enable_bit = OMAP3430_EN_SR1_SHIFT,
3346 .idlest_bit = OMAP3430_ST_SR1_SHIFT,
3347 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | WAIT_READY,
3348 .clkdm = { .name = "prm_clkdm" },
3349 .recalc = &followparent_recalc,
3352 /* SmartReflex fclk (VDD2) */
3353 static struct clk sr2_fck = {
3356 .prcm_mod = WKUP_MOD,
3357 .enable_reg = CM_FCLKEN,
3358 .enable_bit = OMAP3430_EN_SR2_SHIFT,
3359 .idlest_bit = OMAP3430_ST_SR2_SHIFT,
3360 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | WAIT_READY,
3361 .clkdm = { .name = "prm_clkdm" },
3362 .recalc = &followparent_recalc,
3365 static struct clk sr_l4_ick = {
3366 .name = "sr_l4_ick",
3368 .flags = CLOCK_IN_OMAP343X,
3369 .clkdm = { .name = "core_l4_clkdm" },
3370 .recalc = &followparent_recalc,
3373 /* SECURE_32K_FCK clocks */
3375 /* XXX Make sure idlest_bit/wait_ready with no enable_bit works */
3376 static struct clk gpt12_fck = {
3377 .name = "gpt12_fck",
3378 .parent = &secure_32k_fck,
3379 .idlest_bit = OMAP3430_ST_GPT12_SHIFT,
3380 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | WAIT_READY,
3381 .clkdm = { .name = "prm_clkdm" },
3382 .recalc = &followparent_recalc,
3385 static struct clk wdt1_fck = {
3387 .parent = &secure_32k_fck,
3388 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3389 .clkdm = { .name = "prm_clkdm" },
3390 .recalc = &followparent_recalc,
3393 static struct clk *onchip_34xx_clks[] __initdata = {
3421 &omap_96m_alwon_fck,
3487 &ssi_ssr_fck_3430es1,
3488 &ssi_ssr_fck_3430es2,
3489 &ssi_sst_fck_3430es1,
3490 &ssi_sst_fck_3430es2,
3492 &hsotgusb_ick_3430es1,
3493 &hsotgusb_ick_3430es2,
3534 &dss1_alwon_fck_3430es1,
3535 &dss1_alwon_fck_3430es2,