arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk, unsigned long parent_rate,
  31                               u8 rate_storage);
  32 static void omap3_clkoutx2_recalc(struct clk *clk, unsigned long parent_rate,
  33                               u8 rate_storage);
  34 static void omap3_dpll_allow_idle(struct clk *clk);
  35 static void omap3_dpll_deny_idle(struct clk *clk);
  36 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  37 static int omap3_noncore_dpll_enable(struct clk *clk);
  38 static void omap3_noncore_dpll_disable(struct clk *clk);
  39 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  40 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
  41
  42 /* Maximum DPLL multiplier, divider values for OMAP3 */
  43 #define OMAP3_MAX_DPLL_MULT             2048
  44 #define OMAP3_MAX_DPLL_DIV              128
  45
  46 /*
  47  * DPLL1 supplies clock to the MPU.
  48  * DPLL2 supplies clock to the IVA2.
  49  * DPLL3 supplies CORE domain clocks.
  50  * DPLL4 supplies peripheral clocks.
  51  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  52  */
  53
  54 /* Forward declarations for DPLL bypass clocks */
  55 static struct clk dpll1_fck;
  56 static struct clk dpll2_fck;
  57
  58 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  59 #define DPLL_LOW_POWER_STOP             0x1
  60 #define DPLL_LOW_POWER_BYPASS           0x5
  61 #define DPLL_LOCKED                     0x7
  62
  63 /* PRM CLOCKS */
  64
  65 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  66 static struct clk omap_32k_fck = {
  67         .name           = "omap_32k_fck",
  68         .rate           = 32768,
  69         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | ALWAYS_ENABLED,
  70         .clkdm          = { .name = "prm_clkdm" },
  71 };
  72
  73 static struct clk secure_32k_fck = {
  74         .name           = "secure_32k_fck",
  75         .rate           = 32768,
  76         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | ALWAYS_ENABLED,
  77         .clkdm          = { .name = "prm_clkdm" },
  78 };
  79
  80 /* Virtual source clocks for osc_sys_ck */
  81 static struct clk virt_12m_ck = {
  82         .name           = "virt_12m_ck",
  83         .rate           = 12000000,
  84         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | ALWAYS_ENABLED,
  85         .clkdm          = { .name = "prm_clkdm" },
  86 };
  87
  88 static struct clk virt_13m_ck = {
  89         .name           = "virt_13m_ck",
  90         .rate           = 13000000,
  91         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | ALWAYS_ENABLED,
  92         .clkdm          = { .name = "prm_clkdm" },
  93 };
  94
  95 static struct clk virt_16_8m_ck = {
  96         .name           = "virt_16_8m_ck",
  97         .rate           = 16800000,
  98         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | ALWAYS_ENABLED,
  99         .clkdm          = { .name = "prm_clkdm" },
 100 };
 101
 102 static struct clk virt_19_2m_ck = {
 103         .name           = "virt_19_2m_ck",
 104         .rate           = 19200000,
 105         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | ALWAYS_ENABLED,
 106         .clkdm          = { .name = "prm_clkdm" },
 107 };
 108
 109 static struct clk virt_26m_ck = {
 110         .name           = "virt_26m_ck",
 111         .rate           = 26000000,
 112         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | ALWAYS_ENABLED,
 113         .clkdm          = { .name = "prm_clkdm" },
 114 };
 115
 116 static struct clk virt_38_4m_ck = {
 117         .name           = "virt_38_4m_ck",
 118         .rate           = 38400000,
 119         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | ALWAYS_ENABLED,
 120         .clkdm          = { .name = "prm_clkdm" },
 121 };
 122
 123 static const struct clksel_rate osc_sys_12m_rates[] = {
 124         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 125         { .div = 0 }
 126 };
 127
 128 static const struct clksel_rate osc_sys_13m_rates[] = {
 129         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 130         { .div = 0 }
 131 };
 132
 133 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 134         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 135         { .div = 0 }
 136 };
 137
 138 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 139         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 140         { .div = 0 }
 141 };
 142
 143 static const struct clksel_rate osc_sys_26m_rates[] = {
 144         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 145         { .div = 0 }
 146 };
 147
 148 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 149         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 150         { .div = 0 }
 151 };
 152
 153 static const struct clksel osc_sys_clksel[] = {
 154         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 155         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 156         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 157         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 158         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 159         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 160         { .parent = NULL },
 161 };
 162
 163 /* Oscillator clock */
 164 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 165 static struct clk osc_sys_ck = {
 166         .name           = "osc_sys_ck",
 167         .prcm_mod       = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
 168         .init           = &omap2_init_clksel_parent,
 169         .clksel_reg     = OMAP3_PRM_CLKSEL_OFFSET,
 170         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 171         .clksel         = osc_sys_clksel,
 172         /* REVISIT: deal with autoextclkmode? */
 173         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED |
 174                                 ALWAYS_ENABLED,
 175         .clkdm          = { .name = "prm_clkdm" },
 176         .recalc         = &omap2_clksel_recalc,
 177 };
 178
 179 static const struct clksel_rate div2_rates[] = {
 180         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 181         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 182         { .div = 0 }
 183 };
 184
 185 static const struct clksel sys_clksel[] = {
 186         { .parent = &osc_sys_ck, .rates = div2_rates },
 187         { .parent = NULL }
 188 };
 189
 190 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 191 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 192 static struct clk sys_ck = {
 193         .name           = "sys_ck",
 194         .parent         = &osc_sys_ck,
 195         .prcm_mod       = OMAP3430_GR_MOD | CLK_REG_IN_PRM,
 196         .init           = &omap2_init_clksel_parent,
 197         .clksel_reg     = OMAP3_PRM_CLKSRC_CTRL_OFFSET,
 198         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 199         .clksel         = sys_clksel,
 200         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
 201         .clkdm          = { .name = "prm_clkdm" },
 202         .recalc         = &omap2_clksel_recalc,
 203 };
 204
 205 static struct clk sys_altclk = {
 206         .name           = "sys_altclk",
 207         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
 208         .clkdm          = { .name = "cm_clkdm" },
 209 };
 210
 211 /*
 212  * Optional external clock input for some McBSPs
 213  * Apparently this is not really in prm_clkdm, but rather is fed into
 214  * both CORE and PER separately.
 215  */
 216 static struct clk mcbsp_clks = {
 217         .name           = "mcbsp_clks",
 218         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
 219         .clkdm          = { .name = "prm_clkdm" },
 220 };
 221
 222 /* PRM EXTERNAL CLOCK OUTPUT */
 223
 224 static struct clk sys_clkout1 = {
 225         .name           = "sys_clkout1",
 226         .parent         = &osc_sys_ck,
 227         .prcm_mod       = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
 228         .enable_reg     = OMAP3_PRM_CLKOUT_CTRL_OFFSET,
 229         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 230         .flags          = CLOCK_IN_OMAP343X,
 231         .clkdm          = { .name = "prm_clkdm" },
 232         .recalc         = &followparent_recalc,
 233 };
 234
 235 /* DPLLS */
 236
 237 /* CM CLOCKS */
 238
 239 static const struct clksel_rate div16_dpll_rates[] = {
 240         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 241         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 242         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 243         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 244         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 245         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 246         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 247         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 248         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 249         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 250         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 251         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 252         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 253         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 254         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 255         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 256         { .div = 0 }
 257 };
 258
 259 /* DPLL1 */
 260 /* MPU clock source */
 261 /* Type: DPLL */
 262 static struct dpll_data dpll1_dd = {
 263         .mult_div1_reg  = OMAP3430_CM_CLKSEL1_PLL,
 264         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 265         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 266         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 267         .control_reg    = OMAP3430_CM_CLKEN_PLL,
 268         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 269         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 270         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 271         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 272         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 273         .autoidle_reg   = OMAP3430_CM_AUTOIDLE_PLL,
 274         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 275         .idlest_reg     = OMAP3430_CM_IDLEST_PLL,
 276         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
 277         .bypass_clk     = &dpll1_fck,
 278         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 279         .min_divider    = 1,
 280         .max_divider    = OMAP3_MAX_DPLL_DIV,
 281         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 282 };
 283
 284 static struct clk dpll1_ck = {
 285         .name           = "dpll1_ck",
 286         .parent         = &sys_ck,
 287         .prcm_mod       = MPU_MOD,
 288         .dpll_data      = &dpll1_dd,
 289         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | RECALC_ON_ENABLE,
 290         .round_rate     = &omap2_dpll_round_rate,
 291         .set_rate       = &omap3_noncore_dpll_set_rate,
 292         .clkdm          = { .name = "dpll1_clkdm" },
 293         .recalc         = &omap3_dpll_recalc,
 294 };
 295
 296 /*
 297  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 298  * DPLL isn't bypassed.
 299  */
 300 static struct clk dpll1_x2_ck = {
 301         .name           = "dpll1_x2_ck",
 302         .parent         = &dpll1_ck,
 303         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 304         .clkdm          = { .name = "dpll1_clkdm" },
 305         .recalc         = &omap3_clkoutx2_recalc,
 306 };
 307
 308 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 309 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 310         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 311         { .parent = NULL }
 312 };
 313
 314 /*
 315  * Does not exist in the TRM - needed to separate the M2 divider from
 316  * bypass selection in mpu_ck
 317  */
 318 static struct clk dpll1_x2m2_ck = {
 319         .name           = "dpll1_x2m2_ck",
 320         .parent         = &dpll1_x2_ck,
 321         .prcm_mod       = MPU_MOD,
 322         .init           = &omap2_init_clksel_parent,
 323         .clksel_reg     = OMAP3430_CM_CLKSEL2_PLL,
 324         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 325         .clksel         = div16_dpll1_x2m2_clksel,
 326         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 327         .clkdm          = { .name = "dpll1_clkdm" },
 328         .recalc         = &omap2_clksel_recalc,
 329 };
 330
 331 /* DPLL2 */
 332 /* IVA2 clock source */
 333 /* Type: DPLL */
 334
 335 static struct dpll_data dpll2_dd = {
 336         .mult_div1_reg  = OMAP3430_CM_CLKSEL1_PLL,
 337         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 338         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 339         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 340         .control_reg    = OMAP3430_CM_CLKEN_PLL,
 341         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 342         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 343                                 (1 << DPLL_LOW_POWER_BYPASS),
 344         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 345         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 346         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 347         .autoidle_reg   = OMAP3430_CM_AUTOIDLE_PLL,
 348         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 349         .idlest_reg     = OMAP3430_CM_IDLEST_PLL,
 350         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
 351         .bypass_clk     = &dpll2_fck,
 352         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 353         .min_divider    = 1,
 354         .max_divider    = OMAP3_MAX_DPLL_DIV,
 355         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 356 };
 357
 358 static struct clk dpll2_ck = {
 359         .name           = "dpll2_ck",
 360         .parent         = &sys_ck,
 361         .prcm_mod       = OMAP3430_IVA2_MOD,
 362         .dpll_data      = &dpll2_dd,
 363         .flags          = CLOCK_IN_OMAP343X | RECALC_ON_ENABLE,
 364         .enable         = &omap3_noncore_dpll_enable,
 365         .disable        = &omap3_noncore_dpll_disable,
 366         .round_rate     = &omap2_dpll_round_rate,
 367         .set_rate       = &omap3_noncore_dpll_set_rate,
 368         .clkdm          = { .name = "dpll2_clkdm" },
 369         .recalc         = &omap3_dpll_recalc,
 370 };
 371
 372 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 373         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 374         { .parent = NULL }
 375 };
 376
 377 /*
 378  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 379  * or CLKOUTX2. CLKOUT seems most plausible.
 380  */
 381 static struct clk dpll2_m2_ck = {
 382         .name           = "dpll2_m2_ck",
 383         .parent         = &dpll2_ck,
 384         .prcm_mod       = OMAP3430_IVA2_MOD,
 385         .init           = &omap2_init_clksel_parent,
 386         .clksel_reg     = OMAP3430_CM_CLKSEL2_PLL,
 387         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 388         .clksel         = div16_dpll2_m2x2_clksel,
 389         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 390         .clkdm          = { .name = "dpll2_clkdm" },
 391         .recalc         = &omap2_clksel_recalc,
 392 };
 393
 394 /*
 395  * DPLL3
 396  * Source clock for all interfaces and for some device fclks
 397  * REVISIT: Also supports fast relock bypass - not included below
 398  */
 399 static struct dpll_data dpll3_dd = {
 400         .mult_div1_reg  = CM_CLKSEL1,
 401         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 402         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 403         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 404         .control_reg    = CM_CLKEN,
 405         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 406         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 407         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 408         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 409         .autoidle_reg   = CM_AUTOIDLE,
 410         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 411         .idlest_reg     = CM_IDLEST,
 412         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
 413         .bypass_clk     = &sys_ck,
 414         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 415         .min_divider    = 1,
 416         .max_divider    = OMAP3_MAX_DPLL_DIV,
 417         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 418 };
 419
 420 static struct clk dpll3_ck = {
 421         .name           = "dpll3_ck",
 422         .parent         = &sys_ck,
 423         .prcm_mod       = PLL_MOD,
 424         .dpll_data      = &dpll3_dd,
 425         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | RECALC_ON_ENABLE,
 426         .round_rate     = &omap2_dpll_round_rate,
 427         .clkdm          = { .name = "dpll3_clkdm" },
 428         .recalc         = &omap3_dpll_recalc,
 429 };
 430
 431 /*
 432  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 433  * DPLL isn't bypassed
 434  */
 435 static struct clk dpll3_x2_ck = {
 436         .name           = "dpll3_x2_ck",
 437         .parent         = &dpll3_ck,
 438         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 439         .clkdm          = { .name = "dpll3_clkdm" },
 440         .recalc         = &omap3_clkoutx2_recalc,
 441 };
 442
 443 static const struct clksel_rate div31_dpll3_rates[] = {
 444         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 445         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 446         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 447         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 448         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 449         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 450         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 451         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 452         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 453         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 454         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 455         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 456         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 457         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 458         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 459         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 460         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 461         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 462         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 463         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 464         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 465         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 466         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 467         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 468         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 469         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 470         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 471         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 472         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 473         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 474         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 475         { .div = 0 },
 476 };
 477
 478 static const struct clksel div31_dpll3m2_clksel[] = {
 479         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 480         { .parent = NULL }
 481 };
 482
 483 /* DPLL3 output M2 - primary control point for CORE speed */
 484 static struct clk dpll3_m2_ck = {
 485         .name           = "dpll3_m2_ck",
 486         .parent         = &dpll3_ck,
 487         .prcm_mod       = PLL_MOD,
 488         .init           = &omap2_init_clksel_parent,
 489         .clksel_reg     = CM_CLKSEL1,
 490         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 491         .clksel         = div31_dpll3m2_clksel,
 492         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 493         .clkdm          = { .name = "dpll3_clkdm" },
 494         .round_rate     = &omap2_clksel_round_rate,
 495         .set_rate       = &omap3_core_dpll_m2_set_rate,
 496         .recalc         = &omap2_clksel_recalc,
 497 };
 498
 499 static struct clk core_ck = {
 500         .name           = "core_ck",
 501         .parent         = &dpll3_m2_ck,
 502         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 503         .clkdm          = { .name = "cm_clkdm" },
 504         .recalc         = &followparent_recalc,
 505 };
 506
 507 static struct clk dpll3_m2x2_ck = {
 508         .name           = "dpll3_m2x2_ck",
 509         .parent         = &dpll3_x2_ck,
 510         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 511         .clkdm          = { .name = "dpll3_clkdm" },
 512         .recalc         = &followparent_recalc,
 513 };
 514
 515 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 516 static const struct clksel div16_dpll3_clksel[] = {
 517         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 518         { .parent = NULL }
 519 };
 520
 521 /* This virtual clock is the source for dpll3_m3x2_ck */
 522 static struct clk dpll3_m3_ck = {
 523         .name           = "dpll3_m3_ck",
 524         .parent         = &dpll3_ck,
 525         .prcm_mod       = OMAP3430_EMU_MOD,
 526         .init           = &omap2_init_clksel_parent,
 527         .clksel_reg     = CM_CLKSEL1,
 528         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 529         .clksel         = div16_dpll3_clksel,
 530         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 531         .clkdm          = { .name = "dpll3_clkdm" },
 532         .recalc         = &omap2_clksel_recalc,
 533 };
 534
 535 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 536 static struct clk dpll3_m3x2_ck = {
 537         .name           = "dpll3_m3x2_ck",
 538         .parent         = &dpll3_m3_ck,
 539         .prcm_mod       = PLL_MOD,
 540         .enable_reg     = CM_CLKEN,
 541         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 542         .flags          = CLOCK_IN_OMAP343X | INVERT_ENABLE,
 543         .clkdm          = { .name = "dpll3_clkdm" },
 544         .recalc         = &omap3_clkoutx2_recalc,
 545 };
 546
 547 static struct clk emu_core_alwon_ck = {
 548         .name           = "emu_core_alwon_ck",
 549         .parent         = &dpll3_m3x2_ck,
 550         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 551         .clkdm          = { .name = "dpll3_clkdm" },
 552         .recalc         = &followparent_recalc,
 553 };
 554
 555 /* DPLL4 */
 556 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 557 /* Type: DPLL */
 558 static struct dpll_data dpll4_dd = {
 559         .mult_div1_reg  = CM_CLKSEL2,
 560         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 561         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 562         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 563         .control_reg    = CM_CLKEN,
 564         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 565         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 566         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 567         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 568         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 569         .autoidle_reg   = CM_AUTOIDLE,
 570         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 571         .idlest_reg     = CM_IDLEST,
 572         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 573         .bypass_clk     = &sys_ck,
 574         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 575         .min_divider    = 1,
 576         .max_divider    = OMAP3_MAX_DPLL_DIV,
 577         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 578 };
 579
 580 static struct clk dpll4_ck = {
 581         .name           = "dpll4_ck",
 582         .parent         = &sys_ck,
 583         .prcm_mod       = PLL_MOD,
 584         .dpll_data      = &dpll4_dd,
 585         .flags          = CLOCK_IN_OMAP343X | RECALC_ON_ENABLE,
 586         .enable         = &omap3_noncore_dpll_enable,
 587         .disable        = &omap3_noncore_dpll_disable,
 588         .round_rate     = &omap2_dpll_round_rate,
 589         .set_rate       = &omap3_noncore_dpll_set_rate,
 590         .clkdm          = { .name = "dpll4_clkdm" },
 591         .recalc         = &omap3_dpll_recalc,
 592 };
 593
 594 /*
 595  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 596  * DPLL isn't bypassed --
 597  * XXX does this serve any downstream clocks?
 598  */
 599 static struct clk dpll4_x2_ck = {
 600         .name           = "dpll4_x2_ck",
 601         .parent         = &dpll4_ck,
 602         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 603         .clkdm          = { .name = "dpll4_clkdm" },
 604         .recalc         = &omap3_clkoutx2_recalc,
 605 };
 606
 607 static const struct clksel div16_dpll4_clksel[] = {
 608         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 609         { .parent = NULL }
 610 };
 611
 612 /* This virtual clock is the source for dpll4_m2x2_ck */
 613 static struct clk dpll4_m2_ck = {
 614         .name           = "dpll4_m2_ck",
 615         .parent         = &dpll4_ck,
 616         .prcm_mod       = PLL_MOD,
 617         .init           = &omap2_init_clksel_parent,
 618         .clksel_reg     = OMAP3430_CM_CLKSEL3,
 619         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 620         .clksel         = div16_dpll4_clksel,
 621         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 622         .clkdm          = { .name = "dpll4_clkdm" },
 623         .recalc         = &omap2_clksel_recalc,
 624 };
 625
 626 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 627 static struct clk dpll4_m2x2_ck = {
 628         .name           = "dpll4_m2x2_ck",
 629         .parent         = &dpll4_m2_ck,
 630         .prcm_mod       = PLL_MOD,
 631         .enable_reg     = CM_CLKEN,
 632         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 633         .flags          = CLOCK_IN_OMAP343X | INVERT_ENABLE,
 634         .clkdm          = { .name = "dpll4_clkdm" },
 635         .recalc         = &omap3_clkoutx2_recalc,
 636 };
 637
 638 /*
 639  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 640  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 641  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 642  * CM_96K_(F)CLK.
 643  */
 644 static struct clk omap_96m_alwon_fck = {
 645         .name           = "omap_96m_alwon_fck",
 646         .parent         = &dpll4_m2x2_ck,
 647         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 648         .clkdm          = { .name = "prm_clkdm" },
 649         .recalc         = &followparent_recalc,
 650 };
 651
 652 static struct clk cm_96m_fck = {
 653         .name           = "cm_96m_fck",
 654         .parent         = &omap_96m_alwon_fck,
 655         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 656         .clkdm          = { .name = "cm_clkdm" },
 657         .recalc         = &followparent_recalc,
 658 };
 659
 660 static const struct clksel_rate omap_96m_dpll_rates[] = {
 661         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 662         { .div = 0 }
 663 };
 664
 665 static const struct clksel_rate omap_96m_sys_rates[] = {
 666         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 667         { .div = 0 }
 668 };
 669
 670 static const struct clksel omap_96m_fck_clksel[] = {
 671         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 672         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 673         { .parent = NULL }
 674 };
 675
 676 static struct clk omap_96m_fck = {
 677         .name           = "omap_96m_fck",
 678         .parent         = &sys_ck,
 679         .prcm_mod       = PLL_MOD,
 680         .init           = &omap2_init_clksel_parent,
 681         .clksel_reg     = CM_CLKSEL1,
 682         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 683         .clksel         = omap_96m_fck_clksel,
 684         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 685         .clkdm          = { .name = "cm_clkdm" },
 686         .recalc         = &omap2_clksel_recalc,
 687 };
 688
 689 /* This virtual clock is the source for dpll4_m3x2_ck */
 690 static struct clk dpll4_m3_ck = {
 691         .name           = "dpll4_m3_ck",
 692         .parent         = &dpll4_ck,
 693         .prcm_mod       = OMAP3430_DSS_MOD,
 694         .init           = &omap2_init_clksel_parent,
 695         .clksel_reg     = CM_CLKSEL,
 696         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 697         .clksel         = div16_dpll4_clksel,
 698         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 699         .clkdm          = { .name = "dpll4_clkdm" },
 700         .recalc         = &omap2_clksel_recalc,
 701 };
 702
 703 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 704 static struct clk dpll4_m3x2_ck = {
 705         .name           = "dpll4_m3x2_ck",
 706         .parent         = &dpll4_m3_ck,
 707         .prcm_mod       = PLL_MOD,
 708         .init           = &omap2_init_clksel_parent,
 709         .enable_reg     = CM_CLKEN,
 710         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 711         .flags          = CLOCK_IN_OMAP343X | INVERT_ENABLE,
 712         .clkdm          = { .name = "dpll4_clkdm" },
 713         .recalc         = &omap3_clkoutx2_recalc,
 714 };
 715
 716 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 717         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 718         { .div = 0 }
 719 };
 720
 721 static const struct clksel_rate omap_54m_alt_rates[] = {
 722         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 723         { .div = 0 }
 724 };
 725
 726 static const struct clksel omap_54m_clksel[] = {
 727         { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
 728         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 729         { .parent = NULL }
 730 };
 731
 732 static struct clk omap_54m_fck = {
 733         .name           = "omap_54m_fck",
 734         .prcm_mod       = PLL_MOD,
 735         .init           = &omap2_init_clksel_parent,
 736         .clksel_reg     = CM_CLKSEL1,
 737         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 738         .clksel         = omap_54m_clksel,
 739         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 740         .clkdm          = { .name = "cm_clkdm" },
 741         .recalc         = &omap2_clksel_recalc,
 742 };
 743
 744 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 745         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 746         { .div = 0 }
 747 };
 748
 749 static const struct clksel_rate omap_48m_alt_rates[] = {
 750         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 751         { .div = 0 }
 752 };
 753
 754 static const struct clksel omap_48m_clksel[] = {
 755         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 756         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 757         { .parent = NULL }
 758 };
 759
 760 static struct clk omap_48m_fck = {
 761         .name           = "omap_48m_fck",
 762         .prcm_mod       = PLL_MOD,
 763         .init           = &omap2_init_clksel_parent,
 764         .clksel_reg     = CM_CLKSEL1,
 765         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 766         .clksel         = omap_48m_clksel,
 767         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 768         .clkdm          = { .name = "cm_clkdm" },
 769         .recalc         = &omap2_clksel_recalc,
 770 };
 771
 772 static struct clk omap_12m_fck = {
 773         .name           = "omap_12m_fck",
 774         .parent         = &omap_48m_fck,
 775         .fixed_div      = 4,
 776         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 777         .clkdm          = { .name = "cm_clkdm" },
 778         .recalc         = &omap2_fixed_divisor_recalc,
 779 };
 780
 781 /* This virstual clock is the source for dpll4_m4x2_ck */
 782 static struct clk dpll4_m4_ck = {
 783         .name           = "dpll4_m4_ck",
 784         .parent         = &dpll4_ck,
 785         .prcm_mod       = OMAP3430_DSS_MOD,
 786         .init           = &omap2_init_clksel_parent,
 787         .clksel_reg     = CM_CLKSEL,
 788         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 789         .clksel         = div16_dpll4_clksel,
 790         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 791         .clkdm          = { .name = "dpll4_clkdm" },
 792         .recalc         = &omap2_clksel_recalc,
 793         .set_rate       = &omap2_clksel_set_rate,
 794         .round_rate     = &omap2_clksel_round_rate,
 795 };
 796
 797 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 798 static struct clk dpll4_m4x2_ck = {
 799         .name           = "dpll4_m4x2_ck",
 800         .parent         = &dpll4_m4_ck,
 801         .prcm_mod       = PLL_MOD,
 802         .enable_reg     = CM_CLKEN,
 803         .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
 804         .flags          = CLOCK_IN_OMAP343X | INVERT_ENABLE,
 805         .clkdm          = { .name = "dpll4_clkdm" },
 806         .recalc         = &omap3_clkoutx2_recalc,
 807 };
 808
 809 /* This virtual clock is the source for dpll4_m5x2_ck */
 810 static struct clk dpll4_m5_ck = {
 811         .name           = "dpll4_m5_ck",
 812         .parent         = &dpll4_ck,
 813         .prcm_mod       = OMAP3430_CAM_MOD,
 814         .init           = &omap2_init_clksel_parent,
 815         .clksel_reg     = CM_CLKSEL,
 816         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 817         .clksel         = div16_dpll4_clksel,
 818         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 819         .clkdm          = { .name = "dpll4_clkdm" },
 820         .recalc         = &omap2_clksel_recalc,
 821 };
 822
 823 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 824 static struct clk dpll4_m5x2_ck = {
 825         .name           = "dpll4_m5x2_ck",
 826         .parent         = &dpll4_m5_ck,
 827         .prcm_mod       = PLL_MOD,
 828         .enable_reg     = CM_CLKEN,
 829         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 830         .flags          = CLOCK_IN_OMAP343X | INVERT_ENABLE,
 831         .clkdm          = { .name = "dpll4_clkdm" },
 832         .recalc         = &omap3_clkoutx2_recalc,
 833 };
 834
 835 /* This virtual clock is the source for dpll4_m6x2_ck */
 836 static struct clk dpll4_m6_ck = {
 837         .name           = "dpll4_m6_ck",
 838         .parent         = &dpll4_ck,
 839         .prcm_mod       = OMAP3430_EMU_MOD,
 840         .init           = &omap2_init_clksel_parent,
 841         .clksel_reg     = CM_CLKSEL1,
 842         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 843         .clksel         = div16_dpll4_clksel,
 844         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 845         .clkdm          = { .name = "dpll4_clkdm" },
 846         .recalc         = &omap2_clksel_recalc,
 847 };
 848
 849 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 850 static struct clk dpll4_m6x2_ck = {
 851         .name           = "dpll4_m6x2_ck",
 852         .parent         = &dpll4_m6_ck,
 853         .prcm_mod       = PLL_MOD,
 854         .init           = &omap2_init_clksel_parent,
 855         .enable_reg     = CM_CLKEN,
 856         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 857         .flags          = CLOCK_IN_OMAP343X | INVERT_ENABLE,
 858         .clkdm          = { .name = "dpll4_clkdm" },
 859         .recalc         = &omap3_clkoutx2_recalc,
 860 };
 861
 862 static struct clk emu_per_alwon_ck = {
 863         .name           = "emu_per_alwon_ck",
 864         .parent         = &dpll4_m6x2_ck,
 865         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 866         .clkdm          = { .name = "dpll4_clkdm" },
 867         .recalc         = &followparent_recalc,
 868 };
 869
 870 /* DPLL5 */
 871 /* Supplies 120MHz clock, USIM source clock */
 872 /* Type: DPLL */
 873 /* 3430ES2 only */
 874 static struct dpll_data dpll5_dd = {
 875         .mult_div1_reg  = OMAP3430ES2_CM_CLKSEL4,
 876         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 877         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 878         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 879         .control_reg    = OMAP3430ES2_CM_CLKEN2,
 880         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 881         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 882         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 883         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 884         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 885         .autoidle_reg   = OMAP3430ES2_CM_AUTOIDLE2_PLL,
 886         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 887         .idlest_reg     = CM_IDLEST2,
 888         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 889         .bypass_clk     = &sys_ck,
 890         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 891         .min_divider    = 1,
 892         .max_divider    = OMAP3_MAX_DPLL_DIV,
 893         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 894 };
 895
 896 static struct clk dpll5_ck = {
 897         .name           = "dpll5_ck",
 898         .parent         = &sys_ck,
 899         .prcm_mod       = PLL_MOD,
 900         .dpll_data      = &dpll5_dd,
 901         .flags          = CLOCK_IN_OMAP3430ES2 | RECALC_ON_ENABLE,
 902         .enable         = &omap3_noncore_dpll_enable,
 903         .disable        = &omap3_noncore_dpll_disable,
 904         .round_rate     = &omap2_dpll_round_rate,
 905         .set_rate       = &omap3_noncore_dpll_set_rate,
 906         .clkdm          = { .name = "dpll5_clkdm" },
 907         .recalc         = &omap3_dpll_recalc,
 908 };
 909
 910 static const struct clksel div16_dpll5_clksel[] = {
 911         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 912         { .parent = NULL }
 913 };
 914
 915 static struct clk dpll5_m2_ck = {
 916         .name           = "dpll5_m2_ck",
 917         .parent         = &dpll5_ck,
 918         .prcm_mod       = PLL_MOD,
 919         .init           = &omap2_init_clksel_parent,
 920         .clksel_reg     = OMAP3430ES2_CM_CLKSEL5,
 921         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 922         .clksel         = div16_dpll5_clksel,
 923         .flags          = CLOCK_IN_OMAP3430ES2 | PARENT_CONTROLS_CLOCK,
 924         .clkdm          = { .name = "dpll5_clkdm" },
 925         .recalc         = &omap2_clksel_recalc,
 926 };
 927
 928 /* CM EXTERNAL CLOCK OUTPUTS */
 929
 930 static const struct clksel_rate clkout2_src_core_rates[] = {
 931         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 932         { .div = 0 }
 933 };
 934
 935 static const struct clksel_rate clkout2_src_sys_rates[] = {
 936         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 937         { .div = 0 }
 938 };
 939
 940 static const struct clksel_rate clkout2_src_96m_rates[] = {
 941         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 942         { .div = 0 }
 943 };
 944
 945 static const struct clksel_rate clkout2_src_54m_rates[] = {
 946         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 947         { .div = 0 }
 948 };
 949
 950 static const struct clksel clkout2_src_clksel[] = {
 951         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
 952         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
 953         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
 954         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
 955         { .parent = NULL }
 956 };
 957
 958 static struct clk clkout2_src_ck = {
 959         .name           = "clkout2_src_ck",
 960         .prcm_mod       = OMAP3430_CCR_MOD,
 961         .init           = &omap2_init_clksel_parent,
 962         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
 963         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 964         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
 965         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 966         .clksel         = clkout2_src_clksel,
 967         .flags          = CLOCK_IN_OMAP343X,
 968         .clkdm          = { .name = "cm_clkdm" },
 969         .recalc         = &omap2_clksel_recalc,
 970 };
 971
 972 static const struct clksel_rate sys_clkout2_rates[] = {
 973         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 974         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 975         { .div = 4, .val = 2, .flags = RATE_IN_343X },
 976         { .div = 8, .val = 3, .flags = RATE_IN_343X },
 977         { .div = 16, .val = 4, .flags = RATE_IN_343X },
 978         { .div = 0 },
 979 };
 980
 981 static const struct clksel sys_clkout2_clksel[] = {
 982         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
 983         { .parent = NULL },
 984 };
 985
 986 static struct clk sys_clkout2 = {
 987         .name           = "sys_clkout2",
 988         .prcm_mod       = OMAP3430_CCR_MOD,
 989         .init           = &omap2_init_clksel_parent,
 990         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
 991         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
 992         .clksel         = sys_clkout2_clksel,
 993         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 994         .clkdm          = { .name = "cm_clkdm" },
 995         .recalc         = &omap2_clksel_recalc,
 996 };
 997
 998 /* CM OUTPUT CLOCKS */
 999
1000 static struct clk corex2_fck = {
1001         .name           = "corex2_fck",
1002         .parent         = &dpll3_m2x2_ck,
1003         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1004         .clkdm          = { .name = "cm_clkdm" },
1005         .recalc         = &followparent_recalc,
1006 };
1007
1008 /* DPLL power domain clock controls */
1009
1010 static const struct clksel_rate div4_rates[] = {
1011         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1012         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1013         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1014         { .div = 0 }
1015 };
1016
1017 static const struct clksel div4_core_clksel[] = {
1018         { .parent = &core_ck, .rates = div4_rates },
1019         { .parent = NULL }
1020 };
1021
1022 static struct clk dpll1_fck = {
1023         .name           = "dpll1_fck",
1024         .parent         = &core_ck,
1025         .prcm_mod       = MPU_MOD,
1026         .init           = &omap2_init_clksel_parent,
1027         .clksel_reg     = OMAP3430_CM_CLKSEL1_PLL,
1028         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1029         .clksel         = div4_core_clksel,
1030         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1031         .clkdm          = { .name = "cm_clkdm" },
1032         .recalc         = &omap2_clksel_recalc,
1033 };
1034
1035 static struct clk mpu_ck = {
1036         .name           = "mpu_ck",
1037         .parent         = &dpll1_x2m2_ck,
1038         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1039         .clkdm          = { .name = "mpu_clkdm" },
1040         .recalc         = &followparent_recalc,
1041 };
1042
1043 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1044 static const struct clksel_rate arm_fck_rates[] = {
1045         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1046         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1047         { .div = 0 },
1048 };
1049
1050 static const struct clksel arm_fck_clksel[] = {
1051         { .parent = &mpu_ck, .rates = arm_fck_rates },
1052         { .parent = NULL }
1053 };
1054
1055 static struct clk arm_fck = {
1056         .name           = "arm_fck",
1057         .parent         = &mpu_ck,
1058         .prcm_mod       = MPU_MOD,
1059         .init           = &omap2_init_clksel_parent,
1060         .clksel_reg     = OMAP3430_CM_IDLEST_PLL,
1061         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1062         .clksel         = arm_fck_clksel,
1063         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1064         .clkdm          = { .name = "mpu_clkdm" },
1065         .recalc         = &omap2_clksel_recalc,
1066 };
1067
1068 /* XXX What about neon_clkdm ? */
1069
1070 /*
1071  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1072  * although it is referenced - so this is a guess
1073  */
1074 static struct clk emu_mpu_alwon_ck = {
1075         .name           = "emu_mpu_alwon_ck",
1076         .parent         = &mpu_ck,
1077         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1078         .clkdm          = { .name = "mpu_clkdm" },
1079         .recalc         = &followparent_recalc,
1080 };
1081
1082 static struct clk dpll2_fck = {
1083         .name           = "dpll2_fck",
1084         .parent         = &core_ck,
1085         .prcm_mod       = OMAP3430_IVA2_MOD,
1086         .init           = &omap2_init_clksel_parent,
1087         .clksel_reg     = OMAP3430_CM_CLKSEL1_PLL,
1088         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1089         .clksel         = div4_core_clksel,
1090         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1091         .clkdm          = { .name = "cm_clkdm" },
1092         .recalc         = &omap2_clksel_recalc,
1093 };
1094
1095 static struct clk iva2_ck = {
1096         .name           = "iva2_ck",
1097         .parent         = &dpll2_m2_ck,
1098         .prcm_mod       = OMAP3430_IVA2_MOD,
1099         .init           = &omap2_init_clksel_parent,
1100         .enable_reg     = CM_FCLKEN,
1101         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1102         .flags          = CLOCK_IN_OMAP343X,
1103         .clkdm          = { .name = "iva2_clkdm" },
1104         .recalc         = &followparent_recalc,
1105 };
1106
1107 /* Common interface clocks */
1108
1109 static const struct clksel div2_core_clksel[] = {
1110         { .parent = &core_ck, .rates = div2_rates },
1111         { .parent = NULL }
1112 };
1113
1114 static struct clk l3_ick = {
1115         .name           = "l3_ick",
1116         .parent         = &core_ck,
1117         .prcm_mod       = CORE_MOD,
1118         .init           = &omap2_init_clksel_parent,
1119         .clksel_reg     = CM_CLKSEL,
1120         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1121         .clksel         = div2_core_clksel,
1122         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1123         .clkdm          = { .name = "core_l3_clkdm" },
1124         .recalc         = &omap2_clksel_recalc,
1125 };
1126
1127 static const struct clksel div2_l3_clksel[] = {
1128         { .parent = &l3_ick, .rates = div2_rates },
1129         { .parent = NULL }
1130 };
1131
1132 static struct clk l4_ick = {
1133         .name           = "l4_ick",
1134         .parent         = &l3_ick,
1135         .prcm_mod       = CORE_MOD,
1136         .init           = &omap2_init_clksel_parent,
1137         .clksel_reg     = CM_CLKSEL,
1138         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1139         .clksel         = div2_l3_clksel,
1140         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1141         .clkdm          = { .name = "core_l4_clkdm" },
1142         .recalc         = &omap2_clksel_recalc,
1143
1144 };
1145
1146 static const struct clksel div2_l4_clksel[] = {
1147         { .parent = &l4_ick, .rates = div2_rates },
1148         { .parent = NULL }
1149 };
1150
1151 static struct clk rm_ick = {
1152         .name           = "rm_ick",
1153         .parent         = &l4_ick,
1154         .prcm_mod       = WKUP_MOD,
1155         .init           = &omap2_init_clksel_parent,
1156         .clksel_reg     = CM_CLKSEL,
1157         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1158         .clksel         = div2_l4_clksel,
1159         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1160         .clkdm          = { .name = "cm_clkdm" },
1161         .recalc         = &omap2_clksel_recalc,
1162 };
1163
1164 /* GFX power domain */
1165
1166 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1167
1168 static const struct clksel gfx_l3_clksel[] = {
1169         { .parent = &l3_ick, .rates = gfx_l3_rates },
1170         { .parent = NULL }
1171 };
1172
1173 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1174 static struct clk gfx_l3_ck = {
1175         .name           = "gfx_l3_ck",
1176         .parent         = &l3_ick,
1177         .prcm_mod       = GFX_MOD,
1178         .init           = &omap2_init_clksel_parent,
1179         .enable_reg     = CM_ICLKEN,
1180         .enable_bit     = OMAP_EN_GFX_SHIFT,
1181         .flags          = CLOCK_IN_OMAP3430ES1,
1182         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1183         .recalc         = &followparent_recalc,
1184 };
1185
1186 static struct clk gfx_l3_fck = {
1187         .name           = "gfx_l3_fck",
1188         .parent         = &gfx_l3_ck,
1189         .prcm_mod       = GFX_MOD,
1190         .init           = &omap2_init_clksel_parent,
1191         .clksel_reg     = CM_CLKSEL,
1192         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1193         .clksel         = gfx_l3_clksel,
1194         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1195         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1196         .recalc         = &omap2_clksel_recalc,
1197 };
1198
1199 static struct clk gfx_l3_ick = {
1200         .name           = "gfx_l3_ick",
1201         .parent         = &gfx_l3_ck,
1202         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1203         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1204         .recalc         = &followparent_recalc,
1205 };
1206
1207 static struct clk gfx_cg1_ck = {
1208         .name           = "gfx_cg1_ck",
1209         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1210         .prcm_mod       = GFX_MOD,
1211         .enable_reg     = CM_FCLKEN,
1212         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1213         .flags          = CLOCK_IN_OMAP3430ES1,
1214         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1215         .recalc         = &followparent_recalc,
1216 };
1217
1218 static struct clk gfx_cg2_ck = {
1219         .name           = "gfx_cg2_ck",
1220         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1221         .prcm_mod       = GFX_MOD,
1222         .enable_reg     = CM_FCLKEN,
1223         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1224         .flags          = CLOCK_IN_OMAP3430ES1,
1225         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1226         .recalc         = &followparent_recalc,
1227 };
1228
1229 /* SGX power domain - 3430ES2 only */
1230
1231 static const struct clksel_rate sgx_core_rates[] = {
1232         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1233         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1234         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1235         { .div = 0 },
1236 };
1237
1238 static const struct clksel_rate sgx_96m_rates[] = {
1239         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1240         { .div = 0 },
1241 };
1242
1243 static const struct clksel sgx_clksel[] = {
1244         { .parent = &core_ck,    .rates = sgx_core_rates },
1245         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1246         { .parent = NULL },
1247 };
1248
1249 static struct clk sgx_fck = {
1250         .name           = "sgx_fck",
1251         .init           = &omap2_init_clksel_parent,
1252         .prcm_mod       = OMAP3430ES2_SGX_MOD,
1253         .enable_reg     = CM_FCLKEN,
1254         .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1255         .clksel_reg     = CM_CLKSEL,
1256         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1257         .clksel         = sgx_clksel,
1258         .flags          = CLOCK_IN_OMAP3430ES2,
1259         .clkdm          = { .name = "sgx_clkdm" },
1260         .recalc         = &omap2_clksel_recalc,
1261 };
1262
1263 static struct clk sgx_ick = {
1264         .name           = "sgx_ick",
1265         .parent         = &l3_ick,
1266         .prcm_mod       = OMAP3430ES2_SGX_MOD,
1267         .enable_reg     = CM_ICLKEN,
1268         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1269         .flags          = CLOCK_IN_OMAP3430ES2,
1270         .clkdm          = { .name = "sgx_clkdm" },
1271         .recalc         = &followparent_recalc,
1272 };
1273
1274 /* CORE power domain */
1275
1276 static struct clk d2d_26m_fck = {
1277         .name           = "d2d_26m_fck",
1278         .parent         = &sys_ck,
1279         .prcm_mod       = CORE_MOD,
1280         .enable_reg     = CM_FCLKEN1,
1281         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1282         .flags          = CLOCK_IN_OMAP3430ES1,
1283         .clkdm          = { .name = "d2d_clkdm" },
1284         .recalc         = &followparent_recalc,
1285 };
1286
1287 static const struct clksel omap343x_gpt_clksel[] = {
1288         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1289         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1290         { .parent = NULL}
1291 };
1292
1293 static struct clk gpt10_fck = {
1294         .name           = "gpt10_fck",
1295         .parent         = &sys_ck,
1296         .prcm_mod       = CORE_MOD,
1297         .init           = &omap2_init_clksel_parent,
1298         .enable_reg     = CM_FCLKEN1,
1299         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1300         .idlest_bit     = OMAP3430_ST_GPT10_SHIFT,
1301         .clksel_reg     = CM_CLKSEL,
1302         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1303         .clksel         = omap343x_gpt_clksel,
1304         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1305         .clkdm          = { .name = "core_l4_clkdm" },
1306         .recalc         = &omap2_clksel_recalc,
1307 };
1308
1309 static struct clk gpt11_fck = {
1310         .name           = "gpt11_fck",
1311         .parent         = &sys_ck,
1312         .prcm_mod       = CORE_MOD,
1313         .init           = &omap2_init_clksel_parent,
1314         .enable_reg     = CM_FCLKEN1,
1315         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1316         .idlest_bit     = OMAP3430_ST_GPT11_SHIFT,
1317         .clksel_reg     = CM_CLKSEL,
1318         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1319         .clksel         = omap343x_gpt_clksel,
1320         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1321         .clkdm          = { .name = "core_l4_clkdm" },
1322         .recalc         = &omap2_clksel_recalc,
1323 };
1324
1325 static struct clk cpefuse_fck = {
1326         .name           = "cpefuse_fck",
1327         .parent         = &sys_ck,
1328         .prcm_mod       = CORE_MOD,
1329         .enable_reg     = OMAP3430ES2_CM_FCLKEN3,
1330         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1331         .idlest_bit     = OMAP3430ES2_ST_CPEFUSE_SHIFT,
1332         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1333         .clkdm          = { .name = "cm_clkdm" },
1334         .recalc         = &followparent_recalc,
1335 };
1336
1337 static struct clk ts_fck = {
1338         .name           = "ts_fck",
1339         .parent         = &omap_32k_fck,
1340         .prcm_mod       = CORE_MOD,
1341         .enable_reg     = OMAP3430ES2_CM_FCLKEN3,
1342         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1343         .flags          = CLOCK_IN_OMAP3430ES2,
1344         .clkdm          = { .name = "core_l4_clkdm" },
1345         .recalc         = &followparent_recalc,
1346 };
1347
1348 static struct clk usbtll_fck = {
1349         .name           = "usbtll_fck",
1350         .parent         = &dpll5_m2_ck,
1351         .prcm_mod       = CORE_MOD,
1352         .enable_reg     = OMAP3430ES2_CM_FCLKEN3,
1353         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1354         .idlest_bit     = OMAP3430ES2_ST_USBTLL_SHIFT,
1355         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1356         .clkdm          = { .name = "core_l4_clkdm" },
1357         .recalc         = &followparent_recalc,
1358 };
1359
1360 /* CORE 96M FCLK-derived clocks */
1361
1362 static struct clk core_96m_fck = {
1363         .name           = "core_96m_fck",
1364         .parent         = &omap_96m_fck,
1365         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1366         .clkdm          = { .name = "core_l4_clkdm" },
1367         .recalc         = &followparent_recalc,
1368 };
1369
1370 static struct clk mmchs3_fck = {
1371         .name           = "mmchs_fck",
1372         .id             = 2,
1373         .parent         = &core_96m_fck,
1374         .prcm_mod       = CORE_MOD,
1375         .enable_reg     = CM_FCLKEN1,
1376         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1377         .idlest_bit     = OMAP3430ES2_ST_MMC3_SHIFT,
1378         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1379         .clkdm          = { .name = "core_l4_clkdm" },
1380         .recalc         = &followparent_recalc,
1381 };
1382
1383 static struct clk mmchs2_fck = {
1384         .name           = "mmchs_fck",
1385         .id             = 1,
1386         .parent         = &core_96m_fck,
1387         .prcm_mod       = CORE_MOD,
1388         .enable_reg     = CM_FCLKEN1,
1389         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1390         .idlest_bit     = OMAP3430_ST_MMC2_SHIFT,
1391         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1392         .clkdm          = { .name = "core_l4_clkdm" },
1393         .recalc         = &followparent_recalc,
1394 };
1395
1396 static struct clk mspro_fck = {
1397         .name           = "mspro_fck",
1398         .parent         = &core_96m_fck,
1399         .prcm_mod       = CORE_MOD,
1400         .enable_reg     = CM_FCLKEN1,
1401         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1402         .idlest_bit     = OMAP3430_ST_MSPRO_SHIFT,
1403         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1404         .clkdm          = { .name = "core_l4_clkdm" },
1405         .recalc         = &followparent_recalc,
1406 };
1407
1408 static struct clk mmchs1_fck = {
1409         .name           = "mmchs_fck",
1410         .parent         = &core_96m_fck,
1411         .prcm_mod       = CORE_MOD,
1412         .enable_reg     = CM_FCLKEN1,
1413         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1414         .idlest_bit     = OMAP3430_ST_MMC1_SHIFT,
1415         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1416         .clkdm          = { .name = "core_l4_clkdm" },
1417         .recalc         = &followparent_recalc,
1418 };
1419
1420 static struct clk i2c3_fck = {
1421         .name           = "i2c_fck",
1422         .id             = 3,
1423         .parent         = &core_96m_fck,
1424         .prcm_mod       = CORE_MOD,
1425         .enable_reg     = CM_FCLKEN1,
1426         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1427         .idlest_bit     = OMAP3430_ST_I2C3_SHIFT,
1428         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1429         .clkdm          = { .name = "core_l4_clkdm" },
1430         .recalc         = &followparent_recalc,
1431 };
1432
1433 static struct clk i2c2_fck = {
1434         .name           = "i2c_fck",
1435         .id             = 2,
1436         .parent         = &core_96m_fck,
1437         .prcm_mod       = CORE_MOD,
1438         .enable_reg     = CM_FCLKEN1,
1439         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1440         .idlest_bit     = OMAP3430_ST_I2C2_SHIFT,
1441         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1442         .clkdm          = { .name = "core_l4_clkdm" },
1443         .recalc         = &followparent_recalc,
1444 };
1445
1446 static struct clk i2c1_fck = {
1447         .name           = "i2c_fck",
1448         .id             = 1,
1449         .parent         = &core_96m_fck,
1450         .prcm_mod       = CORE_MOD,
1451         .enable_reg     = CM_FCLKEN1,
1452         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1453         .idlest_bit     = OMAP3430_ST_I2C1_SHIFT,
1454         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1455         .clkdm          = { .name = "core_l4_clkdm" },
1456         .recalc         = &followparent_recalc,
1457 };
1458
1459 /*
1460  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1461  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1462  */
1463 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1464         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1465         { .div = 0 }
1466 };
1467
1468 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1469         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1470         { .div = 0 }
1471 };
1472
1473 static const struct clksel mcbsp_15_clksel[] = {
1474         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1475         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1476         { .parent = NULL }
1477 };
1478
1479 static struct clk mcbsp5_src_fck = {
1480         .name           = "mcbsp_src_fck",
1481         .id             = 5,
1482         .prcm_mod       = CLK_REG_IN_SCM,
1483         .init           = &omap2_init_clksel_parent,
1484         .clksel_reg     = OMAP343X_CONTROL_DEVCONF1,
1485         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1486         .clksel         = mcbsp_15_clksel,
1487         .flags          = CLOCK_IN_OMAP343X,
1488         .clkdm          = { .name = "core_l4_clkdm" },
1489         .recalc         = &omap2_clksel_recalc,
1490 };
1491
1492 static struct clk mcbsp5_fck = {
1493         .name           = "mcbsp_fck",
1494         .id             = 5,
1495         .parent         = &mcbsp5_src_fck,
1496         .prcm_mod       = CORE_MOD,
1497         .enable_reg     = CM_FCLKEN1,
1498         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1499         .idlest_bit     = OMAP3430_ST_MCBSP5_SHIFT,
1500         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1501         .clkdm          = { .name = "core_l4_clkdm" },
1502         .recalc         = &followparent_recalc,
1503 };
1504
1505 static struct clk mcbsp1_src_fck = {
1506         .name           = "mcbsp_src_fck",
1507         .id             = 1,
1508         .prcm_mod       = CLK_REG_IN_SCM,
1509         .init           = &omap2_init_clksel_parent,
1510         .clksel_reg     = OMAP2_CONTROL_DEVCONF0,
1511         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1512         .clksel         = mcbsp_15_clksel,
1513         .flags          = CLOCK_IN_OMAP343X,
1514         .clkdm          = { .name = "core_l4_clkdm" },
1515         .recalc         = &omap2_clksel_recalc,
1516 };
1517
1518 static struct clk mcbsp1_fck = {
1519         .name           = "mcbsp_fck",
1520         .id             = 1,
1521         .parent         = &mcbsp1_src_fck,
1522         .prcm_mod       = CORE_MOD,
1523         .enable_reg     = CM_FCLKEN1,
1524         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1525         .idlest_bit     = OMAP3430_ST_MCBSP1_SHIFT,
1526         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1527         .clkdm          = { .name = "core_l4_clkdm" },
1528         .recalc         = &followparent_recalc,
1529 };
1530
1531 /* CORE_48M_FCK-derived clocks */
1532
1533 static struct clk core_48m_fck = {
1534         .name           = "core_48m_fck",
1535         .parent         = &omap_48m_fck,
1536         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1537         .clkdm          = { .name = "core_l4_clkdm" },
1538         .recalc         = &followparent_recalc,
1539 };
1540
1541 static struct clk mcspi4_fck = {
1542         .name           = "mcspi_fck",
1543         .id             = 4,
1544         .parent         = &core_48m_fck,
1545         .prcm_mod       = CORE_MOD,
1546         .enable_reg     = CM_FCLKEN1,
1547         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1548         .idlest_bit     = OMAP3430_ST_MCSPI4_SHIFT,
1549         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1550         .clkdm          = { .name = "core_l4_clkdm" },
1551         .recalc         = &followparent_recalc,
1552 };
1553
1554 static struct clk mcspi3_fck = {
1555         .name           = "mcspi_fck",
1556         .id             = 3,
1557         .parent         = &core_48m_fck,
1558         .prcm_mod       = CORE_MOD,
1559         .enable_reg     = CM_FCLKEN1,
1560         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1561         .idlest_bit     = OMAP3430_ST_MCSPI3_SHIFT,
1562         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1563         .clkdm          = { .name = "core_l4_clkdm" },
1564         .recalc         = &followparent_recalc,
1565 };
1566
1567 static struct clk mcspi2_fck = {
1568         .name           = "mcspi_fck",
1569         .id             = 2,
1570         .parent         = &core_48m_fck,
1571         .prcm_mod       = CORE_MOD,
1572         .enable_reg     = CM_FCLKEN1,
1573         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1574         .idlest_bit     = OMAP3430_ST_MCSPI2_SHIFT,
1575         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1576         .clkdm          = { .name = "core_l4_clkdm" },
1577         .recalc         = &followparent_recalc,
1578 };
1579
1580 static struct clk mcspi1_fck = {
1581         .name           = "mcspi_fck",
1582         .id             = 1,
1583         .parent         = &core_48m_fck,
1584         .prcm_mod       = CORE_MOD,
1585         .enable_reg     = CM_FCLKEN1,
1586         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1587         .idlest_bit     = OMAP3430_ST_MCSPI1_SHIFT,
1588         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1589         .clkdm          = { .name = "core_l4_clkdm" },
1590         .recalc         = &followparent_recalc,
1591 };
1592
1593 static struct clk uart2_fck = {
1594         .name           = "uart2_fck",
1595         .parent         = &core_48m_fck,
1596         .prcm_mod       = CORE_MOD,
1597         .enable_reg     = CM_FCLKEN1,
1598         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1599         .idlest_bit     = OMAP3430_ST_UART2_SHIFT,
1600         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1601         .clkdm          = { .name = "core_l4_clkdm" },
1602         .recalc         = &followparent_recalc,
1603 };
1604
1605 static struct clk uart1_fck = {
1606         .name           = "uart1_fck",
1607         .parent         = &core_48m_fck,
1608         .prcm_mod       = CORE_MOD,
1609         .enable_reg     = CM_FCLKEN1,
1610         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1611         .idlest_bit     = OMAP3430_ST_UART1_SHIFT,
1612         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1613         .clkdm          = { .name = "core_l4_clkdm" },
1614         .recalc         = &followparent_recalc,
1615 };
1616
1617 /* XXX doublecheck: is this idle or standby? */
1618 static struct clk fshostusb_fck = {
1619         .name           = "fshostusb_fck",
1620         .parent         = &core_48m_fck,
1621         .prcm_mod       = CORE_MOD,
1622         .enable_reg     = CM_FCLKEN1,
1623         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1624         .idlest_bit     = OMAP3430ES1_ST_FSHOSTUSB_SHIFT,
1625         .flags          = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
1626         .clkdm          = { .name = "core_l4_clkdm" },
1627         .recalc         = &followparent_recalc,
1628 };
1629
1630 /* CORE_12M_FCK based clocks */
1631
1632 static struct clk core_12m_fck = {
1633         .name           = "core_12m_fck",
1634         .parent         = &omap_12m_fck,
1635         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1636         .clkdm          = { .name = "core_l4_clkdm" },
1637         .recalc         = &followparent_recalc,
1638 };
1639
1640 static struct clk hdq_fck = {
1641         .name           = "hdq_fck",
1642         .parent         = &core_12m_fck,
1643         .prcm_mod       = CORE_MOD,
1644         .enable_reg     = CM_FCLKEN1,
1645         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1646         .idlest_bit     = OMAP3430_ST_HDQ_SHIFT,
1647         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1648         .clkdm          = { .name = "core_l4_clkdm" },
1649         .recalc         = &followparent_recalc,
1650 };
1651
1652 /* DPLL3-derived clock */
1653
1654 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1655         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1656         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1657         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1658         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1659         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1660         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1661         { .div = 0 }
1662 };
1663
1664 static const struct clksel ssi_ssr_clksel[] = {
1665         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1666         { .parent = NULL }
1667 };
1668
1669 static struct clk ssi_ssr_fck_3430es1 = {
1670         .name           = "ssi_ssr_fck",
1671         .init           = &omap2_init_clksel_parent,
1672         .prcm_mod       = CORE_MOD,
1673         .enable_reg     = CM_FCLKEN1,
1674         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1675         .clksel_reg     = CM_CLKSEL,
1676         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1677         .clksel         = ssi_ssr_clksel,
1678         .flags          = CLOCK_IN_OMAP3430ES1,
1679         .clkdm          = { .name = "core_l4_clkdm" },
1680         .recalc         = &omap2_clksel_recalc,
1681 };
1682
1683 static struct clk ssi_ssr_fck_3430es2 = {
1684         .name           = "ssi_ssr_fck",
1685         .init           = &omap2_init_clksel_parent,
1686         .prcm_mod       = CORE_MOD,
1687         .enable_reg     = CM_FCLKEN1,
1688         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1689         .idlest_bit     = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
1690         .clksel_reg     = CM_CLKSEL,
1691         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1692         .clksel         = ssi_ssr_clksel,
1693         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1694         .clkdm          = { .name = "core_l4_clkdm" },
1695         .recalc         = &omap2_clksel_recalc,
1696 };
1697
1698 /* It's unfortunate that we need to duplicate this clock. */
1699 static struct clk ssi_sst_fck_3430es1 = {
1700         .name           = "ssi_sst_fck",
1701         .parent         = &ssi_ssr_fck_3430es1,
1702         .fixed_div      = 2,
1703         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1704         .clkdm          = { .name = "core_l4_clkdm" },
1705         .recalc         = &omap2_fixed_divisor_recalc,
1706 };
1707
1708 static struct clk ssi_sst_fck_3430es2 = {
1709         .name           = "ssi_sst_fck",
1710         .parent         = &ssi_ssr_fck_3430es2,
1711         .fixed_div      = 2,
1712         .flags          = CLOCK_IN_OMAP3430ES2 | PARENT_CONTROLS_CLOCK,
1713         .clkdm          = { .name = "core_l4_clkdm" },
1714         .recalc         = &omap2_fixed_divisor_recalc,
1715 };
1716
1717
1718
1719 /* CORE_L3_ICK based clocks */
1720
1721 /*
1722  * XXX must add clk_enable/clk_disable for these if standard code won't
1723  * handle it
1724  */
1725 static struct clk core_l3_ick = {
1726         .name           = "core_l3_ick",
1727         .parent         = &l3_ick,
1728         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1729         .clkdm          = { .name = "core_l3_clkdm" },
1730         .recalc         = &followparent_recalc,
1731 };
1732
1733 static struct clk hsotgusb_ick_3430es1 = {
1734         .name           = "hsotgusb_ick",
1735         .parent         = &core_l3_ick,
1736         .prcm_mod       = CORE_MOD,
1737         .enable_reg     = CM_ICLKEN1,
1738         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1739         .flags          = CLOCK_IN_OMAP3430ES1,
1740         .clkdm          = { .name = "core_l3_clkdm" },
1741         .recalc         = &followparent_recalc,
1742 };
1743
1744 static struct clk hsotgusb_ick_3430es2 = {
1745         .name           = "hsotgusb_ick",
1746         .parent         = &core_l3_ick,
1747         .prcm_mod       = CORE_MOD,
1748         .enable_reg     = CM_ICLKEN1,
1749         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1750         .idlest_bit     = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1751         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1752         .clkdm          = { .name = "core_l3_clkdm" },
1753         .recalc         = &followparent_recalc,
1754 };
1755
1756 static struct clk sdrc_ick = {
1757         .name           = "sdrc_ick",
1758         .parent         = &core_l3_ick,
1759         .prcm_mod       = CORE_MOD,
1760         .enable_reg     = CM_ICLKEN1,
1761         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1762         .idlest_bit     = OMAP3430_ST_SDRC_SHIFT,
1763         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT | WAIT_READY,
1764         .clkdm          = { .name = "core_l3_clkdm" },
1765         .recalc         = &followparent_recalc,
1766 };
1767
1768 static struct clk gpmc_fck = {
1769         .name           = "gpmc_fck",
1770         .parent         = &core_l3_ick,
1771         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1772                                 ENABLE_ON_INIT,
1773         .clkdm          = { .name = "core_l3_clkdm" },
1774         .recalc         = &followparent_recalc,
1775 };
1776
1777 /* SECURITY_L3_ICK based clocks */
1778
1779 static struct clk security_l3_ick = {
1780         .name           = "security_l3_ick",
1781         .parent         = &l3_ick,
1782         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1783         .clkdm          = { .name = "core_l3_clkdm" },
1784         .recalc         = &followparent_recalc,
1785 };
1786
1787 static struct clk pka_ick = {
1788         .name           = "pka_ick",
1789         .parent         = &security_l3_ick,
1790         .prcm_mod       = CORE_MOD,
1791         .enable_reg     = CM_ICLKEN2,
1792         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1793         .idlest_bit     = OMAP3430_ST_PKA_SHIFT,
1794         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1795         .clkdm          = { .name = "core_l3_clkdm" },
1796         .recalc         = &followparent_recalc,
1797 };
1798
1799 /* CORE_L4_ICK based clocks */
1800
1801 static struct clk core_l4_ick = {
1802         .name           = "core_l4_ick",
1803         .parent         = &l4_ick,
1804         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1805         .clkdm          = { .name = "core_l4_clkdm" },
1806         .recalc         = &followparent_recalc,
1807 };
1808
1809 static struct clk usbtll_ick = {
1810         .name           = "usbtll_ick",
1811         .parent         = &core_l4_ick,
1812         .prcm_mod       = CORE_MOD,
1813         .enable_reg     = CM_ICLKEN3,
1814         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1815         .idlest_bit     = OMAP3430ES2_ST_USBTLL_SHIFT,
1816         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1817         .clkdm          = { .name = "core_l4_clkdm" },
1818         .recalc         = &followparent_recalc,
1819 };
1820
1821 static struct clk mmchs3_ick = {
1822         .name           = "mmchs_ick",
1823         .id             = 2,
1824         .parent         = &core_l4_ick,
1825         .prcm_mod       = CORE_MOD,
1826         .enable_reg     = CM_ICLKEN1,
1827         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1828         .idlest_bit     = OMAP3430ES2_ST_MMC3_SHIFT,
1829         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1830         .clkdm          = { .name = "core_l4_clkdm" },
1831         .recalc         = &followparent_recalc,
1832 };
1833
1834 /* Intersystem Communication Registers - chassis mode only */
1835 static struct clk icr_ick = {
1836         .name           = "icr_ick",
1837         .parent         = &core_l4_ick,
1838         .prcm_mod       = CORE_MOD,
1839         .enable_reg     = CM_ICLKEN1,
1840         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1841         .idlest_bit     = OMAP3430_ST_ICR_SHIFT,
1842         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1843         .clkdm          = { .name = "core_l4_clkdm" },
1844         .recalc         = &followparent_recalc,
1845 };
1846
1847 static struct clk aes2_ick = {
1848         .name           = "aes2_ick",
1849         .parent         = &core_l4_ick,
1850         .prcm_mod       = CORE_MOD,
1851         .enable_reg     = CM_ICLKEN1,
1852         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1853         .idlest_bit     = OMAP3430_ST_AES2_SHIFT,
1854         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1855         .clkdm          = { .name = "core_l4_clkdm" },
1856         .recalc         = &followparent_recalc,
1857 };
1858
1859 static struct clk sha12_ick = {
1860         .name           = "sha12_ick",
1861         .parent         = &core_l4_ick,
1862         .prcm_mod       = CORE_MOD,
1863         .enable_reg     = CM_ICLKEN1,
1864         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1865         .idlest_bit     = OMAP3430_ST_SHA12_SHIFT,
1866         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1867         .clkdm          = { .name = "core_l4_clkdm" },
1868         .recalc         = &followparent_recalc,
1869 };
1870
1871 static struct clk des2_ick = {
1872         .name           = "des2_ick",
1873         .parent         = &core_l4_ick,
1874         .prcm_mod       = CORE_MOD,
1875         .enable_reg     = CM_ICLKEN1,
1876         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1877         .idlest_bit     = OMAP3430_ST_DES2_SHIFT,
1878         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1879         .clkdm          = { .name = "core_l4_clkdm" },
1880         .recalc         = &followparent_recalc,
1881 };
1882
1883 static struct clk mmchs2_ick = {
1884         .name           = "mmchs_ick",
1885         .id             = 1,
1886         .parent         = &core_l4_ick,
1887         .prcm_mod       = CORE_MOD,
1888         .enable_reg     = CM_ICLKEN1,
1889         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1890         .idlest_bit     = OMAP3430_ST_MMC2_SHIFT,
1891         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1892         .clkdm          = { .name = "core_l4_clkdm" },
1893         .recalc         = &followparent_recalc,
1894 };
1895
1896 static struct clk mmchs1_ick = {
1897         .name           = "mmchs_ick",
1898         .parent         = &core_l4_ick,
1899         .prcm_mod       = CORE_MOD,
1900         .enable_reg     = CM_ICLKEN1,
1901         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1902         .idlest_bit     = OMAP3430_ST_MMC1_SHIFT,
1903         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1904         .clkdm          = { .name = "core_l4_clkdm" },
1905         .recalc         = &followparent_recalc,
1906 };
1907
1908 static struct clk mspro_ick = {
1909         .name           = "mspro_ick",
1910         .parent         = &core_l4_ick,
1911         .prcm_mod       = CORE_MOD,
1912         .enable_reg     = CM_ICLKEN1,
1913         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1914         .idlest_bit     = OMAP3430_ST_MSPRO_SHIFT,
1915         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1916         .clkdm          = { .name = "core_l4_clkdm" },
1917         .recalc         = &followparent_recalc,
1918 };
1919
1920 static struct clk hdq_ick = {
1921         .name           = "hdq_ick",
1922         .parent         = &core_l4_ick,
1923         .prcm_mod       = CORE_MOD,
1924         .enable_reg     = CM_ICLKEN1,
1925         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1926         .idlest_bit     = OMAP3430_ST_HDQ_SHIFT,
1927         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1928         .clkdm          = { .name = "core_l4_clkdm" },
1929         .recalc         = &followparent_recalc,
1930 };
1931
1932 static struct clk mcspi4_ick = {
1933         .name           = "mcspi_ick",
1934         .id             = 4,
1935         .parent         = &core_l4_ick,
1936         .prcm_mod       = CORE_MOD,
1937         .enable_reg     = CM_ICLKEN1,
1938         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1939         .idlest_bit     = OMAP3430_ST_MCSPI4_SHIFT,
1940         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1941         .clkdm          = { .name = "core_l4_clkdm" },
1942         .recalc         = &followparent_recalc,
1943 };
1944
1945 static struct clk mcspi3_ick = {
1946         .name           = "mcspi_ick",
1947         .id             = 3,
1948         .parent         = &core_l4_ick,
1949         .prcm_mod       = CORE_MOD,
1950         .enable_reg     = CM_ICLKEN1,
1951         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1952         .idlest_bit     = OMAP3430_ST_MCSPI3_SHIFT,
1953         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1954         .clkdm          = { .name = "core_l4_clkdm" },
1955         .recalc         = &followparent_recalc,
1956 };
1957
1958 static struct clk mcspi2_ick = {
1959         .name           = "mcspi_ick",
1960         .id             = 2,
1961         .parent         = &core_l4_ick,
1962         .prcm_mod       = CORE_MOD,
1963         .enable_reg     = CM_ICLKEN1,
1964         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1965         .idlest_bit     = OMAP3430_ST_MCSPI2_SHIFT,
1966         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1967         .clkdm          = { .name = "core_l4_clkdm" },
1968         .recalc         = &followparent_recalc,
1969 };
1970
1971 static struct clk mcspi1_ick = {
1972         .name           = "mcspi_ick",
1973         .id             = 1,
1974         .parent         = &core_l4_ick,
1975         .prcm_mod       = CORE_MOD,
1976         .enable_reg     = CM_ICLKEN1,
1977         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1978         .idlest_bit     = OMAP3430_ST_MCSPI1_SHIFT,
1979         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1980         .clkdm          = { .name = "core_l4_clkdm" },
1981         .recalc         = &followparent_recalc,
1982 };
1983
1984 static struct clk i2c3_ick = {
1985         .name           = "i2c_ick",
1986         .id             = 3,
1987         .parent         = &core_l4_ick,
1988         .prcm_mod       = CORE_MOD,
1989         .enable_reg     = CM_ICLKEN1,
1990         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1991         .idlest_bit     = OMAP3430_ST_I2C3_SHIFT,
1992         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1993         .clkdm          = { .name = "core_l4_clkdm" },
1994         .recalc         = &followparent_recalc,
1995 };
1996
1997 static struct clk i2c2_ick = {
1998         .name           = "i2c_ick",
1999         .id             = 2,
2000         .parent         = &core_l4_ick,
2001         .prcm_mod       = CORE_MOD,
2002         .enable_reg     = CM_ICLKEN1,
2003         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
2004         .idlest_bit     = OMAP3430_ST_I2C2_SHIFT,
2005         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2006         .clkdm          = { .name = "core_l4_clkdm" },
2007         .recalc         = &followparent_recalc,
2008 };
2009
2010 static struct clk i2c1_ick = {
2011         .name           = "i2c_ick",
2012         .id             = 1,
2013         .parent         = &core_l4_ick,
2014         .prcm_mod       = CORE_MOD,
2015         .enable_reg     = CM_ICLKEN1,
2016         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
2017         .idlest_bit     = OMAP3430_ST_I2C1_SHIFT,
2018         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2019         .clkdm          = { .name = "core_l4_clkdm" },
2020         .recalc         = &followparent_recalc,
2021 };
2022
2023 static struct clk uart2_ick = {
2024         .name           = "uart2_ick",
2025         .parent         = &core_l4_ick,
2026         .prcm_mod       = CORE_MOD,
2027         .enable_reg     = CM_ICLKEN1,
2028         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
2029         .idlest_bit     = OMAP3430_ST_UART2_SHIFT,
2030         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2031         .clkdm          = { .name = "core_l4_clkdm" },
2032         .recalc         = &followparent_recalc,
2033 };
2034
2035 static struct clk uart1_ick = {
2036         .name           = "uart1_ick",
2037         .parent         = &core_l4_ick,
2038         .prcm_mod       = CORE_MOD,
2039         .enable_reg     = CM_ICLKEN1,
2040         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
2041         .idlest_bit     = OMAP3430_ST_UART1_SHIFT,
2042         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2043         .clkdm          = { .name = "core_l4_clkdm" },
2044         .recalc         = &followparent_recalc,
2045 };
2046
2047 static struct clk gpt11_ick = {
2048         .name           = "gpt11_ick",
2049         .parent         = &core_l4_ick,
2050         .prcm_mod       = CORE_MOD,
2051         .enable_reg     = CM_ICLKEN1,
2052         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
2053         .idlest_bit     = OMAP3430_ST_GPT11_SHIFT,
2054         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2055         .clkdm          = { .name = "core_l4_clkdm" },
2056         .recalc         = &followparent_recalc,
2057 };
2058
2059 static struct clk gpt10_ick = {
2060         .name           = "gpt10_ick",
2061         .parent         = &core_l4_ick,
2062         .prcm_mod       = CORE_MOD,
2063         .enable_reg     = CM_ICLKEN1,
2064         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
2065         .idlest_bit     = OMAP3430_ST_GPT10_SHIFT,
2066         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2067         .clkdm          = { .name = "core_l4_clkdm" },
2068         .recalc         = &followparent_recalc,
2069 };
2070
2071 static struct clk mcbsp5_ick = {
2072         .name           = "mcbsp_ick",
2073         .id             = 5,
2074         .parent         = &core_l4_ick,
2075         .prcm_mod       = CORE_MOD,
2076         .enable_reg     = CM_ICLKEN1,
2077         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
2078         .idlest_bit     = OMAP3430_ST_MCBSP5_SHIFT,
2079         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2080         .clkdm          = { .name = "core_l4_clkdm" },
2081         .recalc         = &followparent_recalc,
2082 };
2083
2084 static struct clk mcbsp1_ick = {
2085         .name           = "mcbsp_ick",
2086         .id             = 1,
2087         .parent         = &core_l4_ick,
2088         .prcm_mod       = CORE_MOD,
2089         .enable_reg     = CM_ICLKEN1,
2090         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2091         .idlest_bit     = OMAP3430_ST_MCBSP1_SHIFT,
2092         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2093         .clkdm          = { .name = "core_l4_clkdm" },
2094         .recalc         = &followparent_recalc,
2095 };
2096
2097 static struct clk fac_ick = {
2098         .name           = "fac_ick",
2099         .parent         = &core_l4_ick,
2100         .prcm_mod       = CORE_MOD,
2101         .enable_reg     = CM_ICLKEN1,
2102         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
2103         .idlest_bit     = OMAP3430ES1_ST_FAC_SHIFT,
2104         .flags          = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
2105         .clkdm          = { .name = "core_l4_clkdm" },
2106         .recalc         = &followparent_recalc,
2107 };
2108
2109 static struct clk mailboxes_ick = {
2110         .name           = "mailboxes_ick",
2111         .parent         = &core_l4_ick,
2112         .prcm_mod       = CORE_MOD,
2113         .enable_reg     = CM_ICLKEN1,
2114         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2115         .idlest_bit     = OMAP3430_ST_MAILBOXES_SHIFT,
2116         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2117         .clkdm          = { .name = "core_l4_clkdm" },
2118         .recalc         = &followparent_recalc,
2119 };
2120
2121 static struct clk omapctrl_ick = {
2122         .name           = "omapctrl_ick",
2123         .parent         = &core_l4_ick,
2124         .prcm_mod       = CORE_MOD,
2125         .enable_reg     = CM_ICLKEN1,
2126         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2127         .idlest_bit     = OMAP3430_ST_OMAPCTRL_SHIFT,
2128         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT | WAIT_READY,
2129         .clkdm          = { .name = "core_l4_clkdm" },
2130         .recalc         = &followparent_recalc,
2131 };
2132
2133 /* SSI_L4_ICK based clocks */
2134
2135 static struct clk ssi_l4_ick = {
2136         .name           = "ssi_l4_ick",
2137         .parent         = &l4_ick,
2138         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
2139         .clkdm          = { .name = "core_l4_clkdm" },
2140         .recalc         = &followparent_recalc,
2141 };
2142
2143 static struct clk ssi_ick_3430es1 = {
2144         .name           = "ssi_ick",
2145         .parent         = &ssi_l4_ick,
2146         .prcm_mod       = CORE_MOD,
2147         .enable_reg     = CM_ICLKEN1,
2148         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2149         .flags          = CLOCK_IN_OMAP3430ES1,
2150         .clkdm          = { .name = "core_l4_clkdm" },
2151         .recalc         = &followparent_recalc,
2152 };
2153
2154 static struct clk ssi_ick_3430es2 = {
2155         .name           = "ssi_ick",
2156         .parent         = &ssi_l4_ick,
2157         .prcm_mod       = CORE_MOD,
2158         .enable_reg     = CM_ICLKEN1,
2159         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2160         .idlest_bit     = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
2161         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2162         .clkdm          = { .name = "core_l4_clkdm" },
2163         .recalc         = &followparent_recalc,
2164 };
2165
2166 /*
2167  * REVISIT: Technically the TRM claims that this is CORE_CLK based,
2168  * but l4_ick makes more sense to me
2169  */
2170 static const struct clksel usb_l4_clksel[] = {
2171         { .parent = &l4_ick, .rates = div2_rates },
2172         { .parent = NULL },
2173 };
2174
2175 static struct clk usb_l4_ick = {
2176         .name           = "usb_l4_ick",
2177         .parent         = &l4_ick,
2178         .prcm_mod       = CORE_MOD,
2179         .init           = &omap2_init_clksel_parent,
2180         .enable_reg     = CM_ICLKEN1,
2181         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2182         .idlest_bit     = OMAP3430ES1_ST_FSHOSTUSB_SHIFT,
2183         .clksel_reg     = CM_CLKSEL,
2184         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2185         .clksel         = usb_l4_clksel,
2186         .flags          = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
2187         .clkdm          = { .name = "core_l4_clkdm" },
2188         .recalc         = &omap2_clksel_recalc,
2189 };
2190
2191 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2192
2193 /* SECURITY_L4_ICK2 based clocks */
2194
2195 static struct clk security_l4_ick2 = {
2196         .name           = "security_l4_ick2",
2197         .parent         = &l4_ick,
2198         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
2199         .clkdm          = { .name = "core_l4_clkdm" },
2200         .recalc         = &followparent_recalc,
2201 };
2202
2203 static struct clk aes1_ick = {
2204         .name           = "aes1_ick",
2205         .parent         = &security_l4_ick2,
2206         .prcm_mod       = CORE_MOD,
2207         .enable_reg     = CM_ICLKEN2,
2208         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2209         .idlest_bit     = OMAP3430_ST_AES1_SHIFT,
2210         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2211         .clkdm          = { .name = "core_l4_clkdm" },
2212         .recalc         = &followparent_recalc,
2213 };
2214
2215 static struct clk rng_ick = {
2216         .name           = "rng_ick",
2217         .parent         = &security_l4_ick2,
2218         .prcm_mod       = CORE_MOD,
2219         .enable_reg     = CM_ICLKEN2,
2220         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2221         .idlest_bit     = OMAP3430_ST_RNG_SHIFT,
2222         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2223         .clkdm          = { .name = "core_l4_clkdm" },
2224         .recalc         = &followparent_recalc,
2225 };
2226
2227 static struct clk sha11_ick = {
2228         .name           = "sha11_ick",
2229         .parent         = &security_l4_ick2,
2230         .prcm_mod       = CORE_MOD,
2231         .enable_reg     = CM_ICLKEN2,
2232         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2233         .idlest_bit     = OMAP3430_ST_SHA11_SHIFT,
2234         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2235         .clkdm          = { .name = "core_l4_clkdm" },
2236         .recalc         = &followparent_recalc,
2237 };
2238
2239 static struct clk des1_ick = {
2240         .name           = "des1_ick",
2241         .parent         = &security_l4_ick2,
2242         .prcm_mod       = CORE_MOD,
2243         .enable_reg     = CM_ICLKEN2,
2244         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2245         .idlest_bit     = OMAP3430_ST_DES1_SHIFT,
2246         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2247         .clkdm          = { .name = "core_l4_clkdm" },
2248         .recalc         = &followparent_recalc,
2249 };
2250
2251 /* DSS */
2252 static struct clk dss1_alwon_fck_3430es1 = {
2253         .name           = "dss1_alwon_fck",
2254         .parent         = &dpll4_m4x2_ck,
2255         .prcm_mod       = OMAP3430_DSS_MOD,
2256         .enable_reg     = CM_FCLKEN,
2257         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2258         .flags          = CLOCK_IN_OMAP3430ES1,
2259         .clkdm          = { .name = "dss_clkdm" },
2260         .recalc         = &followparent_recalc,
2261 };
2262
2263 static struct clk dss1_alwon_fck_3430es2 = {
2264         .name           = "dss1_alwon_fck",
2265         .parent         = &dpll4_m4x2_ck,
2266         .init           = &omap2_init_clksel_parent,
2267         .prcm_mod       = OMAP3430_DSS_MOD,
2268         .enable_reg     = CM_FCLKEN,
2269         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2270         .idlest_bit     = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
2271         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2272         .clkdm          = { .name = "dss_clkdm" },
2273         .recalc         = &followparent_recalc,
2274 };
2275
2276 static struct clk dss_tv_fck = {
2277         .name           = "dss_tv_fck",
2278         .parent         = &omap_54m_fck,
2279         .prcm_mod       = OMAP3430_DSS_MOD,
2280         .enable_reg     = CM_FCLKEN,
2281         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2282         .flags          = CLOCK_IN_OMAP343X,
2283         .clkdm          = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */
2284         .recalc         = &followparent_recalc,
2285 };
2286
2287 static struct clk dss_96m_fck = {
2288         .name           = "dss_96m_fck",
2289         .parent         = &omap_96m_fck,
2290         .prcm_mod       = OMAP3430_DSS_MOD,
2291         .enable_reg     = CM_FCLKEN,
2292         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2293         .flags          = CLOCK_IN_OMAP343X,
2294         .clkdm          = { .name = "dss_clkdm" },
2295         .recalc         = &followparent_recalc,
2296 };
2297
2298 static struct clk dss2_alwon_fck = {
2299         .name           = "dss2_alwon_fck",
2300         .parent         = &sys_ck,
2301         .prcm_mod       = OMAP3430_DSS_MOD,
2302         .enable_reg     = CM_FCLKEN,
2303         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2304         .flags          = CLOCK_IN_OMAP343X,
2305         .clkdm          = { .name = "dss_clkdm" },
2306         .recalc         = &followparent_recalc,
2307 };
2308
2309 static struct clk dss_ick_3430es1 = {
2310         /* Handles both L3 and L4 clocks */
2311         .name           = "dss_ick",
2312         .parent         = &l4_ick,
2313         .prcm_mod       = OMAP3430_DSS_MOD,
2314         .enable_reg     = CM_ICLKEN,
2315         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2316         .flags          = CLOCK_IN_OMAP3430ES1,
2317         .clkdm          = { .name = "dss_clkdm" },
2318         .recalc         = &followparent_recalc,
2319 };
2320
2321 static struct clk dss_ick_3430es2 = {
2322         /* Handles both L3 and L4 clocks */
2323         .name           = "dss_ick",
2324         .parent         = &l4_ick,
2325         .prcm_mod       = OMAP3430_DSS_MOD,
2326         .enable_reg     = CM_ICLKEN,
2327         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2328         .idlest_bit     = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
2329         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2330         .clkdm          = { .name = "dss_clkdm" },
2331         .recalc         = &followparent_recalc,
2332 };
2333
2334 /* CAM */
2335
2336 static struct clk cam_mclk = {
2337         .name           = "cam_mclk",
2338         .parent         = &dpll4_m5x2_ck,
2339         .prcm_mod       = OMAP3430_CAM_MOD,
2340         .enable_reg     = CM_FCLKEN,
2341         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2342         .flags          = CLOCK_IN_OMAP343X,
2343         .clkdm          = { .name = "cam_clkdm" },
2344         .recalc         = &followparent_recalc,
2345 };
2346
2347 static struct clk cam_ick = {
2348         /* Handles both L3 and L4 clocks */
2349         .name           = "cam_ick",
2350         .parent         = &l4_ick,
2351         .prcm_mod       = OMAP3430_CAM_MOD,
2352         .enable_reg     = CM_ICLKEN,
2353         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2354         .flags          = CLOCK_IN_OMAP343X,
2355         .clkdm          = { .name = "cam_clkdm" },
2356         .recalc         = &followparent_recalc,
2357 };
2358
2359 static struct clk csi2_96m_fck = {
2360         .name           = "csi2_96m_fck",
2361         .parent         = &core_96m_fck,
2362         .prcm_mod       = OMAP3430_CAM_MOD,
2363         .enable_reg     = CM_FCLKEN,
2364         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2365         .flags          = CLOCK_IN_OMAP343X,
2366         .clkdm          = { .name = "cam_clkdm" },
2367         .recalc         = &followparent_recalc,
2368 };
2369
2370 /* USBHOST - 3430ES2 only */
2371
2372 static struct clk usbhost_120m_fck = {
2373         .name           = "usbhost_120m_fck",
2374         .parent         = &dpll5_m2_ck,
2375         .prcm_mod       = OMAP3430ES2_USBHOST_MOD,
2376         .enable_reg     = CM_FCLKEN,
2377         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2378         .flags          = CLOCK_IN_OMAP3430ES2,
2379         .clkdm          = { .name = "usbhost_clkdm" },
2380         .recalc         = &followparent_recalc,
2381 };
2382
2383 static struct clk usbhost_48m_fck = {
2384         .name           = "usbhost_48m_fck",
2385         .parent         = &omap_48m_fck,
2386         .prcm_mod       = OMAP3430ES2_USBHOST_MOD,
2387         .enable_reg     = CM_FCLKEN,
2388         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2389         .idlest_bit     = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
2390         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2391         .clkdm          = { .name = "usbhost_clkdm" },
2392         .recalc         = &followparent_recalc,
2393 };
2394
2395 static struct clk usbhost_ick = {
2396         /* Handles both L3 and L4 clocks */
2397         .name           = "usbhost_ick",
2398         .parent         = &l4_ick,
2399         .prcm_mod       = OMAP3430ES2_USBHOST_MOD,
2400         .enable_reg     = CM_ICLKEN,
2401         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2402         .idlest_bit     = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
2403         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2404         .clkdm          = { .name = "usbhost_clkdm" },
2405         .recalc         = &followparent_recalc,
2406 };
2407
2408 /* WKUP */
2409
2410 static const struct clksel_rate usim_96m_rates[] = {
2411         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2412         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2413         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2414         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2415         { .div = 0 },
2416 };
2417
2418 static const struct clksel_rate usim_120m_rates[] = {
2419         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2420         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2421         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2422         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2423         { .div = 0 },
2424 };
2425
2426 static const struct clksel usim_clksel[] = {
2427         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2428         { .parent = &dpll5_m2_ck,       .rates = usim_120m_rates },
2429         { .parent = &sys_ck,            .rates = div2_rates },
2430         { .parent = NULL },
2431 };
2432
2433 /* 3430ES2 only */
2434 static struct clk usim_fck = {
2435         .name           = "usim_fck",
2436         .prcm_mod       = WKUP_MOD,
2437         .init           = &omap2_init_clksel_parent,
2438         .enable_reg     = CM_FCLKEN,
2439         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2440         .idlest_bit     = OMAP3430ES2_ST_USIMOCP_SHIFT,
2441         .clksel_reg     = CM_CLKSEL,
2442         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2443         .clksel         = usim_clksel,
2444         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2445         .clkdm          = { .name = "prm_clkdm" },
2446         .recalc         = &omap2_clksel_recalc,
2447 };
2448
2449 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2450 static struct clk gpt1_fck = {
2451         .name           = "gpt1_fck",
2452         .prcm_mod       = WKUP_MOD,
2453         .init           = &omap2_init_clksel_parent,
2454         .enable_reg     = CM_FCLKEN,
2455         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2456         .idlest_bit     = OMAP3430_ST_GPT1_SHIFT,
2457         .clksel_reg     = CM_CLKSEL,
2458         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2459         .clksel         = omap343x_gpt_clksel,
2460         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2461         .clkdm          = { .name = "prm_clkdm" },
2462         .recalc         = &omap2_clksel_recalc,
2463 };
2464
2465 static struct clk wkup_32k_fck = {
2466         .name           = "wkup_32k_fck",
2467         .parent         = &omap_32k_fck,
2468         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2469         .clkdm          = { .name = "prm_clkdm" },
2470         .recalc         = &followparent_recalc,
2471 };
2472
2473 static struct clk gpio1_dbck = {
2474         .name           = "gpio1_dbck",
2475         .parent         = &wkup_32k_fck,
2476         .prcm_mod       = WKUP_MOD,
2477         .enable_reg     = CM_FCLKEN,
2478         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2479         .idlest_bit     = OMAP3430_ST_GPIO1_SHIFT,
2480         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2481         .clkdm          = { .name = "prm_clkdm" },
2482         .recalc         = &followparent_recalc,
2483 };
2484
2485 static struct clk wdt2_fck = {
2486         .name           = "wdt2_fck",
2487         .parent         = &wkup_32k_fck,
2488         .prcm_mod       = WKUP_MOD,
2489         .enable_reg     = CM_FCLKEN,
2490         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2491         .idlest_bit     = OMAP3430_ST_WDT2_SHIFT,
2492         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2493         .clkdm          = { .name = "prm_clkdm" },
2494         .recalc         = &followparent_recalc,
2495 };
2496
2497 static struct clk wkup_l4_ick = {
2498         .name           = "wkup_l4_ick",
2499         .parent         = &sys_ck,
2500         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2501         .clkdm          = { .name = "prm_clkdm" },
2502         .recalc         = &followparent_recalc,
2503 };
2504
2505 static struct clk usim_ick = {
2506         .name           = "usim_ick",
2507         .parent         = &wkup_l4_ick,
2508         .prcm_mod       = WKUP_MOD,
2509         .enable_reg     = CM_ICLKEN,
2510         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2511         .idlest_bit     = OMAP3430ES2_ST_USIMOCP_SHIFT,
2512         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2513         .clkdm          = { .name = "prm_clkdm" },
2514         .recalc         = &followparent_recalc,
2515 };
2516
2517 static struct clk wdt2_ick = {
2518         .name           = "wdt2_ick",
2519         .parent         = &wkup_l4_ick,
2520         .prcm_mod       = WKUP_MOD,
2521         .enable_reg     = CM_ICLKEN,
2522         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2523         .idlest_bit     = OMAP3430_ST_WDT2_SHIFT,
2524         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2525         .clkdm          = { .name = "prm_clkdm" },
2526         .recalc         = &followparent_recalc,
2527 };
2528
2529 static struct clk wdt1_ick = {
2530         .name           = "wdt1_ick",
2531         .parent         = &wkup_l4_ick,
2532         .prcm_mod       = WKUP_MOD,
2533         .enable_reg     = CM_ICLKEN,
2534         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2535         .idlest_bit     = OMAP3430_ST_WDT1_SHIFT,
2536         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2537         .clkdm          = { .name = "prm_clkdm" },
2538         .recalc         = &followparent_recalc,
2539 };
2540
2541 static struct clk gpio1_ick = {
2542         .name           = "gpio1_ick",
2543         .parent         = &wkup_l4_ick,
2544         .prcm_mod       = WKUP_MOD,
2545         .enable_reg     = CM_ICLKEN,
2546         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2547         .idlest_bit     = OMAP3430_ST_GPIO1_SHIFT,
2548         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2549         .clkdm          = { .name = "prm_clkdm" },
2550         .recalc         = &followparent_recalc,
2551 };
2552
2553 static struct clk omap_32ksync_ick = {
2554         .name           = "omap_32ksync_ick",
2555         .parent         = &wkup_l4_ick,
2556         .prcm_mod       = WKUP_MOD,
2557         .enable_reg     = CM_ICLKEN,
2558         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2559         .idlest_bit     = OMAP3430_ST_32KSYNC_SHIFT,
2560         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2561         .clkdm          = { .name = "prm_clkdm" },
2562         .recalc         = &followparent_recalc,
2563 };
2564
2565 static struct clk gpt12_ick = {
2566         .name           = "gpt12_ick",
2567         .parent         = &wkup_l4_ick,
2568         .prcm_mod       = WKUP_MOD,
2569         .enable_reg     = CM_ICLKEN,
2570         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2571         .idlest_bit     = OMAP3430_ST_GPT12_SHIFT,
2572         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2573         .clkdm          = { .name = "prm_clkdm" },
2574         .recalc         = &followparent_recalc,
2575 };
2576
2577 static struct clk gpt1_ick = {
2578         .name           = "gpt1_ick",
2579         .parent         = &wkup_l4_ick,
2580         .prcm_mod       = WKUP_MOD,
2581         .enable_reg     = CM_ICLKEN,
2582         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2583         .idlest_bit     = OMAP3430_ST_GPT1_SHIFT,
2584         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2585         .clkdm          = { .name = "prm_clkdm" },
2586         .recalc         = &followparent_recalc,
2587 };
2588
2589
2590
2591 /* PER clock domain */
2592
2593 static struct clk per_96m_fck = {
2594         .name           = "per_96m_fck",
2595         .parent         = &omap_96m_alwon_fck,
2596         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
2597         .clkdm          = { .name = "per_clkdm" },
2598         .recalc         = &followparent_recalc,
2599 };
2600
2601 static struct clk per_48m_fck = {
2602         .name           = "per_48m_fck",
2603         .parent         = &omap_48m_fck,
2604         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
2605         .clkdm          = { .name = "per_clkdm" },
2606         .recalc         = &followparent_recalc,
2607 };
2608
2609 static struct clk uart3_fck = {
2610         .name           = "uart3_fck",
2611         .parent         = &per_48m_fck,
2612         .prcm_mod       = OMAP3430_PER_MOD,
2613         .enable_reg     = CM_FCLKEN,
2614         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2615         .idlest_bit     = OMAP3430_ST_UART3_SHIFT,
2616         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2617         .clkdm          = { .name = "per_clkdm" },
2618         .recalc         = &followparent_recalc,
2619 };
2620
2621 static struct clk gpt2_fck = {
2622         .name           = "gpt2_fck",
2623         .prcm_mod       = OMAP3430_PER_MOD,
2624         .init           = &omap2_init_clksel_parent,
2625         .enable_reg     = CM_FCLKEN,
2626         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2627         .idlest_bit     = OMAP3430_ST_GPT2_SHIFT,
2628         .clksel_reg     = CM_CLKSEL,
2629         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2630         .clksel         = omap343x_gpt_clksel,
2631         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2632         .clkdm          = { .name = "per_clkdm" },
2633         .recalc         = &omap2_clksel_recalc,
2634 };
2635
2636 static struct clk gpt3_fck = {
2637         .name           = "gpt3_fck",
2638         .prcm_mod       = OMAP3430_PER_MOD,
2639         .init           = &omap2_init_clksel_parent,
2640         .enable_reg     = CM_FCLKEN,
2641         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2642         .idlest_bit     = OMAP3430_ST_GPT3_SHIFT,
2643         .clksel_reg     = CM_CLKSEL,
2644         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2645         .clksel         = omap343x_gpt_clksel,
2646         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2647         .clkdm          = { .name = "per_clkdm" },
2648         .recalc         = &omap2_clksel_recalc,
2649 };
2650
2651 static struct clk gpt4_fck = {
2652         .name           = "gpt4_fck",
2653         .prcm_mod       = OMAP3430_PER_MOD,
2654         .init           = &omap2_init_clksel_parent,
2655         .enable_reg     = CM_FCLKEN,
2656         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2657         .idlest_bit     = OMAP3430_ST_GPT4_SHIFT,
2658         .clksel_reg     = CM_CLKSEL,
2659         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2660         .clksel         = omap343x_gpt_clksel,
2661         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2662         .clkdm          = { .name = "per_clkdm" },
2663         .recalc         = &omap2_clksel_recalc,
2664 };
2665
2666 static struct clk gpt5_fck = {
2667         .name           = "gpt5_fck",
2668         .prcm_mod       = OMAP3430_PER_MOD,
2669         .init           = &omap2_init_clksel_parent,
2670         .enable_reg     = CM_FCLKEN,
2671         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2672         .idlest_bit     = OMAP3430_ST_GPT5_SHIFT,
2673         .clksel_reg     = CM_CLKSEL,
2674         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2675         .clksel         = omap343x_gpt_clksel,
2676         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2677         .clkdm          = { .name = "per_clkdm" },
2678         .recalc         = &omap2_clksel_recalc,
2679 };
2680
2681 static struct clk gpt6_fck = {
2682         .name           = "gpt6_fck",
2683         .prcm_mod       = OMAP3430_PER_MOD,
2684         .init           = &omap2_init_clksel_parent,
2685         .enable_reg     = CM_FCLKEN,
2686         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2687         .idlest_bit     = OMAP3430_ST_GPT6_SHIFT,
2688         .clksel_reg     = CM_CLKSEL,
2689         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2690         .clksel         = omap343x_gpt_clksel,
2691         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2692         .clkdm          = { .name = "per_clkdm" },
2693         .recalc         = &omap2_clksel_recalc,
2694 };
2695
2696 static struct clk gpt7_fck = {
2697         .name           = "gpt7_fck",
2698         .prcm_mod       = OMAP3430_PER_MOD,
2699         .init           = &omap2_init_clksel_parent,
2700         .enable_reg     = CM_FCLKEN,
2701         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2702         .idlest_bit     = OMAP3430_ST_GPT7_SHIFT,
2703         .clksel_reg     = CM_CLKSEL,
2704         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2705         .clksel         = omap343x_gpt_clksel,
2706         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2707         .clkdm          = { .name = "per_clkdm" },
2708         .recalc         = &omap2_clksel_recalc,
2709 };
2710
2711 static struct clk gpt8_fck = {
2712         .name           = "gpt8_fck",
2713         .prcm_mod       = OMAP3430_PER_MOD,
2714         .init           = &omap2_init_clksel_parent,
2715         .enable_reg     = CM_FCLKEN,
2716         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2717         .idlest_bit     = OMAP3430_ST_GPT8_SHIFT,
2718         .clksel_reg     = CM_CLKSEL,
2719         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2720         .clksel         = omap343x_gpt_clksel,
2721         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2722         .clkdm          = { .name = "per_clkdm" },
2723         .recalc         = &omap2_clksel_recalc,
2724 };
2725
2726 static struct clk gpt9_fck = {
2727         .name           = "gpt9_fck",
2728         .prcm_mod       = OMAP3430_PER_MOD,
2729         .init           = &omap2_init_clksel_parent,
2730         .enable_reg     = CM_FCLKEN,
2731         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2732         .idlest_bit     = OMAP3430_ST_GPT9_SHIFT,
2733         .clksel_reg     = CM_CLKSEL,
2734         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2735         .clksel         = omap343x_gpt_clksel,
2736         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2737         .clkdm          = { .name = "per_clkdm" },
2738         .recalc         = &omap2_clksel_recalc,
2739 };
2740
2741 static struct clk per_32k_alwon_fck = {
2742         .name           = "per_32k_alwon_fck",
2743         .parent         = &omap_32k_fck,
2744         .clkdm          = { .name = "per_clkdm" },
2745         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2746         .recalc         = &followparent_recalc,
2747 };
2748
2749 static struct clk gpio6_dbck = {
2750         .name           = "gpio6_dbck",
2751         .parent         = &per_32k_alwon_fck,
2752         .prcm_mod       = OMAP3430_PER_MOD,
2753         .enable_reg     = CM_FCLKEN,
2754         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2755         .idlest_bit     = OMAP3430_ST_GPIO6_SHIFT,
2756         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2757         .clkdm          = { .name = "per_clkdm" },
2758         .recalc         = &followparent_recalc,
2759 };
2760
2761 static struct clk gpio5_dbck = {
2762         .name           = "gpio5_dbck",
2763         .parent         = &per_32k_alwon_fck,
2764         .prcm_mod       = OMAP3430_PER_MOD,
2765         .enable_reg     = CM_FCLKEN,
2766         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2767         .idlest_bit     = OMAP3430_ST_GPIO5_SHIFT,
2768         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2769         .clkdm          = { .name = "per_clkdm" },
2770         .recalc         = &followparent_recalc,
2771 };
2772
2773 static struct clk gpio4_dbck = {
2774         .name           = "gpio4_dbck",
2775         .parent         = &per_32k_alwon_fck,
2776         .prcm_mod       = OMAP3430_PER_MOD,
2777         .enable_reg     = CM_FCLKEN,
2778         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2779         .idlest_bit     = OMAP3430_ST_GPIO4_SHIFT,
2780         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2781         .clkdm          = { .name = "per_clkdm" },
2782         .recalc         = &followparent_recalc,
2783 };
2784
2785 static struct clk gpio3_dbck = {
2786         .name           = "gpio3_dbck",
2787         .parent         = &per_32k_alwon_fck,
2788         .prcm_mod       = OMAP3430_PER_MOD,
2789         .enable_reg     = CM_FCLKEN,
2790         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2791         .idlest_bit     = OMAP3430_ST_GPIO3_SHIFT,
2792         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2793         .clkdm          = { .name = "per_clkdm" },
2794         .recalc         = &followparent_recalc,
2795 };
2796
2797 static struct clk gpio2_dbck = {
2798         .name           = "gpio2_dbck",
2799         .parent         = &per_32k_alwon_fck,
2800         .prcm_mod       = OMAP3430_PER_MOD,
2801         .enable_reg     = CM_FCLKEN,
2802         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2803         .idlest_bit     = OMAP3430_ST_GPIO2_SHIFT,
2804         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2805         .clkdm          = { .name = "per_clkdm" },
2806         .recalc         = &followparent_recalc,
2807 };
2808
2809 static struct clk wdt3_fck = {
2810         .name           = "wdt3_fck",
2811         .parent         = &per_32k_alwon_fck,
2812         .prcm_mod       = OMAP3430_PER_MOD,
2813         .enable_reg     = CM_FCLKEN,
2814         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2815         .idlest_bit     = OMAP3430_ST_WDT3_SHIFT,
2816         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2817         .clkdm          = { .name = "per_clkdm" },
2818         .recalc         = &followparent_recalc,
2819 };
2820
2821 static struct clk per_l4_ick = {
2822         .name           = "per_l4_ick",
2823         .parent         = &l4_ick,
2824         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
2825         .clkdm          = { .name = "per_clkdm" },
2826         .recalc         = &followparent_recalc,
2827 };
2828
2829 static struct clk gpio6_ick = {
2830         .name           = "gpio6_ick",
2831         .parent         = &per_l4_ick,
2832         .prcm_mod       = OMAP3430_PER_MOD,
2833         .enable_reg     = CM_ICLKEN,
2834         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2835         .idlest_bit     = OMAP3430_ST_GPIO6_SHIFT,
2836         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2837         .clkdm          = { .name = "per_clkdm" },
2838         .recalc         = &followparent_recalc,
2839 };
2840
2841 static struct clk gpio5_ick = {
2842         .name           = "gpio5_ick",
2843         .parent         = &per_l4_ick,
2844         .prcm_mod       = OMAP3430_PER_MOD,
2845         .enable_reg     = CM_ICLKEN,
2846         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2847         .idlest_bit     = OMAP3430_ST_GPIO5_SHIFT,
2848         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2849         .clkdm          = { .name = "per_clkdm" },
2850         .recalc         = &followparent_recalc,
2851 };
2852
2853 static struct clk gpio4_ick = {
2854         .name           = "gpio4_ick",
2855         .parent         = &per_l4_ick,
2856         .prcm_mod       = OMAP3430_PER_MOD,
2857         .enable_reg     = CM_ICLKEN,
2858         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2859         .idlest_bit     = OMAP3430_ST_GPIO4_SHIFT,
2860         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2861         .clkdm          = { .name = "per_clkdm" },
2862         .recalc         = &followparent_recalc,
2863 };
2864
2865 static struct clk gpio3_ick = {
2866         .name           = "gpio3_ick",
2867         .parent         = &per_l4_ick,
2868         .prcm_mod       = OMAP3430_PER_MOD,
2869         .enable_reg     = CM_ICLKEN,
2870         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2871         .idlest_bit     = OMAP3430_ST_GPIO3_SHIFT,
2872         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2873         .clkdm          = { .name = "per_clkdm" },
2874         .recalc         = &followparent_recalc,
2875 };
2876
2877 static struct clk gpio2_ick = {
2878         .name           = "gpio2_ick",
2879         .parent         = &per_l4_ick,
2880         .prcm_mod       = OMAP3430_PER_MOD,
2881         .enable_reg     = CM_ICLKEN,
2882         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2883         .idlest_bit     = OMAP3430_ST_GPIO2_SHIFT,
2884         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2885         .clkdm          = { .name = "per_clkdm" },
2886         .recalc         = &followparent_recalc,
2887 };
2888
2889 static struct clk wdt3_ick = {
2890         .name           = "wdt3_ick",
2891         .parent         = &per_l4_ick,
2892         .prcm_mod       = OMAP3430_PER_MOD,
2893         .enable_reg     = CM_ICLKEN,
2894         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2895         .idlest_bit     = OMAP3430_ST_WDT3_SHIFT,
2896         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2897         .clkdm          = { .name = "per_clkdm" },
2898         .recalc         = &followparent_recalc,
2899 };
2900
2901 static struct clk uart3_ick = {
2902         .name           = "uart3_ick",
2903         .parent         = &per_l4_ick,
2904         .prcm_mod       = OMAP3430_PER_MOD,
2905         .enable_reg     = CM_ICLKEN,
2906         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2907         .idlest_bit     = OMAP3430_ST_UART3_SHIFT,
2908         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2909         .clkdm          = { .name = "per_clkdm" },
2910         .recalc         = &followparent_recalc,
2911 };
2912
2913 static struct clk gpt9_ick = {
2914         .name           = "gpt9_ick",
2915         .parent         = &per_l4_ick,
2916         .prcm_mod       = OMAP3430_PER_MOD,
2917         .enable_reg     = CM_ICLKEN,
2918         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2919         .idlest_bit     = OMAP3430_ST_GPT9_SHIFT,
2920         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2921         .clkdm          = { .name = "per_clkdm" },
2922         .recalc         = &followparent_recalc,
2923 };
2924
2925 static struct clk gpt8_ick = {
2926         .name           = "gpt8_ick",
2927         .parent         = &per_l4_ick,
2928         .prcm_mod       = OMAP3430_PER_MOD,
2929         .enable_reg     = CM_ICLKEN,
2930         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2931         .idlest_bit     = OMAP3430_ST_GPT8_SHIFT,
2932         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2933         .clkdm          = { .name = "per_clkdm" },
2934         .recalc         = &followparent_recalc,
2935 };
2936
2937 static struct clk gpt7_ick = {
2938         .name           = "gpt7_ick",
2939         .parent         = &per_l4_ick,
2940         .prcm_mod       = OMAP3430_PER_MOD,
2941         .enable_reg     = CM_ICLKEN,
2942         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2943         .idlest_bit     = OMAP3430_ST_GPT7_SHIFT,
2944         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2945         .clkdm          = { .name = "per_clkdm" },
2946         .recalc         = &followparent_recalc,
2947 };
2948
2949 static struct clk gpt6_ick = {
2950         .name           = "gpt6_ick",
2951         .parent         = &per_l4_ick,
2952         .prcm_mod       = OMAP3430_PER_MOD,
2953         .enable_reg     = CM_ICLKEN,
2954         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2955         .idlest_bit     = OMAP3430_ST_GPT6_SHIFT,
2956         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2957         .clkdm          = { .name = "per_clkdm" },
2958         .recalc         = &followparent_recalc,
2959 };
2960
2961 static struct clk gpt5_ick = {
2962         .name           = "gpt5_ick",
2963         .parent         = &per_l4_ick,
2964         .prcm_mod       = OMAP3430_PER_MOD,
2965         .enable_reg     = CM_ICLKEN,
2966         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2967         .idlest_bit     = OMAP3430_ST_GPT5_SHIFT,
2968         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2969         .clkdm          = { .name = "per_clkdm" },
2970         .recalc         = &followparent_recalc,
2971 };
2972
2973 static struct clk gpt4_ick = {
2974         .name           = "gpt4_ick",
2975         .parent         = &per_l4_ick,
2976         .prcm_mod       = OMAP3430_PER_MOD,
2977         .enable_reg     = CM_ICLKEN,
2978         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2979         .idlest_bit     = OMAP3430_ST_GPT4_SHIFT,
2980         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2981         .clkdm          = { .name = "per_clkdm" },
2982         .recalc         = &followparent_recalc,
2983 };
2984
2985 static struct clk gpt3_ick = {
2986         .name           = "gpt3_ick",
2987         .parent         = &per_l4_ick,
2988         .prcm_mod       = OMAP3430_PER_MOD,
2989         .enable_reg     = CM_ICLKEN,
2990         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2991         .idlest_bit     = OMAP3430_ST_GPT3_SHIFT,
2992         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2993         .clkdm          = { .name = "per_clkdm" },
2994         .recalc         = &followparent_recalc,
2995 };
2996
2997 static struct clk gpt2_ick = {
2998         .name           = "gpt2_ick",
2999         .parent         = &per_l4_ick,
3000         .prcm_mod       = OMAP3430_PER_MOD,
3001         .enable_reg     = CM_ICLKEN,
3002         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
3003         .idlest_bit     = OMAP3430_ST_GPT2_SHIFT,
3004         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3005         .clkdm          = { .name = "per_clkdm" },
3006         .recalc         = &followparent_recalc,
3007 };
3008
3009 static struct clk mcbsp2_ick = {
3010         .name           = "mcbsp_ick",
3011         .id             = 2,
3012         .parent         = &per_l4_ick,
3013         .prcm_mod       = OMAP3430_PER_MOD,
3014         .enable_reg     = CM_ICLKEN,
3015         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
3016         .idlest_bit     = OMAP3430_ST_MCBSP2_SHIFT,
3017         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3018         .clkdm          = { .name = "per_clkdm" },
3019         .recalc         = &followparent_recalc,
3020 };
3021
3022 static struct clk mcbsp3_ick = {
3023         .name           = "mcbsp_ick",
3024         .id             = 3,
3025         .parent         = &per_l4_ick,
3026         .prcm_mod       = OMAP3430_PER_MOD,
3027         .enable_reg     = CM_ICLKEN,
3028         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
3029         .idlest_bit     = OMAP3430_ST_MCBSP3_SHIFT,
3030         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3031         .clkdm          = { .name = "per_clkdm" },
3032         .recalc         = &followparent_recalc,
3033 };
3034
3035 static struct clk mcbsp4_ick = {
3036         .name           = "mcbsp_ick",
3037         .id             = 4,
3038         .parent         = &per_l4_ick,
3039         .prcm_mod       = OMAP3430_PER_MOD,
3040         .enable_reg     = CM_ICLKEN,
3041         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
3042         .idlest_bit     = OMAP3430_ST_MCBSP4_SHIFT,
3043         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3044         .clkdm          = { .name = "per_clkdm" },
3045         .recalc         = &followparent_recalc,
3046 };
3047
3048 static const struct clksel mcbsp_234_clksel[] = {
3049         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
3050         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
3051         { .parent = NULL }
3052 };
3053
3054 static struct clk mcbsp2_src_fck = {
3055         .name           = "mcbsp_src_fck",
3056         .id             = 2,
3057         .prcm_mod       = CLK_REG_IN_SCM,
3058         .init           = &omap2_init_clksel_parent,
3059         .clksel_reg     = OMAP2_CONTROL_DEVCONF0,
3060         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
3061         .clksel         = mcbsp_234_clksel,
3062         .flags          = CLOCK_IN_OMAP343X,
3063         .clkdm          = { .name = "per_clkdm" },
3064         .recalc         = &omap2_clksel_recalc,
3065 };
3066
3067 static struct clk mcbsp2_fck = {
3068         .name           = "mcbsp_fck",
3069         .id             = 2,
3070         .parent         = &mcbsp2_src_fck,
3071         .prcm_mod       = OMAP3430_PER_MOD,
3072         .enable_reg     = CM_FCLKEN,
3073         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
3074         .idlest_bit     = OMAP3430_ST_MCBSP2_SHIFT,
3075         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3076         .clkdm          = { .name = "per_clkdm" },
3077         .recalc         = &omap2_clksel_recalc,
3078 };
3079
3080 static struct clk mcbsp3_src_fck = {
3081         .name           = "mcbsp_src_fck",
3082         .id             = 3,
3083         .prcm_mod       = CLK_REG_IN_SCM,
3084         .init           = &omap2_init_clksel_parent,
3085         .clksel_reg     = OMAP343X_CONTROL_DEVCONF1,
3086         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
3087         .clksel         = mcbsp_234_clksel,
3088         .flags          = CLOCK_IN_OMAP343X,
3089         .clkdm          = { .name = "per_clkdm" },
3090         .recalc         = &omap2_clksel_recalc,
3091 };
3092
3093 static struct clk mcbsp3_fck = {
3094         .name           = "mcbsp_fck",
3095         .id             = 3,
3096         .parent         = &mcbsp3_src_fck,
3097         .prcm_mod       = OMAP3430_PER_MOD,
3098         .enable_reg     = CM_FCLKEN,
3099         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
3100         .idlest_bit     = OMAP3430_ST_MCBSP3_SHIFT,
3101         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3102         .clkdm          = { .name = "per_clkdm" },
3103         .recalc         = &omap2_clksel_recalc,
3104 };
3105
3106 static struct clk mcbsp4_src_fck = {
3107         .name           = "mcbsp_src_fck",
3108         .id             = 4,
3109         .prcm_mod       = CLK_REG_IN_SCM,
3110         .init           = &omap2_init_clksel_parent,
3111         .clksel_reg     = OMAP343X_CONTROL_DEVCONF1,
3112         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
3113         .clksel         = mcbsp_234_clksel,
3114         .flags          = CLOCK_IN_OMAP343X,
3115         .clkdm          = { .name = "per_clkdm" },
3116         .recalc         = &omap2_clksel_recalc,
3117 };
3118
3119 static struct clk mcbsp4_fck = {
3120         .name           = "mcbsp_fck",
3121         .id             = 4,
3122         .parent         = &mcbsp4_src_fck,
3123         .prcm_mod       = OMAP3430_PER_MOD,
3124         .enable_reg     = CM_FCLKEN,
3125         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
3126         .idlest_bit     = OMAP3430_ST_MCBSP4_SHIFT,
3127         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3128         .clkdm          = { .name = "per_clkdm" },
3129         .recalc         = &omap2_clksel_recalc,
3130 };
3131
3132 /* EMU clocks */
3133
3134 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
3135
3136 static const struct clksel_rate emu_src_sys_rates[] = {
3137         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
3138         { .div = 0 },
3139 };
3140
3141 static const struct clksel_rate emu_src_core_rates[] = {
3142         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3143         { .div = 0 },
3144 };
3145
3146 static const struct clksel_rate emu_src_per_rates[] = {
3147         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3148         { .div = 0 },
3149 };
3150
3151 static const struct clksel_rate emu_src_mpu_rates[] = {
3152         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
3153         { .div = 0 },
3154 };
3155
3156 static const struct clksel emu_src_clksel[] = {
3157         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
3158         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
3159         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
3160         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
3161         { .parent = NULL },
3162 };
3163
3164 /*
3165  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
3166  * to switch the source of some of the EMU clocks.
3167  * XXX Are there CLKEN bits for these EMU clks?
3168  */
3169 static struct clk emu_src_ck = {
3170         .name           = "emu_src_ck",
3171         .prcm_mod       = OMAP3430_EMU_MOD,
3172         .init           = &omap2_init_clksel_parent,
3173         .clksel_reg     = CM_CLKSEL1,
3174         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
3175         .clksel         = emu_src_clksel,
3176         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3177         .clkdm          = { .name = "emu_clkdm" },
3178         .recalc         = &omap2_clksel_recalc,
3179 };
3180
3181 static const struct clksel_rate pclk_emu_rates[] = {
3182         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3183         { .div = 3, .val = 3, .flags = RATE_IN_343X },
3184         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3185         { .div = 6, .val = 6, .flags = RATE_IN_343X },
3186         { .div = 0 },
3187 };
3188
3189 static const struct clksel pclk_emu_clksel[] = {
3190         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
3191         { .parent = NULL },
3192 };
3193
3194 static struct clk pclk_fck = {
3195         .name           = "pclk_fck",
3196         .prcm_mod       = OMAP3430_EMU_MOD,
3197         .init           = &omap2_init_clksel_parent,
3198         .clksel_reg     = CM_CLKSEL1,
3199         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
3200         .clksel         = pclk_emu_clksel,
3201         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3202         .clkdm          = { .name = "emu_clkdm" },
3203         .recalc         = &omap2_clksel_recalc,
3204 };
3205
3206 static const struct clksel_rate pclkx2_emu_rates[] = {
3207         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3208         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3209         { .div = 3, .val = 3, .flags = RATE_IN_343X },
3210         { .div = 0 },
3211 };
3212
3213 static const struct clksel pclkx2_emu_clksel[] = {
3214         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
3215         { .parent = NULL },
3216 };
3217
3218 static struct clk pclkx2_fck = {
3219         .name           = "pclkx2_fck",
3220         .prcm_mod       = OMAP3430_EMU_MOD,
3221         .init           = &omap2_init_clksel_parent,
3222         .clksel_reg     = CM_CLKSEL1,
3223         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
3224         .clksel         = pclkx2_emu_clksel,
3225         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3226         .clkdm          = { .name = "emu_clkdm" },
3227         .recalc         = &omap2_clksel_recalc,
3228 };
3229
3230 static const struct clksel atclk_emu_clksel[] = {
3231         { .parent = &emu_src_ck, .rates = div2_rates },
3232         { .parent = NULL },
3233 };
3234
3235 static struct clk atclk_fck = {
3236         .name           = "atclk_fck",
3237         .prcm_mod       = OMAP3430_EMU_MOD,
3238         .init           = &omap2_init_clksel_parent,
3239         .clksel_reg     = CM_CLKSEL1,
3240         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
3241         .clksel         = atclk_emu_clksel,
3242         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3243         .clkdm          = { .name = "emu_clkdm" },
3244         .recalc         = &omap2_clksel_recalc,
3245 };
3246
3247 static struct clk traceclk_src_fck = {
3248         .name           = "traceclk_src_fck",
3249         .prcm_mod       = OMAP3430_EMU_MOD,
3250         .init           = &omap2_init_clksel_parent,
3251         .clksel_reg     = CM_CLKSEL1,
3252         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
3253         .clksel         = emu_src_clksel,
3254         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3255         .clkdm          = { .name = "emu_clkdm" },
3256         .recalc         = &omap2_clksel_recalc,
3257 };
3258
3259 static const struct clksel_rate traceclk_rates[] = {
3260         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3261         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3262         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3263         { .div = 0 },
3264 };
3265
3266 static const struct clksel traceclk_clksel[] = {
3267         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3268         { .parent = NULL },
3269 };
3270
3271 static struct clk traceclk_fck = {
3272         .name           = "traceclk_fck",
3273         .prcm_mod       = OMAP3430_EMU_MOD,
3274         .init           = &omap2_init_clksel_parent,
3275         .clksel_reg     = CM_CLKSEL1,
3276         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3277         .clksel         = traceclk_clksel,
3278         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3279         .clkdm          = { .name = "emu_clkdm" },
3280         .recalc         = &omap2_clksel_recalc,
3281 };
3282
3283 /* SR clocks */
3284
3285 /* SmartReflex fclk (VDD1) */
3286 static struct clk sr1_fck = {
3287         .name           = "sr1_fck",
3288         .parent         = &sys_ck,
3289         .prcm_mod       = WKUP_MOD,
3290         .enable_reg     = CM_FCLKEN,
3291         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3292         .idlest_bit     = OMAP3430_ST_SR1_SHIFT,
3293         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3294         .clkdm          = { .name = "prm_clkdm" },
3295         .recalc         = &followparent_recalc,
3296 };
3297
3298 /* SmartReflex fclk (VDD2) */
3299 static struct clk sr2_fck = {
3300         .name           = "sr2_fck",
3301         .parent         = &sys_ck,
3302         .prcm_mod       = WKUP_MOD,
3303         .enable_reg     = CM_FCLKEN,
3304         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3305         .idlest_bit     = OMAP3430_ST_SR2_SHIFT,
3306         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3307         .clkdm          = { .name = "prm_clkdm" },
3308         .recalc         = &followparent_recalc,
3309 };
3310
3311 static struct clk sr_l4_ick = {
3312         .name           = "sr_l4_ick",
3313         .parent         = &l4_ick,
3314         .flags          = CLOCK_IN_OMAP343X,
3315         .clkdm          = { .name = "core_l4_clkdm" },
3316         .recalc         = &followparent_recalc,
3317 };
3318
3319 /* SECURE_32K_FCK clocks */
3320
3321 /* XXX Make sure idlest_bit/wait_ready with no enable_bit works */
3322 static struct clk gpt12_fck = {
3323         .name           = "gpt12_fck",
3324         .parent         = &secure_32k_fck,
3325         .idlest_bit     = OMAP3430_ST_GPT12_SHIFT,
3326         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | WAIT_READY,
3327         .clkdm          = { .name = "prm_clkdm" },
3328         .recalc         = &followparent_recalc,
3329 };
3330
3331 static struct clk wdt1_fck = {
3332         .name           = "wdt1_fck",
3333         .parent         = &secure_32k_fck,
3334         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3335         .clkdm          = { .name = "prm_clkdm" },
3336         .recalc         = &followparent_recalc,
3337 };
3338
3339 static struct clk *onchip_34xx_clks[] __initdata = {
3340         &omap_32k_fck,
3341         &virt_12m_ck,
3342         &virt_13m_ck,
3343         &virt_16_8m_ck,
3344         &virt_19_2m_ck,
3345         &virt_26m_ck,
3346         &virt_38_4m_ck,
3347         &osc_sys_ck,
3348         &sys_ck,
3349         &sys_altclk,
3350         &mcbsp_clks,
3351         &sys_clkout1,
3352         &dpll1_ck,
3353         &dpll1_x2_ck,
3354         &dpll1_x2m2_ck,
3355         &dpll2_ck,
3356         &dpll2_m2_ck,
3357         &dpll3_ck,
3358         &core_ck,
3359         &dpll3_x2_ck,
3360         &dpll3_m2_ck,
3361         &dpll3_m2x2_ck,
3362         &dpll3_m3_ck,
3363         &dpll3_m3x2_ck,
3364         &emu_core_alwon_ck,
3365         &dpll4_ck,
3366         &dpll4_x2_ck,
3367         &omap_96m_alwon_fck,
3368         &omap_96m_fck,
3369         &cm_96m_fck,
3370         &omap_54m_fck,
3371         &omap_48m_fck,
3372         &omap_12m_fck,
3373         &dpll4_m2_ck,
3374         &dpll4_m2x2_ck,
3375         &dpll4_m3_ck,
3376         &dpll4_m3x2_ck,
3377         &dpll4_m4_ck,
3378         &dpll4_m4x2_ck,
3379         &dpll4_m5_ck,
3380         &dpll4_m5x2_ck,
3381         &dpll4_m6_ck,
3382         &dpll4_m6x2_ck,
3383         &emu_per_alwon_ck,
3384         &dpll5_ck,
3385         &dpll5_m2_ck,
3386         &clkout2_src_ck,
3387         &sys_clkout2,
3388         &corex2_fck,
3389         &dpll1_fck,
3390         &mpu_ck,
3391         &arm_fck,
3392         &emu_mpu_alwon_ck,
3393         &dpll2_fck,
3394         &iva2_ck,
3395         &l3_ick,
3396         &l4_ick,
3397         &rm_ick,
3398         &gfx_l3_ck,
3399         &gfx_l3_fck,
3400         &gfx_l3_ick,
3401         &gfx_cg1_ck,
3402         &gfx_cg2_ck,
3403         &sgx_fck,
3404         &sgx_ick,
3405         &d2d_26m_fck,
3406         &gpt10_fck,
3407         &gpt11_fck,
3408         &cpefuse_fck,
3409         &ts_fck,
3410         &usbtll_fck,
3411         &core_96m_fck,
3412         &mmchs3_fck,
3413         &mmchs2_fck,
3414         &mspro_fck,
3415         &mmchs1_fck,
3416         &i2c3_fck,
3417         &i2c2_fck,
3418         &i2c1_fck,
3419         &mcbsp5_src_fck,
3420         &mcbsp5_fck,
3421         &mcbsp1_src_fck,
3422         &mcbsp1_fck,
3423         &core_48m_fck,
3424         &mcspi4_fck,
3425         &mcspi3_fck,
3426         &mcspi2_fck,
3427         &mcspi1_fck,
3428         &uart2_fck,
3429         &uart1_fck,
3430         &fshostusb_fck,
3431         &core_12m_fck,
3432         &hdq_fck,
3433         &ssi_ssr_fck_3430es1,
3434         &ssi_ssr_fck_3430es2,
3435         &ssi_sst_fck_3430es1,
3436         &ssi_sst_fck_3430es2,
3437         &core_l3_ick,
3438         &hsotgusb_ick_3430es1,
3439         &hsotgusb_ick_3430es2,
3440         &sdrc_ick,
3441         &gpmc_fck,
3442         &security_l3_ick,
3443         &pka_ick,
3444         &core_l4_ick,
3445         &usbtll_ick,
3446         &mmchs3_ick,
3447         &icr_ick,
3448         &aes2_ick,
3449         &sha12_ick,
3450         &des2_ick,
3451         &mmchs2_ick,
3452         &mmchs1_ick,
3453         &mspro_ick,
3454         &hdq_ick,
3455         &mcspi4_ick,
3456         &mcspi3_ick,
3457         &mcspi2_ick,
3458         &mcspi1_ick,
3459         &i2c3_ick,
3460         &i2c2_ick,
3461         &i2c1_ick,
3462         &uart2_ick,
3463         &uart1_ick,
3464         &gpt11_ick,
3465         &gpt10_ick,
3466         &mcbsp5_ick,
3467         &mcbsp1_ick,
3468         &fac_ick,
3469         &mailboxes_ick,
3470         &omapctrl_ick,
3471         &ssi_l4_ick,
3472         &ssi_ick_3430es1,
3473         &ssi_ick_3430es2,
3474         &usb_l4_ick,
3475         &security_l4_ick2,
3476         &aes1_ick,
3477         &rng_ick,
3478         &sha11_ick,
3479         &des1_ick,
3480         &dss1_alwon_fck_3430es1,
3481         &dss1_alwon_fck_3430es2,
3482         &dss_tv_fck,
3483         &dss_96m_fck,
3484         &dss2_alwon_fck,
3485         &dss_ick_3430es1,
3486         &dss_ick_3430es2,
3487         &cam_mclk,
3488         &cam_ick,
3489         &csi2_96m_fck,
3490         &usbhost_120m_fck,
3491         &usbhost_48m_fck,
3492         &usbhost_ick,
3493         &usim_fck,
3494         &gpt1_fck,
3495         &wkup_32k_fck,
3496         &gpio1_dbck,
3497         &wdt2_fck,
3498         &wkup_l4_ick,
3499         &usim_ick,
3500         &wdt2_ick,
3501         &wdt1_ick,
3502         &gpio1_ick,
3503         &omap_32ksync_ick,
3504         &gpt12_ick,
3505         &gpt1_ick,
3506         &per_96m_fck,
3507         &per_48m_fck,
3508         &uart3_fck,
3509         &gpt2_fck,
3510         &gpt3_fck,
3511         &gpt4_fck,
3512         &gpt5_fck,
3513         &gpt6_fck,
3514         &gpt7_fck,
3515         &gpt8_fck,
3516         &gpt9_fck,
3517         &per_32k_alwon_fck,
3518         &gpio6_dbck,
3519         &gpio5_dbck,
3520         &gpio4_dbck,
3521         &gpio3_dbck,
3522         &gpio2_dbck,
3523         &wdt3_fck,
3524         &per_l4_ick,
3525         &gpio6_ick,
3526         &gpio5_ick,
3527         &gpio4_ick,
3528         &gpio3_ick,
3529         &gpio2_ick,
3530         &wdt3_ick,
3531         &uart3_ick,
3532         &gpt9_ick,
3533         &gpt8_ick,
3534         &gpt7_ick,
3535         &gpt6_ick,
3536         &gpt5_ick,
3537         &gpt4_ick,
3538         &gpt3_ick,
3539         &gpt2_ick,
3540         &mcbsp2_ick,
3541         &mcbsp3_ick,
3542         &mcbsp4_ick,
3543         &mcbsp2_src_fck,
3544         &mcbsp2_fck,
3545         &mcbsp3_src_fck,
3546         &mcbsp3_fck,
3547         &mcbsp4_src_fck,
3548         &mcbsp4_fck,
3549         &emu_src_ck,
3550         &pclk_fck,
3551         &pclkx2_fck,
3552         &atclk_fck,
3553         &traceclk_src_fck,
3554         &traceclk_fck,
3555         &sr1_fck,
3556         &sr2_fck,
3557         &sr_l4_ick,
3558         &secure_32k_fck,
3559         &gpt12_fck,
3560         &wdt1_fck,
3561 };
3562
3563 #endif