arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007 Texas Instruments, Inc.
   5  * Copyright (C) 2007 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  */
   9
  10 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  11 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  12
  13 #include "clock.h"
  14 #include "cm.h"
  15 #include "cm_regbits_34xx.h"
  16 #include "prm.h"
  17 #include "prm_regbits_34xx.h"
  18 #include "control.h"
  19
  20 static void omap3_dpll_recalc(struct clk *clk);
  21 static void omap3_clkoutx2_recalc(struct clk *clk);
  22
  23 /*
  24  * DPLL1 supplies clock to the MPU.
  25  * DPLL2 supplies clock to the IVA2.
  26  * DPLL3 supplies CORE domain clocks.
  27  * DPLL4 supplies peripheral clocks.
  28  */
  29
  30 /* PRM CLOCKS */
  31
  32 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  33 static struct clk omap_32k_fck = {
  34         .name           = "omap_32k_fck",
  35         .rate           = 32768,
  36         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  37                                 ALWAYS_ENABLED,
  38         .recalc         = &propagate_rate,
  39 };
  40
  41 static struct clk secure_32k_fck = {
  42         .name           = "secure_32k_fck",
  43         .rate           = 32768,
  44         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  45                                 ALWAYS_ENABLED,
  46         .recalc         = &propagate_rate,
  47 };
  48
  49 /* Virtual source clocks for osc_sys_ck */
  50 static struct clk virt_12m_ck = {
  51         .name           = "virt_12m_ck",
  52         .rate           = 12000000,
  53         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  54                                 ALWAYS_ENABLED,
  55         .recalc         = &propagate_rate,
  56 };
  57
  58 static struct clk virt_13m_ck = {
  59         .name           = "virt_13m_ck",
  60         .rate           = 13000000,
  61         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  62                                 ALWAYS_ENABLED,
  63         .recalc         = &propagate_rate,
  64 };
  65
  66 /* 3430ES2 only */
  67 static struct clk virt_16_8m_ck = {
  68         .name           = "virt_16_8m_ck",
  69         .rate           = 16800000,
  70         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  71                                 ALWAYS_ENABLED,
  72         .recalc         = &propagate_rate,
  73 };
  74
  75 static struct clk virt_19_2m_ck = {
  76         .name           = "virt_19_2m_ck",
  77         .rate           = 19200000,
  78         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  79                                 ALWAYS_ENABLED,
  80         .recalc         = &propagate_rate,
  81 };
  82
  83 static struct clk virt_26m_ck = {
  84         .name           = "virt_26m_ck",
  85         .rate           = 26000000,
  86         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  87                                 ALWAYS_ENABLED,
  88         .recalc         = &propagate_rate,
  89 };
  90
  91 static struct clk virt_38_4m_ck = {
  92         .name           = "virt_38_4m_ck",
  93         .rate           = 38400000,
  94         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  95                                 ALWAYS_ENABLED,
  96         .recalc         = &propagate_rate,
  97 };
  98
  99 static const struct clksel_rate osc_sys_12m_rates[] = {
 100         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 101         { .div = 0 }
 102 };
 103
 104 static const struct clksel_rate osc_sys_13m_rates[] = {
 105         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 106         { .div = 0 }
 107 };
 108
 109 /* 3430ES2 only */
 110 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 111         { .div = 1, .val = 5, .flags = RATE_IN_343X | DEFAULT_RATE },
 112         { .div = 0 }
 113 };
 114
 115 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 116         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 117         { .div = 0 }
 118 };
 119
 120 static const struct clksel_rate osc_sys_26m_rates[] = {
 121         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 122         { .div = 0 }
 123 };
 124
 125 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 126         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 127         { .div = 0 }
 128 };
 129
 130 static const struct clksel osc_sys_clksel[] = {
 131         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 132         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 133         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 134         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 135         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 136         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 137         { .parent = NULL },
 138 };
 139
 140 /* Oscillator clock */
 141 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 142 static struct clk osc_sys_ck = {
 143         .name           = "osc_sys_ck",
 144         .init           = &omap2_init_clksel_parent,
 145         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 146         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 147         .clksel         = osc_sys_clksel,
 148         /* REVISIT: deal with autoextclkmode? */
 149         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 150                                 ALWAYS_ENABLED,
 151         .recalc         = &omap2_clksel_recalc,
 152 };
 153
 154 static const struct clksel_rate div2_rates[] = {
 155         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 156         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 157         { .div = 0 }
 158 };
 159
 160 static const struct clksel sys_clksel[] = {
 161         { .parent = &osc_sys_ck, .rates = div2_rates },
 162         { .parent = NULL }
 163 };
 164
 165 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 166 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 167 static struct clk sys_ck = {
 168         .name           = "sys_ck",
 169         .parent         = &osc_sys_ck,
 170         .init           = &omap2_init_clksel_parent,
 171         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 172         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 173         .clksel         = sys_clksel,
 174         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 175         .recalc         = &omap2_clksel_recalc,
 176 };
 177
 178 static struct clk sys_altclk = {
 179         .name           = "sys_altclk",
 180         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 181         .recalc         = &propagate_rate,
 182 };
 183
 184 /* Optional external clock input for some McBSPs */
 185 static struct clk mcbsp_clks = {
 186         .name           = "mcbsp_clks",
 187         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 188         .recalc         = &propagate_rate,
 189 };
 190
 191 /* PRM EXTERNAL CLOCK OUTPUT */
 192
 193 static struct clk sys_clkout1 = {
 194         .name           = "sys_clkout1",
 195         .parent         = &osc_sys_ck,
 196         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 197         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 198         .flags          = CLOCK_IN_OMAP343X,
 199         .recalc         = &followparent_recalc,
 200 };
 201
 202 /* DPLLS */
 203
 204 /* CM CLOCKS */
 205
 206 /* DPLL1 */
 207 /* MPU clock source */
 208 /* Type: DPLL */
 209 static const struct dpll_data dpll1_dd = {
 210         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 211         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 212         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 213         .div2_reg       = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 214         .div2_mask      = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 215         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 216         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 217         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 218         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 219         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 220 };
 221
 222 static struct clk dpll1_ck = {
 223         .name           = "dpll1_ck",
 224         .parent         = &sys_ck,
 225         .dpll_data      = &dpll1_dd,
 226         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 227         .recalc         = &omap3_dpll_recalc,
 228 };
 229
 230 /*
 231  * REVISIT: This clock is never specifically defined in the 3430 TRM,
 232  * although it is referenced - so this is a guess
 233  */
 234 static struct clk emu_mpu_alwon_ck = {
 235         .name           = "emu_mpu_alwon_ck",
 236         .parent         = &dpll1_ck,
 237         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 238                                 PARENT_CONTROLS_CLOCK,
 239         .recalc         = &followparent_recalc,
 240 };
 241
 242 /* DPLL2 */
 243 /* IVA2 clock source */
 244 /* Type: DPLL */
 245
 246 static const struct dpll_data dpll2_dd = {
 247         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 248         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 249         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 250         .div2_reg       = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL),
 251         .div2_mask      = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 252         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 253         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 254         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 255         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 256         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 257 };
 258
 259 static struct clk dpll2_ck = {
 260         .name           = "dpll2_ck",
 261         .parent         = &sys_ck,
 262         .dpll_data      = &dpll2_dd,
 263         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 264         .recalc         = &omap3_dpll_recalc,
 265 };
 266
 267 /* DPLL3 */
 268 /* Source clock for all interfaces and for some device fclks */
 269 /* Type: DPLL */
 270 static const struct dpll_data dpll3_dd = {
 271         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 272         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 273         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 274         .div2_reg       = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 275         .div2_mask      = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 276         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 277         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 278         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 279         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 280         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 281 };
 282
 283 static struct clk dpll3_ck = {
 284         .name           = "dpll3_ck",
 285         .parent         = &sys_ck,
 286         .dpll_data      = &dpll3_dd,
 287         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 288         .recalc         = &omap3_dpll_recalc,
 289 };
 290
 291 static const struct clksel_rate div16_dpll_rates[] = {
 292         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 293         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 294         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 295         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 296         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 297         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 298         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 299         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 300         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 301         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 302         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 303         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 304         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 305         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 306         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 307         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 308         { .div = 0 }
 309 };
 310
 311 static const struct clksel div2_dpll3m2_clksel[] = {
 312         { .parent = &dpll3_ck, .rates = div2_rates },
 313         { .parent = NULL }
 314 };
 315
 316 /*
 317  * REVISIT: Not sure what to do about clksel & these M2 divider clocks.
 318  * Shouldn't they be changed in SRAM?
 319  * This should probably remain a 'read-only' clksel clock.
 320  */
 321 static struct clk dpll3_m2_ck = {
 322         .name           = "dpll3_m2_ck",
 323         .parent         = &dpll3_ck,
 324         .init           = &omap2_init_clksel_parent,
 325         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 326         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 327         .clksel         = div2_dpll3m2_clksel,
 328         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 329                                 PARENT_CONTROLS_CLOCK,
 330         .recalc         = &omap2_clksel_recalc,
 331 };
 332
 333 static struct clk core_ck = {
 334         .name           = "core_ck",
 335         .parent         = &dpll3_m2_ck,
 336         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 337                                 PARENT_CONTROLS_CLOCK,
 338         .recalc         = &followparent_recalc,
 339 };
 340
 341 /*
 342  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 343  * DPLL isn't bypassed
 344  */
 345 static struct clk dpll3_x2_ck = {
 346         .name           = "dpll3_x2_ck",
 347         .parent         = &core_ck,
 348         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 349                                 PARENT_CONTROLS_CLOCK,
 350         .recalc         = &omap3_clkoutx2_recalc,
 351 };
 352
 353 static struct clk dpll3_m2x2_ck = {
 354         .name           = "dpll3_m2x2_ck",
 355         .parent         = &dpll3_x2_ck,
 356         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 357                                 PARENT_CONTROLS_CLOCK,
 358         .recalc         = &followparent_recalc,
 359 };
 360
 361 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 362 static struct clk dpll3_m3x2_ck = {
 363         .name           = "dpll3_m3x2_ck",
 364         .parent         = &dpll3_x2_ck,
 365         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 366         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 367         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 368         .recalc         = &followparent_recalc,
 369 };
 370
 371 static const struct clksel div16_dpll3_clksel[] = {
 372         { .parent = &dpll3_x2_ck, .rates = div16_dpll_rates },
 373         { .parent = NULL }
 374 };
 375
 376 static struct clk emu_core_alwon_ck = {
 377         .name           = "emu_core_alwon_ck",
 378         .parent         = &dpll3_x2_ck,
 379         .init           = &omap2_init_clksel_parent,
 380         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 381         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 382         .clksel         = div16_dpll3_clksel,
 383         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 384         .recalc         = &followparent_recalc,
 385 };
 386
 387 /* DPLL4 */
 388 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 389 /* Type: DPLL */
 390 static const struct dpll_data dpll4_dd = {
 391         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 392         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 393         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 394         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 395         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 396         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 397         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 398         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 399 };
 400
 401 static struct clk dpll4_ck = {
 402         .name           = "dpll4_ck",
 403         .parent         = &sys_ck,
 404         .dpll_data      = &dpll4_dd,
 405         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 406         .recalc         = &omap3_dpll_recalc,
 407 };
 408
 409 /*
 410  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 411  * DPLL isn't bypassed
 412  */
 413 static struct clk dpll4_x2_ck = {
 414         .name           = "dpll4_x2_ck",
 415         .parent         = &dpll4_ck,
 416         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 417                                 PARENT_CONTROLS_CLOCK,
 418         .recalc         = &omap3_clkoutx2_recalc,
 419 };
 420
 421 static const struct clksel div16_dpll4_clksel[] = {
 422         { .parent = &dpll4_x2_ck, .rates = div16_dpll_rates },
 423         { .parent = NULL }
 424 };
 425
 426 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 427 static struct clk dpll4_m2x2_ck = {
 428         .name           = "dpll4_m2x2_ck",
 429         .parent         = &dpll4_x2_ck,
 430         .init           = &omap2_init_clksel_parent,
 431         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 432         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 433         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 434         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 435         .clksel         = div16_dpll4_clksel,
 436         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 437         .recalc         = &omap2_clksel_recalc,
 438 };
 439
 440 static struct clk omap_96m_alwon_fck = {
 441         .name           = "omap_96m_alwon_fck",
 442         .parent         = &dpll4_m2x2_ck,
 443         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 444                                  PARENT_CONTROLS_CLOCK,
 445         .recalc         = &followparent_recalc,
 446 };
 447
 448 static struct clk omap_96m_fck = {
 449         .name           = "omap_96m_fck",
 450         .parent         = &omap_96m_alwon_fck,
 451         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 452                                 PARENT_CONTROLS_CLOCK,
 453         .recalc         = &followparent_recalc,
 454 };
 455
 456 static struct clk cm_96m_fck = {
 457         .name           = "cm_96m_fck",
 458         .parent         = &dpll4_m2x2_ck,
 459         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 460                                 PARENT_CONTROLS_CLOCK,
 461         .recalc         = &followparent_recalc,
 462 };
 463
 464 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 465 static struct clk dpll4_m3x2_ck = {
 466         .name           = "dpll4_m3x2_ck",
 467         .parent         = &dpll4_x2_ck,
 468         .init           = &omap2_init_clksel_parent,
 469         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 470         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 471         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 472         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 473         .clksel         = div16_dpll4_clksel,
 474         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 475         .recalc         = &omap2_clksel_recalc,
 476 };
 477
 478 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 479         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 480         { .div = 0 }
 481 };
 482
 483 static const struct clksel_rate omap_54m_alt_rates[] = {
 484         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 485         { .div = 0 }
 486 };
 487
 488 static const struct clksel omap_54m_clksel[] = {
 489         { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
 490         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 491         { .parent = NULL }
 492 };
 493
 494 static struct clk omap_54m_fck = {
 495         .name           = "omap_54m_fck",
 496         .init           = &omap2_init_clksel_parent,
 497         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 498         .clksel_mask    = OMAP3430_SOURCE_54M,
 499         .clksel         = omap_54m_clksel,
 500         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 501                                 PARENT_CONTROLS_CLOCK,
 502         .recalc         = &omap2_clksel_recalc,
 503 };
 504
 505 static const struct clksel_rate omap_48m_96md2_rates[] = {
 506         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 507         { .div = 0 }
 508 };
 509
 510 static const struct clksel_rate omap_48m_alt_rates[] = {
 511         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 512         { .div = 0 }
 513 };
 514
 515 static const struct clksel omap_48m_clksel[] = {
 516         { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
 517         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 518         { .parent = NULL }
 519 };
 520
 521 static struct clk omap_48m_fck = {
 522         .name           = "omap_48m_fck",
 523         .init           = &omap2_init_clksel_parent,
 524         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 525         .clksel_mask    = OMAP3430_SOURCE_48M,
 526         .clksel         = omap_48m_clksel,
 527         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 528                                 PARENT_CONTROLS_CLOCK,
 529         .recalc         = &omap2_clksel_recalc,
 530 };
 531
 532 static struct clk omap_12m_fck = {
 533         .name           = "omap_12m_fck",
 534         .parent         = &omap_48m_fck,
 535         .fixed_div      = 4,
 536         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 537                                 PARENT_CONTROLS_CLOCK,
 538         .recalc         = &omap2_fixed_divisor_recalc,
 539 };
 540
 541 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 542 static struct clk dpll4_m4x2_ck = {
 543         .name           = "dpll4_m4x2_ck",
 544         .parent         = &dpll4_x2_ck,
 545         .init           = &omap2_init_clksel_parent,
 546         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 547         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 548         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 549         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 550         .clksel         = div16_dpll4_clksel,
 551         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 552         .recalc         = &omap2_clksel_recalc,
 553 };
 554
 555 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 556 static struct clk dpll4_m5x2_ck = {
 557         .name           = "dpll4_m5x2_ck",
 558         .parent         = &dpll4_x2_ck,
 559         .init           = &omap2_init_clksel_parent,
 560         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 561         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 562         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 563         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 564         .clksel         = div16_dpll4_clksel,
 565         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 566         .recalc         = &omap2_clksel_recalc,
 567 };
 568
 569 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 570 static struct clk dpll4_m6x2_ck = {
 571         .name           = "dpll4_m6x2_ck",
 572         .parent         = &dpll4_x2_ck,
 573         .init           = &omap2_init_clksel_parent,
 574         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 575         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 576         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 577         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 578         .clksel         = div16_dpll4_clksel,
 579         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 580         .recalc         = &omap2_clksel_recalc,
 581 };
 582
 583 static struct clk emu_per_alwon_ck = {
 584         .name           = "emu_per_alwon_ck",
 585         .parent         = &dpll4_m6x2_ck,
 586         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 587                                 PARENT_CONTROLS_CLOCK,
 588         .recalc         = &followparent_recalc,
 589 };
 590
 591
 592 /* CM EXTERNAL CLOCK OUTPUTS */
 593
 594 static const struct clksel_rate clkout2_src_core_rates[] = {
 595         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 596         { .div = 0 }
 597 };
 598
 599 static const struct clksel_rate clkout2_src_sys_rates[] = {
 600         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 601         { .div = 0 }
 602 };
 603
 604 static const struct clksel_rate clkout2_src_96m_rates[] = {
 605         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 606         { .div = 0 }
 607 };
 608
 609 static const struct clksel_rate clkout2_src_54m_rates[] = {
 610         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 611         { .div = 0 }
 612 };
 613
 614 static const struct clksel clkout2_src_clksel[] = {
 615         { .parent = &core_ck,             .rates = clkout2_src_core_rates },
 616         { .parent = &sys_ck,              .rates = clkout2_src_sys_rates },
 617         { .parent = &omap_96m_alwon_fck,  .rates = clkout2_src_96m_rates },
 618         { .parent = &omap_54m_fck,        .rates = clkout2_src_54m_rates },
 619         { .parent = NULL }
 620 };
 621
 622 static struct clk clkout2_src_ck = {
 623         .name           = "clkout2_src_ck",
 624         .init           = &omap2_init_clksel_parent,
 625         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
 626         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 627         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 628         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 629         .clksel         = clkout2_src_clksel,
 630         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 631         .recalc         = &omap2_clksel_recalc,
 632 };
 633
 634 static const struct clksel_rate sys_clkout2_rates[] = {
 635         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 636         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 637         { .div = 4, .val = 2, .flags = RATE_IN_343X },
 638         { .div = 8, .val = 3, .flags = RATE_IN_343X },
 639         { .div = 16, .val = 4, .flags = RATE_IN_343X },
 640         { .div = 0 },
 641 };
 642
 643 static const struct clksel sys_clkout2_clksel[] = {
 644         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
 645         { .parent = NULL },
 646 };
 647
 648 static struct clk sys_clkout2 = {
 649         .name           = "sys_clkout2",
 650         .init           = &omap2_init_clksel_parent,
 651         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 652         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
 653         .clksel         = sys_clkout2_clksel,
 654         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 655         .recalc         = &omap2_clksel_recalc,
 656 };
 657
 658 /* CM OUTPUT CLOCKS */
 659
 660 static struct clk corex2_fck = {
 661         .name           = "corex2_fck",
 662         .parent         = &dpll3_m2x2_ck,
 663         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 664                                 PARENT_CONTROLS_CLOCK,
 665         .recalc         = &followparent_recalc,
 666 };
 667
 668 /* DPLL power domain clock controls */
 669
 670 static const struct clksel div2_core_clksel[] = {
 671         { .parent = &core_ck, .rates = div2_rates },
 672         { .parent = NULL }
 673 };
 674
 675 /* TRM s. 4.7.7.4 lists the input for these two clocks as CORE_CK,
 676    but presuming that is an error, or at least an overgeneralization */
 677 /* REVISIT: Are these in DPLL power domain or CM power domain?  docs
 678    may be inconsistent here? */
 679 static struct clk dpll1_fck = {
 680         .name           = "dpll1_fck",
 681         .parent         = &core_ck,
 682         .init           = &omap2_init_clksel_parent,
 683         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 684         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
 685         .clksel         = div2_core_clksel,
 686         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 687                                 PARENT_CONTROLS_CLOCK,
 688         .recalc         = &omap2_clksel_recalc,
 689 };
 690
 691 static struct clk dpll2_fck = {
 692         .name           = "dpll2_fck",
 693         .parent         = &core_ck,
 694         .init           = &omap2_init_clksel_parent,
 695         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 696         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
 697         .clksel         = div2_core_clksel,
 698         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 699                                 PARENT_CONTROLS_CLOCK,
 700         .recalc         = &omap2_clksel_recalc,
 701 };
 702
 703 /* Common interface clocks */
 704
 705 static struct clk l3_ick = {
 706         .name           = "l3_ick",
 707         .parent         = &core_ck,
 708         .init           = &omap2_init_clksel_parent,
 709         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 710         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
 711         .clksel         = div2_core_clksel,
 712         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 713                                 PARENT_CONTROLS_CLOCK,
 714         .recalc         = &omap2_clksel_recalc,
 715 };
 716
 717 static const struct clksel div2_l3_clksel[] = {
 718         { .parent = &l3_ick, .rates = div2_rates },
 719         { .parent = NULL }
 720 };
 721
 722 static struct clk l4_ick = {
 723         .name           = "l4_ick",
 724         .parent         = &l3_ick,
 725         .init           = &omap2_init_clksel_parent,
 726         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 727         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
 728         .clksel         = div2_l3_clksel,
 729         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 730                                 PARENT_CONTROLS_CLOCK,
 731         .recalc         = &omap2_clksel_recalc,
 732
 733 };
 734
 735 static const struct clksel div2_l4_clksel[] = {
 736         { .parent = &l4_ick, .rates = div2_rates },
 737         { .parent = NULL }
 738 };
 739
 740 static struct clk rm_ick = {
 741         .name           = "rm_ick",
 742         .parent         = &l4_ick,
 743         .init           = &omap2_init_clksel_parent,
 744         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
 745         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
 746         .clksel         = div2_l4_clksel,
 747         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 748         .recalc         = &omap2_clksel_recalc,
 749 };
 750
 751 /* GFX power domain */
 752
 753 /* REVISIT: These clocks have disappeared in the 3430 ES2 TRM ?? */
 754
 755 static const struct clksel gfx_l3_clksel[] = {
 756         { .parent = &l3_ick, .rates = gfx_l3_rates },
 757         { .parent = NULL }
 758 };
 759
 760 static struct clk gfx_l3_fck = {
 761         .name           = "gfx_l3_fck",
 762         .parent         = &l3_ick,
 763         .init           = &omap2_init_clksel_parent,
 764         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
 765         .enable_bit     = OMAP_EN_GFX_SHIFT,
 766         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
 767         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
 768         .clksel         = gfx_l3_clksel,
 769         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 770         .recalc         = &omap2_clksel_recalc,
 771 };
 772
 773 static struct clk gfx_l3_ick = {
 774         .name           = "gfx_l3_ick",
 775         .parent         = &l3_ick,
 776         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
 777         .enable_bit     = OMAP_EN_GFX_SHIFT,
 778         .flags          = CLOCK_IN_OMAP343X,
 779         .recalc         = &followparent_recalc,
 780 };
 781
 782 static struct clk gfx_cg1_ck = {
 783         .name           = "gfx_cg1_ck",
 784         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
 785         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
 786         .enable_bit     = OMAP3430_EN_2D_SHIFT,
 787         .flags          = CLOCK_IN_OMAP343X,
 788         .recalc         = &followparent_recalc,
 789 };
 790
 791 static struct clk gfx_cg2_ck = {
 792         .name           = "gfx_cg2_ck",
 793         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
 794         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
 795         .enable_bit     = OMAP3430_EN_3D_SHIFT,
 796         .flags          = CLOCK_IN_OMAP343X,
 797         .recalc         = &followparent_recalc,
 798 };
 799
 800 /* CORE power domain */
 801
 802 static struct clk d2d_26m_fck = {
 803         .name           = "d2d_26m_fck",
 804         .parent         = &sys_ck,
 805         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 806         .enable_bit     = OMAP3430_EN_D2D_SHIFT,
 807         .flags          = CLOCK_IN_OMAP343X,
 808         .recalc         = &followparent_recalc,
 809 };
 810
 811 static const struct clksel omap343x_gpt_clksel[] = {
 812         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
 813         { .parent = &sys_ck,       .rates = gpt_sys_rates },
 814         { .parent = NULL}
 815 };
 816
 817 static struct clk gpt10_fck = {
 818         .name           = "gpt10_fck",
 819         .parent         = &sys_ck,
 820         .init           = &omap2_init_clksel_parent,
 821         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 822         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
 823         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 824         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
 825         .clksel         = omap343x_gpt_clksel,
 826         .flags          = CLOCK_IN_OMAP343X,
 827         .recalc         = &omap2_clksel_recalc,
 828 };
 829
 830 static struct clk gpt11_fck = {
 831         .name           = "gpt11_fck",
 832         .parent         = &sys_ck,
 833         .init           = &omap2_init_clksel_parent,
 834         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 835         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
 836         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 837         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
 838         .clksel         = omap343x_gpt_clksel,
 839         .flags          = CLOCK_IN_OMAP343X,
 840         .recalc         = &omap2_clksel_recalc,
 841 };
 842
 843 /* CORE 96M FCLK-derived clocks */
 844
 845 static struct clk core_96m_fck = {
 846         .name           = "core_96m_fck",
 847         .parent         = &omap_96m_fck,
 848         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 849                                 PARENT_CONTROLS_CLOCK,
 850         .recalc         = &followparent_recalc,
 851 };
 852
 853 static struct clk mmc2_fck = {
 854         .name           = "mmc2_fck",
 855         .parent         = &core_96m_fck,
 856         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 857         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
 858         .flags          = CLOCK_IN_OMAP343X,
 859         .recalc         = &followparent_recalc,
 860 };
 861
 862 static struct clk mspro_fck = {
 863         .name           = "mspro_fck",
 864         .parent         = &core_96m_fck,
 865         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 866         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
 867         .flags          = CLOCK_IN_OMAP343X,
 868         .recalc         = &followparent_recalc,
 869 };
 870
 871 static struct clk mmc1_fck = {
 872         .name           = "mmc1_fck",
 873         .parent         = &core_96m_fck,
 874         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 875         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
 876         .flags          = CLOCK_IN_OMAP343X,
 877         .recalc         = &followparent_recalc,
 878 };
 879
 880 static struct clk i2c3_fck = {
 881         .name           = "i2c_fck",
 882         .id             = 3,
 883         .parent         = &core_96m_fck,
 884         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 885         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
 886         .flags          = CLOCK_IN_OMAP343X,
 887         .recalc         = &followparent_recalc,
 888 };
 889
 890 static struct clk i2c2_fck = {
 891         .name           = "i2c_fck",
 892         .id             = 2,
 893         .parent         = &core_96m_fck,
 894         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 895         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
 896         .flags          = CLOCK_IN_OMAP343X,
 897         .recalc         = &followparent_recalc,
 898 };
 899
 900 static struct clk i2c1_fck = {
 901         .name           = "i2c_fck",
 902         .id             = 1,
 903         .parent         = &core_96m_fck,
 904         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 905         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
 906         .flags          = CLOCK_IN_OMAP343X,
 907         .recalc         = &followparent_recalc,
 908 };
 909
 910 /*
 911  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
 912  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
 913  */
 914 static const struct clksel_rate common_mcbsp_96m_rates[] = {
 915         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 916         { .div = 0 }
 917 };
 918
 919 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
 920         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 921         { .div = 0 }
 922 };
 923
 924 static const struct clksel mcbsp_15_clksel[] = {
 925         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
 926         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
 927         { .parent = NULL }
 928 };
 929
 930 static struct clk mcbsp5_fck = {
 931         .name           = "mcbsp5_fck",
 932         .init           = &omap2_init_clksel_parent,
 933         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 934         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
 935         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
 936         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
 937         .clksel         = mcbsp_15_clksel,
 938         .flags          = CLOCK_IN_OMAP343X,
 939         .recalc         = &omap2_clksel_recalc,
 940 };
 941
 942 static struct clk mcbsp1_fck = {
 943         .name           = "mcbsp1_fck",
 944         .init           = &omap2_init_clksel_parent,
 945         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 946         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
 947         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
 948         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
 949         .clksel         = mcbsp_15_clksel,
 950         .flags          = CLOCK_IN_OMAP343X,
 951         .recalc         = &omap2_clksel_recalc,
 952 };
 953
 954 /* CORE_48M_FCK-derived clocks */
 955
 956 static struct clk core_48m_fck = {
 957         .name           = "core_48m_fck",
 958         .parent         = &omap_48m_fck,
 959         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 960                                 PARENT_CONTROLS_CLOCK,
 961         .recalc         = &followparent_recalc,
 962 };
 963
 964 static struct clk mcspi4_fck = {
 965         .name           = "mcspi4_fck",
 966         .parent         = &core_48m_fck,
 967         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 968         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
 969         .flags          = CLOCK_IN_OMAP343X,
 970         .recalc         = &followparent_recalc,
 971 };
 972
 973 static struct clk mcspi3_fck = {
 974         .name           = "mcspi3_fck",
 975         .parent         = &core_48m_fck,
 976         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 977         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
 978         .flags          = CLOCK_IN_OMAP343X,
 979         .recalc         = &followparent_recalc,
 980 };
 981
 982 static struct clk mcspi2_fck = {
 983         .name           = "mcspi2_fck",
 984         .parent         = &core_48m_fck,
 985         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 986         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
 987         .flags          = CLOCK_IN_OMAP343X,
 988         .recalc         = &followparent_recalc,
 989 };
 990
 991 static struct clk mcspi1_fck = {
 992         .name           = "mcspi1_fck",
 993         .parent         = &core_48m_fck,
 994         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 995         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
 996         .flags          = CLOCK_IN_OMAP343X,
 997         .recalc         = &followparent_recalc,
 998 };
 999
1000 static struct clk uart2_fck = {
1001         .name           = "uart2_fck",
1002         .parent         = &core_48m_fck,
1003         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1004         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1005         .flags          = CLOCK_IN_OMAP343X,
1006         .recalc         = &followparent_recalc,
1007 };
1008
1009 static struct clk uart1_fck = {
1010         .name           = "uart1_fck",
1011         .parent         = &core_48m_fck,
1012         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1013         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1014         .flags          = CLOCK_IN_OMAP343X,
1015         .recalc         = &followparent_recalc,
1016 };
1017
1018 static struct clk fshostusb_fck = {
1019         .name           = "fshostusb_fck",
1020         .parent         = &core_48m_fck,
1021         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1022         .enable_bit     = OMAP3430_EN_FSHOSTUSB_SHIFT,
1023         .flags          = CLOCK_IN_OMAP343X,
1024         .recalc         = &followparent_recalc,
1025 };
1026
1027 /* CORE_12M_FCK based clocks */
1028
1029 static struct clk core_12m_fck = {
1030         .name           = "core_12m_fck",
1031         .parent         = &omap_12m_fck,
1032         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1033                                 PARENT_CONTROLS_CLOCK,
1034         .recalc         = &followparent_recalc,
1035 };
1036
1037 static struct clk hdq_fck = {
1038         .name           = "hdq_fck",
1039         .parent         = &core_12m_fck,
1040         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1041         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1042         .flags          = CLOCK_IN_OMAP343X,
1043         .recalc         = &followparent_recalc,
1044 };
1045
1046 /* DPLL3-derived clock */
1047
1048 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1049         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1050         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1051         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1052         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1053         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1054         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1055         { .div = 0 }
1056 };
1057
1058 static const struct clksel ssi_ssr_clksel[] = {
1059         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1060         { .parent = NULL }
1061 };
1062
1063 static struct clk ssi_ssr_fck = {
1064         .name           = "ssi_ssr_fck",
1065         .init           = &omap2_init_clksel_parent,
1066         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1067         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1068         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1069         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1070         .clksel         = ssi_ssr_clksel,
1071         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1072         .recalc         = &omap2_clksel_recalc,
1073 };
1074
1075 static struct clk ssi_sst_fck = {
1076         .name           = "ssi_sst_fck",
1077         .parent         = &ssi_ssr_fck,
1078         .fixed_div      = 2,
1079         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1080         .recalc         = &omap2_fixed_divisor_recalc,
1081 };
1082
1083
1084
1085 /* CORE_L3_ICK based clocks */
1086
1087 static struct clk core_l3_ick = {
1088         .name           = "core_l3_ick",
1089         .parent         = &l3_ick,
1090         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1091                                 PARENT_CONTROLS_CLOCK,
1092         .recalc         = &followparent_recalc,
1093 };
1094
1095 static struct clk hsotgusb_ick = {
1096         .name           = "hsotgusb_ick",
1097         .parent         = &core_l3_ick,
1098         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1099         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1100         .flags          = CLOCK_IN_OMAP343X,
1101         .recalc         = &followparent_recalc,
1102 };
1103
1104 static struct clk sdrc_ick = {
1105         .name           = "sdrc_ick",
1106         .parent         = &core_l3_ick,
1107         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1108         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1109         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1110         .recalc         = &followparent_recalc,
1111 };
1112
1113 static struct clk gpmc_fck = {
1114         .name           = "gpmc_fck",
1115         .parent         = &core_l3_ick,
1116         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1117         .recalc         = &followparent_recalc,
1118 };
1119
1120 /* SECURITY_L3_ICK based clocks */
1121
1122 static struct clk security_l3_ick = {
1123         .name           = "security_l3_ick",
1124         .parent         = &l3_ick,
1125         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1126                                 PARENT_CONTROLS_CLOCK,
1127         .recalc         = &followparent_recalc,
1128 };
1129
1130 static struct clk pka_ick = {
1131         .name           = "pka_ick",
1132         .parent         = &security_l3_ick,
1133         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1134         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1135         .flags          = CLOCK_IN_OMAP343X,
1136         .recalc         = &followparent_recalc,
1137 };
1138
1139 /* CORE_L4_ICK based clocks */
1140
1141 static struct clk core_l4_ick = {
1142         .name           = "core_l4_ick",
1143         .parent         = &l4_ick,
1144         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1145                                 PARENT_CONTROLS_CLOCK,
1146         .recalc         = &followparent_recalc,
1147 };
1148
1149 /* Intersystem Communication Registers - chassis mode only */
1150 static struct clk icr_ick = {
1151         .name           = "icr_ick",
1152         .parent         = &core_l4_ick,
1153         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1154         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1155         .flags          = CLOCK_IN_OMAP343X,
1156         .recalc         = &followparent_recalc,
1157 };
1158
1159 static struct clk aes2_ick = {
1160         .name           = "aes2_ick",
1161         .parent         = &core_l4_ick,
1162         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1163         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1164         .flags          = CLOCK_IN_OMAP343X,
1165         .recalc         = &followparent_recalc,
1166 };
1167
1168 static struct clk sha12_ick = {
1169         .name           = "sha12_ick",
1170         .parent         = &core_l4_ick,
1171         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1172         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1173         .flags          = CLOCK_IN_OMAP343X,
1174         .recalc         = &followparent_recalc,
1175 };
1176
1177 static struct clk des2_ick = {
1178         .name           = "des2_ick",
1179         .parent         = &core_l4_ick,
1180         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1181         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1182         .flags          = CLOCK_IN_OMAP343X,
1183         .recalc         = &followparent_recalc,
1184 };
1185
1186 static struct clk mmc2_ick = {
1187         .name           = "mmc2_ick",
1188         .parent         = &core_l4_ick,
1189         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1190         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1191         .flags          = CLOCK_IN_OMAP343X,
1192         .recalc         = &followparent_recalc,
1193 };
1194
1195 static struct clk mmc1_ick = {
1196         .name           = "mmc1_ick",
1197         .parent         = &core_l4_ick,
1198         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1199         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1200         .flags          = CLOCK_IN_OMAP343X,
1201         .recalc         = &followparent_recalc,
1202 };
1203
1204 static struct clk mspro_ick = {
1205         .name           = "mspro_ick",
1206         .parent         = &core_l4_ick,
1207         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1208         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1209         .flags          = CLOCK_IN_OMAP343X,
1210         .recalc         = &followparent_recalc,
1211 };
1212
1213 static struct clk hdq_ick = {
1214         .name           = "hdq_ick",
1215         .parent         = &core_l4_ick,
1216         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1217         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1218         .flags          = CLOCK_IN_OMAP343X,
1219         .recalc         = &followparent_recalc,
1220 };
1221
1222 static struct clk mcspi4_ick = {
1223         .name           = "mcspi4_ick",
1224         .parent         = &core_l4_ick,
1225         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1226         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1227         .flags          = CLOCK_IN_OMAP343X,
1228         .recalc         = &followparent_recalc,
1229 };
1230
1231 static struct clk mcspi3_ick = {
1232         .name           = "mcspi3_ick",
1233         .parent         = &core_l4_ick,
1234         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1235         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1236         .flags          = CLOCK_IN_OMAP343X,
1237         .recalc         = &followparent_recalc,
1238 };
1239
1240 static struct clk mcspi2_ick = {
1241         .name           = "mcspi2_ick",
1242         .parent         = &core_l4_ick,
1243         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1244         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1245         .flags          = CLOCK_IN_OMAP343X,
1246         .recalc         = &followparent_recalc,
1247 };
1248
1249 static struct clk mcspi1_ick = {
1250         .name           = "mcspi1_ick",
1251         .parent         = &core_l4_ick,
1252         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1253         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1254         .flags          = CLOCK_IN_OMAP343X,
1255         .recalc         = &followparent_recalc,
1256 };
1257
1258 static struct clk i2c3_ick = {
1259         .name           = "i2c_ick",
1260         .id             = 3,
1261         .parent         = &core_l4_ick,
1262         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1263         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1264         .flags          = CLOCK_IN_OMAP343X,
1265         .recalc         = &followparent_recalc,
1266 };
1267
1268 static struct clk i2c2_ick = {
1269         .name           = "i2c_ick",
1270         .id             = 2,
1271         .parent         = &core_l4_ick,
1272         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1273         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1274         .flags          = CLOCK_IN_OMAP343X,
1275         .recalc         = &followparent_recalc,
1276 };
1277
1278 static struct clk i2c1_ick = {
1279         .name           = "i2c_ick",
1280         .id             = 1,
1281         .parent         = &core_l4_ick,
1282         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1283         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1284         .flags          = CLOCK_IN_OMAP343X,
1285         .recalc         = &followparent_recalc,
1286 };
1287
1288 static struct clk uart2_ick = {
1289         .name           = "uart2_ick",
1290         .parent         = &core_l4_ick,
1291         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1292         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1293         .flags          = CLOCK_IN_OMAP343X,
1294         .recalc         = &followparent_recalc,
1295 };
1296
1297 static struct clk uart1_ick = {
1298         .name           = "uart1_ick",
1299         .parent         = &core_l4_ick,
1300         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1301         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1302         .flags          = CLOCK_IN_OMAP343X,
1303         .recalc         = &followparent_recalc,
1304 };
1305
1306 static struct clk gpt11_ick = {
1307         .name           = "gpt11_ick",
1308         .parent         = &core_l4_ick,
1309         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1310         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1311         .flags          = CLOCK_IN_OMAP343X,
1312         .recalc         = &followparent_recalc,
1313 };
1314
1315 static struct clk gpt10_ick = {
1316         .name           = "gpt10_ick",
1317         .parent         = &core_l4_ick,
1318         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1319         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1320         .flags          = CLOCK_IN_OMAP343X,
1321         .recalc         = &followparent_recalc,
1322 };
1323
1324 static struct clk mcbsp5_ick = {
1325         .name           = "mcbsp5_ick",
1326         .parent         = &core_l4_ick,
1327         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1328         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1329         .flags          = CLOCK_IN_OMAP343X,
1330         .recalc         = &followparent_recalc,
1331 };
1332
1333 static struct clk mcbsp1_ick = {
1334         .name           = "mcbsp1_ick",
1335         .parent         = &core_l4_ick,
1336         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1337         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1338         .flags          = CLOCK_IN_OMAP343X,
1339         .recalc         = &followparent_recalc,
1340 };
1341
1342 static struct clk fac_ick = {
1343         .name           = "fac_ick",
1344         .parent         = &core_l4_ick,
1345         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1346         .enable_bit     = OMAP3430_EN_FAC_SHIFT,
1347         .flags          = CLOCK_IN_OMAP343X,
1348         .recalc         = &followparent_recalc,
1349 };
1350
1351 static struct clk mailboxes_ick = {
1352         .name           = "mailboxes_ick",
1353         .parent         = &core_l4_ick,
1354         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1355         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
1356         .flags          = CLOCK_IN_OMAP343X,
1357         .recalc         = &followparent_recalc,
1358 };
1359
1360 static struct clk omapctrl_ick = {
1361         .name           = "omapctrl_ick",
1362         .parent         = &core_l4_ick,
1363         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1364         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
1365         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1366         .recalc         = &followparent_recalc,
1367 };
1368
1369 /* SSI_L4_ICK based clocks */
1370
1371 static struct clk ssi_l4_ick = {
1372         .name           = "ssi_l4_ick",
1373         .parent         = &l4_ick,
1374         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1375         .recalc         = &followparent_recalc,
1376 };
1377
1378 static struct clk ssi_ick = {
1379         .name           = "ssi_ick",
1380         .parent         = &ssi_l4_ick,
1381         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1382         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1383         .flags          = CLOCK_IN_OMAP343X,
1384         .recalc         = &followparent_recalc,
1385 };
1386
1387 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
1388  * but l4_ick makes more sense to me */
1389
1390 static const struct clksel usb_l4_clksel[] = {
1391         { .parent = &l4_ick, .rates = div2_rates },
1392         { .parent = NULL },
1393 };
1394
1395 static struct clk usb_l4_ick = {
1396         .name           = "usb_l4_ick",
1397         .parent         = &l4_ick,
1398         .init           = &omap2_init_clksel_parent,
1399         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1400         .enable_bit     = OMAP3430_EN_FSHOSTUSB_SHIFT,
1401         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1402         .clksel_mask    = OMAP3430_CLKSEL_FSHOSTUSB_MASK,
1403         .clksel         = usb_l4_clksel,
1404         .flags          = CLOCK_IN_OMAP343X,
1405         .recalc         = &omap2_clksel_recalc,
1406 };
1407
1408 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
1409
1410 /* SECURITY_L4_ICK2 based clocks */
1411
1412 static struct clk security_l4_ick2 = {
1413         .name           = "security_l4_ick2",
1414         .parent         = &l4_ick,
1415         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1416                                 PARENT_CONTROLS_CLOCK,
1417         .recalc         = &followparent_recalc,
1418 };
1419
1420 static struct clk aes1_ick = {
1421         .name           = "aes1_ick",
1422         .parent         = &security_l4_ick2,
1423         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1424         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
1425         .flags          = CLOCK_IN_OMAP343X,
1426         .recalc         = &followparent_recalc,
1427 };
1428
1429 static struct clk rng_ick = {
1430         .name           = "rng_ick",
1431         .parent         = &security_l4_ick2,
1432         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1433         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
1434         .flags          = CLOCK_IN_OMAP343X,
1435         .recalc         = &followparent_recalc,
1436 };
1437
1438 static struct clk sha11_ick = {
1439         .name           = "sha11_ick",
1440         .parent         = &security_l4_ick2,
1441         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1442         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
1443         .flags          = CLOCK_IN_OMAP343X,
1444         .recalc         = &followparent_recalc,
1445 };
1446
1447 static struct clk des1_ick = {
1448         .name           = "des1_ick",
1449         .parent         = &security_l4_ick2,
1450         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1451         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
1452         .flags          = CLOCK_IN_OMAP343X,
1453         .recalc         = &followparent_recalc,
1454 };
1455
1456 /* DSS */
1457
1458 static struct clk dss1_alwon_fck = {
1459         .name           = "dss1_alwon_fck",
1460         .parent         = &dpll4_m4x2_ck,
1461         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1462         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
1463         .flags          = CLOCK_IN_OMAP343X,
1464         .recalc         = &followparent_recalc,
1465 };
1466
1467 static struct clk dss_tv_fck = {
1468         .name           = "dss_tv_fck",
1469         .parent         = &omap_54m_fck,
1470         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1471         .enable_bit     = OMAP3430_EN_TV_SHIFT,
1472         .flags          = CLOCK_IN_OMAP343X,
1473         .recalc         = &followparent_recalc,
1474 };
1475
1476 static struct clk dss_96m_fck = {
1477         .name           = "dss_96m_fck",
1478         .parent         = &omap_96m_fck,
1479         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1480         .enable_bit     = OMAP3430_EN_TV_SHIFT,
1481         .flags          = CLOCK_IN_OMAP343X,
1482         .recalc         = &followparent_recalc,
1483 };
1484
1485 static struct clk dss2_alwon_fck = {
1486         .name           = "dss2_alwon_fck",
1487         .parent         = &sys_ck,
1488         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1489         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
1490         .flags          = CLOCK_IN_OMAP343X,
1491         .recalc         = &followparent_recalc,
1492 };
1493
1494 static struct clk dss_ick = {
1495         /* Handles both L3 and L4 clocks */
1496         .name           = "dss_ick",
1497         .parent         = &l4_ick,
1498         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1499         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1500         .flags          = CLOCK_IN_OMAP343X,
1501         .recalc         = &followparent_recalc,
1502 };
1503
1504 /* CAM */
1505
1506 static struct clk cam_mclk = {
1507         .name           = "cam_mclk",
1508         .parent         = &dpll4_m5x2_ck,
1509         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
1510         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
1511         .flags          = CLOCK_IN_OMAP343X,
1512         .recalc         = &followparent_recalc,
1513 };
1514
1515 static struct clk cam_l3_ick = {
1516         .name           = "cam_l3_ick",
1517         .parent         = &l3_ick,
1518         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
1519         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
1520         .flags          = CLOCK_IN_OMAP343X,
1521         .recalc         = &followparent_recalc,
1522 };
1523
1524 static struct clk cam_l4_ick = {
1525         .name           = "cam_l4_ick",
1526         .parent         = &l4_ick,
1527         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
1528         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
1529         .flags          = CLOCK_IN_OMAP343X,
1530         .recalc         = &followparent_recalc,
1531 };
1532
1533 /* WKUP */
1534
1535 static struct clk gpt1_fck = {
1536         .name           = "gpt1_fck",
1537         .init           = &omap2_init_clksel_parent,
1538         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1539         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
1540         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1541         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
1542         .clksel         = omap343x_gpt_clksel,
1543         .flags          = CLOCK_IN_OMAP343X,
1544         .recalc         = &omap2_clksel_recalc,
1545 };
1546
1547 static struct clk wkup_32k_fck = {
1548         .name           = "wkup_32k_fck",
1549         .parent         = &omap_32k_fck,
1550         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
1551         .recalc         = &followparent_recalc,
1552 };
1553
1554 static struct clk gpio1_fck = {
1555         .name           = "gpio1_fck",
1556         .parent         = &wkup_32k_fck,
1557         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1558         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
1559         .flags          = CLOCK_IN_OMAP343X,
1560         .recalc         = &followparent_recalc,
1561 };
1562
1563 static struct clk wdt2_fck = {
1564         .name           = "wdt2_fck",
1565         .parent         = &wkup_32k_fck,
1566         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1567         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
1568         .flags          = CLOCK_IN_OMAP343X,
1569         .recalc         = &followparent_recalc,
1570 };
1571
1572 static struct clk wkup_l4_ick = {
1573         .name           = "wkup_l4_ick",
1574         .parent         = &sys_ck,
1575         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
1576         .recalc         = &followparent_recalc,
1577 };
1578
1579 static struct clk wdt2_ick = {
1580         .name           = "wdt2_ick",
1581         .parent         = &wkup_l4_ick,
1582         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1583         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
1584         .flags          = CLOCK_IN_OMAP343X,
1585         .recalc         = &followparent_recalc,
1586 };
1587
1588 static struct clk wdt1_ick = {
1589         .name           = "wdt1_ick",
1590         .parent         = &wkup_l4_ick,
1591         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1592         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
1593         .flags          = CLOCK_IN_OMAP343X,
1594         .recalc         = &followparent_recalc,
1595 };
1596
1597 static struct clk gpio1_ick = {
1598         .name           = "gpio1_ick",
1599         .parent         = &wkup_l4_ick,
1600         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1601         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
1602         .flags          = CLOCK_IN_OMAP343X,
1603         .recalc         = &followparent_recalc,
1604 };
1605
1606 static struct clk omap_32ksync_ick = {
1607         .name           = "omap_32ksync_ick",
1608         .parent         = &wkup_l4_ick,
1609         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1610         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
1611         .flags          = CLOCK_IN_OMAP343X,
1612         .recalc         = &followparent_recalc,
1613 };
1614
1615 static struct clk gpt12_ick = {
1616         .name           = "gpt12_ick",
1617         .parent         = &wkup_l4_ick,
1618         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1619         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
1620         .flags          = CLOCK_IN_OMAP343X,
1621         .recalc         = &followparent_recalc,
1622 };
1623
1624 static struct clk gpt1_ick = {
1625         .name           = "gpt1_ick",
1626         .parent         = &wkup_l4_ick,
1627         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1628         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
1629         .flags          = CLOCK_IN_OMAP343X,
1630         .recalc         = &followparent_recalc,
1631 };
1632
1633
1634
1635 /* PER clock domain */
1636
1637 static struct clk per_96m_fck = {
1638         .name           = "per_96m_fck",
1639         .parent         = &omap_96m_alwon_fck,
1640         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1641                                 PARENT_CONTROLS_CLOCK,
1642         .recalc         = &followparent_recalc,
1643 };
1644
1645 static struct clk per_48m_fck = {
1646         .name           = "per_48m_fck",
1647         .parent         = &omap_48m_fck,
1648         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1649                                 PARENT_CONTROLS_CLOCK,
1650         .recalc         = &followparent_recalc,
1651 };
1652
1653 static struct clk uart3_fck = {
1654         .name           = "uart3_fck",
1655         .parent         = &per_48m_fck,
1656         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1657         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
1658         .flags          = CLOCK_IN_OMAP343X,
1659         .recalc         = &followparent_recalc,
1660 };
1661
1662 static struct clk gpt2_fck = {
1663         .name           = "gpt2_fck",
1664         .init           = &omap2_init_clksel_parent,
1665         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1666         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
1667         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1668         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
1669         .clksel         = omap343x_gpt_clksel,
1670         .flags          = CLOCK_IN_OMAP343X,
1671         .recalc         = &omap2_clksel_recalc,
1672 };
1673
1674 static struct clk gpt3_fck = {
1675         .name           = "gpt3_fck",
1676         .init           = &omap2_init_clksel_parent,
1677         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1678         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
1679         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1680         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
1681         .clksel         = omap343x_gpt_clksel,
1682         .flags          = CLOCK_IN_OMAP343X,
1683         .recalc         = &omap2_clksel_recalc,
1684 };
1685
1686 static struct clk gpt4_fck = {
1687         .name           = "gpt4_fck",
1688         .init           = &omap2_init_clksel_parent,
1689         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1690         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
1691         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1692         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
1693         .clksel         = omap343x_gpt_clksel,
1694         .flags          = CLOCK_IN_OMAP343X,
1695         .recalc         = &omap2_clksel_recalc,
1696 };
1697
1698 static struct clk gpt5_fck = {
1699         .name           = "gpt5_fck",
1700         .init           = &omap2_init_clksel_parent,
1701         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1702         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
1703         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1704         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
1705         .clksel         = omap343x_gpt_clksel,
1706         .flags          = CLOCK_IN_OMAP343X,
1707         .recalc         = &omap2_clksel_recalc,
1708 };
1709
1710 static struct clk gpt6_fck = {
1711         .name           = "gpt6_fck",
1712         .init           = &omap2_init_clksel_parent,
1713         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1714         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
1715         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1716         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
1717         .clksel         = omap343x_gpt_clksel,
1718         .flags          = CLOCK_IN_OMAP343X,
1719         .recalc         = &omap2_clksel_recalc,
1720 };
1721
1722 static struct clk gpt7_fck = {
1723         .name           = "gpt7_fck",
1724         .init           = &omap2_init_clksel_parent,
1725         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1726         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
1727         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1728         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
1729         .clksel         = omap343x_gpt_clksel,
1730         .flags          = CLOCK_IN_OMAP343X,
1731         .recalc         = &omap2_clksel_recalc,
1732 };
1733
1734 static struct clk gpt8_fck = {
1735         .name           = "gpt8_fck",
1736         .init           = &omap2_init_clksel_parent,
1737         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1738         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
1739         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1740         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
1741         .clksel         = omap343x_gpt_clksel,
1742         .flags          = CLOCK_IN_OMAP343X,
1743         .recalc         = &omap2_clksel_recalc,
1744 };
1745
1746 static struct clk gpt9_fck = {
1747         .name           = "gpt9_fck",
1748         .init           = &omap2_init_clksel_parent,
1749         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1750         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
1751         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1752         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
1753         .clksel         = omap343x_gpt_clksel,
1754         .flags          = CLOCK_IN_OMAP343X,
1755         .recalc         = &omap2_clksel_recalc,
1756 };
1757
1758 static struct clk per_32k_alwon_fck = {
1759         .name           = "per_32k_alwon_fck",
1760         .parent         = &omap_32k_fck,
1761         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
1762         .recalc         = &followparent_recalc,
1763 };
1764
1765 static struct clk gpio6_fck = {
1766         .name           = "gpio6_fck",
1767         .parent         = &per_32k_alwon_fck,
1768         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1769         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
1770         .flags          = CLOCK_IN_OMAP343X,
1771         .recalc         = &followparent_recalc,
1772 };
1773
1774 static struct clk gpio5_fck = {
1775         .name           = "gpio5_fck",
1776         .parent         = &per_32k_alwon_fck,
1777         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1778         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
1779         .flags          = CLOCK_IN_OMAP343X,
1780         .recalc         = &followparent_recalc,
1781 };
1782
1783 static struct clk gpio4_fck = {
1784         .name           = "gpio4_fck",
1785         .parent         = &per_32k_alwon_fck,
1786         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1787         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
1788         .flags          = CLOCK_IN_OMAP343X,
1789         .recalc         = &followparent_recalc,
1790 };
1791
1792 static struct clk gpio3_fck = {
1793         .name           = "gpio3_fck",
1794         .parent         = &per_32k_alwon_fck,
1795         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1796         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
1797         .flags          = CLOCK_IN_OMAP343X,
1798         .recalc         = &followparent_recalc,
1799 };
1800
1801 static struct clk gpio2_fck = {
1802         .name           = "gpio2_fck",
1803         .parent         = &per_32k_alwon_fck,
1804         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1805         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
1806         .flags          = CLOCK_IN_OMAP343X,
1807         .recalc         = &followparent_recalc,
1808 };
1809
1810 static struct clk wdt3_fck = {
1811         .name           = "wdt3_fck",
1812         .parent         = &per_32k_alwon_fck,
1813         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1814         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
1815         .flags          = CLOCK_IN_OMAP343X,
1816         .recalc         = &followparent_recalc,
1817 };
1818
1819 static struct clk per_l4_ick = {
1820         .name           = "per_l4_ick",
1821         .parent         = &l4_ick,
1822         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1823                                 PARENT_CONTROLS_CLOCK,
1824         .recalc         = &followparent_recalc,
1825 };
1826
1827 static struct clk gpio6_ick = {
1828         .name           = "gpio6_ick",
1829         .parent         = &per_l4_ick,
1830         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1831         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
1832         .flags          = CLOCK_IN_OMAP343X,
1833         .recalc         = &followparent_recalc,
1834 };
1835
1836 static struct clk gpio5_ick = {
1837         .name           = "gpio5_ick",
1838         .parent         = &per_l4_ick,
1839         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1840         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
1841         .flags          = CLOCK_IN_OMAP343X,
1842         .recalc         = &followparent_recalc,
1843 };
1844
1845 static struct clk gpio4_ick = {
1846         .name           = "gpio4_ick",
1847         .parent         = &per_l4_ick,
1848         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1849         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
1850         .flags          = CLOCK_IN_OMAP343X,
1851         .recalc         = &followparent_recalc,
1852 };
1853
1854 static struct clk gpio3_ick = {
1855         .name           = "gpio3_ick",
1856         .parent         = &per_l4_ick,
1857         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1858         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
1859         .flags          = CLOCK_IN_OMAP343X,
1860         .recalc         = &followparent_recalc,
1861 };
1862
1863 static struct clk gpio2_ick = {
1864         .name           = "gpio2_ick",
1865         .parent         = &per_l4_ick,
1866         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1867         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
1868         .flags          = CLOCK_IN_OMAP343X,
1869         .recalc         = &followparent_recalc,
1870 };
1871
1872 static struct clk wdt3_ick = {
1873         .name           = "wdt3_ick",
1874         .parent         = &per_l4_ick,
1875         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1876         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
1877         .flags          = CLOCK_IN_OMAP343X,
1878         .recalc         = &followparent_recalc,
1879 };
1880
1881 static struct clk uart3_ick = {
1882         .name           = "uart3_ick",
1883         .parent         = &per_l4_ick,
1884         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1885         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
1886         .flags          = CLOCK_IN_OMAP343X,
1887         .recalc         = &followparent_recalc,
1888 };
1889
1890 static struct clk gpt9_ick = {
1891         .name           = "gpt9_ick",
1892         .parent         = &per_l4_ick,
1893         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1894         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
1895         .flags          = CLOCK_IN_OMAP343X,
1896         .recalc         = &followparent_recalc,
1897 };
1898
1899 static struct clk gpt8_ick = {
1900         .name           = "gpt8_ick",
1901         .parent         = &per_l4_ick,
1902         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1903         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
1904         .flags          = CLOCK_IN_OMAP343X,
1905         .recalc         = &followparent_recalc,
1906 };
1907
1908 static struct clk gpt7_ick = {
1909         .name           = "gpt7_ick",
1910         .parent         = &per_l4_ick,
1911         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1912         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
1913         .flags          = CLOCK_IN_OMAP343X,
1914         .recalc         = &followparent_recalc,
1915 };
1916
1917 static struct clk gpt6_ick = {
1918         .name           = "gpt6_ick",
1919         .parent         = &per_l4_ick,
1920         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1921         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
1922         .flags          = CLOCK_IN_OMAP343X,
1923         .recalc         = &followparent_recalc,
1924 };
1925
1926 static struct clk gpt5_ick = {
1927         .name           = "gpt5_ick",
1928         .parent         = &per_l4_ick,
1929         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1930         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
1931         .flags          = CLOCK_IN_OMAP343X,
1932         .recalc         = &followparent_recalc,
1933 };
1934
1935 static struct clk gpt4_ick = {
1936         .name           = "gpt4_ick",
1937         .parent         = &per_l4_ick,
1938         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1939         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
1940         .flags          = CLOCK_IN_OMAP343X,
1941         .recalc         = &followparent_recalc,
1942 };
1943
1944 static struct clk gpt3_ick = {
1945         .name           = "gpt3_ick",
1946         .parent         = &per_l4_ick,
1947         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1948         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
1949         .flags          = CLOCK_IN_OMAP343X,
1950         .recalc         = &followparent_recalc,
1951 };
1952
1953 static struct clk gpt2_ick = {
1954         .name           = "gpt2_ick",
1955         .parent         = &per_l4_ick,
1956         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1957         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
1958         .flags          = CLOCK_IN_OMAP343X,
1959         .recalc         = &followparent_recalc,
1960 };
1961
1962 static struct clk mcbsp2_ick = {
1963         .name           = "mcbsp2_ick",
1964         .parent         = &per_l4_ick,
1965         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1966         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
1967         .flags          = CLOCK_IN_OMAP343X,
1968         .recalc         = &followparent_recalc,
1969 };
1970
1971 static struct clk mcbsp3_ick = {
1972         .name           = "mcbsp3_ick",
1973         .parent         = &per_l4_ick,
1974         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1975         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
1976         .flags          = CLOCK_IN_OMAP343X,
1977         .recalc         = &followparent_recalc,
1978 };
1979
1980 static struct clk mcbsp4_ick = {
1981         .name           = "mcbsp4_ick",
1982         .parent         = &per_l4_ick,
1983         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1984         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
1985         .flags          = CLOCK_IN_OMAP343X,
1986         .recalc         = &followparent_recalc,
1987 };
1988
1989 static const struct clksel mcbsp_234_clksel[] = {
1990         { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
1991         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1992         { .parent = NULL }
1993 };
1994
1995 static struct clk mcbsp2_fck = {
1996         .name           = "mcbsp2_fck",
1997         .init           = &omap2_init_clksel_parent,
1998         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1999         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2000         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2001         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2002         .clksel         = mcbsp_234_clksel,
2003         .flags          = CLOCK_IN_OMAP343X,
2004         .recalc         = &omap2_clksel_recalc,
2005 };
2006
2007 static struct clk mcbsp3_fck = {
2008         .name           = "mcbsp3_fck",
2009         .init           = &omap2_init_clksel_parent,
2010         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2011         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2012         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2013         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2014         .clksel         = mcbsp_234_clksel,
2015         .flags          = CLOCK_IN_OMAP343X,
2016         .recalc         = &omap2_clksel_recalc,
2017 };
2018
2019 static struct clk mcbsp4_fck = {
2020         .name           = "mcbsp4_fck",
2021         .init           = &omap2_init_clksel_parent,
2022         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2023         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2024         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2025         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2026         .clksel         = mcbsp_234_clksel,
2027         .flags          = CLOCK_IN_OMAP343X,
2028         .recalc         = &omap2_clksel_recalc,
2029 };
2030
2031 /* EMU clocks */
2032
2033 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2034
2035 static const struct clksel_rate emu_src_sys_rates[] = {
2036         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2037         { .div = 0 },
2038 };
2039
2040 static const struct clksel_rate emu_src_core_rates[] = {
2041         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2042         { .div = 0 },
2043 };
2044
2045 static const struct clksel_rate emu_src_per_rates[] = {
2046         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2047         { .div = 0 },
2048 };
2049
2050 static const struct clksel_rate emu_src_mpu_rates[] = {
2051         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2052         { .div = 0 },
2053 };
2054
2055 static const struct clksel emu_src_clksel[] = {
2056         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2057         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2058         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2059         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2060         { .parent = NULL },
2061 };
2062
2063 /*
2064  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2065  * to switch the source of some of the EMU clocks.
2066  * XXX Are there CLKEN bits for these EMU clks?
2067  */
2068 static struct clk emu_src_ck = {
2069         .name           = "emu_src_ck",
2070         .init           = &omap2_init_clksel_parent,
2071         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2072         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2073         .clksel         = emu_src_clksel,
2074         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2075         .recalc         = &omap2_clksel_recalc,
2076 };
2077
2078 static const struct clksel_rate pclk_emu_rates[] = {
2079         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2080         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2081         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2082         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2083         { .div = 0 },
2084 };
2085
2086 static const struct clksel pclk_emu_clksel[] = {
2087         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2088         { .parent = NULL },
2089 };
2090
2091 static struct clk pclk_fck = {
2092         .name           = "pclk_fck",
2093         .init           = &omap2_init_clksel_parent,
2094         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2095         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2096         .clksel         = pclk_emu_clksel,
2097         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2098         .recalc         = &omap2_clksel_recalc,
2099 };
2100
2101 static const struct clksel_rate pclkx2_emu_rates[] = {
2102         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2103         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2104         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2105         { .div = 0 },
2106 };
2107
2108 static const struct clksel pclkx2_emu_clksel[] = {
2109         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2110         { .parent = NULL },
2111 };
2112
2113 static struct clk pclkx2_fck = {
2114         .name           = "pclkx2_fck",
2115         .init           = &omap2_init_clksel_parent,
2116         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2117         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2118         .clksel         = pclkx2_emu_clksel,
2119         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2120         .recalc         = &omap2_clksel_recalc,
2121 };
2122
2123 static const struct clksel atclk_emu_clksel[] = {
2124         { .parent = &emu_src_ck, .rates = div2_rates },
2125         { .parent = NULL },
2126 };
2127
2128 static struct clk atclk_fck = {
2129         .name           = "atclk_fck",
2130         .init           = &omap2_init_clksel_parent,
2131         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2132         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2133         .clksel         = atclk_emu_clksel,
2134         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2135         .recalc         = &omap2_clksel_recalc,
2136 };
2137
2138 static struct clk traceclk_src_fck = {
2139         .name           = "traceclk_src_fck",
2140         .init           = &omap2_init_clksel_parent,
2141         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2142         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2143         .clksel         = emu_src_clksel,
2144         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2145         .recalc         = &omap2_clksel_recalc,
2146 };
2147
2148 static const struct clksel_rate traceclk_rates[] = {
2149         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2150         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2151         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2152         { .div = 0 },
2153 };
2154
2155 static const struct clksel traceclk_clksel[] = {
2156         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2157         { .parent = NULL },
2158 };
2159
2160 static struct clk traceclk_fck = {
2161         .name           = "traceclk_fck",
2162         .init           = &omap2_init_clksel_parent,
2163         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2164         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
2165         .clksel         = traceclk_clksel,
2166         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2167         .recalc         = &omap2_clksel_recalc,
2168 };
2169
2170 /* SR clocks */
2171
2172 /* SmartReflex fclk (VDD1) */
2173 static struct clk sr1_fck = {
2174         .name           = "sr1_fck",
2175         .parent         = &sys_ck,
2176         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2177         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
2178         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2179         .recalc         = &followparent_recalc,
2180 };
2181
2182 /* SmartReflex fclk (VDD2) */
2183 static struct clk sr2_fck = {
2184         .name           = "sr2_fck",
2185         .parent         = &sys_ck,
2186         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2187         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
2188         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2189         .recalc         = &followparent_recalc,
2190 };
2191
2192 static struct clk sr_l4_ick = {
2193         .name           = "sr_l4_ick",
2194         .parent         = &l4_ick,
2195         .flags          = CLOCK_IN_OMAP343X,
2196         .recalc         = &followparent_recalc,
2197 };
2198
2199 /* SECURE_32K_FCK clocks */
2200
2201 static struct clk gpt12_fck = {
2202         .name           = "gpt12_fck",
2203         .parent         = &secure_32k_fck,
2204         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2205         .recalc         = &followparent_recalc,
2206 };
2207
2208 static struct clk wdt1_fck = {
2209         .name           = "wdt1_fck",
2210         .parent         = &secure_32k_fck,
2211         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2212         .recalc         = &followparent_recalc,
2213 };
2214
2215
2216 static struct clk *onchip_34xx_clks[] __initdata = {
2217         &omap_32k_fck,
2218         &virt_12m_ck,
2219         &virt_13m_ck,
2220         &virt_16_8m_ck,
2221         &virt_19_2m_ck,
2222         &virt_26m_ck,
2223         &virt_38_4m_ck,
2224         &osc_sys_ck,
2225         &sys_ck,
2226         &sys_altclk,
2227         &sys_clkout1,
2228         &dpll1_ck,
2229         &emu_mpu_alwon_ck,
2230         &dpll2_ck,
2231         &dpll3_ck,
2232         &core_ck,
2233         &dpll3_x2_ck,
2234         &dpll3_m2_ck,
2235         &dpll3_m2x2_ck,
2236         &dpll3_m3x2_ck,
2237         &emu_core_alwon_ck,
2238         &dpll4_ck,
2239         &dpll4_x2_ck,
2240         &omap_96m_alwon_fck,
2241         &omap_96m_fck,
2242         &cm_96m_fck,
2243         &omap_54m_fck,
2244         &omap_48m_fck,
2245         &omap_12m_fck,
2246         &dpll4_m2x2_ck,
2247         &dpll4_m3x2_ck,
2248         &dpll4_m4x2_ck,
2249         &dpll4_m5x2_ck,
2250         &dpll4_m6x2_ck,
2251         &emu_per_alwon_ck,
2252         &clkout2_src_ck,
2253         &sys_clkout2,
2254         &corex2_fck,
2255         &dpll1_fck,
2256         &dpll2_fck,
2257         &l3_ick,
2258         &l4_ick,
2259         &rm_ick,
2260         &gfx_l3_fck,
2261         &gfx_l3_ick,
2262         &gfx_cg1_ck,
2263         &gfx_cg2_ck,
2264         &d2d_26m_fck,
2265         &gpt10_fck,
2266         &gpt11_fck,
2267         &core_96m_fck,
2268         &mmc2_fck,
2269         &mspro_fck,
2270         &mmc1_fck,
2271         &i2c3_fck,
2272         &i2c2_fck,
2273         &i2c1_fck,
2274         &mcbsp5_fck,
2275         &mcbsp1_fck,
2276         &core_48m_fck,
2277         &mcspi4_fck,
2278         &mcspi3_fck,
2279         &mcspi2_fck,
2280         &mcspi1_fck,
2281         &uart2_fck,
2282         &uart1_fck,
2283         &fshostusb_fck,
2284         &core_12m_fck,
2285         &hdq_fck,
2286         &ssi_ssr_fck,
2287         &ssi_sst_fck,
2288         &core_l3_ick,
2289         &hsotgusb_ick,
2290         &sdrc_ick,
2291         &gpmc_fck,
2292         &security_l3_ick,
2293         &pka_ick,
2294         &core_l4_ick,
2295         &icr_ick,
2296         &aes2_ick,
2297         &sha12_ick,
2298         &des2_ick,
2299         &mmc2_ick,
2300         &mmc1_ick,
2301         &mspro_ick,
2302         &hdq_ick,
2303         &mcspi4_ick,
2304         &mcspi3_ick,
2305         &mcspi2_ick,
2306         &mcspi1_ick,
2307         &i2c3_ick,
2308         &i2c2_ick,
2309         &i2c1_ick,
2310         &uart2_ick,
2311         &uart1_ick,
2312         &gpt11_ick,
2313         &gpt10_ick,
2314         &mcbsp5_ick,
2315         &mcbsp1_ick,
2316         &fac_ick,
2317         &mailboxes_ick,
2318         &omapctrl_ick,
2319         &ssi_l4_ick,
2320         &ssi_ick,
2321         &usb_l4_ick,
2322         &security_l4_ick2,
2323         &aes1_ick,
2324         &rng_ick,
2325         &sha11_ick,
2326         &des1_ick,
2327         &dss1_alwon_fck,
2328         &dss_tv_fck,
2329         &dss_96m_fck,
2330         &dss2_alwon_fck,
2331         &dss_ick,
2332         &cam_mclk,
2333         &cam_l3_ick,
2334         &cam_l4_ick,
2335         &gpt1_fck,
2336         &wkup_32k_fck,
2337         &gpio1_fck,
2338         &wdt2_fck,
2339         &wkup_l4_ick,
2340         &wdt2_ick,
2341         &wdt1_ick,
2342         &gpio1_ick,
2343         &omap_32ksync_ick,
2344         &gpt12_ick,
2345         &gpt1_ick,
2346         &per_96m_fck,
2347         &per_48m_fck,
2348         &uart3_fck,
2349         &gpt2_fck,
2350         &gpt3_fck,
2351         &gpt4_fck,
2352         &gpt5_fck,
2353         &gpt6_fck,
2354         &gpt7_fck,
2355         &gpt8_fck,
2356         &gpt9_fck,
2357         &per_32k_alwon_fck,
2358         &gpio6_fck,
2359         &gpio5_fck,
2360         &gpio4_fck,
2361         &gpio3_fck,
2362         &gpio2_fck,
2363         &wdt3_fck,
2364         &per_l4_ick,
2365         &gpio6_ick,
2366         &gpio5_ick,
2367         &gpio4_ick,
2368         &gpio3_ick,
2369         &gpio2_ick,
2370         &wdt3_ick,
2371         &uart3_ick,
2372         &gpt9_ick,
2373         &gpt8_ick,
2374         &gpt7_ick,
2375         &gpt6_ick,
2376         &gpt5_ick,
2377         &gpt4_ick,
2378         &gpt3_ick,
2379         &gpt2_ick,
2380         &mcbsp2_ick,
2381         &mcbsp3_ick,
2382         &mcbsp4_ick,
2383         &mcbsp2_fck,
2384         &mcbsp3_fck,
2385         &mcbsp4_fck,
2386         &emu_src_ck,
2387         &pclk_fck,
2388         &pclkx2_fck,
2389         &atclk_fck,
2390         &traceclk_src_fck,
2391         &traceclk_fck,
2392         &sr1_fck,
2393         &sr2_fck,
2394         &sr_l4_ick,
2395         &secure_32k_fck,
2396         &gpt12_fck,
2397         &wdt1_fck,
2398 };
2399
2400 #endif