arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk, unsigned long parent_rate,
  31                               u8 rate_storage);
  32 static void omap3_clkoutx2_recalc(struct clk *clk, unsigned long parent_rate,
  33                               u8 rate_storage);
  34 static void omap3_dpll_allow_idle(struct clk *clk);
  35 static void omap3_dpll_deny_idle(struct clk *clk);
  36 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  37 static int omap3_noncore_dpll_enable(struct clk *clk);
  38 static void omap3_noncore_dpll_disable(struct clk *clk);
  39 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  40 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
  41
  42 /* Maximum DPLL multiplier, divider values for OMAP3 */
  43 #define OMAP3_MAX_DPLL_MULT             2048
  44 #define OMAP3_MAX_DPLL_DIV              128
  45
  46 /*
  47  * DPLL1 supplies clock to the MPU.
  48  * DPLL2 supplies clock to the IVA2.
  49  * DPLL3 supplies CORE domain clocks.
  50  * DPLL4 supplies peripheral clocks.
  51  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  52  */
  53
  54 /* Forward declarations for DPLL bypass clocks */
  55 static struct clk dpll1_fck;
  56 static struct clk dpll2_fck;
  57
  58 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  59 #define DPLL_LOW_POWER_STOP             0x1
  60 #define DPLL_LOW_POWER_BYPASS           0x5
  61 #define DPLL_LOCKED                     0x7
  62
  63 /* PRM CLOCKS */
  64
  65 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  66 static struct clk omap_32k_fck = {
  67         .name           = "omap_32k_fck",
  68         .rate           = 32768,
  69         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  70                                 ALWAYS_ENABLED,
  71         .clkdm          = { .name = "prm_clkdm" },
  72 };
  73
  74 static struct clk secure_32k_fck = {
  75         .name           = "secure_32k_fck",
  76         .rate           = 32768,
  77         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  78                                 ALWAYS_ENABLED,
  79         .clkdm          = { .name = "prm_clkdm" },
  80 };
  81
  82 /* Virtual source clocks for osc_sys_ck */
  83 static struct clk virt_12m_ck = {
  84         .name           = "virt_12m_ck",
  85         .rate           = 12000000,
  86         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  87                                 ALWAYS_ENABLED,
  88         .clkdm          = { .name = "prm_clkdm" },
  89 };
  90
  91 static struct clk virt_13m_ck = {
  92         .name           = "virt_13m_ck",
  93         .rate           = 13000000,
  94         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  95                                 ALWAYS_ENABLED,
  96         .clkdm          = { .name = "prm_clkdm" },
  97 };
  98
  99 static struct clk virt_16_8m_ck = {
 100         .name           = "virt_16_8m_ck",
 101         .rate           = 16800000,
 102         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
 103                                 ALWAYS_ENABLED,
 104         .clkdm          = { .name = "prm_clkdm" },
 105 };
 106
 107 static struct clk virt_19_2m_ck = {
 108         .name           = "virt_19_2m_ck",
 109         .rate           = 19200000,
 110         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 111                                 ALWAYS_ENABLED,
 112         .clkdm          = { .name = "prm_clkdm" },
 113 };
 114
 115 static struct clk virt_26m_ck = {
 116         .name           = "virt_26m_ck",
 117         .rate           = 26000000,
 118         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 119                                 ALWAYS_ENABLED,
 120         .clkdm          = { .name = "prm_clkdm" },
 121 };
 122
 123 static struct clk virt_38_4m_ck = {
 124         .name           = "virt_38_4m_ck",
 125         .rate           = 38400000,
 126         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 127                                 ALWAYS_ENABLED,
 128         .clkdm          = { .name = "prm_clkdm" },
 129 };
 130
 131 static const struct clksel_rate osc_sys_12m_rates[] = {
 132         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 133         { .div = 0 }
 134 };
 135
 136 static const struct clksel_rate osc_sys_13m_rates[] = {
 137         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 138         { .div = 0 }
 139 };
 140
 141 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 142         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 143         { .div = 0 }
 144 };
 145
 146 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 147         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 148         { .div = 0 }
 149 };
 150
 151 static const struct clksel_rate osc_sys_26m_rates[] = {
 152         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 153         { .div = 0 }
 154 };
 155
 156 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 157         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 158         { .div = 0 }
 159 };
 160
 161 static const struct clksel osc_sys_clksel[] = {
 162         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 163         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 164         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 165         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 166         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 167         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 168         { .parent = NULL },
 169 };
 170
 171 /* Oscillator clock */
 172 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 173 static struct clk osc_sys_ck = {
 174         .name           = "osc_sys_ck",
 175         .prcm_mod       = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
 176         .init           = &omap2_init_clksel_parent,
 177         .clksel_reg     = OMAP3_PRM_CLKSEL_OFFSET,
 178         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 179         .clksel         = osc_sys_clksel,
 180         /* REVISIT: deal with autoextclkmode? */
 181         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 182                                 ALWAYS_ENABLED,
 183         .clkdm          = { .name = "prm_clkdm" },
 184         .recalc         = &omap2_clksel_recalc,
 185 };
 186
 187 static const struct clksel_rate div2_rates[] = {
 188         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 189         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 190         { .div = 0 }
 191 };
 192
 193 static const struct clksel sys_clksel[] = {
 194         { .parent = &osc_sys_ck, .rates = div2_rates },
 195         { .parent = NULL }
 196 };
 197
 198 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 199 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 200 static struct clk sys_ck = {
 201         .name           = "sys_ck",
 202         .parent         = &osc_sys_ck,
 203         .prcm_mod       = OMAP3430_GR_MOD | CLK_REG_IN_PRM,
 204         .init           = &omap2_init_clksel_parent,
 205         .clksel_reg     = OMAP3_PRM_CLKSRC_CTRL_OFFSET,
 206         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 207         .clksel         = sys_clksel,
 208         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 209         .clkdm          = { .name = "prm_clkdm" },
 210         .recalc         = &omap2_clksel_recalc,
 211 };
 212
 213 static struct clk sys_altclk = {
 214         .name           = "sys_altclk",
 215         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 216         .clkdm          = { .name = "cm_clkdm" },
 217 };
 218
 219 /*
 220  * Optional external clock input for some McBSPs
 221  * Apparently this is not really in prm_clkdm, but rather is fed into
 222  * both CORE and PER separately.
 223  */
 224 static struct clk mcbsp_clks = {
 225         .name           = "mcbsp_clks",
 226         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 227         .clkdm          = { .name = "prm_clkdm" },
 228 };
 229
 230 /* PRM EXTERNAL CLOCK OUTPUT */
 231
 232 static struct clk sys_clkout1 = {
 233         .name           = "sys_clkout1",
 234         .parent         = &osc_sys_ck,
 235         .prcm_mod       = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
 236         .enable_reg     = OMAP3_PRM_CLKOUT_CTRL_OFFSET,
 237         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 238         .flags          = CLOCK_IN_OMAP343X,
 239         .clkdm          = { .name = "prm_clkdm" },
 240         .recalc         = &followparent_recalc,
 241 };
 242
 243 /* DPLLS */
 244
 245 /* CM CLOCKS */
 246
 247 static const struct clksel_rate div16_dpll_rates[] = {
 248         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 249         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 250         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 251         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 252         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 253         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 254         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 255         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 256         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 257         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 258         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 259         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 260         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 261         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 262         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 263         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 264         { .div = 0 }
 265 };
 266
 267 /* DPLL1 */
 268 /* MPU clock source */
 269 /* Type: DPLL */
 270 static struct dpll_data dpll1_dd = {
 271         .mult_div1_reg  = OMAP3430_CM_CLKSEL1_PLL,
 272         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 273         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 274         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 275         .control_reg    = OMAP3430_CM_CLKEN_PLL,
 276         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 277         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 278         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 279         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 280         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 281         .autoidle_reg   = OMAP3430_CM_AUTOIDLE_PLL,
 282         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 283         .idlest_reg     = OMAP3430_CM_IDLEST_PLL,
 284         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
 285         .bypass_clk     = &dpll1_fck,
 286         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 287         .min_divider    = 1,
 288         .max_divider    = OMAP3_MAX_DPLL_DIV,
 289         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 290 };
 291
 292 static struct clk dpll1_ck = {
 293         .name           = "dpll1_ck",
 294         .parent         = &sys_ck,
 295         .prcm_mod       = MPU_MOD,
 296         .dpll_data      = &dpll1_dd,
 297         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 298                           ALWAYS_ENABLED | RECALC_ON_ENABLE,
 299         .round_rate     = &omap2_dpll_round_rate,
 300         .set_rate       = &omap3_noncore_dpll_set_rate,
 301         .clkdm          = { .name = "dpll1_clkdm" },
 302         .recalc         = &omap3_dpll_recalc,
 303 };
 304
 305 /*
 306  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 307  * DPLL isn't bypassed.
 308  */
 309 static struct clk dpll1_x2_ck = {
 310         .name           = "dpll1_x2_ck",
 311         .parent         = &dpll1_ck,
 312         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 313                                 PARENT_CONTROLS_CLOCK,
 314         .clkdm          = { .name = "dpll1_clkdm" },
 315         .recalc         = &omap3_clkoutx2_recalc,
 316 };
 317
 318 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 319 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 320         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 321         { .parent = NULL }
 322 };
 323
 324 /*
 325  * Does not exist in the TRM - needed to separate the M2 divider from
 326  * bypass selection in mpu_ck
 327  */
 328 static struct clk dpll1_x2m2_ck = {
 329         .name           = "dpll1_x2m2_ck",
 330         .parent         = &dpll1_x2_ck,
 331         .prcm_mod       = MPU_MOD,
 332         .init           = &omap2_init_clksel_parent,
 333         .clksel_reg     = OMAP3430_CM_CLKSEL2_PLL,
 334         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 335         .clksel         = div16_dpll1_x2m2_clksel,
 336         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 337                                 PARENT_CONTROLS_CLOCK,
 338         .clkdm          = { .name = "dpll1_clkdm" },
 339         .recalc         = &omap2_clksel_recalc,
 340 };
 341
 342 /* DPLL2 */
 343 /* IVA2 clock source */
 344 /* Type: DPLL */
 345
 346 static struct dpll_data dpll2_dd = {
 347         .mult_div1_reg  = OMAP3430_CM_CLKSEL1_PLL,
 348         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 349         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 350         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 351         .control_reg    = OMAP3430_CM_CLKEN_PLL,
 352         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 353         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 354                                 (1 << DPLL_LOW_POWER_BYPASS),
 355         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 356         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 357         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 358         .autoidle_reg   = OMAP3430_CM_AUTOIDLE_PLL,
 359         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 360         .idlest_reg     = OMAP3430_CM_IDLEST_PLL,
 361         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
 362         .bypass_clk     = &dpll2_fck,
 363         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 364         .min_divider    = 1,
 365         .max_divider    = OMAP3_MAX_DPLL_DIV,
 366         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 367 };
 368
 369 static struct clk dpll2_ck = {
 370         .name           = "dpll2_ck",
 371         .parent         = &sys_ck,
 372         .prcm_mod       = OMAP3430_IVA2_MOD,
 373         .dpll_data      = &dpll2_dd,
 374         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 375                           RECALC_ON_ENABLE,
 376         .enable         = &omap3_noncore_dpll_enable,
 377         .disable        = &omap3_noncore_dpll_disable,
 378         .round_rate     = &omap2_dpll_round_rate,
 379         .set_rate       = &omap3_noncore_dpll_set_rate,
 380         .clkdm          = { .name = "dpll2_clkdm" },
 381         .recalc         = &omap3_dpll_recalc,
 382 };
 383
 384 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 385         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 386         { .parent = NULL }
 387 };
 388
 389 /*
 390  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 391  * or CLKOUTX2. CLKOUT seems most plausible.
 392  */
 393 static struct clk dpll2_m2_ck = {
 394         .name           = "dpll2_m2_ck",
 395         .parent         = &dpll2_ck,
 396         .prcm_mod       = OMAP3430_IVA2_MOD,
 397         .init           = &omap2_init_clksel_parent,
 398         .clksel_reg     = OMAP3430_CM_CLKSEL2_PLL,
 399         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 400         .clksel         = div16_dpll2_m2x2_clksel,
 401         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 402                                 PARENT_CONTROLS_CLOCK,
 403         .clkdm          = { .name = "dpll2_clkdm" },
 404         .recalc         = &omap2_clksel_recalc,
 405 };
 406
 407 /*
 408  * DPLL3
 409  * Source clock for all interfaces and for some device fclks
 410  * REVISIT: Also supports fast relock bypass - not included below
 411  */
 412 static struct dpll_data dpll3_dd = {
 413         .mult_div1_reg  = CM_CLKSEL1,
 414         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 415         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 416         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 417         .control_reg    = CM_CLKEN,
 418         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 419         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 420         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 421         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 422         .autoidle_reg   = CM_AUTOIDLE,
 423         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 424         .idlest_reg     = CM_IDLEST,
 425         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
 426         .bypass_clk     = &sys_ck,
 427         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 428         .min_divider    = 1,
 429         .max_divider    = OMAP3_MAX_DPLL_DIV,
 430         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 431 };
 432
 433 static struct clk dpll3_ck = {
 434         .name           = "dpll3_ck",
 435         .parent         = &sys_ck,
 436         .prcm_mod       = PLL_MOD,
 437         .dpll_data      = &dpll3_dd,
 438         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 439                           ALWAYS_ENABLED | RECALC_ON_ENABLE,
 440         .round_rate     = &omap2_dpll_round_rate,
 441         .clkdm          = { .name = "dpll3_clkdm" },
 442         .recalc         = &omap3_dpll_recalc,
 443 };
 444
 445 /*
 446  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 447  * DPLL isn't bypassed
 448  */
 449 static struct clk dpll3_x2_ck = {
 450         .name           = "dpll3_x2_ck",
 451         .parent         = &dpll3_ck,
 452         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 453                                 PARENT_CONTROLS_CLOCK,
 454         .clkdm          = { .name = "dpll3_clkdm" },
 455         .recalc         = &omap3_clkoutx2_recalc,
 456 };
 457
 458 static const struct clksel_rate div31_dpll3_rates[] = {
 459         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 460         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 461         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 462         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 463         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 464         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 465         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 466         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 467         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 468         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 469         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 470         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 471         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 472         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 473         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 474         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 475         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 476         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 477         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 478         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 479         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 480         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 481         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 482         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 483         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 484         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 485         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 486         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 487         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 488         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 489         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 490         { .div = 0 },
 491 };
 492
 493 static const struct clksel div31_dpll3m2_clksel[] = {
 494         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 495         { .parent = NULL }
 496 };
 497
 498 /* DPLL3 output M2 - primary control point for CORE speed */
 499 static struct clk dpll3_m2_ck = {
 500         .name           = "dpll3_m2_ck",
 501         .parent         = &dpll3_ck,
 502         .prcm_mod       = PLL_MOD,
 503         .init           = &omap2_init_clksel_parent,
 504         .clksel_reg     = CM_CLKSEL1,
 505         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 506         .clksel         = div31_dpll3m2_clksel,
 507         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 508                                 PARENT_CONTROLS_CLOCK,
 509         .clkdm          = { .name = "dpll3_clkdm" },
 510         .round_rate     = &omap2_clksel_round_rate,
 511         .set_rate       = &omap3_core_dpll_m2_set_rate,
 512         .recalc         = &omap2_clksel_recalc,
 513 };
 514
 515 static struct clk core_ck = {
 516         .name           = "core_ck",
 517         .parent         = &dpll3_m2_ck,
 518         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 519                                 PARENT_CONTROLS_CLOCK,
 520         .clkdm          = { .name = "cm_clkdm" },
 521         .recalc         = &followparent_recalc,
 522 };
 523
 524 static struct clk dpll3_m2x2_ck = {
 525         .name           = "dpll3_m2x2_ck",
 526         .parent         = &dpll3_x2_ck,
 527         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 528                                 PARENT_CONTROLS_CLOCK,
 529         .clkdm          = { .name = "dpll3_clkdm" },
 530         .recalc         = &followparent_recalc,
 531 };
 532
 533 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 534 static const struct clksel div16_dpll3_clksel[] = {
 535         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 536         { .parent = NULL }
 537 };
 538
 539 /* This virtual clock is the source for dpll3_m3x2_ck */
 540 static struct clk dpll3_m3_ck = {
 541         .name           = "dpll3_m3_ck",
 542         .parent         = &dpll3_ck,
 543         .prcm_mod       = OMAP3430_EMU_MOD,
 544         .init           = &omap2_init_clksel_parent,
 545         .clksel_reg     = CM_CLKSEL1,
 546         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 547         .clksel         = div16_dpll3_clksel,
 548         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 549                                 PARENT_CONTROLS_CLOCK,
 550         .clkdm          = { .name = "dpll3_clkdm" },
 551         .recalc         = &omap2_clksel_recalc,
 552 };
 553
 554 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 555 static struct clk dpll3_m3x2_ck = {
 556         .name           = "dpll3_m3x2_ck",
 557         .parent         = &dpll3_m3_ck,
 558         .prcm_mod       = PLL_MOD,
 559         .enable_reg     = CM_CLKEN,
 560         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 561         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 562         .clkdm          = { .name = "dpll3_clkdm" },
 563         .recalc         = &omap3_clkoutx2_recalc,
 564 };
 565
 566 static struct clk emu_core_alwon_ck = {
 567         .name           = "emu_core_alwon_ck",
 568         .parent         = &dpll3_m3x2_ck,
 569         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 570                                 PARENT_CONTROLS_CLOCK,
 571         .clkdm          = { .name = "dpll3_clkdm" },
 572         .recalc         = &followparent_recalc,
 573 };
 574
 575 /* DPLL4 */
 576 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 577 /* Type: DPLL */
 578 static struct dpll_data dpll4_dd = {
 579         .mult_div1_reg  = CM_CLKSEL2,
 580         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 581         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 582         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 583         .control_reg    = CM_CLKEN,
 584         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 585         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 586         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 587         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 588         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 589         .autoidle_reg   = CM_AUTOIDLE,
 590         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 591         .idlest_reg     = CM_IDLEST,
 592         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 593         .bypass_clk     = &sys_ck,
 594         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 595         .min_divider    = 1,
 596         .max_divider    = OMAP3_MAX_DPLL_DIV,
 597         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 598 };
 599
 600 static struct clk dpll4_ck = {
 601         .name           = "dpll4_ck",
 602         .parent         = &sys_ck,
 603         .prcm_mod       = PLL_MOD,
 604         .dpll_data      = &dpll4_dd,
 605         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 606                           RECALC_ON_ENABLE,
 607         .enable         = &omap3_noncore_dpll_enable,
 608         .disable        = &omap3_noncore_dpll_disable,
 609         .round_rate     = &omap2_dpll_round_rate,
 610         .set_rate       = &omap3_noncore_dpll_set_rate,
 611         .clkdm          = { .name = "dpll4_clkdm" },
 612         .recalc         = &omap3_dpll_recalc,
 613 };
 614
 615 /*
 616  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 617  * DPLL isn't bypassed --
 618  * XXX does this serve any downstream clocks?
 619  */
 620 static struct clk dpll4_x2_ck = {
 621         .name           = "dpll4_x2_ck",
 622         .parent         = &dpll4_ck,
 623         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 624                                 PARENT_CONTROLS_CLOCK,
 625         .clkdm          = { .name = "dpll4_clkdm" },
 626         .recalc         = &omap3_clkoutx2_recalc,
 627 };
 628
 629 static const struct clksel div16_dpll4_clksel[] = {
 630         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 631         { .parent = NULL }
 632 };
 633
 634 /* This virtual clock is the source for dpll4_m2x2_ck */
 635 static struct clk dpll4_m2_ck = {
 636         .name           = "dpll4_m2_ck",
 637         .parent         = &dpll4_ck,
 638         .prcm_mod       = PLL_MOD,
 639         .init           = &omap2_init_clksel_parent,
 640         .clksel_reg     = OMAP3430_CM_CLKSEL3,
 641         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 642         .clksel         = div16_dpll4_clksel,
 643         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 644                                 PARENT_CONTROLS_CLOCK,
 645         .clkdm          = { .name = "dpll4_clkdm" },
 646         .recalc         = &omap2_clksel_recalc,
 647 };
 648
 649 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 650 static struct clk dpll4_m2x2_ck = {
 651         .name           = "dpll4_m2x2_ck",
 652         .parent         = &dpll4_m2_ck,
 653         .prcm_mod       = PLL_MOD,
 654         .enable_reg     = CM_CLKEN,
 655         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 656         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 657         .clkdm          = { .name = "dpll4_clkdm" },
 658         .recalc         = &omap3_clkoutx2_recalc,
 659 };
 660
 661 /*
 662  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 663  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 664  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 665  * CM_96K_(F)CLK.
 666  */
 667 static struct clk omap_96m_alwon_fck = {
 668         .name           = "omap_96m_alwon_fck",
 669         .parent         = &dpll4_m2x2_ck,
 670         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 671                                 PARENT_CONTROLS_CLOCK,
 672         .clkdm          = { .name = "prm_clkdm" },
 673         .recalc         = &followparent_recalc,
 674 };
 675
 676 static struct clk cm_96m_fck = {
 677         .name           = "cm_96m_fck",
 678         .parent         = &omap_96m_alwon_fck,
 679         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 680                                 PARENT_CONTROLS_CLOCK,
 681         .clkdm          = { .name = "cm_clkdm" },
 682         .recalc         = &followparent_recalc,
 683 };
 684
 685 static const struct clksel_rate omap_96m_dpll_rates[] = {
 686         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 687         { .div = 0 }
 688 };
 689
 690 static const struct clksel_rate omap_96m_sys_rates[] = {
 691         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 692         { .div = 0 }
 693 };
 694
 695 static const struct clksel omap_96m_fck_clksel[] = {
 696         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 697         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 698         { .parent = NULL }
 699 };
 700
 701 static struct clk omap_96m_fck = {
 702         .name           = "omap_96m_fck",
 703         .parent         = &sys_ck,
 704         .prcm_mod       = PLL_MOD,
 705         .init           = &omap2_init_clksel_parent,
 706         .clksel_reg     = CM_CLKSEL1,
 707         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 708         .clksel         = omap_96m_fck_clksel,
 709         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 710                                 PARENT_CONTROLS_CLOCK,
 711         .clkdm          = { .name = "cm_clkdm" },
 712         .recalc         = &omap2_clksel_recalc,
 713 };
 714
 715 /* This virtual clock is the source for dpll4_m3x2_ck */
 716 static struct clk dpll4_m3_ck = {
 717         .name           = "dpll4_m3_ck",
 718         .parent         = &dpll4_ck,
 719         .prcm_mod       = OMAP3430_DSS_MOD,
 720         .init           = &omap2_init_clksel_parent,
 721         .clksel_reg     = CM_CLKSEL,
 722         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 723         .clksel         = div16_dpll4_clksel,
 724         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 725                                 PARENT_CONTROLS_CLOCK,
 726         .clkdm          = { .name = "dpll4_clkdm" },
 727         .recalc         = &omap2_clksel_recalc,
 728 };
 729
 730 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 731 static struct clk dpll4_m3x2_ck = {
 732         .name           = "dpll4_m3x2_ck",
 733         .parent         = &dpll4_m3_ck,
 734         .prcm_mod       = PLL_MOD,
 735         .init           = &omap2_init_clksel_parent,
 736         .enable_reg     = CM_CLKEN,
 737         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 738         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 739         .clkdm          = { .name = "dpll4_clkdm" },
 740         .recalc         = &omap3_clkoutx2_recalc,
 741 };
 742
 743 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 744         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 745         { .div = 0 }
 746 };
 747
 748 static const struct clksel_rate omap_54m_alt_rates[] = {
 749         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 750         { .div = 0 }
 751 };
 752
 753 static const struct clksel omap_54m_clksel[] = {
 754         { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
 755         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 756         { .parent = NULL }
 757 };
 758
 759 static struct clk omap_54m_fck = {
 760         .name           = "omap_54m_fck",
 761         .prcm_mod       = PLL_MOD,
 762         .init           = &omap2_init_clksel_parent,
 763         .clksel_reg     = CM_CLKSEL1,
 764         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 765         .clksel         = omap_54m_clksel,
 766         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 767                                 PARENT_CONTROLS_CLOCK,
 768         .clkdm          = { .name = "cm_clkdm" },
 769         .recalc         = &omap2_clksel_recalc,
 770 };
 771
 772 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 773         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 774         { .div = 0 }
 775 };
 776
 777 static const struct clksel_rate omap_48m_alt_rates[] = {
 778         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 779         { .div = 0 }
 780 };
 781
 782 static const struct clksel omap_48m_clksel[] = {
 783         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 784         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 785         { .parent = NULL }
 786 };
 787
 788 static struct clk omap_48m_fck = {
 789         .name           = "omap_48m_fck",
 790         .prcm_mod       = PLL_MOD,
 791         .init           = &omap2_init_clksel_parent,
 792         .clksel_reg     = CM_CLKSEL1,
 793         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 794         .clksel         = omap_48m_clksel,
 795         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 796                                 PARENT_CONTROLS_CLOCK,
 797         .clkdm          = { .name = "cm_clkdm" },
 798         .recalc         = &omap2_clksel_recalc,
 799 };
 800
 801 static struct clk omap_12m_fck = {
 802         .name           = "omap_12m_fck",
 803         .parent         = &omap_48m_fck,
 804         .fixed_div      = 4,
 805         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 806                                 PARENT_CONTROLS_CLOCK,
 807         .clkdm          = { .name = "cm_clkdm" },
 808         .recalc         = &omap2_fixed_divisor_recalc,
 809 };
 810
 811 /* This virstual clock is the source for dpll4_m4x2_ck */
 812 static struct clk dpll4_m4_ck = {
 813         .name           = "dpll4_m4_ck",
 814         .parent         = &dpll4_ck,
 815         .prcm_mod       = OMAP3430_DSS_MOD,
 816         .init           = &omap2_init_clksel_parent,
 817         .clksel_reg     = CM_CLKSEL,
 818         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 819         .clksel         = div16_dpll4_clksel,
 820         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 821                                 PARENT_CONTROLS_CLOCK,
 822         .clkdm          = { .name = "dpll4_clkdm" },
 823         .recalc         = &omap2_clksel_recalc,
 824         .set_rate       = &omap2_clksel_set_rate,
 825         .round_rate     = &omap2_clksel_round_rate,
 826 };
 827
 828 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 829 static struct clk dpll4_m4x2_ck = {
 830         .name           = "dpll4_m4x2_ck",
 831         .parent         = &dpll4_m4_ck,
 832         .prcm_mod       = PLL_MOD,
 833         .enable_reg     = CM_CLKEN,
 834         .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
 835         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 836         .clkdm          = { .name = "dpll4_clkdm" },
 837         .recalc         = &omap3_clkoutx2_recalc,
 838 };
 839
 840 /* This virtual clock is the source for dpll4_m5x2_ck */
 841 static struct clk dpll4_m5_ck = {
 842         .name           = "dpll4_m5_ck",
 843         .parent         = &dpll4_ck,
 844         .prcm_mod       = OMAP3430_CAM_MOD,
 845         .init           = &omap2_init_clksel_parent,
 846         .clksel_reg     = CM_CLKSEL,
 847         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 848         .clksel         = div16_dpll4_clksel,
 849         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 850                                 PARENT_CONTROLS_CLOCK,
 851         .clkdm          = { .name = "dpll4_clkdm" },
 852         .recalc         = &omap2_clksel_recalc,
 853 };
 854
 855 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 856 static struct clk dpll4_m5x2_ck = {
 857         .name           = "dpll4_m5x2_ck",
 858         .parent         = &dpll4_m5_ck,
 859         .prcm_mod       = PLL_MOD,
 860         .enable_reg     = CM_CLKEN,
 861         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 862         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 863         .clkdm          = { .name = "dpll4_clkdm" },
 864         .recalc         = &omap3_clkoutx2_recalc,
 865 };
 866
 867 /* This virtual clock is the source for dpll4_m6x2_ck */
 868 static struct clk dpll4_m6_ck = {
 869         .name           = "dpll4_m6_ck",
 870         .parent         = &dpll4_ck,
 871         .prcm_mod       = OMAP3430_EMU_MOD,
 872         .init           = &omap2_init_clksel_parent,
 873         .clksel_reg     = CM_CLKSEL1,
 874         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 875         .clksel         = div16_dpll4_clksel,
 876         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 877                                 PARENT_CONTROLS_CLOCK,
 878         .clkdm          = { .name = "dpll4_clkdm" },
 879         .recalc         = &omap2_clksel_recalc,
 880 };
 881
 882 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 883 static struct clk dpll4_m6x2_ck = {
 884         .name           = "dpll4_m6x2_ck",
 885         .parent         = &dpll4_m6_ck,
 886         .prcm_mod       = PLL_MOD,
 887         .init           = &omap2_init_clksel_parent,
 888         .enable_reg     = CM_CLKEN,
 889         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 890         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 891         .clkdm          = { .name = "dpll4_clkdm" },
 892         .recalc         = &omap3_clkoutx2_recalc,
 893 };
 894
 895 static struct clk emu_per_alwon_ck = {
 896         .name           = "emu_per_alwon_ck",
 897         .parent         = &dpll4_m6x2_ck,
 898         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 899                                 PARENT_CONTROLS_CLOCK,
 900         .clkdm          = { .name = "dpll4_clkdm" },
 901         .recalc         = &followparent_recalc,
 902 };
 903
 904 /* DPLL5 */
 905 /* Supplies 120MHz clock, USIM source clock */
 906 /* Type: DPLL */
 907 /* 3430ES2 only */
 908 static struct dpll_data dpll5_dd = {
 909         .mult_div1_reg  = OMAP3430ES2_CM_CLKSEL4,
 910         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 911         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 912         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 913         .control_reg    = OMAP3430ES2_CM_CLKEN2,
 914         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 915         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 916         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 917         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 918         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 919         .autoidle_reg   = OMAP3430ES2_CM_AUTOIDLE2_PLL,
 920         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 921         .idlest_reg     = CM_IDLEST2,
 922         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 923         .bypass_clk     = &sys_ck,
 924         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 925         .min_divider    = 1,
 926         .max_divider    = OMAP3_MAX_DPLL_DIV,
 927         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 928 };
 929
 930 static struct clk dpll5_ck = {
 931         .name           = "dpll5_ck",
 932         .parent         = &sys_ck,
 933         .prcm_mod       = PLL_MOD,
 934         .dpll_data      = &dpll5_dd,
 935         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 936                           RECALC_ON_ENABLE,
 937         .enable         = &omap3_noncore_dpll_enable,
 938         .disable        = &omap3_noncore_dpll_disable,
 939         .round_rate     = &omap2_dpll_round_rate,
 940         .set_rate       = &omap3_noncore_dpll_set_rate,
 941         .clkdm          = { .name = "dpll5_clkdm" },
 942         .recalc         = &omap3_dpll_recalc,
 943 };
 944
 945 static const struct clksel div16_dpll5_clksel[] = {
 946         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 947         { .parent = NULL }
 948 };
 949
 950 static struct clk dpll5_m2_ck = {
 951         .name           = "dpll5_m2_ck",
 952         .parent         = &dpll5_ck,
 953         .prcm_mod       = PLL_MOD,
 954         .init           = &omap2_init_clksel_parent,
 955         .clksel_reg     = OMAP3430ES2_CM_CLKSEL5,
 956         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 957         .clksel         = div16_dpll5_clksel,
 958         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 959                                 PARENT_CONTROLS_CLOCK,
 960         .clkdm          = { .name = "dpll5_clkdm" },
 961         .recalc         = &omap2_clksel_recalc,
 962 };
 963
 964 /* CM EXTERNAL CLOCK OUTPUTS */
 965
 966 static const struct clksel_rate clkout2_src_core_rates[] = {
 967         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 968         { .div = 0 }
 969 };
 970
 971 static const struct clksel_rate clkout2_src_sys_rates[] = {
 972         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 973         { .div = 0 }
 974 };
 975
 976 static const struct clksel_rate clkout2_src_96m_rates[] = {
 977         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 978         { .div = 0 }
 979 };
 980
 981 static const struct clksel_rate clkout2_src_54m_rates[] = {
 982         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 983         { .div = 0 }
 984 };
 985
 986 static const struct clksel clkout2_src_clksel[] = {
 987         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
 988         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
 989         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
 990         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
 991         { .parent = NULL }
 992 };
 993
 994 static struct clk clkout2_src_ck = {
 995         .name           = "clkout2_src_ck",
 996         .prcm_mod       = OMAP3430_CCR_MOD,
 997         .init           = &omap2_init_clksel_parent,
 998         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
 999         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
1000         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
1001         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
1002         .clksel         = clkout2_src_clksel,
1003         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1004         .clkdm          = { .name = "cm_clkdm" },
1005         .recalc         = &omap2_clksel_recalc,
1006 };
1007
1008 static const struct clksel_rate sys_clkout2_rates[] = {
1009         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1010         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1011         { .div = 4, .val = 2, .flags = RATE_IN_343X },
1012         { .div = 8, .val = 3, .flags = RATE_IN_343X },
1013         { .div = 16, .val = 4, .flags = RATE_IN_343X },
1014         { .div = 0 },
1015 };
1016
1017 static const struct clksel sys_clkout2_clksel[] = {
1018         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1019         { .parent = NULL },
1020 };
1021
1022 static struct clk sys_clkout2 = {
1023         .name           = "sys_clkout2",
1024         .prcm_mod       = OMAP3430_CCR_MOD,
1025         .init           = &omap2_init_clksel_parent,
1026         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
1027         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1028         .clksel         = sys_clkout2_clksel,
1029         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1030         .clkdm          = { .name = "cm_clkdm" },
1031         .recalc         = &omap2_clksel_recalc,
1032 };
1033
1034 /* CM OUTPUT CLOCKS */
1035
1036 static struct clk corex2_fck = {
1037         .name           = "corex2_fck",
1038         .parent         = &dpll3_m2x2_ck,
1039         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1040                                 PARENT_CONTROLS_CLOCK,
1041         .clkdm          = { .name = "cm_clkdm" },
1042         .recalc         = &followparent_recalc,
1043 };
1044
1045 /* DPLL power domain clock controls */
1046
1047 static const struct clksel_rate div4_rates[] = {
1048         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1049         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1050         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1051         { .div = 0 }
1052 };
1053
1054 static const struct clksel div4_core_clksel[] = {
1055         { .parent = &core_ck, .rates = div4_rates },
1056         { .parent = NULL }
1057 };
1058
1059 static struct clk dpll1_fck = {
1060         .name           = "dpll1_fck",
1061         .parent         = &core_ck,
1062         .prcm_mod       = MPU_MOD,
1063         .init           = &omap2_init_clksel_parent,
1064         .clksel_reg     = OMAP3430_CM_CLKSEL1_PLL,
1065         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1066         .clksel         = div4_core_clksel,
1067         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1068                                 PARENT_CONTROLS_CLOCK,
1069         .clkdm          = { .name = "cm_clkdm" },
1070         .recalc         = &omap2_clksel_recalc,
1071 };
1072
1073 static struct clk mpu_ck = {
1074         .name           = "mpu_ck",
1075         .parent         = &dpll1_x2m2_ck,
1076         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1077                                 PARENT_CONTROLS_CLOCK,
1078         .clkdm          = { .name = "mpu_clkdm" },
1079         .recalc         = &followparent_recalc,
1080 };
1081
1082 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1083 static const struct clksel_rate arm_fck_rates[] = {
1084         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1085         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1086         { .div = 0 },
1087 };
1088
1089 static const struct clksel arm_fck_clksel[] = {
1090         { .parent = &mpu_ck, .rates = arm_fck_rates },
1091         { .parent = NULL }
1092 };
1093
1094 static struct clk arm_fck = {
1095         .name           = "arm_fck",
1096         .parent         = &mpu_ck,
1097         .prcm_mod       = MPU_MOD,
1098         .init           = &omap2_init_clksel_parent,
1099         .clksel_reg     = OMAP3430_CM_IDLEST_PLL,
1100         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1101         .clksel         = arm_fck_clksel,
1102         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1103                                 PARENT_CONTROLS_CLOCK,
1104         .clkdm          = { .name = "mpu_clkdm" },
1105         .recalc         = &omap2_clksel_recalc,
1106 };
1107
1108 /* XXX What about neon_clkdm ? */
1109
1110 /*
1111  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1112  * although it is referenced - so this is a guess
1113  */
1114 static struct clk emu_mpu_alwon_ck = {
1115         .name           = "emu_mpu_alwon_ck",
1116         .parent         = &mpu_ck,
1117         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1118                                 PARENT_CONTROLS_CLOCK,
1119         .clkdm          = { .name = "mpu_clkdm" },
1120         .recalc         = &followparent_recalc,
1121 };
1122
1123 static struct clk dpll2_fck = {
1124         .name           = "dpll2_fck",
1125         .parent         = &core_ck,
1126         .prcm_mod       = OMAP3430_IVA2_MOD,
1127         .init           = &omap2_init_clksel_parent,
1128         .clksel_reg     = OMAP3430_CM_CLKSEL1_PLL,
1129         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1130         .clksel         = div4_core_clksel,
1131         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1132                                 PARENT_CONTROLS_CLOCK,
1133         .clkdm          = { .name = "cm_clkdm" },
1134         .recalc         = &omap2_clksel_recalc,
1135 };
1136
1137 static struct clk iva2_ck = {
1138         .name           = "iva2_ck",
1139         .parent         = &dpll2_m2_ck,
1140         .prcm_mod       = OMAP3430_IVA2_MOD,
1141         .init           = &omap2_init_clksel_parent,
1142         .enable_reg     = CM_FCLKEN,
1143         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1144         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1145         .clkdm          = { .name = "iva2_clkdm" },
1146         .recalc         = &followparent_recalc,
1147 };
1148
1149 /* Common interface clocks */
1150
1151 static const struct clksel div2_core_clksel[] = {
1152         { .parent = &core_ck, .rates = div2_rates },
1153         { .parent = NULL }
1154 };
1155
1156 static struct clk l3_ick = {
1157         .name           = "l3_ick",
1158         .parent         = &core_ck,
1159         .prcm_mod       = CORE_MOD,
1160         .init           = &omap2_init_clksel_parent,
1161         .clksel_reg     = CM_CLKSEL,
1162         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1163         .clksel         = div2_core_clksel,
1164         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1165                                 PARENT_CONTROLS_CLOCK,
1166         .clkdm          = { .name = "core_l3_clkdm" },
1167         .recalc         = &omap2_clksel_recalc,
1168 };
1169
1170 static const struct clksel div2_l3_clksel[] = {
1171         { .parent = &l3_ick, .rates = div2_rates },
1172         { .parent = NULL }
1173 };
1174
1175 static struct clk l4_ick = {
1176         .name           = "l4_ick",
1177         .parent         = &l3_ick,
1178         .prcm_mod       = CORE_MOD,
1179         .init           = &omap2_init_clksel_parent,
1180         .clksel_reg     = CM_CLKSEL,
1181         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1182         .clksel         = div2_l3_clksel,
1183         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1184                                 PARENT_CONTROLS_CLOCK,
1185         .clkdm          = { .name = "core_l4_clkdm" },
1186         .recalc         = &omap2_clksel_recalc,
1187
1188 };
1189
1190 static const struct clksel div2_l4_clksel[] = {
1191         { .parent = &l4_ick, .rates = div2_rates },
1192         { .parent = NULL }
1193 };
1194
1195 static struct clk rm_ick = {
1196         .name           = "rm_ick",
1197         .parent         = &l4_ick,
1198         .prcm_mod       = WKUP_MOD,
1199         .init           = &omap2_init_clksel_parent,
1200         .clksel_reg     = CM_CLKSEL,
1201         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1202         .clksel         = div2_l4_clksel,
1203         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1204         .clkdm          = { .name = "cm_clkdm" },
1205         .recalc         = &omap2_clksel_recalc,
1206 };
1207
1208 /* GFX power domain */
1209
1210 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1211
1212 static const struct clksel gfx_l3_clksel[] = {
1213         { .parent = &l3_ick, .rates = gfx_l3_rates },
1214         { .parent = NULL }
1215 };
1216
1217 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1218 static struct clk gfx_l3_ck = {
1219         .name           = "gfx_l3_ck",
1220         .parent         = &l3_ick,
1221         .prcm_mod       = GFX_MOD,
1222         .init           = &omap2_init_clksel_parent,
1223         .enable_reg     = CM_ICLKEN,
1224         .enable_bit     = OMAP_EN_GFX_SHIFT,
1225         .flags          = CLOCK_IN_OMAP3430ES1,
1226         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1227         .recalc         = &followparent_recalc,
1228 };
1229
1230 static struct clk gfx_l3_fck = {
1231         .name           = "gfx_l3_fck",
1232         .parent         = &gfx_l3_ck,
1233         .prcm_mod       = GFX_MOD,
1234         .init           = &omap2_init_clksel_parent,
1235         .clksel_reg     = CM_CLKSEL,
1236         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1237         .clksel         = gfx_l3_clksel,
1238         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1239                                 PARENT_CONTROLS_CLOCK,
1240         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1241         .recalc         = &omap2_clksel_recalc,
1242 };
1243
1244 static struct clk gfx_l3_ick = {
1245         .name           = "gfx_l3_ick",
1246         .parent         = &gfx_l3_ck,
1247         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1248         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1249         .recalc         = &followparent_recalc,
1250 };
1251
1252 static struct clk gfx_cg1_ck = {
1253         .name           = "gfx_cg1_ck",
1254         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1255         .prcm_mod       = GFX_MOD,
1256         .enable_reg     = CM_FCLKEN,
1257         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1258         .flags          = CLOCK_IN_OMAP3430ES1,
1259         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1260         .recalc         = &followparent_recalc,
1261 };
1262
1263 static struct clk gfx_cg2_ck = {
1264         .name           = "gfx_cg2_ck",
1265         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1266         .prcm_mod       = GFX_MOD,
1267         .enable_reg     = CM_FCLKEN,
1268         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1269         .flags          = CLOCK_IN_OMAP3430ES1,
1270         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1271         .recalc         = &followparent_recalc,
1272 };
1273
1274 /* SGX power domain - 3430ES2 only */
1275
1276 static const struct clksel_rate sgx_core_rates[] = {
1277         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1278         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1279         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1280         { .div = 0 },
1281 };
1282
1283 static const struct clksel_rate sgx_96m_rates[] = {
1284         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1285         { .div = 0 },
1286 };
1287
1288 static const struct clksel sgx_clksel[] = {
1289         { .parent = &core_ck,    .rates = sgx_core_rates },
1290         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1291         { .parent = NULL },
1292 };
1293
1294 static struct clk sgx_fck = {
1295         .name           = "sgx_fck",
1296         .init           = &omap2_init_clksel_parent,
1297         .prcm_mod       = OMAP3430ES2_SGX_MOD,
1298         .enable_reg     = CM_FCLKEN,
1299         .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1300         .clksel_reg     = CM_CLKSEL,
1301         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1302         .clksel         = sgx_clksel,
1303         .flags          = CLOCK_IN_OMAP3430ES2,
1304         .clkdm          = { .name = "sgx_clkdm" },
1305         .recalc         = &omap2_clksel_recalc,
1306 };
1307
1308 static struct clk sgx_ick = {
1309         .name           = "sgx_ick",
1310         .parent         = &l3_ick,
1311         .prcm_mod       = OMAP3430ES2_SGX_MOD,
1312         .enable_reg     = CM_ICLKEN,
1313         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1314         .flags          = CLOCK_IN_OMAP3430ES2,
1315         .clkdm          = { .name = "sgx_clkdm" },
1316         .recalc         = &followparent_recalc,
1317 };
1318
1319 /* CORE power domain */
1320
1321 static struct clk d2d_26m_fck = {
1322         .name           = "d2d_26m_fck",
1323         .parent         = &sys_ck,
1324         .prcm_mod       = CORE_MOD,
1325         .enable_reg     = CM_FCLKEN1,
1326         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1327         .flags          = CLOCK_IN_OMAP3430ES1,
1328         .clkdm          = { .name = "d2d_clkdm" },
1329         .recalc         = &followparent_recalc,
1330 };
1331
1332 static const struct clksel omap343x_gpt_clksel[] = {
1333         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1334         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1335         { .parent = NULL}
1336 };
1337
1338 static struct clk gpt10_fck = {
1339         .name           = "gpt10_fck",
1340         .parent         = &sys_ck,
1341         .prcm_mod       = CORE_MOD,
1342         .init           = &omap2_init_clksel_parent,
1343         .enable_reg     = CM_FCLKEN1,
1344         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1345         .idlest_bit     = OMAP3430_ST_GPT10_SHIFT,
1346         .clksel_reg     = CM_CLKSEL,
1347         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1348         .clksel         = omap343x_gpt_clksel,
1349         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1350         .clkdm          = { .name = "core_l4_clkdm" },
1351         .recalc         = &omap2_clksel_recalc,
1352 };
1353
1354 static struct clk gpt11_fck = {
1355         .name           = "gpt11_fck",
1356         .parent         = &sys_ck,
1357         .prcm_mod       = CORE_MOD,
1358         .init           = &omap2_init_clksel_parent,
1359         .enable_reg     = CM_FCLKEN1,
1360         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1361         .idlest_bit     = OMAP3430_ST_GPT11_SHIFT,
1362         .clksel_reg     = CM_CLKSEL,
1363         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1364         .clksel         = omap343x_gpt_clksel,
1365         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1366         .clkdm          = { .name = "core_l4_clkdm" },
1367         .recalc         = &omap2_clksel_recalc,
1368 };
1369
1370 static struct clk cpefuse_fck = {
1371         .name           = "cpefuse_fck",
1372         .parent         = &sys_ck,
1373         .prcm_mod       = CORE_MOD,
1374         .enable_reg     = OMAP3430ES2_CM_FCLKEN3,
1375         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1376         .idlest_bit     = OMAP3430ES2_ST_CPEFUSE_SHIFT,
1377         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1378         .clkdm          = { .name = "cm_clkdm" },
1379         .recalc         = &followparent_recalc,
1380 };
1381
1382 static struct clk ts_fck = {
1383         .name           = "ts_fck",
1384         .parent         = &omap_32k_fck,
1385         .prcm_mod       = CORE_MOD,
1386         .enable_reg     = OMAP3430ES2_CM_FCLKEN3,
1387         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1388         .flags          = CLOCK_IN_OMAP3430ES2,
1389         .clkdm          = { .name = "core_l4_clkdm" },
1390         .recalc         = &followparent_recalc,
1391 };
1392
1393 static struct clk usbtll_fck = {
1394         .name           = "usbtll_fck",
1395         .parent         = &dpll5_m2_ck,
1396         .prcm_mod       = CORE_MOD,
1397         .enable_reg     = OMAP3430ES2_CM_FCLKEN3,
1398         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1399         .idlest_bit     = OMAP3430ES2_ST_USBTLL_SHIFT,
1400         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1401         .clkdm          = { .name = "core_l4_clkdm" },
1402         .recalc         = &followparent_recalc,
1403 };
1404
1405 /* CORE 96M FCLK-derived clocks */
1406
1407 static struct clk core_96m_fck = {
1408         .name           = "core_96m_fck",
1409         .parent         = &omap_96m_fck,
1410         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1411                                 PARENT_CONTROLS_CLOCK,
1412         .clkdm          = { .name = "core_l4_clkdm" },
1413         .recalc         = &followparent_recalc,
1414 };
1415
1416 static struct clk mmchs3_fck = {
1417         .name           = "mmchs_fck",
1418         .id             = 2,
1419         .parent         = &core_96m_fck,
1420         .prcm_mod       = CORE_MOD,
1421         .enable_reg     = CM_FCLKEN1,
1422         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1423         .idlest_bit     = OMAP3430ES2_ST_MMC3_SHIFT,
1424         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1425         .clkdm          = { .name = "core_l4_clkdm" },
1426         .recalc         = &followparent_recalc,
1427 };
1428
1429 static struct clk mmchs2_fck = {
1430         .name           = "mmchs_fck",
1431         .id             = 1,
1432         .parent         = &core_96m_fck,
1433         .prcm_mod       = CORE_MOD,
1434         .enable_reg     = CM_FCLKEN1,
1435         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1436         .idlest_bit     = OMAP3430_ST_MMC2_SHIFT,
1437         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1438         .clkdm          = { .name = "core_l4_clkdm" },
1439         .recalc         = &followparent_recalc,
1440 };
1441
1442 static struct clk mspro_fck = {
1443         .name           = "mspro_fck",
1444         .parent         = &core_96m_fck,
1445         .prcm_mod       = CORE_MOD,
1446         .enable_reg     = CM_FCLKEN1,
1447         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1448         .idlest_bit     = OMAP3430_ST_MSPRO_SHIFT,
1449         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1450         .clkdm          = { .name = "core_l4_clkdm" },
1451         .recalc         = &followparent_recalc,
1452 };
1453
1454 static struct clk mmchs1_fck = {
1455         .name           = "mmchs_fck",
1456         .parent         = &core_96m_fck,
1457         .prcm_mod       = CORE_MOD,
1458         .enable_reg     = CM_FCLKEN1,
1459         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1460         .idlest_bit     = OMAP3430_ST_MMC1_SHIFT,
1461         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1462         .clkdm          = { .name = "core_l4_clkdm" },
1463         .recalc         = &followparent_recalc,
1464 };
1465
1466 static struct clk i2c3_fck = {
1467         .name           = "i2c_fck",
1468         .id             = 3,
1469         .parent         = &core_96m_fck,
1470         .prcm_mod       = CORE_MOD,
1471         .enable_reg     = CM_FCLKEN1,
1472         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1473         .idlest_bit     = OMAP3430_ST_I2C3_SHIFT,
1474         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1475         .clkdm          = { .name = "core_l4_clkdm" },
1476         .recalc         = &followparent_recalc,
1477 };
1478
1479 static struct clk i2c2_fck = {
1480         .name           = "i2c_fck",
1481         .id             = 2,
1482         .parent         = &core_96m_fck,
1483         .prcm_mod       = CORE_MOD,
1484         .enable_reg     = CM_FCLKEN1,
1485         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1486         .idlest_bit     = OMAP3430_ST_I2C2_SHIFT,
1487         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1488         .clkdm          = { .name = "core_l4_clkdm" },
1489         .recalc         = &followparent_recalc,
1490 };
1491
1492 static struct clk i2c1_fck = {
1493         .name           = "i2c_fck",
1494         .id             = 1,
1495         .parent         = &core_96m_fck,
1496         .prcm_mod       = CORE_MOD,
1497         .enable_reg     = CM_FCLKEN1,
1498         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1499         .idlest_bit     = OMAP3430_ST_I2C1_SHIFT,
1500         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1501         .clkdm          = { .name = "core_l4_clkdm" },
1502         .recalc         = &followparent_recalc,
1503 };
1504
1505 /*
1506  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1507  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1508  */
1509 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1510         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1511         { .div = 0 }
1512 };
1513
1514 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1515         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1516         { .div = 0 }
1517 };
1518
1519 static const struct clksel mcbsp_15_clksel[] = {
1520         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1521         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1522         { .parent = NULL }
1523 };
1524
1525 static struct clk mcbsp5_src_fck = {
1526         .name           = "mcbsp_src_fck",
1527         .id             = 5,
1528         .prcm_mod       = CLK_REG_IN_SCM,
1529         .init           = &omap2_init_clksel_parent,
1530         .clksel_reg     = OMAP343X_CONTROL_DEVCONF1,
1531         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1532         .clksel         = mcbsp_15_clksel,
1533         .flags          = CLOCK_IN_OMAP343X,
1534         .clkdm          = { .name = "core_l4_clkdm" },
1535         .recalc         = &omap2_clksel_recalc,
1536 };
1537
1538 static struct clk mcbsp5_fck = {
1539         .name           = "mcbsp_fck",
1540         .id             = 5,
1541         .parent         = &mcbsp5_src_fck,
1542         .prcm_mod       = CORE_MOD,
1543         .enable_reg     = CM_FCLKEN1,
1544         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1545         .idlest_bit     = OMAP3430_ST_MCBSP5_SHIFT,
1546         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1547         .clkdm          = { .name = "core_l4_clkdm" },
1548         .recalc         = &followparent_recalc,
1549 };
1550
1551 static struct clk mcbsp1_src_fck = {
1552         .name           = "mcbsp_src_fck",
1553         .id             = 1,
1554         .prcm_mod       = CLK_REG_IN_SCM,
1555         .init           = &omap2_init_clksel_parent,
1556         .clksel_reg     = OMAP2_CONTROL_DEVCONF0,
1557         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1558         .clksel         = mcbsp_15_clksel,
1559         .flags          = CLOCK_IN_OMAP343X,
1560         .clkdm          = { .name = "core_l4_clkdm" },
1561         .recalc         = &omap2_clksel_recalc,
1562 };
1563
1564 static struct clk mcbsp1_fck = {
1565         .name           = "mcbsp_fck",
1566         .id             = 1,
1567         .parent         = &mcbsp1_src_fck,
1568         .prcm_mod       = CORE_MOD,
1569         .enable_reg     = CM_FCLKEN1,
1570         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1571         .idlest_bit     = OMAP3430_ST_MCBSP1_SHIFT,
1572         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1573         .clkdm          = { .name = "core_l4_clkdm" },
1574         .recalc         = &followparent_recalc,
1575 };
1576
1577 /* CORE_48M_FCK-derived clocks */
1578
1579 static struct clk core_48m_fck = {
1580         .name           = "core_48m_fck",
1581         .parent         = &omap_48m_fck,
1582         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1583                                 PARENT_CONTROLS_CLOCK,
1584         .clkdm          = { .name = "core_l4_clkdm" },
1585         .recalc         = &followparent_recalc,
1586 };
1587
1588 static struct clk mcspi4_fck = {
1589         .name           = "mcspi_fck",
1590         .id             = 4,
1591         .parent         = &core_48m_fck,
1592         .prcm_mod       = CORE_MOD,
1593         .enable_reg     = CM_FCLKEN1,
1594         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1595         .idlest_bit     = OMAP3430_ST_MCSPI4_SHIFT,
1596         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1597         .clkdm          = { .name = "core_l4_clkdm" },
1598         .recalc         = &followparent_recalc,
1599 };
1600
1601 static struct clk mcspi3_fck = {
1602         .name           = "mcspi_fck",
1603         .id             = 3,
1604         .parent         = &core_48m_fck,
1605         .prcm_mod       = CORE_MOD,
1606         .enable_reg     = CM_FCLKEN1,
1607         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1608         .idlest_bit     = OMAP3430_ST_MCSPI3_SHIFT,
1609         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1610         .clkdm          = { .name = "core_l4_clkdm" },
1611         .recalc         = &followparent_recalc,
1612 };
1613
1614 static struct clk mcspi2_fck = {
1615         .name           = "mcspi_fck",
1616         .id             = 2,
1617         .parent         = &core_48m_fck,
1618         .prcm_mod       = CORE_MOD,
1619         .enable_reg     = CM_FCLKEN1,
1620         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1621         .idlest_bit     = OMAP3430_ST_MCSPI2_SHIFT,
1622         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1623         .clkdm          = { .name = "core_l4_clkdm" },
1624         .recalc         = &followparent_recalc,
1625 };
1626
1627 static struct clk mcspi1_fck = {
1628         .name           = "mcspi_fck",
1629         .id             = 1,
1630         .parent         = &core_48m_fck,
1631         .prcm_mod       = CORE_MOD,
1632         .enable_reg     = CM_FCLKEN1,
1633         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1634         .idlest_bit     = OMAP3430_ST_MCSPI1_SHIFT,
1635         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1636         .clkdm          = { .name = "core_l4_clkdm" },
1637         .recalc         = &followparent_recalc,
1638 };
1639
1640 static struct clk uart2_fck = {
1641         .name           = "uart2_fck",
1642         .parent         = &core_48m_fck,
1643         .prcm_mod       = CORE_MOD,
1644         .enable_reg     = CM_FCLKEN1,
1645         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1646         .idlest_bit     = OMAP3430_ST_UART2_SHIFT,
1647         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1648         .clkdm          = { .name = "core_l4_clkdm" },
1649         .recalc         = &followparent_recalc,
1650 };
1651
1652 static struct clk uart1_fck = {
1653         .name           = "uart1_fck",
1654         .parent         = &core_48m_fck,
1655         .prcm_mod       = CORE_MOD,
1656         .enable_reg     = CM_FCLKEN1,
1657         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1658         .idlest_bit     = OMAP3430_ST_UART1_SHIFT,
1659         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1660         .clkdm          = { .name = "core_l4_clkdm" },
1661         .recalc         = &followparent_recalc,
1662 };
1663
1664 /* XXX doublecheck: is this idle or standby? */
1665 static struct clk fshostusb_fck = {
1666         .name           = "fshostusb_fck",
1667         .parent         = &core_48m_fck,
1668         .prcm_mod       = CORE_MOD,
1669         .enable_reg     = CM_FCLKEN1,
1670         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1671         .idlest_bit     = OMAP3430ES1_ST_FSHOSTUSB_SHIFT,
1672         .flags          = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
1673         .clkdm          = { .name = "core_l4_clkdm" },
1674         .recalc         = &followparent_recalc,
1675 };
1676
1677 /* CORE_12M_FCK based clocks */
1678
1679 static struct clk core_12m_fck = {
1680         .name           = "core_12m_fck",
1681         .parent         = &omap_12m_fck,
1682         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1683                                 PARENT_CONTROLS_CLOCK,
1684         .clkdm          = { .name = "core_l4_clkdm" },
1685         .recalc         = &followparent_recalc,
1686 };
1687
1688 static struct clk hdq_fck = {
1689         .name           = "hdq_fck",
1690         .parent         = &core_12m_fck,
1691         .prcm_mod       = CORE_MOD,
1692         .enable_reg     = CM_FCLKEN1,
1693         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1694         .idlest_bit     = OMAP3430_ST_HDQ_SHIFT,
1695         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1696         .clkdm          = { .name = "core_l4_clkdm" },
1697         .recalc         = &followparent_recalc,
1698 };
1699
1700 /* DPLL3-derived clock */
1701
1702 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1703         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1704         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1705         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1706         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1707         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1708         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1709         { .div = 0 }
1710 };
1711
1712 static const struct clksel ssi_ssr_clksel[] = {
1713         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1714         { .parent = NULL }
1715 };
1716
1717 static struct clk ssi_ssr_fck_3430es1 = {
1718         .name           = "ssi_ssr_fck",
1719         .init           = &omap2_init_clksel_parent,
1720         .prcm_mod       = CORE_MOD,
1721         .enable_reg     = CM_FCLKEN1,
1722         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1723         .clksel_reg     = CM_CLKSEL,
1724         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1725         .clksel         = ssi_ssr_clksel,
1726         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
1727         .clkdm          = { .name = "core_l4_clkdm" },
1728         .recalc         = &omap2_clksel_recalc,
1729 };
1730
1731 static struct clk ssi_ssr_fck_3430es2 = {
1732         .name           = "ssi_ssr_fck",
1733         .init           = &omap2_init_clksel_parent,
1734         .prcm_mod       = CORE_MOD,
1735         .enable_reg     = CM_FCLKEN1,
1736         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1737         .idlest_bit     = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
1738         .clksel_reg     = CM_CLKSEL,
1739         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1740         .clksel         = ssi_ssr_clksel,
1741         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | WAIT_READY,
1742         .clkdm          = { .name = "core_l4_clkdm" },
1743         .recalc         = &omap2_clksel_recalc,
1744 };
1745
1746 /* It's unfortunate that we need to duplicate this clock. */
1747 static struct clk ssi_sst_fck_3430es1 = {
1748         .name           = "ssi_sst_fck",
1749         .parent         = &ssi_ssr_fck_3430es1,
1750         .fixed_div      = 2,
1751         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1752         .clkdm          = { .name = "core_l4_clkdm" },
1753         .recalc         = &omap2_fixed_divisor_recalc,
1754 };
1755
1756 static struct clk ssi_sst_fck_3430es2 = {
1757         .name           = "ssi_sst_fck",
1758         .parent         = &ssi_ssr_fck_3430es2,
1759         .fixed_div      = 2,
1760         .flags          = CLOCK_IN_OMAP3430ES2 | PARENT_CONTROLS_CLOCK,
1761         .clkdm          = { .name = "core_l4_clkdm" },
1762         .recalc         = &omap2_fixed_divisor_recalc,
1763 };
1764
1765
1766
1767 /* CORE_L3_ICK based clocks */
1768
1769 /*
1770  * XXX must add clk_enable/clk_disable for these if standard code won't
1771  * handle it
1772  */
1773 static struct clk core_l3_ick = {
1774         .name           = "core_l3_ick",
1775         .parent         = &l3_ick,
1776         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1777                                 PARENT_CONTROLS_CLOCK,
1778         .clkdm          = { .name = "core_l3_clkdm" },
1779         .recalc         = &followparent_recalc,
1780 };
1781
1782 static struct clk hsotgusb_ick_3430es1 = {
1783         .name           = "hsotgusb_ick",
1784         .parent         = &core_l3_ick,
1785         .prcm_mod       = CORE_MOD,
1786         .enable_reg     = CM_ICLKEN1,
1787         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1788         .flags          = CLOCK_IN_OMAP3430ES1,
1789         .clkdm          = { .name = "core_l3_clkdm" },
1790         .recalc         = &followparent_recalc,
1791 };
1792
1793 static struct clk hsotgusb_ick_3430es2 = {
1794         .name           = "hsotgusb_ick",
1795         .parent         = &core_l3_ick,
1796         .prcm_mod       = CORE_MOD,
1797         .enable_reg     = CM_ICLKEN1,
1798         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1799         .idlest_bit     = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1800         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1801         .clkdm          = { .name = "core_l3_clkdm" },
1802         .recalc         = &followparent_recalc,
1803 };
1804
1805 static struct clk sdrc_ick = {
1806         .name           = "sdrc_ick",
1807         .parent         = &core_l3_ick,
1808         .prcm_mod       = CORE_MOD,
1809         .enable_reg     = CM_ICLKEN1,
1810         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1811         .idlest_bit     = OMAP3430_ST_SDRC_SHIFT,
1812         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT | WAIT_READY,
1813         .clkdm          = { .name = "core_l3_clkdm" },
1814         .recalc         = &followparent_recalc,
1815 };
1816
1817 static struct clk gpmc_fck = {
1818         .name           = "gpmc_fck",
1819         .parent         = &core_l3_ick,
1820         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1821                                 ENABLE_ON_INIT,
1822         .clkdm          = { .name = "core_l3_clkdm" },
1823         .recalc         = &followparent_recalc,
1824 };
1825
1826 /* SECURITY_L3_ICK based clocks */
1827
1828 static struct clk security_l3_ick = {
1829         .name           = "security_l3_ick",
1830         .parent         = &l3_ick,
1831         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1832                                 PARENT_CONTROLS_CLOCK,
1833         .clkdm          = { .name = "core_l3_clkdm" },
1834         .recalc         = &followparent_recalc,
1835 };
1836
1837 static struct clk pka_ick = {
1838         .name           = "pka_ick",
1839         .parent         = &security_l3_ick,
1840         .prcm_mod       = CORE_MOD,
1841         .enable_reg     = CM_ICLKEN2,
1842         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1843         .idlest_bit     = OMAP3430_ST_PKA_SHIFT,
1844         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1845         .clkdm          = { .name = "core_l3_clkdm" },
1846         .recalc         = &followparent_recalc,
1847 };
1848
1849 /* CORE_L4_ICK based clocks */
1850
1851 static struct clk core_l4_ick = {
1852         .name           = "core_l4_ick",
1853         .parent         = &l4_ick,
1854         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1855                                 PARENT_CONTROLS_CLOCK,
1856         .clkdm          = { .name = "core_l4_clkdm" },
1857         .recalc         = &followparent_recalc,
1858 };
1859
1860 static struct clk usbtll_ick = {
1861         .name           = "usbtll_ick",
1862         .parent         = &core_l4_ick,
1863         .prcm_mod       = CORE_MOD,
1864         .enable_reg     = CM_ICLKEN3,
1865         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1866         .idlest_bit     = OMAP3430ES2_ST_USBTLL_SHIFT,
1867         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1868         .clkdm          = { .name = "core_l4_clkdm" },
1869         .recalc         = &followparent_recalc,
1870 };
1871
1872 static struct clk mmchs3_ick = {
1873         .name           = "mmchs_ick",
1874         .id             = 2,
1875         .parent         = &core_l4_ick,
1876         .prcm_mod       = CORE_MOD,
1877         .enable_reg     = CM_ICLKEN1,
1878         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1879         .idlest_bit     = OMAP3430ES2_ST_MMC3_SHIFT,
1880         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1881         .clkdm          = { .name = "core_l4_clkdm" },
1882         .recalc         = &followparent_recalc,
1883 };
1884
1885 /* Intersystem Communication Registers - chassis mode only */
1886 static struct clk icr_ick = {
1887         .name           = "icr_ick",
1888         .parent         = &core_l4_ick,
1889         .prcm_mod       = CORE_MOD,
1890         .enable_reg     = CM_ICLKEN1,
1891         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1892         .idlest_bit     = OMAP3430_ST_ICR_SHIFT,
1893         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1894         .clkdm          = { .name = "core_l4_clkdm" },
1895         .recalc         = &followparent_recalc,
1896 };
1897
1898 static struct clk aes2_ick = {
1899         .name           = "aes2_ick",
1900         .parent         = &core_l4_ick,
1901         .prcm_mod       = CORE_MOD,
1902         .enable_reg     = CM_ICLKEN1,
1903         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1904         .idlest_bit     = OMAP3430_ST_AES2_SHIFT,
1905         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1906         .clkdm          = { .name = "core_l4_clkdm" },
1907         .recalc         = &followparent_recalc,
1908 };
1909
1910 static struct clk sha12_ick = {
1911         .name           = "sha12_ick",
1912         .parent         = &core_l4_ick,
1913         .prcm_mod       = CORE_MOD,
1914         .enable_reg     = CM_ICLKEN1,
1915         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1916         .idlest_bit     = OMAP3430_ST_SHA12_SHIFT,
1917         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1918         .clkdm          = { .name = "core_l4_clkdm" },
1919         .recalc         = &followparent_recalc,
1920 };
1921
1922 static struct clk des2_ick = {
1923         .name           = "des2_ick",
1924         .parent         = &core_l4_ick,
1925         .prcm_mod       = CORE_MOD,
1926         .enable_reg     = CM_ICLKEN1,
1927         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1928         .idlest_bit     = OMAP3430_ST_DES2_SHIFT,
1929         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1930         .clkdm          = { .name = "core_l4_clkdm" },
1931         .recalc         = &followparent_recalc,
1932 };
1933
1934 static struct clk mmchs2_ick = {
1935         .name           = "mmchs_ick",
1936         .id             = 1,
1937         .parent         = &core_l4_ick,
1938         .prcm_mod       = CORE_MOD,
1939         .enable_reg     = CM_ICLKEN1,
1940         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1941         .idlest_bit     = OMAP3430_ST_MMC2_SHIFT,
1942         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1943         .clkdm          = { .name = "core_l4_clkdm" },
1944         .recalc         = &followparent_recalc,
1945 };
1946
1947 static struct clk mmchs1_ick = {
1948         .name           = "mmchs_ick",
1949         .parent         = &core_l4_ick,
1950         .prcm_mod       = CORE_MOD,
1951         .enable_reg     = CM_ICLKEN1,
1952         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1953         .idlest_bit     = OMAP3430_ST_MMC1_SHIFT,
1954         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1955         .clkdm          = { .name = "core_l4_clkdm" },
1956         .recalc         = &followparent_recalc,
1957 };
1958
1959 static struct clk mspro_ick = {
1960         .name           = "mspro_ick",
1961         .parent         = &core_l4_ick,
1962         .prcm_mod       = CORE_MOD,
1963         .enable_reg     = CM_ICLKEN1,
1964         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1965         .idlest_bit     = OMAP3430_ST_MSPRO_SHIFT,
1966         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1967         .clkdm          = { .name = "core_l4_clkdm" },
1968         .recalc         = &followparent_recalc,
1969 };
1970
1971 static struct clk hdq_ick = {
1972         .name           = "hdq_ick",
1973         .parent         = &core_l4_ick,
1974         .prcm_mod       = CORE_MOD,
1975         .enable_reg     = CM_ICLKEN1,
1976         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1977         .idlest_bit     = OMAP3430_ST_HDQ_SHIFT,
1978         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1979         .clkdm          = { .name = "core_l4_clkdm" },
1980         .recalc         = &followparent_recalc,
1981 };
1982
1983 static struct clk mcspi4_ick = {
1984         .name           = "mcspi_ick",
1985         .id             = 4,
1986         .parent         = &core_l4_ick,
1987         .prcm_mod       = CORE_MOD,
1988         .enable_reg     = CM_ICLKEN1,
1989         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1990         .idlest_bit     = OMAP3430_ST_MCSPI4_SHIFT,
1991         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1992         .clkdm          = { .name = "core_l4_clkdm" },
1993         .recalc         = &followparent_recalc,
1994 };
1995
1996 static struct clk mcspi3_ick = {
1997         .name           = "mcspi_ick",
1998         .id             = 3,
1999         .parent         = &core_l4_ick,
2000         .prcm_mod       = CORE_MOD,
2001         .enable_reg     = CM_ICLKEN1,
2002         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
2003         .idlest_bit     = OMAP3430_ST_MCSPI3_SHIFT,
2004         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2005         .clkdm          = { .name = "core_l4_clkdm" },
2006         .recalc         = &followparent_recalc,
2007 };
2008
2009 static struct clk mcspi2_ick = {
2010         .name           = "mcspi_ick",
2011         .id             = 2,
2012         .parent         = &core_l4_ick,
2013         .prcm_mod       = CORE_MOD,
2014         .enable_reg     = CM_ICLKEN1,
2015         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
2016         .idlest_bit     = OMAP3430_ST_MCSPI2_SHIFT,
2017         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2018         .clkdm          = { .name = "core_l4_clkdm" },
2019         .recalc         = &followparent_recalc,
2020 };
2021
2022 static struct clk mcspi1_ick = {
2023         .name           = "mcspi_ick",
2024         .id             = 1,
2025         .parent         = &core_l4_ick,
2026         .prcm_mod       = CORE_MOD,
2027         .enable_reg     = CM_ICLKEN1,
2028         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
2029         .idlest_bit     = OMAP3430_ST_MCSPI1_SHIFT,
2030         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2031         .clkdm          = { .name = "core_l4_clkdm" },
2032         .recalc         = &followparent_recalc,
2033 };
2034
2035 static struct clk i2c3_ick = {
2036         .name           = "i2c_ick",
2037         .id             = 3,
2038         .parent         = &core_l4_ick,
2039         .prcm_mod       = CORE_MOD,
2040         .enable_reg     = CM_ICLKEN1,
2041         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
2042         .idlest_bit     = OMAP3430_ST_I2C3_SHIFT,
2043         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2044         .clkdm          = { .name = "core_l4_clkdm" },
2045         .recalc         = &followparent_recalc,
2046 };
2047
2048 static struct clk i2c2_ick = {
2049         .name           = "i2c_ick",
2050         .id             = 2,
2051         .parent         = &core_l4_ick,
2052         .prcm_mod       = CORE_MOD,
2053         .enable_reg     = CM_ICLKEN1,
2054         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
2055         .idlest_bit     = OMAP3430_ST_I2C2_SHIFT,
2056         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2057         .clkdm          = { .name = "core_l4_clkdm" },
2058         .recalc         = &followparent_recalc,
2059 };
2060
2061 static struct clk i2c1_ick = {
2062         .name           = "i2c_ick",
2063         .id             = 1,
2064         .parent         = &core_l4_ick,
2065         .prcm_mod       = CORE_MOD,
2066         .enable_reg     = CM_ICLKEN1,
2067         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
2068         .idlest_bit     = OMAP3430_ST_I2C1_SHIFT,
2069         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2070         .clkdm          = { .name = "core_l4_clkdm" },
2071         .recalc         = &followparent_recalc,
2072 };
2073
2074 static struct clk uart2_ick = {
2075         .name           = "uart2_ick",
2076         .parent         = &core_l4_ick,
2077         .prcm_mod       = CORE_MOD,
2078         .enable_reg     = CM_ICLKEN1,
2079         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
2080         .idlest_bit     = OMAP3430_ST_UART2_SHIFT,
2081         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2082         .clkdm          = { .name = "core_l4_clkdm" },
2083         .recalc         = &followparent_recalc,
2084 };
2085
2086 static struct clk uart1_ick = {
2087         .name           = "uart1_ick",
2088         .parent         = &core_l4_ick,
2089         .prcm_mod       = CORE_MOD,
2090         .enable_reg     = CM_ICLKEN1,
2091         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
2092         .idlest_bit     = OMAP3430_ST_UART1_SHIFT,
2093         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2094         .clkdm          = { .name = "core_l4_clkdm" },
2095         .recalc         = &followparent_recalc,
2096 };
2097
2098 static struct clk gpt11_ick = {
2099         .name           = "gpt11_ick",
2100         .parent         = &core_l4_ick,
2101         .prcm_mod       = CORE_MOD,
2102         .enable_reg     = CM_ICLKEN1,
2103         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
2104         .idlest_bit     = OMAP3430_ST_GPT11_SHIFT,
2105         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2106         .clkdm          = { .name = "core_l4_clkdm" },
2107         .recalc         = &followparent_recalc,
2108 };
2109
2110 static struct clk gpt10_ick = {
2111         .name           = "gpt10_ick",
2112         .parent         = &core_l4_ick,
2113         .prcm_mod       = CORE_MOD,
2114         .enable_reg     = CM_ICLKEN1,
2115         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
2116         .idlest_bit     = OMAP3430_ST_GPT10_SHIFT,
2117         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2118         .clkdm          = { .name = "core_l4_clkdm" },
2119         .recalc         = &followparent_recalc,
2120 };
2121
2122 static struct clk mcbsp5_ick = {
2123         .name           = "mcbsp_ick",
2124         .id             = 5,
2125         .parent         = &core_l4_ick,
2126         .prcm_mod       = CORE_MOD,
2127         .enable_reg     = CM_ICLKEN1,
2128         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
2129         .idlest_bit     = OMAP3430_ST_MCBSP5_SHIFT,
2130         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2131         .clkdm          = { .name = "core_l4_clkdm" },
2132         .recalc         = &followparent_recalc,
2133 };
2134
2135 static struct clk mcbsp1_ick = {
2136         .name           = "mcbsp_ick",
2137         .id             = 1,
2138         .parent         = &core_l4_ick,
2139         .prcm_mod       = CORE_MOD,
2140         .enable_reg     = CM_ICLKEN1,
2141         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2142         .idlest_bit     = OMAP3430_ST_MCBSP1_SHIFT,
2143         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2144         .clkdm          = { .name = "core_l4_clkdm" },
2145         .recalc         = &followparent_recalc,
2146 };
2147
2148 static struct clk fac_ick = {
2149         .name           = "fac_ick",
2150         .parent         = &core_l4_ick,
2151         .prcm_mod       = CORE_MOD,
2152         .enable_reg     = CM_ICLKEN1,
2153         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
2154         .idlest_bit     = OMAP3430ES1_ST_FAC_SHIFT,
2155         .flags          = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
2156         .clkdm          = { .name = "core_l4_clkdm" },
2157         .recalc         = &followparent_recalc,
2158 };
2159
2160 static struct clk mailboxes_ick = {
2161         .name           = "mailboxes_ick",
2162         .parent         = &core_l4_ick,
2163         .prcm_mod       = CORE_MOD,
2164         .enable_reg     = CM_ICLKEN1,
2165         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2166         .idlest_bit     = OMAP3430_ST_MAILBOXES_SHIFT,
2167         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2168         .clkdm          = { .name = "core_l4_clkdm" },
2169         .recalc         = &followparent_recalc,
2170 };
2171
2172 static struct clk omapctrl_ick = {
2173         .name           = "omapctrl_ick",
2174         .parent         = &core_l4_ick,
2175         .prcm_mod       = CORE_MOD,
2176         .enable_reg     = CM_ICLKEN1,
2177         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2178         .idlest_bit     = OMAP3430_ST_OMAPCTRL_SHIFT,
2179         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT | WAIT_READY,
2180         .clkdm          = { .name = "core_l4_clkdm" },
2181         .recalc         = &followparent_recalc,
2182 };
2183
2184 /* SSI_L4_ICK based clocks */
2185
2186 static struct clk ssi_l4_ick = {
2187         .name           = "ssi_l4_ick",
2188         .parent         = &l4_ick,
2189         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2190                                 PARENT_CONTROLS_CLOCK,
2191         .clkdm          = { .name = "core_l4_clkdm" },
2192         .recalc         = &followparent_recalc,
2193 };
2194
2195 static struct clk ssi_ick_3430es1 = {
2196         .name           = "ssi_ick",
2197         .parent         = &ssi_l4_ick,
2198         .prcm_mod       = CORE_MOD,
2199         .enable_reg     = CM_ICLKEN1,
2200         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2201         .flags          = CLOCK_IN_OMAP3430ES1,
2202         .clkdm          = { .name = "core_l4_clkdm" },
2203         .recalc         = &followparent_recalc,
2204 };
2205
2206 static struct clk ssi_ick_3430es2 = {
2207         .name           = "ssi_ick",
2208         .parent         = &ssi_l4_ick,
2209         .prcm_mod       = CORE_MOD,
2210         .enable_reg     = CM_ICLKEN1,
2211         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2212         .idlest_bit     = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
2213         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2214         .clkdm          = { .name = "core_l4_clkdm" },
2215         .recalc         = &followparent_recalc,
2216 };
2217
2218 /*
2219  * REVISIT: Technically the TRM claims that this is CORE_CLK based,
2220  * but l4_ick makes more sense to me
2221  */
2222 static const struct clksel usb_l4_clksel[] = {
2223         { .parent = &l4_ick, .rates = div2_rates },
2224         { .parent = NULL },
2225 };
2226
2227 static struct clk usb_l4_ick = {
2228         .name           = "usb_l4_ick",
2229         .parent         = &l4_ick,
2230         .prcm_mod       = CORE_MOD,
2231         .init           = &omap2_init_clksel_parent,
2232         .enable_reg     = CM_ICLKEN1,
2233         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2234         .idlest_bit     = OMAP3430ES1_ST_FSHOSTUSB_SHIFT,
2235         .clksel_reg     = CM_CLKSEL,
2236         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2237         .clksel         = usb_l4_clksel,
2238         .flags          = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
2239         .clkdm          = { .name = "core_l4_clkdm" },
2240         .recalc         = &omap2_clksel_recalc,
2241 };
2242
2243 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2244
2245 /* SECURITY_L4_ICK2 based clocks */
2246
2247 static struct clk security_l4_ick2 = {
2248         .name           = "security_l4_ick2",
2249         .parent         = &l4_ick,
2250         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2251                                 PARENT_CONTROLS_CLOCK,
2252         .clkdm          = { .name = "core_l4_clkdm" },
2253         .recalc         = &followparent_recalc,
2254 };
2255
2256 static struct clk aes1_ick = {
2257         .name           = "aes1_ick",
2258         .parent         = &security_l4_ick2,
2259         .prcm_mod       = CORE_MOD,
2260         .enable_reg     = CM_ICLKEN2,
2261         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2262         .idlest_bit     = OMAP3430_ST_AES1_SHIFT,
2263         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2264         .clkdm          = { .name = "core_l4_clkdm" },
2265         .recalc         = &followparent_recalc,
2266 };
2267
2268 static struct clk rng_ick = {
2269         .name           = "rng_ick",
2270         .parent         = &security_l4_ick2,
2271         .prcm_mod       = CORE_MOD,
2272         .enable_reg     = CM_ICLKEN2,
2273         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2274         .idlest_bit     = OMAP3430_ST_RNG_SHIFT,
2275         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2276         .clkdm          = { .name = "core_l4_clkdm" },
2277         .recalc         = &followparent_recalc,
2278 };
2279
2280 static struct clk sha11_ick = {
2281         .name           = "sha11_ick",
2282         .parent         = &security_l4_ick2,
2283         .prcm_mod       = CORE_MOD,
2284         .enable_reg     = CM_ICLKEN2,
2285         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2286         .idlest_bit     = OMAP3430_ST_SHA11_SHIFT,
2287         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2288         .clkdm          = { .name = "core_l4_clkdm" },
2289         .recalc         = &followparent_recalc,
2290 };
2291
2292 static struct clk des1_ick = {
2293         .name           = "des1_ick",
2294         .parent         = &security_l4_ick2,
2295         .prcm_mod       = CORE_MOD,
2296         .enable_reg     = CM_ICLKEN2,
2297         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2298         .idlest_bit     = OMAP3430_ST_DES1_SHIFT,
2299         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2300         .clkdm          = { .name = "core_l4_clkdm" },
2301         .recalc         = &followparent_recalc,
2302 };
2303
2304 /* DSS */
2305 static struct clk dss1_alwon_fck_3430es1 = {
2306         .name           = "dss1_alwon_fck",
2307         .parent         = &dpll4_m4x2_ck,
2308         .prcm_mod       = OMAP3430_DSS_MOD,
2309         .enable_reg     = CM_FCLKEN,
2310         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2311         .flags          = CLOCK_IN_OMAP3430ES1,
2312         .clkdm          = { .name = "dss_clkdm" },
2313         .recalc         = &followparent_recalc,
2314 };
2315
2316 static struct clk dss1_alwon_fck_3430es2 = {
2317         .name           = "dss1_alwon_fck",
2318         .parent         = &dpll4_m4x2_ck,
2319         .init           = &omap2_init_clksel_parent,
2320         .prcm_mod       = OMAP3430_DSS_MOD,
2321         .enable_reg     = CM_FCLKEN,
2322         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2323         .idlest_bit     = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
2324         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2325         .clkdm          = { .name = "dss_clkdm" },
2326         .recalc         = &followparent_recalc,
2327 };
2328
2329 static struct clk dss_tv_fck = {
2330         .name           = "dss_tv_fck",
2331         .parent         = &omap_54m_fck,
2332         .prcm_mod       = OMAP3430_DSS_MOD,
2333         .enable_reg     = CM_FCLKEN,
2334         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2335         .flags          = CLOCK_IN_OMAP343X,
2336         .clkdm          = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */
2337         .recalc         = &followparent_recalc,
2338 };
2339
2340 static struct clk dss_96m_fck = {
2341         .name           = "dss_96m_fck",
2342         .parent         = &omap_96m_fck,
2343         .prcm_mod       = OMAP3430_DSS_MOD,
2344         .enable_reg     = CM_FCLKEN,
2345         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2346         .flags          = CLOCK_IN_OMAP343X,
2347         .clkdm          = { .name = "dss_clkdm" },
2348         .recalc         = &followparent_recalc,
2349 };
2350
2351 static struct clk dss2_alwon_fck = {
2352         .name           = "dss2_alwon_fck",
2353         .parent         = &sys_ck,
2354         .prcm_mod       = OMAP3430_DSS_MOD,
2355         .enable_reg     = CM_FCLKEN,
2356         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2357         .flags          = CLOCK_IN_OMAP343X,
2358         .clkdm          = { .name = "dss_clkdm" },
2359         .recalc         = &followparent_recalc,
2360 };
2361
2362 static struct clk dss_ick_3430es1 = {
2363         /* Handles both L3 and L4 clocks */
2364         .name           = "dss_ick",
2365         .parent         = &l4_ick,
2366         .prcm_mod       = OMAP3430_DSS_MOD,
2367         .enable_reg     = CM_ICLKEN,
2368         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2369         .flags          = CLOCK_IN_OMAP3430ES1,
2370         .clkdm          = { .name = "dss_clkdm" },
2371         .recalc         = &followparent_recalc,
2372 };
2373
2374 static struct clk dss_ick_3430es2 = {
2375         /* Handles both L3 and L4 clocks */
2376         .name           = "dss_ick",
2377         .parent         = &l4_ick,
2378         .prcm_mod       = OMAP3430_DSS_MOD,
2379         .enable_reg     = CM_ICLKEN,
2380         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2381         .idlest_bit     = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
2382         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2383         .clkdm          = { .name = "dss_clkdm" },
2384         .recalc         = &followparent_recalc,
2385 };
2386
2387 /* CAM */
2388
2389 static struct clk cam_mclk = {
2390         .name           = "cam_mclk",
2391         .parent         = &dpll4_m5x2_ck,
2392         .prcm_mod       = OMAP3430_CAM_MOD,
2393         .enable_reg     = CM_FCLKEN,
2394         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2395         .flags          = CLOCK_IN_OMAP343X,
2396         .clkdm          = { .name = "cam_clkdm" },
2397         .recalc         = &followparent_recalc,
2398 };
2399
2400 static struct clk cam_ick = {
2401         /* Handles both L3 and L4 clocks */
2402         .name           = "cam_ick",
2403         .parent         = &l4_ick,
2404         .prcm_mod       = OMAP3430_CAM_MOD,
2405         .enable_reg     = CM_ICLKEN,
2406         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2407         .flags          = CLOCK_IN_OMAP343X,
2408         .clkdm          = { .name = "cam_clkdm" },
2409         .recalc         = &followparent_recalc,
2410 };
2411
2412 static struct clk csi2_96m_fck = {
2413         .name           = "csi2_96m_fck",
2414         .parent         = &core_96m_fck,
2415         .prcm_mod       = OMAP3430_CAM_MOD,
2416         .enable_reg     = CM_FCLKEN,
2417         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2418         .flags          = CLOCK_IN_OMAP343X,
2419         .clkdm          = { .name = "cam_clkdm" },
2420         .recalc         = &followparent_recalc,
2421 };
2422
2423 /* USBHOST - 3430ES2 only */
2424
2425 static struct clk usbhost_120m_fck = {
2426         .name           = "usbhost_120m_fck",
2427         .parent         = &dpll5_m2_ck,
2428         .prcm_mod       = OMAP3430ES2_USBHOST_MOD,
2429         .enable_reg     = CM_FCLKEN,
2430         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2431         .flags          = CLOCK_IN_OMAP3430ES2,
2432         .clkdm          = { .name = "usbhost_clkdm" },
2433         .recalc         = &followparent_recalc,
2434 };
2435
2436 static struct clk usbhost_48m_fck = {
2437         .name           = "usbhost_48m_fck",
2438         .parent         = &omap_48m_fck,
2439         .prcm_mod       = OMAP3430ES2_USBHOST_MOD,
2440         .enable_reg     = CM_FCLKEN,
2441         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2442         .idlest_bit     = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
2443         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2444         .clkdm          = { .name = "usbhost_clkdm" },
2445         .recalc         = &followparent_recalc,
2446 };
2447
2448 static struct clk usbhost_ick = {
2449         /* Handles both L3 and L4 clocks */
2450         .name           = "usbhost_ick",
2451         .parent         = &l4_ick,
2452         .prcm_mod       = OMAP3430ES2_USBHOST_MOD,
2453         .enable_reg     = CM_ICLKEN,
2454         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2455         .idlest_bit     = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
2456         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2457         .clkdm          = { .name = "usbhost_clkdm" },
2458         .recalc         = &followparent_recalc,
2459 };
2460
2461 /* WKUP */
2462
2463 static const struct clksel_rate usim_96m_rates[] = {
2464         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2465         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2466         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2467         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2468         { .div = 0 },
2469 };
2470
2471 static const struct clksel_rate usim_120m_rates[] = {
2472         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2473         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2474         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2475         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2476         { .div = 0 },
2477 };
2478
2479 static const struct clksel usim_clksel[] = {
2480         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2481         { .parent = &dpll5_m2_ck,       .rates = usim_120m_rates },
2482         { .parent = &sys_ck,            .rates = div2_rates },
2483         { .parent = NULL },
2484 };
2485
2486 /* 3430ES2 only */
2487 static struct clk usim_fck = {
2488         .name           = "usim_fck",
2489         .prcm_mod       = WKUP_MOD,
2490         .init           = &omap2_init_clksel_parent,
2491         .enable_reg     = CM_FCLKEN,
2492         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2493         .idlest_bit     = OMAP3430ES2_ST_USIMOCP_SHIFT,
2494         .clksel_reg     = CM_CLKSEL,
2495         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2496         .clksel         = usim_clksel,
2497         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2498         .clkdm          = { .name = "prm_clkdm" },
2499         .recalc         = &omap2_clksel_recalc,
2500 };
2501
2502 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2503 static struct clk gpt1_fck = {
2504         .name           = "gpt1_fck",
2505         .prcm_mod       = WKUP_MOD,
2506         .init           = &omap2_init_clksel_parent,
2507         .enable_reg     = CM_FCLKEN,
2508         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2509         .idlest_bit     = OMAP3430_ST_GPT1_SHIFT,
2510         .clksel_reg     = CM_CLKSEL,
2511         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2512         .clksel         = omap343x_gpt_clksel,
2513         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2514         .clkdm          = { .name = "prm_clkdm" },
2515         .recalc         = &omap2_clksel_recalc,
2516 };
2517
2518 static struct clk wkup_32k_fck = {
2519         .name           = "wkup_32k_fck",
2520         .parent         = &omap_32k_fck,
2521         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2522         .clkdm          = { .name = "prm_clkdm" },
2523         .recalc         = &followparent_recalc,
2524 };
2525
2526 static struct clk gpio1_dbck = {
2527         .name           = "gpio1_dbck",
2528         .parent         = &wkup_32k_fck,
2529         .prcm_mod       = WKUP_MOD,
2530         .enable_reg     = CM_FCLKEN,
2531         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2532         .idlest_bit     = OMAP3430_ST_GPIO1_SHIFT,
2533         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2534         .clkdm          = { .name = "prm_clkdm" },
2535         .recalc         = &followparent_recalc,
2536 };
2537
2538 static struct clk wdt2_fck = {
2539         .name           = "wdt2_fck",
2540         .parent         = &wkup_32k_fck,
2541         .prcm_mod       = WKUP_MOD,
2542         .enable_reg     = CM_FCLKEN,
2543         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2544         .idlest_bit     = OMAP3430_ST_WDT2_SHIFT,
2545         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2546         .clkdm          = { .name = "prm_clkdm" },
2547         .recalc         = &followparent_recalc,
2548 };
2549
2550 static struct clk wkup_l4_ick = {
2551         .name           = "wkup_l4_ick",
2552         .parent         = &sys_ck,
2553         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2554         .clkdm          = { .name = "prm_clkdm" },
2555         .recalc         = &followparent_recalc,
2556 };
2557
2558 static struct clk usim_ick = {
2559         .name           = "usim_ick",
2560         .parent         = &wkup_l4_ick,
2561         .prcm_mod       = WKUP_MOD,
2562         .enable_reg     = CM_ICLKEN,
2563         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2564         .idlest_bit     = OMAP3430ES2_ST_USIMOCP_SHIFT,
2565         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2566         .clkdm          = { .name = "prm_clkdm" },
2567         .recalc         = &followparent_recalc,
2568 };
2569
2570 static struct clk wdt2_ick = {
2571         .name           = "wdt2_ick",
2572         .parent         = &wkup_l4_ick,
2573         .prcm_mod       = WKUP_MOD,
2574         .enable_reg     = CM_ICLKEN,
2575         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2576         .idlest_bit     = OMAP3430_ST_WDT2_SHIFT,
2577         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2578         .clkdm          = { .name = "prm_clkdm" },
2579         .recalc         = &followparent_recalc,
2580 };
2581
2582 static struct clk wdt1_ick = {
2583         .name           = "wdt1_ick",
2584         .parent         = &wkup_l4_ick,
2585         .prcm_mod       = WKUP_MOD,
2586         .enable_reg     = CM_ICLKEN,
2587         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2588         .idlest_bit     = OMAP3430_ST_WDT1_SHIFT,
2589         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2590         .clkdm          = { .name = "prm_clkdm" },
2591         .recalc         = &followparent_recalc,
2592 };
2593
2594 static struct clk gpio1_ick = {
2595         .name           = "gpio1_ick",
2596         .parent         = &wkup_l4_ick,
2597         .prcm_mod       = WKUP_MOD,
2598         .enable_reg     = CM_ICLKEN,
2599         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2600         .idlest_bit     = OMAP3430_ST_GPIO1_SHIFT,
2601         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2602         .clkdm          = { .name = "prm_clkdm" },
2603         .recalc         = &followparent_recalc,
2604 };
2605
2606 static struct clk omap_32ksync_ick = {
2607         .name           = "omap_32ksync_ick",
2608         .parent         = &wkup_l4_ick,
2609         .prcm_mod       = WKUP_MOD,
2610         .enable_reg     = CM_ICLKEN,
2611         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2612         .idlest_bit     = OMAP3430_ST_32KSYNC_SHIFT,
2613         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2614         .clkdm          = { .name = "prm_clkdm" },
2615         .recalc         = &followparent_recalc,
2616 };
2617
2618 static struct clk gpt12_ick = {
2619         .name           = "gpt12_ick",
2620         .parent         = &wkup_l4_ick,
2621         .prcm_mod       = WKUP_MOD,
2622         .enable_reg     = CM_ICLKEN,
2623         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2624         .idlest_bit     = OMAP3430_ST_GPT12_SHIFT,
2625         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2626         .clkdm          = { .name = "prm_clkdm" },
2627         .recalc         = &followparent_recalc,
2628 };
2629
2630 static struct clk gpt1_ick = {
2631         .name           = "gpt1_ick",
2632         .parent         = &wkup_l4_ick,
2633         .prcm_mod       = WKUP_MOD,
2634         .enable_reg     = CM_ICLKEN,
2635         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2636         .idlest_bit     = OMAP3430_ST_GPT1_SHIFT,
2637         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2638         .clkdm          = { .name = "prm_clkdm" },
2639         .recalc         = &followparent_recalc,
2640 };
2641
2642
2643
2644 /* PER clock domain */
2645
2646 static struct clk per_96m_fck = {
2647         .name           = "per_96m_fck",
2648         .parent         = &omap_96m_alwon_fck,
2649         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2650                                 PARENT_CONTROLS_CLOCK,
2651         .clkdm          = { .name = "per_clkdm" },
2652         .recalc         = &followparent_recalc,
2653 };
2654
2655 static struct clk per_48m_fck = {
2656         .name           = "per_48m_fck",
2657         .parent         = &omap_48m_fck,
2658         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2659                                 PARENT_CONTROLS_CLOCK,
2660         .clkdm          = { .name = "per_clkdm" },
2661         .recalc         = &followparent_recalc,
2662 };
2663
2664 static struct clk uart3_fck = {
2665         .name           = "uart3_fck",
2666         .parent         = &per_48m_fck,
2667         .prcm_mod       = OMAP3430_PER_MOD,
2668         .enable_reg     = CM_FCLKEN,
2669         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2670         .idlest_bit     = OMAP3430_ST_UART3_SHIFT,
2671         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2672         .clkdm          = { .name = "per_clkdm" },
2673         .recalc         = &followparent_recalc,
2674 };
2675
2676 static struct clk gpt2_fck = {
2677         .name           = "gpt2_fck",
2678         .prcm_mod       = OMAP3430_PER_MOD,
2679         .init           = &omap2_init_clksel_parent,
2680         .enable_reg     = CM_FCLKEN,
2681         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2682         .idlest_bit     = OMAP3430_ST_GPT2_SHIFT,
2683         .clksel_reg     = CM_CLKSEL,
2684         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2685         .clksel         = omap343x_gpt_clksel,
2686         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2687         .clkdm          = { .name = "per_clkdm" },
2688         .recalc         = &omap2_clksel_recalc,
2689 };
2690
2691 static struct clk gpt3_fck = {
2692         .name           = "gpt3_fck",
2693         .prcm_mod       = OMAP3430_PER_MOD,
2694         .init           = &omap2_init_clksel_parent,
2695         .enable_reg     = CM_FCLKEN,
2696         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2697         .idlest_bit     = OMAP3430_ST_GPT3_SHIFT,
2698         .clksel_reg     = CM_CLKSEL,
2699         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2700         .clksel         = omap343x_gpt_clksel,
2701         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2702         .clkdm          = { .name = "per_clkdm" },
2703         .recalc         = &omap2_clksel_recalc,
2704 };
2705
2706 static struct clk gpt4_fck = {
2707         .name           = "gpt4_fck",
2708         .prcm_mod       = OMAP3430_PER_MOD,
2709         .init           = &omap2_init_clksel_parent,
2710         .enable_reg     = CM_FCLKEN,
2711         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2712         .idlest_bit     = OMAP3430_ST_GPT4_SHIFT,
2713         .clksel_reg     = CM_CLKSEL,
2714         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2715         .clksel         = omap343x_gpt_clksel,
2716         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2717         .clkdm          = { .name = "per_clkdm" },
2718         .recalc         = &omap2_clksel_recalc,
2719 };
2720
2721 static struct clk gpt5_fck = {
2722         .name           = "gpt5_fck",
2723         .prcm_mod       = OMAP3430_PER_MOD,
2724         .init           = &omap2_init_clksel_parent,
2725         .enable_reg     = CM_FCLKEN,
2726         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2727         .idlest_bit     = OMAP3430_ST_GPT5_SHIFT,
2728         .clksel_reg     = CM_CLKSEL,
2729         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2730         .clksel         = omap343x_gpt_clksel,
2731         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2732         .clkdm          = { .name = "per_clkdm" },
2733         .recalc         = &omap2_clksel_recalc,
2734 };
2735
2736 static struct clk gpt6_fck = {
2737         .name           = "gpt6_fck",
2738         .prcm_mod       = OMAP3430_PER_MOD,
2739         .init           = &omap2_init_clksel_parent,
2740         .enable_reg     = CM_FCLKEN,
2741         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2742         .idlest_bit     = OMAP3430_ST_GPT6_SHIFT,
2743         .clksel_reg     = CM_CLKSEL,
2744         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2745         .clksel         = omap343x_gpt_clksel,
2746         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2747         .clkdm          = { .name = "per_clkdm" },
2748         .recalc         = &omap2_clksel_recalc,
2749 };
2750
2751 static struct clk gpt7_fck = {
2752         .name           = "gpt7_fck",
2753         .prcm_mod       = OMAP3430_PER_MOD,
2754         .init           = &omap2_init_clksel_parent,
2755         .enable_reg     = CM_FCLKEN,
2756         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2757         .idlest_bit     = OMAP3430_ST_GPT7_SHIFT,
2758         .clksel_reg     = CM_CLKSEL,
2759         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2760         .clksel         = omap343x_gpt_clksel,
2761         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2762         .clkdm          = { .name = "per_clkdm" },
2763         .recalc         = &omap2_clksel_recalc,
2764 };
2765
2766 static struct clk gpt8_fck = {
2767         .name           = "gpt8_fck",
2768         .prcm_mod       = OMAP3430_PER_MOD,
2769         .init           = &omap2_init_clksel_parent,
2770         .enable_reg     = CM_FCLKEN,
2771         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2772         .idlest_bit     = OMAP3430_ST_GPT8_SHIFT,
2773         .clksel_reg     = CM_CLKSEL,
2774         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2775         .clksel         = omap343x_gpt_clksel,
2776         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2777         .clkdm          = { .name = "per_clkdm" },
2778         .recalc         = &omap2_clksel_recalc,
2779 };
2780
2781 static struct clk gpt9_fck = {
2782         .name           = "gpt9_fck",
2783         .prcm_mod       = OMAP3430_PER_MOD,
2784         .init           = &omap2_init_clksel_parent,
2785         .enable_reg     = CM_FCLKEN,
2786         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2787         .idlest_bit     = OMAP3430_ST_GPT9_SHIFT,
2788         .clksel_reg     = CM_CLKSEL,
2789         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2790         .clksel         = omap343x_gpt_clksel,
2791         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2792         .clkdm          = { .name = "per_clkdm" },
2793         .recalc         = &omap2_clksel_recalc,
2794 };
2795
2796 static struct clk per_32k_alwon_fck = {
2797         .name           = "per_32k_alwon_fck",
2798         .parent         = &omap_32k_fck,
2799         .clkdm          = { .name = "per_clkdm" },
2800         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2801         .recalc         = &followparent_recalc,
2802 };
2803
2804 static struct clk gpio6_dbck = {
2805         .name           = "gpio6_dbck",
2806         .parent         = &per_32k_alwon_fck,
2807         .prcm_mod       = OMAP3430_PER_MOD,
2808         .enable_reg     = CM_FCLKEN,
2809         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2810         .idlest_bit     = OMAP3430_ST_GPIO6_SHIFT,
2811         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2812         .clkdm          = { .name = "per_clkdm" },
2813         .recalc         = &followparent_recalc,
2814 };
2815
2816 static struct clk gpio5_dbck = {
2817         .name           = "gpio5_dbck",
2818         .parent         = &per_32k_alwon_fck,
2819         .prcm_mod       = OMAP3430_PER_MOD,
2820         .enable_reg     = CM_FCLKEN,
2821         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2822         .idlest_bit     = OMAP3430_ST_GPIO5_SHIFT,
2823         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2824         .clkdm          = { .name = "per_clkdm" },
2825         .recalc         = &followparent_recalc,
2826 };
2827
2828 static struct clk gpio4_dbck = {
2829         .name           = "gpio4_dbck",
2830         .parent         = &per_32k_alwon_fck,
2831         .prcm_mod       = OMAP3430_PER_MOD,
2832         .enable_reg     = CM_FCLKEN,
2833         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2834         .idlest_bit     = OMAP3430_ST_GPIO4_SHIFT,
2835         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2836         .clkdm          = { .name = "per_clkdm" },
2837         .recalc         = &followparent_recalc,
2838 };
2839
2840 static struct clk gpio3_dbck = {
2841         .name           = "gpio3_dbck",
2842         .parent         = &per_32k_alwon_fck,
2843         .prcm_mod       = OMAP3430_PER_MOD,
2844         .enable_reg     = CM_FCLKEN,
2845         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2846         .idlest_bit     = OMAP3430_ST_GPIO3_SHIFT,
2847         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2848         .clkdm          = { .name = "per_clkdm" },
2849         .recalc         = &followparent_recalc,
2850 };
2851
2852 static struct clk gpio2_dbck = {
2853         .name           = "gpio2_dbck",
2854         .parent         = &per_32k_alwon_fck,
2855         .prcm_mod       = OMAP3430_PER_MOD,
2856         .enable_reg     = CM_FCLKEN,
2857         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2858         .idlest_bit     = OMAP3430_ST_GPIO2_SHIFT,
2859         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2860         .clkdm          = { .name = "per_clkdm" },
2861         .recalc         = &followparent_recalc,
2862 };
2863
2864 static struct clk wdt3_fck = {
2865         .name           = "wdt3_fck",
2866         .parent         = &per_32k_alwon_fck,
2867         .prcm_mod       = OMAP3430_PER_MOD,
2868         .enable_reg     = CM_FCLKEN,
2869         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2870         .idlest_bit     = OMAP3430_ST_WDT3_SHIFT,
2871         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2872         .clkdm          = { .name = "per_clkdm" },
2873         .recalc         = &followparent_recalc,
2874 };
2875
2876 static struct clk per_l4_ick = {
2877         .name           = "per_l4_ick",
2878         .parent         = &l4_ick,
2879         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2880                                 PARENT_CONTROLS_CLOCK,
2881         .clkdm          = { .name = "per_clkdm" },
2882         .recalc         = &followparent_recalc,
2883 };
2884
2885 static struct clk gpio6_ick = {
2886         .name           = "gpio6_ick",
2887         .parent         = &per_l4_ick,
2888         .prcm_mod       = OMAP3430_PER_MOD,
2889         .enable_reg     = CM_ICLKEN,
2890         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2891         .idlest_bit     = OMAP3430_ST_GPIO6_SHIFT,
2892         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2893         .clkdm          = { .name = "per_clkdm" },
2894         .recalc         = &followparent_recalc,
2895 };
2896
2897 static struct clk gpio5_ick = {
2898         .name           = "gpio5_ick",
2899         .parent         = &per_l4_ick,
2900         .prcm_mod       = OMAP3430_PER_MOD,
2901         .enable_reg     = CM_ICLKEN,
2902         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2903         .idlest_bit     = OMAP3430_ST_GPIO5_SHIFT,
2904         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2905         .clkdm          = { .name = "per_clkdm" },
2906         .recalc         = &followparent_recalc,
2907 };
2908
2909 static struct clk gpio4_ick = {
2910         .name           = "gpio4_ick",
2911         .parent         = &per_l4_ick,
2912         .prcm_mod       = OMAP3430_PER_MOD,
2913         .enable_reg     = CM_ICLKEN,
2914         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2915         .idlest_bit     = OMAP3430_ST_GPIO4_SHIFT,
2916         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2917         .clkdm          = { .name = "per_clkdm" },
2918         .recalc         = &followparent_recalc,
2919 };
2920
2921 static struct clk gpio3_ick = {
2922         .name           = "gpio3_ick",
2923         .parent         = &per_l4_ick,
2924         .prcm_mod       = OMAP3430_PER_MOD,
2925         .enable_reg     = CM_ICLKEN,
2926         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2927         .idlest_bit     = OMAP3430_ST_GPIO3_SHIFT,
2928         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2929         .clkdm          = { .name = "per_clkdm" },
2930         .recalc         = &followparent_recalc,
2931 };
2932
2933 static struct clk gpio2_ick = {
2934         .name           = "gpio2_ick",
2935         .parent         = &per_l4_ick,
2936         .prcm_mod       = OMAP3430_PER_MOD,
2937         .enable_reg     = CM_ICLKEN,
2938         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2939         .idlest_bit     = OMAP3430_ST_GPIO2_SHIFT,
2940         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2941         .clkdm          = { .name = "per_clkdm" },
2942         .recalc         = &followparent_recalc,
2943 };
2944
2945 static struct clk wdt3_ick = {
2946         .name           = "wdt3_ick",
2947         .parent         = &per_l4_ick,
2948         .prcm_mod       = OMAP3430_PER_MOD,
2949         .enable_reg     = CM_ICLKEN,
2950         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2951         .idlest_bit     = OMAP3430_ST_WDT3_SHIFT,
2952         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2953         .clkdm          = { .name = "per_clkdm" },
2954         .recalc         = &followparent_recalc,
2955 };
2956
2957 static struct clk uart3_ick = {
2958         .name           = "uart3_ick",
2959         .parent         = &per_l4_ick,
2960         .prcm_mod       = OMAP3430_PER_MOD,
2961         .enable_reg     = CM_ICLKEN,
2962         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2963         .idlest_bit     = OMAP3430_ST_UART3_SHIFT,
2964         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2965         .clkdm          = { .name = "per_clkdm" },
2966         .recalc         = &followparent_recalc,
2967 };
2968
2969 static struct clk gpt9_ick = {
2970         .name           = "gpt9_ick",
2971         .parent         = &per_l4_ick,
2972         .prcm_mod       = OMAP3430_PER_MOD,
2973         .enable_reg     = CM_ICLKEN,
2974         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2975         .idlest_bit     = OMAP3430_ST_GPT9_SHIFT,
2976         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2977         .clkdm          = { .name = "per_clkdm" },
2978         .recalc         = &followparent_recalc,
2979 };
2980
2981 static struct clk gpt8_ick = {
2982         .name           = "gpt8_ick",
2983         .parent         = &per_l4_ick,
2984         .prcm_mod       = OMAP3430_PER_MOD,
2985         .enable_reg     = CM_ICLKEN,
2986         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2987         .idlest_bit     = OMAP3430_ST_GPT8_SHIFT,
2988         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2989         .clkdm          = { .name = "per_clkdm" },
2990         .recalc         = &followparent_recalc,
2991 };
2992
2993 static struct clk gpt7_ick = {
2994         .name           = "gpt7_ick",
2995         .parent         = &per_l4_ick,
2996         .prcm_mod       = OMAP3430_PER_MOD,
2997         .enable_reg     = CM_ICLKEN,
2998         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2999         .idlest_bit     = OMAP3430_ST_GPT7_SHIFT,
3000         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3001         .clkdm          = { .name = "per_clkdm" },
3002         .recalc         = &followparent_recalc,
3003 };
3004
3005 static struct clk gpt6_ick = {
3006         .name           = "gpt6_ick",
3007         .parent         = &per_l4_ick,
3008         .prcm_mod       = OMAP3430_PER_MOD,
3009         .enable_reg     = CM_ICLKEN,
3010         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
3011         .idlest_bit     = OMAP3430_ST_GPT6_SHIFT,
3012         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3013         .clkdm          = { .name = "per_clkdm" },
3014         .recalc         = &followparent_recalc,
3015 };
3016
3017 static struct clk gpt5_ick = {
3018         .name           = "gpt5_ick",
3019         .parent         = &per_l4_ick,
3020         .prcm_mod       = OMAP3430_PER_MOD,
3021         .enable_reg     = CM_ICLKEN,
3022         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
3023         .idlest_bit     = OMAP3430_ST_GPT5_SHIFT,
3024         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3025         .clkdm          = { .name = "per_clkdm" },
3026         .recalc         = &followparent_recalc,
3027 };
3028
3029 static struct clk gpt4_ick = {
3030         .name           = "gpt4_ick",
3031         .parent         = &per_l4_ick,
3032         .prcm_mod       = OMAP3430_PER_MOD,
3033         .enable_reg     = CM_ICLKEN,
3034         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
3035         .idlest_bit     = OMAP3430_ST_GPT4_SHIFT,
3036         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3037         .clkdm          = { .name = "per_clkdm" },
3038         .recalc         = &followparent_recalc,
3039 };
3040
3041 static struct clk gpt3_ick = {
3042         .name           = "gpt3_ick",
3043         .parent         = &per_l4_ick,
3044         .prcm_mod       = OMAP3430_PER_MOD,
3045         .enable_reg     = CM_ICLKEN,
3046         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
3047         .idlest_bit     = OMAP3430_ST_GPT3_SHIFT,
3048         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3049         .clkdm          = { .name = "per_clkdm" },
3050         .recalc         = &followparent_recalc,
3051 };
3052
3053 static struct clk gpt2_ick = {
3054         .name           = "gpt2_ick",
3055         .parent         = &per_l4_ick,
3056         .prcm_mod       = OMAP3430_PER_MOD,
3057         .enable_reg     = CM_ICLKEN,
3058         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
3059         .idlest_bit     = OMAP3430_ST_GPT2_SHIFT,
3060         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3061         .clkdm          = { .name = "per_clkdm" },
3062         .recalc         = &followparent_recalc,
3063 };
3064
3065 static struct clk mcbsp2_ick = {
3066         .name           = "mcbsp_ick",
3067         .id             = 2,
3068         .parent         = &per_l4_ick,
3069         .prcm_mod       = OMAP3430_PER_MOD,
3070         .enable_reg     = CM_ICLKEN,
3071         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
3072         .idlest_bit     = OMAP3430_ST_MCBSP2_SHIFT,
3073         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3074         .clkdm          = { .name = "per_clkdm" },
3075         .recalc         = &followparent_recalc,
3076 };
3077
3078 static struct clk mcbsp3_ick = {
3079         .name           = "mcbsp_ick",
3080         .id             = 3,
3081         .parent         = &per_l4_ick,
3082         .prcm_mod       = OMAP3430_PER_MOD,
3083         .enable_reg     = CM_ICLKEN,
3084         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
3085         .idlest_bit     = OMAP3430_ST_MCBSP3_SHIFT,
3086         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3087         .clkdm          = { .name = "per_clkdm" },
3088         .recalc         = &followparent_recalc,
3089 };
3090
3091 static struct clk mcbsp4_ick = {
3092         .name           = "mcbsp_ick",
3093         .id             = 4,
3094         .parent         = &per_l4_ick,
3095         .prcm_mod       = OMAP3430_PER_MOD,
3096         .enable_reg     = CM_ICLKEN,
3097         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
3098         .idlest_bit     = OMAP3430_ST_MCBSP4_SHIFT,
3099         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3100         .clkdm          = { .name = "per_clkdm" },
3101         .recalc         = &followparent_recalc,
3102 };
3103
3104 static const struct clksel mcbsp_234_clksel[] = {
3105         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
3106         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
3107         { .parent = NULL }
3108 };
3109
3110 static struct clk mcbsp2_src_fck = {
3111         .name           = "mcbsp_src_fck",
3112         .id             = 2,
3113         .prcm_mod       = CLK_REG_IN_SCM,
3114         .init           = &omap2_init_clksel_parent,
3115         .clksel_reg     = OMAP2_CONTROL_DEVCONF0,
3116         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
3117         .clksel         = mcbsp_234_clksel,
3118         .flags          = CLOCK_IN_OMAP343X,
3119         .clkdm          = { .name = "per_clkdm" },
3120         .recalc         = &omap2_clksel_recalc,
3121 };
3122
3123 static struct clk mcbsp2_fck = {
3124         .name           = "mcbsp_fck",
3125         .id             = 2,
3126         .parent         = &mcbsp2_src_fck,
3127         .prcm_mod       = OMAP3430_PER_MOD,
3128         .enable_reg     = CM_FCLKEN,
3129         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
3130         .idlest_bit     = OMAP3430_ST_MCBSP2_SHIFT,
3131         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3132         .clkdm          = { .name = "per_clkdm" },
3133         .recalc         = &omap2_clksel_recalc,
3134 };
3135
3136 static struct clk mcbsp3_src_fck = {
3137         .name           = "mcbsp_src_fck",
3138         .id             = 3,
3139         .prcm_mod       = CLK_REG_IN_SCM,
3140         .init           = &omap2_init_clksel_parent,
3141         .clksel_reg     = OMAP343X_CONTROL_DEVCONF1,
3142         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
3143         .clksel         = mcbsp_234_clksel,
3144         .flags          = CLOCK_IN_OMAP343X,
3145         .clkdm          = { .name = "per_clkdm" },
3146         .recalc         = &omap2_clksel_recalc,
3147 };
3148
3149 static struct clk mcbsp3_fck = {
3150         .name           = "mcbsp_fck",
3151         .id             = 3,
3152         .parent         = &mcbsp3_src_fck,
3153         .prcm_mod       = OMAP3430_PER_MOD,
3154         .enable_reg     = CM_FCLKEN,
3155         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
3156         .idlest_bit     = OMAP3430_ST_MCBSP3_SHIFT,
3157         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3158         .clkdm          = { .name = "per_clkdm" },
3159         .recalc         = &omap2_clksel_recalc,
3160 };
3161
3162 static struct clk mcbsp4_src_fck = {
3163         .name           = "mcbsp_src_fck",
3164         .id             = 4,
3165         .prcm_mod       = CLK_REG_IN_SCM,
3166         .init           = &omap2_init_clksel_parent,
3167         .clksel_reg     = OMAP343X_CONTROL_DEVCONF1,
3168         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
3169         .clksel         = mcbsp_234_clksel,
3170         .flags          = CLOCK_IN_OMAP343X,
3171         .clkdm          = { .name = "per_clkdm" },
3172         .recalc         = &omap2_clksel_recalc,
3173 };
3174
3175 static struct clk mcbsp4_fck = {
3176         .name           = "mcbsp_fck",
3177         .id             = 4,
3178         .parent         = &mcbsp4_src_fck,
3179         .prcm_mod       = OMAP3430_PER_MOD,
3180         .enable_reg     = CM_FCLKEN,
3181         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
3182         .idlest_bit     = OMAP3430_ST_MCBSP4_SHIFT,
3183         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3184         .clkdm          = { .name = "per_clkdm" },
3185         .recalc         = &omap2_clksel_recalc,
3186 };
3187
3188 /* EMU clocks */
3189
3190 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
3191
3192 static const struct clksel_rate emu_src_sys_rates[] = {
3193         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
3194         { .div = 0 },
3195 };
3196
3197 static const struct clksel_rate emu_src_core_rates[] = {
3198         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3199         { .div = 0 },
3200 };
3201
3202 static const struct clksel_rate emu_src_per_rates[] = {
3203         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3204         { .div = 0 },
3205 };
3206
3207 static const struct clksel_rate emu_src_mpu_rates[] = {
3208         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
3209         { .div = 0 },
3210 };
3211
3212 static const struct clksel emu_src_clksel[] = {
3213         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
3214         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
3215         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
3216         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
3217         { .parent = NULL },
3218 };
3219
3220 /*
3221  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
3222  * to switch the source of some of the EMU clocks.
3223  * XXX Are there CLKEN bits for these EMU clks?
3224  */
3225 static struct clk emu_src_ck = {
3226         .name           = "emu_src_ck",
3227         .prcm_mod       = OMAP3430_EMU_MOD,
3228         .init           = &omap2_init_clksel_parent,
3229         .clksel_reg     = CM_CLKSEL1,
3230         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
3231         .clksel         = emu_src_clksel,
3232         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3233         .clkdm          = { .name = "emu_clkdm" },
3234         .recalc         = &omap2_clksel_recalc,
3235 };
3236
3237 static const struct clksel_rate pclk_emu_rates[] = {
3238         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3239         { .div = 3, .val = 3, .flags = RATE_IN_343X },
3240         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3241         { .div = 6, .val = 6, .flags = RATE_IN_343X },
3242         { .div = 0 },
3243 };
3244
3245 static const struct clksel pclk_emu_clksel[] = {
3246         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
3247         { .parent = NULL },
3248 };
3249
3250 static struct clk pclk_fck = {
3251         .name           = "pclk_fck",
3252         .prcm_mod       = OMAP3430_EMU_MOD,
3253         .init           = &omap2_init_clksel_parent,
3254         .clksel_reg     = CM_CLKSEL1,
3255         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
3256         .clksel         = pclk_emu_clksel,
3257         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3258         .clkdm          = { .name = "emu_clkdm" },
3259         .recalc         = &omap2_clksel_recalc,
3260 };
3261
3262 static const struct clksel_rate pclkx2_emu_rates[] = {
3263         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3264         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3265         { .div = 3, .val = 3, .flags = RATE_IN_343X },
3266         { .div = 0 },
3267 };
3268
3269 static const struct clksel pclkx2_emu_clksel[] = {
3270         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
3271         { .parent = NULL },
3272 };
3273
3274 static struct clk pclkx2_fck = {
3275         .name           = "pclkx2_fck",
3276         .prcm_mod       = OMAP3430_EMU_MOD,
3277         .init           = &omap2_init_clksel_parent,
3278         .clksel_reg     = CM_CLKSEL1,
3279         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
3280         .clksel         = pclkx2_emu_clksel,
3281         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3282         .clkdm          = { .name = "emu_clkdm" },
3283         .recalc         = &omap2_clksel_recalc,
3284 };
3285
3286 static const struct clksel atclk_emu_clksel[] = {
3287         { .parent = &emu_src_ck, .rates = div2_rates },
3288         { .parent = NULL },
3289 };
3290
3291 static struct clk atclk_fck = {
3292         .name           = "atclk_fck",
3293         .prcm_mod       = OMAP3430_EMU_MOD,
3294         .init           = &omap2_init_clksel_parent,
3295         .clksel_reg     = CM_CLKSEL1,
3296         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
3297         .clksel         = atclk_emu_clksel,
3298         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3299         .clkdm          = { .name = "emu_clkdm" },
3300         .recalc         = &omap2_clksel_recalc,
3301 };
3302
3303 static struct clk traceclk_src_fck = {
3304         .name           = "traceclk_src_fck",
3305         .prcm_mod       = OMAP3430_EMU_MOD,
3306         .init           = &omap2_init_clksel_parent,
3307         .clksel_reg     = CM_CLKSEL1,
3308         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
3309         .clksel         = emu_src_clksel,
3310         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3311         .clkdm          = { .name = "emu_clkdm" },
3312         .recalc         = &omap2_clksel_recalc,
3313 };
3314
3315 static const struct clksel_rate traceclk_rates[] = {
3316         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3317         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3318         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3319         { .div = 0 },
3320 };
3321
3322 static const struct clksel traceclk_clksel[] = {
3323         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3324         { .parent = NULL },
3325 };
3326
3327 static struct clk traceclk_fck = {
3328         .name           = "traceclk_fck",
3329         .prcm_mod       = OMAP3430_EMU_MOD,
3330         .init           = &omap2_init_clksel_parent,
3331         .clksel_reg     = CM_CLKSEL1,
3332         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3333         .clksel         = traceclk_clksel,
3334         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3335         .clkdm          = { .name = "emu_clkdm" },
3336         .recalc         = &omap2_clksel_recalc,
3337 };
3338
3339 /* SR clocks */
3340
3341 /* SmartReflex fclk (VDD1) */
3342 static struct clk sr1_fck = {
3343         .name           = "sr1_fck",
3344         .parent         = &sys_ck,
3345         .prcm_mod       = WKUP_MOD,
3346         .enable_reg     = CM_FCLKEN,
3347         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3348         .idlest_bit     = OMAP3430_ST_SR1_SHIFT,
3349         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | WAIT_READY,
3350         .clkdm          = { .name = "prm_clkdm" },
3351         .recalc         = &followparent_recalc,
3352 };
3353
3354 /* SmartReflex fclk (VDD2) */
3355 static struct clk sr2_fck = {
3356         .name           = "sr2_fck",
3357         .parent         = &sys_ck,
3358         .prcm_mod       = WKUP_MOD,
3359         .enable_reg     = CM_FCLKEN,
3360         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3361         .idlest_bit     = OMAP3430_ST_SR2_SHIFT,
3362         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | WAIT_READY,
3363         .clkdm          = { .name = "prm_clkdm" },
3364         .recalc         = &followparent_recalc,
3365 };
3366
3367 static struct clk sr_l4_ick = {
3368         .name           = "sr_l4_ick",
3369         .parent         = &l4_ick,
3370         .flags          = CLOCK_IN_OMAP343X,
3371         .clkdm          = { .name = "core_l4_clkdm" },
3372         .recalc         = &followparent_recalc,
3373 };
3374
3375 /* SECURE_32K_FCK clocks */
3376
3377 /* XXX Make sure idlest_bit/wait_ready with no enable_bit works */
3378 static struct clk gpt12_fck = {
3379         .name           = "gpt12_fck",
3380         .parent         = &secure_32k_fck,
3381         .idlest_bit     = OMAP3430_ST_GPT12_SHIFT,
3382         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | WAIT_READY,
3383         .clkdm          = { .name = "prm_clkdm" },
3384         .recalc         = &followparent_recalc,
3385 };
3386
3387 static struct clk wdt1_fck = {
3388         .name           = "wdt1_fck",
3389         .parent         = &secure_32k_fck,
3390         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3391         .clkdm          = { .name = "prm_clkdm" },
3392         .recalc         = &followparent_recalc,
3393 };
3394
3395 static struct clk *onchip_34xx_clks[] __initdata = {
3396         &omap_32k_fck,
3397         &virt_12m_ck,
3398         &virt_13m_ck,
3399         &virt_16_8m_ck,
3400         &virt_19_2m_ck,
3401         &virt_26m_ck,
3402         &virt_38_4m_ck,
3403         &osc_sys_ck,
3404         &sys_ck,
3405         &sys_altclk,
3406         &mcbsp_clks,
3407         &sys_clkout1,
3408         &dpll1_ck,
3409         &dpll1_x2_ck,
3410         &dpll1_x2m2_ck,
3411         &dpll2_ck,
3412         &dpll2_m2_ck,
3413         &dpll3_ck,
3414         &core_ck,
3415         &dpll3_x2_ck,
3416         &dpll3_m2_ck,
3417         &dpll3_m2x2_ck,
3418         &dpll3_m3_ck,
3419         &dpll3_m3x2_ck,
3420         &emu_core_alwon_ck,
3421         &dpll4_ck,
3422         &dpll4_x2_ck,
3423         &omap_96m_alwon_fck,
3424         &omap_96m_fck,
3425         &cm_96m_fck,
3426         &omap_54m_fck,
3427         &omap_48m_fck,
3428         &omap_12m_fck,
3429         &dpll4_m2_ck,
3430         &dpll4_m2x2_ck,
3431         &dpll4_m3_ck,
3432         &dpll4_m3x2_ck,
3433         &dpll4_m4_ck,
3434         &dpll4_m4x2_ck,
3435         &dpll4_m5_ck,
3436         &dpll4_m5x2_ck,
3437         &dpll4_m6_ck,
3438         &dpll4_m6x2_ck,
3439         &emu_per_alwon_ck,
3440         &dpll5_ck,
3441         &dpll5_m2_ck,
3442         &clkout2_src_ck,
3443         &sys_clkout2,
3444         &corex2_fck,
3445         &dpll1_fck,
3446         &mpu_ck,
3447         &arm_fck,
3448         &emu_mpu_alwon_ck,
3449         &dpll2_fck,
3450         &iva2_ck,
3451         &l3_ick,
3452         &l4_ick,
3453         &rm_ick,
3454         &gfx_l3_ck,
3455         &gfx_l3_fck,
3456         &gfx_l3_ick,
3457         &gfx_cg1_ck,
3458         &gfx_cg2_ck,
3459         &sgx_fck,
3460         &sgx_ick,
3461         &d2d_26m_fck,
3462         &gpt10_fck,
3463         &gpt11_fck,
3464         &cpefuse_fck,
3465         &ts_fck,
3466         &usbtll_fck,
3467         &core_96m_fck,
3468         &mmchs3_fck,
3469         &mmchs2_fck,
3470         &mspro_fck,
3471         &mmchs1_fck,
3472         &i2c3_fck,
3473         &i2c2_fck,
3474         &i2c1_fck,
3475         &mcbsp5_src_fck,
3476         &mcbsp5_fck,
3477         &mcbsp1_src_fck,
3478         &mcbsp1_fck,
3479         &core_48m_fck,
3480         &mcspi4_fck,
3481         &mcspi3_fck,
3482         &mcspi2_fck,
3483         &mcspi1_fck,
3484         &uart2_fck,
3485         &uart1_fck,
3486         &fshostusb_fck,
3487         &core_12m_fck,
3488         &hdq_fck,
3489         &ssi_ssr_fck_3430es1,
3490         &ssi_ssr_fck_3430es2,
3491         &ssi_sst_fck_3430es1,
3492         &ssi_sst_fck_3430es2,
3493         &core_l3_ick,
3494         &hsotgusb_ick_3430es1,
3495         &hsotgusb_ick_3430es2,
3496         &sdrc_ick,
3497         &gpmc_fck,
3498         &security_l3_ick,
3499         &pka_ick,
3500         &core_l4_ick,
3501         &usbtll_ick,
3502         &mmchs3_ick,
3503         &icr_ick,
3504         &aes2_ick,
3505         &sha12_ick,
3506         &des2_ick,
3507         &mmchs2_ick,
3508         &mmchs1_ick,
3509         &mspro_ick,
3510         &hdq_ick,
3511         &mcspi4_ick,
3512         &mcspi3_ick,
3513         &mcspi2_ick,
3514         &mcspi1_ick,
3515         &i2c3_ick,
3516         &i2c2_ick,
3517         &i2c1_ick,
3518         &uart2_ick,
3519         &uart1_ick,
3520         &gpt11_ick,
3521         &gpt10_ick,
3522         &mcbsp5_ick,
3523         &mcbsp1_ick,
3524         &fac_ick,
3525         &mailboxes_ick,
3526         &omapctrl_ick,
3527         &ssi_l4_ick,
3528         &ssi_ick_3430es1,
3529         &ssi_ick_3430es2,
3530         &usb_l4_ick,
3531         &security_l4_ick2,
3532         &aes1_ick,
3533         &rng_ick,
3534         &sha11_ick,
3535         &des1_ick,
3536         &dss1_alwon_fck_3430es1,
3537         &dss1_alwon_fck_3430es2,
3538         &dss_tv_fck,
3539         &dss_96m_fck,
3540         &dss2_alwon_fck,
3541         &dss_ick_3430es1,
3542         &dss_ick_3430es2,
3543         &cam_mclk,
3544         &cam_ick,
3545         &csi2_96m_fck,
3546         &usbhost_120m_fck,
3547         &usbhost_48m_fck,
3548         &usbhost_ick,
3549         &usim_fck,
3550         &gpt1_fck,
3551         &wkup_32k_fck,
3552         &gpio1_dbck,
3553         &wdt2_fck,
3554         &wkup_l4_ick,
3555         &usim_ick,
3556         &wdt2_ick,
3557         &wdt1_ick,
3558         &gpio1_ick,
3559         &omap_32ksync_ick,
3560         &gpt12_ick,
3561         &gpt1_ick,
3562         &per_96m_fck,
3563         &per_48m_fck,
3564         &uart3_fck,
3565         &gpt2_fck,
3566         &gpt3_fck,
3567         &gpt4_fck,
3568         &gpt5_fck,
3569         &gpt6_fck,
3570         &gpt7_fck,
3571         &gpt8_fck,
3572         &gpt9_fck,
3573         &per_32k_alwon_fck,
3574         &gpio6_dbck,
3575         &gpio5_dbck,
3576         &gpio4_dbck,
3577         &gpio3_dbck,
3578         &gpio2_dbck,
3579         &wdt3_fck,
3580         &per_l4_ick,
3581         &gpio6_ick,
3582         &gpio5_ick,
3583         &gpio4_ick,
3584         &gpio3_ick,
3585         &gpio2_ick,
3586         &wdt3_ick,
3587         &uart3_ick,
3588         &gpt9_ick,
3589         &gpt8_ick,
3590         &gpt7_ick,
3591         &gpt6_ick,
3592         &gpt5_ick,
3593         &gpt4_ick,
3594         &gpt3_ick,
3595         &gpt2_ick,
3596         &mcbsp2_ick,
3597         &mcbsp3_ick,
3598         &mcbsp4_ick,
3599         &mcbsp2_src_fck,
3600         &mcbsp2_fck,
3601         &mcbsp3_src_fck,
3602         &mcbsp3_fck,
3603         &mcbsp4_src_fck,
3604         &mcbsp4_fck,
3605         &emu_src_ck,
3606         &pclk_fck,
3607         &pclkx2_fck,
3608         &atclk_fck,
3609         &traceclk_src_fck,
3610         &traceclk_fck,
3611         &sr1_fck,
3612         &sr2_fck,
3613         &sr_l4_ick,
3614         &secure_32k_fck,
3615         &gpt12_fck,
3616         &wdt1_fck,
3617 };
3618
3619 #endif